68 lines
3.1 KiB
XML
68 lines
3.1 KiB
XML
<?xml version='1.0' encoding='UTF-8'?>
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<!DOCTYPE topic PUBLIC "-//OASIS//DTD DITA Topic//EN" "topic.dtd">
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<topic xml:lang="en-us" id="nestedpaging">
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<title>Nested Paging and VPIDs</title>
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<body>
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<p>
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In addition to normal hardware virtualization, your processor may
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also support the following additional sophisticated techniques:
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</p>
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<ul>
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<li>
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<p>
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Nested paging implements some memory management in hardware,
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which can greatly accelerate hardware virtualization since
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these tasks no longer need to be performed by the
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virtualization software.
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</p>
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<p>
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With nested paging, the hardware provides another level of
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indirection when translating linear to physical addresses.
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Page tables function as before, but linear addresses are now
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translated to "guest physical" addresses first and not
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physical addresses directly. A new set of paging registers now
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exists under the traditional paging mechanism and translates
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from guest physical addresses to host physical addresses,
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which are used to access memory.
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</p>
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<p>
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Nested paging eliminates the overhead caused by VM exits and
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page table accesses. In essence, with nested page tables the
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guest can handle paging without intervention from the
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hypervisor. Nested paging thus significantly improves
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virtualization performance.
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</p>
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<p>
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On AMD processors, nested paging has been available starting
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with the Barcelona (K10) architecture. They now call it rapid
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virtualization indexing (RVI). Intel added support for nested
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paging, which they call extended page tables (EPT), with their
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Core i7 (Nehalem) processors.
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</p>
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<p> If nested paging is enabled, the <ph conkeyref="vbox-conkeyref-phrases/product-name"/> hypervisor can also use <i>large
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pages</i> to reduce TLB usage and overhead. This can yield a performance improvement of
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up to 5%. To enable this feature for a VM, you use the <userinput>VBoxManage modifyvm
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--large-pages</userinput> command. See <xref href="vboxmanage-modifyvm.dita">VBoxManage
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modifyvm</xref>. </p>
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<p>
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If you have an Intel CPU with EPT, please consult
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<xref href="sec-rec-cve-2018-3646.dita#sec-rec-cve-2018-3646"/> for security concerns
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regarding EPT.
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</p>
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</li>
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<li>
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<p>
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On Intel CPUs, a hardware feature called Virtual Processor
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Identifiers (VPIDs) can greatly accelerate context switching
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by reducing the need for expensive flushing of the processor's
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Translation Lookaside Buffers (TLBs).
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</p>
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<p> To enable these features for a VM, you use the <userinput>VBoxManage modifyvm
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--vtx-vpid</userinput> and <userinput>VBoxManage modifyvm --large-pages</userinput>
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commands. See <xref href="vboxmanage-modifyvm.dita">VBoxManage modifyvm</xref>. </p>
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</li>
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</ul>
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</body>
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</topic>
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