90 lines
3.6 KiB
C
90 lines
3.6 KiB
C
/** @file
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* IEM - Interpreted Execution Manager.
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*/
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/*
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* Copyright (C) 2011-2024 Oracle and/or its affiliates.
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*
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* This file is part of VirtualBox base platform packages, as
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* available from https://www.virtualbox.org.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, in version 3 of the
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* License.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <https://www.gnu.org/licenses>.
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*
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* The contents of this file may alternatively be used under the terms
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* of the Common Development and Distribution License Version 1.0
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* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
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* in the VirtualBox distribution, in which case the provisions of the
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* CDDL are applicable instead of those of the GPL.
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*
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* You may elect to license modified versions of this file under the
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* terms and conditions of either the GPL or the CDDL or both.
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*
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* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
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*/
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#ifndef VBOX_INCLUDED_vmm_iem_armv8_h
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#define VBOX_INCLUDED_vmm_iem_armv8_h
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#ifndef RT_WITHOUT_PRAGMA_ONCE
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# pragma once
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#endif
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RT_C_DECLS_BEGIN
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/** @addtogroup grp_iem
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* @{ */
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/** @name Instruction mode.
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* @{ */
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typedef uint8_t IEMMODE;
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/** AARCH64 instruction mode. */
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#define IEMMODE_AARCH64 0
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/** AARCH32 A32 instruction mode. */
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#define IEMMODE_AARCH32_A32 1
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/** AARCH32 T32 (aka Thumb) instruction mode. */
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#define IEMMODE_AARCH32_T32 1
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/** @} */
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/** The CPUMCTX_EXTRN_XXX mask required to be cleared when interpreting anything.
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* IEM will ASSUME the caller of IEM APIs has ensured these are already present. */
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#define IEM_CPUMCTX_EXTRN_MUST_MASK ( CPUMCTX_EXTRN_GPRS_MASK \
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| CPUMCTX_EXTRN_PC \
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| CPUMCTX_EXTRN_SPSR \
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| CPUMCTX_EXTRN_ELR \
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| CPUMCTX_EXTRN_SP \
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| CPUMCTX_EXTRN_PSTATE )
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/** The CPUMCTX_EXTRN_XXX mask needed when injecting an exception/interrupt.
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* IEM will import missing bits, callers are encouraged to make these registers
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* available prior to injection calls if fetching state anyway. */
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#define IEM_CPUMCTX_EXTRN_XCPT_MASK ( IEM_CPUMCTX_EXTRN_MUST_MASK ) /** @todo */
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/** The CPUMCTX_EXTRN_XXX mask required to be cleared when calling any
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* IEMExecDecoded API not using memory. IEM will ASSUME the caller of IEM
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* APIs has ensured these are already present.
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* @note ASSUMES execution engine has checked for instruction breakpoints
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* during decoding. */
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#define IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK ( CPUMCTX_EXTRN_PC \
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| CPUMCTX_EXTRN_PSTATE )
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/** The CPUMCTX_EXTRN_XXX mask required to be cleared when calling any
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* IEMExecDecoded API using memory. IEM will ASSUME the caller of IEM
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* APIs has ensured these are already present.
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* @note ASSUMES execution engine has checked for instruction breakpoints
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* during decoding. */
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#define IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK ( IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK ) /** @todo */
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/** @} */
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RT_C_DECLS_END
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#endif /* !VBOX_INCLUDED_vmm_iem_armv8_h */
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