497 lines
23 KiB
ReStructuredText
497 lines
23 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0+
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=========================================================================
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OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface (TC6) Framework Support
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=========================================================================
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Introduction
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------------
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The IEEE 802.3cg project defines two 10 Mbit/s PHYs operating over a
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single pair of conductors. The 10BASE-T1L (Clause 146) is a long reach
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PHY supporting full duplex point-to-point operation over 1 km of single
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balanced pair of conductors. The 10BASE-T1S (Clause 147) is a short reach
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PHY supporting full / half duplex point-to-point operation over 15 m of
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single balanced pair of conductors, or half duplex multidrop bus
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operation over 25 m of single balanced pair of conductors.
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Furthermore, the IEEE 802.3cg project defines the new Physical Layer
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Collision Avoidance (PLCA) Reconciliation Sublayer (Clause 148) meant to
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provide improved determinism to the CSMA/CD media access method. PLCA
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works in conjunction with the 10BASE-T1S PHY operating in multidrop mode.
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The aforementioned PHYs are intended to cover the low-speed / low-cost
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applications in industrial and automotive environment. The large number
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of pins (16) required by the MII interface, which is specified by the
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IEEE 802.3 in Clause 22, is one of the major cost factors that need to be
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addressed to fulfil this objective.
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The MAC-PHY solution integrates an IEEE Clause 4 MAC and a 10BASE-T1x PHY
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exposing a low pin count Serial Peripheral Interface (SPI) to the host
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microcontroller. This also enables the addition of Ethernet functionality
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to existing low-end microcontrollers which do not integrate a MAC
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controller.
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Overview
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--------
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The MAC-PHY is specified to carry both data (Ethernet frames) and control
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(register access) transactions over a single full-duplex serial peripheral
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interface.
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Protocol Overview
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-----------------
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Two types of transactions are defined in the protocol: data transactions
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for Ethernet frame transfers and control transactions for register
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read/write transfers. A chunk is the basic element of data transactions
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and is composed of 4 bytes of overhead plus 64 bytes of payload size for
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each chunk. Ethernet frames are transferred over one or more data chunks.
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Control transactions consist of one or more register read/write control
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commands.
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SPI transactions are initiated by the SPI host with the assertion of CSn
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low to the MAC-PHY and ends with the deassertion of CSn high. In between
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each SPI transaction, the SPI host may need time for additional
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processing and to setup the next SPI data or control transaction.
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SPI data transactions consist of an equal number of transmit (TX) and
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receive (RX) chunks. Chunks in both transmit and receive directions may
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or may not contain valid frame data independent from each other, allowing
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for the simultaneous transmission and reception of different length
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frames.
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Each transmit data chunk begins with a 32-bit data header followed by a
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data chunk payload on MOSI. The data header indicates whether transmit
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frame data is present and provides the information to determine which
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bytes of the payload contain valid frame data.
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In parallel, receive data chunks are received on MISO. Each receive data
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chunk consists of a data chunk payload ending with a 32-bit data footer.
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The data footer indicates if there is receive frame data present within
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the payload or not and provides the information to determine which bytes
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of the payload contain valid frame data.
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Reference
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---------
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10BASE-T1x MAC-PHY Serial Interface Specification,
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Link: https://opensig.org/download/document/OPEN_Alliance_10BASET1x_MAC-PHY_Serial_Interface_V1.1.pdf
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Hardware Architecture
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---------------------
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.. code-block:: none
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+----------+ +-------------------------------------+
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| | | MAC-PHY |
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| |<---->| +-----------+ +-------+ +-------+ |
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| SPI Host | | | SPI Slave | | MAC | | PHY | |
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| | | +-----------+ +-------+ +-------+ |
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+----------+ +-------------------------------------+
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Software Architecture
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---------------------
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.. code-block:: none
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+----------------------------------------------------------+
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| Networking Subsystem |
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+----------------------------------------------------------+
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/ \ / \
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| |
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| |
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\ / |
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+----------------------+ +-----------------------------+
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| MAC Driver |<--->| OPEN Alliance TC6 Framework |
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+----------------------+ +-----------------------------+
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/ \ / \
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| |
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| |
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| \ /
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+----------------------------------------------------------+
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| SPI Subsystem |
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+----------------------------------------------------------+
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/ \
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\ /
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+----------------------------------------------------------+
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| 10BASE-T1x MAC-PHY Device |
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+----------------------------------------------------------+
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Implementation
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--------------
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MAC Driver
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~~~~~~~~~~
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- Probed by SPI subsystem.
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- Initializes OA TC6 framework for the MAC-PHY.
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- Registers and configures the network device.
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- Sends the tx ethernet frames from n/w subsystem to OA TC6 framework.
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OPEN Alliance TC6 Framework
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~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- Initializes PHYLIB interface.
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- Registers mac-phy interrupt.
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- Performs mac-phy register read/write operation using the control
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transaction protocol specified in the OPEN Alliance 10BASE-T1x MAC-PHY
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Serial Interface specification.
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- Performs Ethernet frames transaction using the data transaction protocol
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for Ethernet frames specified in the OPEN Alliance 10BASE-T1x MAC-PHY
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Serial Interface specification.
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- Forwards the received Ethernet frame from 10Base-T1x MAC-PHY to n/w
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subsystem.
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Data Transaction
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~~~~~~~~~~~~~~~~
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The Ethernet frames that are typically transferred from the SPI host to
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the MAC-PHY will be converted into multiple transmit data chunks. Each
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transmit data chunk will have a 4 bytes header which contains the
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information needed to determine the validity and the location of the
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transmit frame data within the 64 bytes data chunk payload.
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.. code-block:: none
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+---------------------------------------------------+
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| Tx Chunk |
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| +---------------------------+ +----------------+ | MOSI
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| | 64 bytes chunk payload | | 4 bytes header | |------------>
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| +---------------------------+ +----------------+ |
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+---------------------------------------------------+
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4 bytes header contains the below fields,
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DNC (Bit 31) - Data-Not-Control flag. This flag specifies the type of SPI
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transaction. For TX data chunks, this bit shall be ’1’.
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0 - Control command
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1 - Data chunk
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SEQ (Bit 30) - Data Chunk Sequence. This bit is used to indicate an
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even/odd transmit data chunk sequence to the MAC-PHY.
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NORX (Bit 29) - No Receive flag. The SPI host may set this bit to prevent
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the MAC-PHY from conveying RX data on the MISO for the
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current chunk (DV = 0 in the footer), indicating that the
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host would not process it. Typically, the SPI host should
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set NORX = 0 indicating that it will accept and process
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any receive frame data within the current chunk.
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RSVD (Bit 28..24) - Reserved: All reserved bits shall be ‘0’.
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VS (Bit 23..22) - Vendor Specific. These bits are implementation specific.
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If the MAC-PHY does not implement these bits, the host
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shall set them to ‘0’.
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DV (Bit 21) - Data Valid flag. The SPI host uses this bit to indicate
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whether the current chunk contains valid transmit frame data
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(DV = 1) or not (DV = 0). When ‘0’, the MAC-PHY ignores the
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chunk payload. Note that the receive path is unaffected by
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the setting of the DV bit in the data header.
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SV (Bit 20) - Start Valid flag. The SPI host shall set this bit when the
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beginning of an Ethernet frame is present in the current
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transmit data chunk payload. Otherwise, this bit shall be
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zero. This bit is not to be confused with the Start-of-Frame
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Delimiter (SFD) byte described in IEEE 802.3 [2].
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SWO (Bit 19..16) - Start Word Offset. When SV = 1, this field shall
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contain the 32-bit word offset into the transmit data
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chunk payload that points to the start of a new
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Ethernet frame to be transmitted. The host shall write
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this field as zero when SV = 0.
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RSVD (Bit 15) - Reserved: All reserved bits shall be ‘0’.
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EV (Bit 14) - End Valid flag. The SPI host shall set this bit when the end
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of an Ethernet frame is present in the current transmit data
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chunk payload. Otherwise, this bit shall be zero.
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EBO (Bit 13..8) - End Byte Offset. When EV = 1, this field shall contain
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the byte offset into the transmit data chunk payload
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that points to the last byte of the Ethernet frame to
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transmit. This field shall be zero when EV = 0.
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TSC (Bit 7..6) - Timestamp Capture. Request a timestamp capture when the
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frame is transmitted onto the network.
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00 - Do not capture a timestamp
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01 - Capture timestamp into timestamp capture register A
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10 - Capture timestamp into timestamp capture register B
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11 - Capture timestamp into timestamp capture register C
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RSVD (Bit 5..1) - Reserved: All reserved bits shall be ‘0’.
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P (Bit 0) - Parity. Parity bit calculated over the transmit data header.
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Method used is odd parity.
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The number of buffers available in the MAC-PHY to store the incoming
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transmit data chunk payloads is represented as transmit credits. The
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available transmit credits in the MAC-PHY can be read either from the
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Buffer Status Register or footer (Refer below for the footer info)
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received from the MAC-PHY. The SPI host should not write more data chunks
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than the available transmit credits as this will lead to transmit buffer
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overflow error.
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In case the previous data footer had no transmit credits available and
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once the transmit credits become available for transmitting transmit data
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chunks, the MAC-PHY interrupt is asserted to SPI host. On reception of the
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first data header this interrupt will be deasserted and the received
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footer for the first data chunk will have the transmit credits available
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information.
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The Ethernet frames that are typically transferred from MAC-PHY to SPI
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host will be sent as multiple receive data chunks. Each receive data
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chunk will have 64 bytes of data chunk payload followed by 4 bytes footer
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which contains the information needed to determine the validity and the
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location of the receive frame data within the 64 bytes data chunk payload.
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.. code-block:: none
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+---------------------------------------------------+
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| Rx Chunk |
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| +----------------+ +---------------------------+ | MISO
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| | 4 bytes footer | | 64 bytes chunk payload | |------------>
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| +----------------+ +---------------------------+ |
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+---------------------------------------------------+
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4 bytes footer contains the below fields,
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EXST (Bit 31) - Extended Status. This bit is set when any bit in the
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STATUS0 or STATUS1 registers are set and not masked.
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HDRB (Bit 30) - Received Header Bad. When set, indicates that the MAC-PHY
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received a control or data header with a parity error.
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SYNC (Bit 29) - Configuration Synchronized flag. This bit reflects the
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state of the SYNC bit in the CONFIG0 configuration
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register (see Table 12). A zero indicates that the MAC-PHY
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configuration may not be as expected by the SPI host.
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Following configuration, the SPI host sets the
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corresponding bitin the configuration register which is
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reflected in this field.
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RCA (Bit 28..24) - Receive Chunks Available. The RCA field indicates to
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the SPI host the minimum number of additional receive
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data chunks of frame data that are available for
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reading beyond the current receive data chunk. This
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field is zero when there is no receive frame data
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pending in the MAC-PHY’s buffer for reading.
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VS (Bit 23..22) - Vendor Specific. These bits are implementation specific.
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If not implemented, the MAC-PHY shall set these bits to
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‘0’.
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DV (Bit 21) - Data Valid flag. The MAC-PHY uses this bit to indicate
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whether the current receive data chunk contains valid
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receive frame data (DV = 1) or not (DV = 0). When ‘0’, the
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SPI host shall ignore the chunk payload.
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SV (Bit 20) - Start Valid flag. The MAC-PHY sets this bit when the current
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chunk payload contains the start of an Ethernet frame.
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Otherwise, this bit is zero. The SV bit is not to be
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confused with the Start-of-Frame Delimiter (SFD) byte
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described in IEEE 802.3 [2].
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SWO (Bit 19..16) - Start Word Offset. When SV = 1, this field contains the
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32-bit word offset into the receive data chunk payload
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containing the first byte of a new received Ethernet
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frame. When a receive timestamp has been added to the
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beginning of the received Ethernet frame (RTSA = 1)
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then SWO points to the most significant byte of the
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timestamp. This field will be zero when SV = 0.
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FD (Bit 15) - Frame Drop. When set, this bit indicates that the MAC has
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detected a condition for which the SPI host should drop the
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received Ethernet frame. This bit is only valid at the end
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of a received Ethernet frame (EV = 1) and shall be zero at
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all other times.
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EV (Bit 14) - End Valid flag. The MAC-PHY sets this bit when the end of a
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received Ethernet frame is present in this receive data
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chunk payload.
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EBO (Bit 13..8) - End Byte Offset: When EV = 1, this field contains the
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byte offset into the receive data chunk payload that
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locates the last byte of the received Ethernet frame.
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This field is zero when EV = 0.
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RTSA (Bit 7) - Receive Timestamp Added. This bit is set when a 32-bit or
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64-bit timestamp has been added to the beginning of the
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received Ethernet frame. The MAC-PHY shall set this bit to
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zero when SV = 0.
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RTSP (Bit 6) - Receive Timestamp Parity. Parity bit calculated over the
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32-bit/64-bit timestamp added to the beginning of the
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received Ethernet frame. Method used is odd parity. The
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MAC-PHY shall set this bit to zero when RTSA = 0.
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TXC (Bit 5..1) - Transmit Credits. This field contains the minimum number
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of transmit data chunks of frame data that the SPI host
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can write in a single transaction without incurring a
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transmit buffer overflow error.
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P (Bit 0) - Parity. Parity bit calculated over the receive data footer.
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Method used is odd parity.
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SPI host will initiate the data receive transaction based on the receive
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chunks available in the MAC-PHY which is provided in the receive chunk
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footer (RCA - Receive Chunks Available). SPI host will create data invalid
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transmit data chunks (empty chunks) or data valid transmit data chunks in
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case there are valid Ethernet frames to transmit to the MAC-PHY. The
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receive chunks available in MAC-PHY can be read either from the Buffer
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Status Register or footer.
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In case the previous data footer had no receive data chunks available and
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once the receive data chunks become available again for reading, the
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MAC-PHY interrupt is asserted to SPI host. On reception of the first data
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header this interrupt will be deasserted and the received footer for the
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first data chunk will have the receive chunks available information.
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MAC-PHY Interrupt
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~~~~~~~~~~~~~~~~~
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The MAC-PHY interrupt is asserted when the following conditions are met.
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Receive chunks available - This interrupt is asserted when the previous
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data footer had no receive data chunks available and once the receive
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data chunks become available for reading. On reception of the first data
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header this interrupt will be deasserted.
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Transmit chunk credits available - This interrupt is asserted when the
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previous data footer indicated no transmit credits available and once the
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transmit credits become available for transmitting transmit data chunks.
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On reception of the first data header this interrupt will be deasserted.
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Extended status event - This interrupt is asserted when the previous data
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footer indicated no extended status and once the extended event become
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available. In this case the host should read status #0 register to know
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the corresponding error/event. On reception of the first data header this
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interrupt will be deasserted.
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Control Transaction
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~~~~~~~~~~~~~~~~~~~
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4 bytes control header contains the below fields,
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DNC (Bit 31) - Data-Not-Control flag. This flag specifies the type of SPI
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transaction. For control commands, this bit shall be ‘0’.
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0 - Control command
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1 - Data chunk
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HDRB (Bit 30) - Received Header Bad. When set by the MAC-PHY, indicates
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that a header was received with a parity error. The SPI
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host should always clear this bit. The MAC-PHY ignores the
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HDRB value sent by the SPI host on MOSI.
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WNR (Bit 29) - Write-Not-Read. This bit indicates if data is to be written
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to registers (when set) or read from registers
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(when clear).
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AID (Bit 28) - Address Increment Disable. When clear, the address will be
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automatically post-incremented by one following each
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register read or write. When set, address auto increment is
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disabled allowing successive reads and writes to occur at
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the same register address.
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MMS (Bit 27..24) - Memory Map Selector. This field selects the specific
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register memory map to access.
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ADDR (Bit 23..8) - Address. Address of the first register within the
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selected memory map to access.
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LEN (Bit 7..1) - Length. Specifies the number of registers to read/write.
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This field is interpreted as the number of registers
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minus 1 allowing for up to 128 consecutive registers read
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or written starting at the address specified in ADDR. A
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length of zero shall read or write a single register.
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P (Bit 0) - Parity. Parity bit calculated over the control command header.
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Method used is odd parity.
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Control transactions consist of one or more control commands. Control
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commands are used by the SPI host to read and write registers within the
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MAC-PHY. Each control commands are composed of a 4 bytes control command
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header followed by register write data in case of control write command.
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The MAC-PHY ignores the final 4 bytes of data from the SPI host at the end
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of the control write command. The control write command is also echoed
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from the MAC-PHY back to the SPI host to identify which register write
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failed in case of any bus errors. The echoed Control write command will
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have the first 4 bytes unused value to be ignored by the SPI host
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followed by 4 bytes echoed control header followed by echoed register
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write data. Control write commands can write either a single register or
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multiple consecutive registers. When multiple consecutive registers are
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written, the address is automatically post-incremented by the MAC-PHY.
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Writing to any unimplemented or undefined registers shall be ignored and
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yield no effect.
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The MAC-PHY ignores all data from the SPI host following the control
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header for the remainder of the control read command. The control read
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command is also echoed from the MAC-PHY back to the SPI host to identify
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which register read is failed in case of any bus errors. The echoed
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Control read command will have the first 4 bytes of unused value to be
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ignored by the SPI host followed by 4 bytes echoed control header followed
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by register read data. Control read commands can read either a single
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register or multiple consecutive registers. When multiple consecutive
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registers are read, the address is automatically post-incremented by the
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MAC-PHY. Reading any unimplemented or undefined registers shall return
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zero.
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Device drivers API
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==================
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The include/linux/oa_tc6.h defines the following functions:
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.. c:function:: struct oa_tc6 *oa_tc6_init(struct spi_device *spi, \
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struct net_device *netdev)
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Initialize OA TC6 lib.
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.. c:function:: void oa_tc6_exit(struct oa_tc6 *tc6)
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Free allocated OA TC6 lib.
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.. c:function:: int oa_tc6_write_register(struct oa_tc6 *tc6, u32 address, \
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u32 value)
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Write a single register in the MAC-PHY.
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.. c:function:: int oa_tc6_write_registers(struct oa_tc6 *tc6, u32 address, \
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u32 value[], u8 length)
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Writing multiple consecutive registers starting from @address in the MAC-PHY.
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Maximum of 128 consecutive registers can be written starting at @address.
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.. c:function:: int oa_tc6_read_register(struct oa_tc6 *tc6, u32 address, \
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u32 *value)
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Read a single register in the MAC-PHY.
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.. c:function:: int oa_tc6_read_registers(struct oa_tc6 *tc6, u32 address, \
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u32 value[], u8 length)
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Reading multiple consecutive registers starting from @address in the MAC-PHY.
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Maximum of 128 consecutive registers can be read starting at @address.
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.. c:function:: netdev_tx_t oa_tc6_start_xmit(struct oa_tc6 *tc6, \
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struct sk_buff *skb);
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The transmit Ethernet frame in the skb is or going to be transmitted through
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the MAC-PHY.
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.. c:function:: int oa_tc6_zero_align_receive_frame_enable(struct oa_tc6 *tc6);
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Zero align receive frame feature can be enabled to align all receive ethernet
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frames data to start at the beginning of any receive data chunk payload with a
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start word offset (SWO) of zero.
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