368 lines
8.3 KiB
C
368 lines
8.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2015 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*/
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#include <linux/irqflags.h>
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#include <asm/kvm_hyp.h>
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#include <asm/kvm_mmu.h>
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#include <asm/tlbflush.h>
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struct tlb_inv_context {
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struct kvm_s2_mmu *mmu;
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unsigned long flags;
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u64 tcr;
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u64 sctlr;
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};
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static void enter_vmid_context(struct kvm_s2_mmu *mmu,
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struct tlb_inv_context *cxt)
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{
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struct kvm_vcpu *vcpu = kvm_get_running_vcpu();
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u64 val;
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local_irq_save(cxt->flags);
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if (vcpu && mmu != vcpu->arch.hw_mmu)
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cxt->mmu = vcpu->arch.hw_mmu;
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else
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cxt->mmu = NULL;
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if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) {
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/*
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* For CPUs that are affected by ARM errata 1165522 or 1530923,
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* we cannot trust stage-1 to be in a correct state at that
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* point. Since we do not want to force a full load of the
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* vcpu state, we prevent the EL1 page-table walker to
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* allocate new TLBs. This is done by setting the EPD bits
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* in the TCR_EL1 register. We also need to prevent it to
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* allocate IPA->PA walks, so we enable the S1 MMU...
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*/
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val = cxt->tcr = read_sysreg_el1(SYS_TCR);
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val |= TCR_EPD1_MASK | TCR_EPD0_MASK;
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write_sysreg_el1(val, SYS_TCR);
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val = cxt->sctlr = read_sysreg_el1(SYS_SCTLR);
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val |= SCTLR_ELx_M;
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write_sysreg_el1(val, SYS_SCTLR);
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}
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/*
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* With VHE enabled, we have HCR_EL2.{E2H,TGE} = {1,1}, and
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* most TLB operations target EL2/EL0. In order to affect the
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* guest TLBs (EL1/EL0), we need to change one of these two
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* bits. Changing E2H is impossible (goodbye TTBR1_EL2), so
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* let's flip TGE before executing the TLB operation.
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*
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* ARM erratum 1165522 requires some special handling (again),
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* as we need to make sure both stages of translation are in
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* place before clearing TGE. __load_stage2() already
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* has an ISB in order to deal with this.
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*/
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__load_stage2(mmu, mmu->arch);
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val = read_sysreg(hcr_el2);
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val &= ~HCR_TGE;
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write_sysreg(val, hcr_el2);
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isb();
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}
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static void exit_vmid_context(struct tlb_inv_context *cxt)
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{
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/*
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* We're done with the TLB operation, let's restore the host's
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* view of HCR_EL2.
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*/
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write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);
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isb();
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/* ... and the stage-2 MMU context that we switched away from */
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if (cxt->mmu)
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__load_stage2(cxt->mmu, cxt->mmu->arch);
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if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) {
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/* Restore the registers to what they were */
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write_sysreg_el1(cxt->tcr, SYS_TCR);
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write_sysreg_el1(cxt->sctlr, SYS_SCTLR);
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}
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local_irq_restore(cxt->flags);
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}
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void __kvm_tlb_flush_vmid_ipa(struct kvm_s2_mmu *mmu,
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phys_addr_t ipa, int level)
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{
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struct tlb_inv_context cxt;
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dsb(ishst);
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/* Switch to requested VMID */
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enter_vmid_context(mmu, &cxt);
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/*
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* We could do so much better if we had the VA as well.
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* Instead, we invalidate Stage-2 for this IPA, and the
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* whole of Stage-1. Weep...
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*/
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ipa >>= 12;
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__tlbi_level(ipas2e1is, ipa, level);
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/*
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* We have to ensure completion of the invalidation at Stage-2,
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* since a table walk on another CPU could refill a TLB with a
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* complete (S1 + S2) walk based on the old Stage-2 mapping if
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* the Stage-1 invalidation happened first.
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*/
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dsb(ish);
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__tlbi(vmalle1is);
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dsb(ish);
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isb();
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exit_vmid_context(&cxt);
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}
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void __kvm_tlb_flush_vmid_ipa_nsh(struct kvm_s2_mmu *mmu,
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phys_addr_t ipa, int level)
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{
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struct tlb_inv_context cxt;
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dsb(nshst);
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/* Switch to requested VMID */
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enter_vmid_context(mmu, &cxt);
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/*
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* We could do so much better if we had the VA as well.
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* Instead, we invalidate Stage-2 for this IPA, and the
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* whole of Stage-1. Weep...
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*/
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ipa >>= 12;
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__tlbi_level(ipas2e1, ipa, level);
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/*
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* We have to ensure completion of the invalidation at Stage-2,
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* since a table walk on another CPU could refill a TLB with a
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* complete (S1 + S2) walk based on the old Stage-2 mapping if
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* the Stage-1 invalidation happened first.
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*/
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dsb(nsh);
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__tlbi(vmalle1);
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dsb(nsh);
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isb();
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exit_vmid_context(&cxt);
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}
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void __kvm_tlb_flush_vmid_range(struct kvm_s2_mmu *mmu,
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phys_addr_t start, unsigned long pages)
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{
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struct tlb_inv_context cxt;
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unsigned long stride;
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/*
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* Since the range of addresses may not be mapped at
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* the same level, assume the worst case as PAGE_SIZE
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*/
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stride = PAGE_SIZE;
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start = round_down(start, stride);
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dsb(ishst);
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/* Switch to requested VMID */
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enter_vmid_context(mmu, &cxt);
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__flush_s2_tlb_range_op(ipas2e1is, start, pages, stride,
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TLBI_TTL_UNKNOWN);
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dsb(ish);
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__tlbi(vmalle1is);
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dsb(ish);
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isb();
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exit_vmid_context(&cxt);
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}
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void __kvm_tlb_flush_vmid(struct kvm_s2_mmu *mmu)
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{
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struct tlb_inv_context cxt;
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dsb(ishst);
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/* Switch to requested VMID */
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enter_vmid_context(mmu, &cxt);
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__tlbi(vmalls12e1is);
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dsb(ish);
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isb();
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exit_vmid_context(&cxt);
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}
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void __kvm_flush_cpu_context(struct kvm_s2_mmu *mmu)
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{
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struct tlb_inv_context cxt;
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/* Switch to requested VMID */
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enter_vmid_context(mmu, &cxt);
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__tlbi(vmalle1);
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asm volatile("ic iallu");
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dsb(nsh);
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isb();
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exit_vmid_context(&cxt);
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}
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void __kvm_flush_vm_context(void)
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{
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dsb(ishst);
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__tlbi(alle1is);
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dsb(ish);
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}
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/*
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* TLB invalidation emulation for NV. For any given instruction, we
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* perform the following transformtions:
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*
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* - a TLBI targeting EL2 S1 is remapped to EL1 S1
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* - a non-shareable TLBI is upgraded to being inner-shareable
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* - an outer-shareable TLBI is also mapped to inner-shareable
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* - an nXS TLBI is upgraded to XS
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*/
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int __kvm_tlbi_s1e2(struct kvm_s2_mmu *mmu, u64 va, u64 sys_encoding)
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{
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struct tlb_inv_context cxt;
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int ret = 0;
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/*
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* The guest will have provided its own DSB ISHST before trapping.
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* If it hasn't, that's its own problem, and we won't paper over it
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* (plus, there is plenty of extra synchronisation before we even
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* get here...).
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*/
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if (mmu)
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enter_vmid_context(mmu, &cxt);
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switch (sys_encoding) {
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case OP_TLBI_ALLE2:
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case OP_TLBI_ALLE2IS:
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case OP_TLBI_ALLE2OS:
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case OP_TLBI_VMALLE1:
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case OP_TLBI_VMALLE1IS:
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case OP_TLBI_VMALLE1OS:
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case OP_TLBI_ALLE2NXS:
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case OP_TLBI_ALLE2ISNXS:
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case OP_TLBI_ALLE2OSNXS:
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case OP_TLBI_VMALLE1NXS:
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case OP_TLBI_VMALLE1ISNXS:
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case OP_TLBI_VMALLE1OSNXS:
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__tlbi(vmalle1is);
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break;
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case OP_TLBI_VAE2:
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case OP_TLBI_VAE2IS:
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case OP_TLBI_VAE2OS:
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case OP_TLBI_VAE1:
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case OP_TLBI_VAE1IS:
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case OP_TLBI_VAE1OS:
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case OP_TLBI_VAE2NXS:
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case OP_TLBI_VAE2ISNXS:
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case OP_TLBI_VAE2OSNXS:
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case OP_TLBI_VAE1NXS:
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case OP_TLBI_VAE1ISNXS:
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case OP_TLBI_VAE1OSNXS:
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__tlbi(vae1is, va);
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break;
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case OP_TLBI_VALE2:
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case OP_TLBI_VALE2IS:
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case OP_TLBI_VALE2OS:
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case OP_TLBI_VALE1:
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case OP_TLBI_VALE1IS:
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case OP_TLBI_VALE1OS:
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case OP_TLBI_VALE2NXS:
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case OP_TLBI_VALE2ISNXS:
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case OP_TLBI_VALE2OSNXS:
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case OP_TLBI_VALE1NXS:
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case OP_TLBI_VALE1ISNXS:
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case OP_TLBI_VALE1OSNXS:
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__tlbi(vale1is, va);
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break;
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case OP_TLBI_ASIDE1:
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case OP_TLBI_ASIDE1IS:
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case OP_TLBI_ASIDE1OS:
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case OP_TLBI_ASIDE1NXS:
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case OP_TLBI_ASIDE1ISNXS:
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case OP_TLBI_ASIDE1OSNXS:
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__tlbi(aside1is, va);
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break;
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case OP_TLBI_VAAE1:
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case OP_TLBI_VAAE1IS:
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case OP_TLBI_VAAE1OS:
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case OP_TLBI_VAAE1NXS:
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case OP_TLBI_VAAE1ISNXS:
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case OP_TLBI_VAAE1OSNXS:
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__tlbi(vaae1is, va);
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break;
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case OP_TLBI_VAALE1:
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case OP_TLBI_VAALE1IS:
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case OP_TLBI_VAALE1OS:
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case OP_TLBI_VAALE1NXS:
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case OP_TLBI_VAALE1ISNXS:
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case OP_TLBI_VAALE1OSNXS:
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__tlbi(vaale1is, va);
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break;
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case OP_TLBI_RVAE2:
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case OP_TLBI_RVAE2IS:
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case OP_TLBI_RVAE2OS:
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case OP_TLBI_RVAE1:
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case OP_TLBI_RVAE1IS:
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case OP_TLBI_RVAE1OS:
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case OP_TLBI_RVAE2NXS:
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case OP_TLBI_RVAE2ISNXS:
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case OP_TLBI_RVAE2OSNXS:
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case OP_TLBI_RVAE1NXS:
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case OP_TLBI_RVAE1ISNXS:
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case OP_TLBI_RVAE1OSNXS:
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__tlbi(rvae1is, va);
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break;
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case OP_TLBI_RVALE2:
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case OP_TLBI_RVALE2IS:
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case OP_TLBI_RVALE2OS:
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case OP_TLBI_RVALE1:
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case OP_TLBI_RVALE1IS:
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case OP_TLBI_RVALE1OS:
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case OP_TLBI_RVALE2NXS:
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case OP_TLBI_RVALE2ISNXS:
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case OP_TLBI_RVALE2OSNXS:
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case OP_TLBI_RVALE1NXS:
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case OP_TLBI_RVALE1ISNXS:
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case OP_TLBI_RVALE1OSNXS:
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__tlbi(rvale1is, va);
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break;
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case OP_TLBI_RVAAE1:
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case OP_TLBI_RVAAE1IS:
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case OP_TLBI_RVAAE1OS:
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case OP_TLBI_RVAAE1NXS:
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case OP_TLBI_RVAAE1ISNXS:
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case OP_TLBI_RVAAE1OSNXS:
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__tlbi(rvaae1is, va);
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break;
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case OP_TLBI_RVAALE1:
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case OP_TLBI_RVAALE1IS:
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case OP_TLBI_RVAALE1OS:
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case OP_TLBI_RVAALE1NXS:
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case OP_TLBI_RVAALE1ISNXS:
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case OP_TLBI_RVAALE1OSNXS:
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__tlbi(rvaale1is, va);
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break;
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default:
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ret = -EINVAL;
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}
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dsb(ish);
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isb();
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if (mmu)
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exit_vmid_context(&cxt);
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return ret;
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}
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