18 lines
485 B
C
18 lines
485 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_CACHEINFO_H
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#define _ASM_X86_CACHEINFO_H
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/* Kernel controls MTRR and/or PAT MSRs. */
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extern unsigned int memory_caching_control;
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#define CACHE_MTRR 0x01
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#define CACHE_PAT 0x02
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void cache_disable(void);
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void cache_enable(void);
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void set_cache_aps_delayed_init(bool val);
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bool get_cache_aps_delayed_init(void);
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void cache_bp_init(void);
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void cache_bp_restore(void);
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void cache_aps_init(void);
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#endif /* _ASM_X86_CACHEINFO_H */
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