25 lines
718 B
C
25 lines
718 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2024 Intel Corporation
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*/
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#ifndef __INTEL_TDF_H__
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#define __INTEL_TDF_H__
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/*
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* TDF (Transient-Data-Flush) is needed for Xe2+ where special L3:XD caching can
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* be enabled through various PAT index modes. Idea is to use this caching mode
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* when for example rendering onto the display surface, with the promise that
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* KMD will ensure transient cache entries are always flushed by the time we do
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* the display flip, since display engine is never coherent with CPU/GPU caches.
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*/
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struct drm_i915_private;
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#ifdef I915
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static inline void intel_td_flush(struct drm_i915_private *i915) {}
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#else
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void intel_td_flush(struct drm_i915_private *i915);
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#endif
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#endif
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