370 lines
9.7 KiB
C
370 lines
9.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright(c) 2009-2012 Realtek Corporation.*/
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#include "../wifi.h"
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#include "../pci.h"
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#include "../base.h"
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#include "../efuse.h"
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#include "def.h"
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#include "reg.h"
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#include "fw_common.h"
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bool rtl92d_is_fw_downloaded(struct rtl_priv *rtlpriv)
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{
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return !!(rtl_read_dword(rtlpriv, REG_MCUFWDL) & MCUFWDL_RDY);
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}
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EXPORT_SYMBOL_GPL(rtl92d_is_fw_downloaded);
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void rtl92d_enable_fw_download(struct ieee80211_hw *hw, bool enable)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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u8 tmp;
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if (enable) {
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tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
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rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp | 0x04);
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tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
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rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp | 0x01);
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tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL + 2);
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rtl_write_byte(rtlpriv, REG_MCUFWDL + 2, tmp & 0xf7);
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} else {
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tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
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rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp & 0xfe);
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/* Reserved for fw extension.
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* 0x81[7] is used for mac0 status ,
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* so don't write this reg here
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* rtl_write_byte(rtlpriv, REG_MCUFWDL + 1, 0x00);
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*/
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}
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}
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EXPORT_SYMBOL_GPL(rtl92d_enable_fw_download);
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void rtl92d_write_fw(struct ieee80211_hw *hw,
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enum version_8192d version, u8 *buffer, u32 size)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
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u8 *bufferptr = buffer;
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u32 pagenums, remainsize;
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u32 page, offset;
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rtl_dbg(rtlpriv, COMP_FW, DBG_TRACE, "FW size is %d bytes,\n", size);
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if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
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rtl_fill_dummy(bufferptr, &size);
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pagenums = size / FW_8192D_PAGE_SIZE;
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remainsize = size % FW_8192D_PAGE_SIZE;
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if (pagenums > 8)
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pr_err("Page numbers should not greater then 8\n");
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for (page = 0; page < pagenums; page++) {
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offset = page * FW_8192D_PAGE_SIZE;
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rtl_fw_page_write(hw, page, (bufferptr + offset),
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FW_8192D_PAGE_SIZE);
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}
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if (remainsize) {
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offset = pagenums * FW_8192D_PAGE_SIZE;
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page = pagenums;
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rtl_fw_page_write(hw, page, (bufferptr + offset), remainsize);
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}
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}
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EXPORT_SYMBOL_GPL(rtl92d_write_fw);
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int rtl92d_fw_free_to_go(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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u32 counter = 0;
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u32 value32;
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do {
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value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
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} while ((counter++ < FW_8192D_POLLING_TIMEOUT_COUNT) &&
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(!(value32 & FWDL_CHKSUM_RPT)));
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if (counter >= FW_8192D_POLLING_TIMEOUT_COUNT) {
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pr_err("chksum report fail! REG_MCUFWDL:0x%08x\n",
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value32);
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return -EIO;
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}
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value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
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value32 |= MCUFWDL_RDY;
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rtl_write_dword(rtlpriv, REG_MCUFWDL, value32);
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return 0;
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}
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EXPORT_SYMBOL_GPL(rtl92d_fw_free_to_go);
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#define RTL_USB_DELAY_FACTOR 60
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void rtl92d_firmware_selfreset(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
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u8 u1b_tmp;
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u8 delay = 100;
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if (rtlhal->interface == INTF_USB) {
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delay *= RTL_USB_DELAY_FACTOR;
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rtl_write_byte(rtlpriv, REG_FSIMR, 0);
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/* We need to disable other HRCV INT to influence 8051 reset. */
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rtl_write_byte(rtlpriv, REG_FWIMR, 0x20);
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/* Close mask to prevent incorrect FW write operation. */
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rtl_write_byte(rtlpriv, REG_FTIMR, 0);
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}
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/* Set (REG_HMETFR + 3) to 0x20 is reset 8051 */
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rtl_write_byte(rtlpriv, REG_HMETFR + 3, 0x20);
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u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
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while (u1b_tmp & (FEN_CPUEN >> 8)) {
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delay--;
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if (delay == 0)
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break;
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udelay(50);
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u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
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}
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if (rtlhal->interface == INTF_USB) {
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if ((u1b_tmp & (FEN_CPUEN >> 8)) && delay == 0)
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rtl_write_byte(rtlpriv, REG_FWIMR, 0);
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}
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WARN_ONCE((delay <= 0), "rtl8192de: 8051 reset failed!\n");
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rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG,
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"=====> 8051 reset success (%d)\n", delay);
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}
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EXPORT_SYMBOL_GPL(rtl92d_firmware_selfreset);
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int rtl92d_fw_init(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
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u32 counter;
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rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, "FW already have download\n");
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/* polling for FW ready */
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counter = 0;
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do {
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if (rtlhal->interfaceindex == 0) {
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if (rtl_read_byte(rtlpriv, FW_MAC0_READY) &
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MAC0_READY) {
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rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG,
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"Polling FW ready success!! REG_MCUFWDL: 0x%x\n",
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rtl_read_byte(rtlpriv,
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FW_MAC0_READY));
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return 0;
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}
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udelay(5);
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} else {
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if (rtl_read_byte(rtlpriv, FW_MAC1_READY) &
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MAC1_READY) {
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rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG,
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"Polling FW ready success!! REG_MCUFWDL: 0x%x\n",
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rtl_read_byte(rtlpriv,
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FW_MAC1_READY));
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return 0;
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}
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udelay(5);
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}
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} while (counter++ < POLLING_READY_TIMEOUT_COUNT);
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if (rtlhal->interfaceindex == 0) {
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rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG,
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"Polling FW ready fail!! MAC0 FW init not ready: 0x%x\n",
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rtl_read_byte(rtlpriv, FW_MAC0_READY));
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} else {
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rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG,
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"Polling FW ready fail!! MAC1 FW init not ready: 0x%x\n",
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rtl_read_byte(rtlpriv, FW_MAC1_READY));
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}
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rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG,
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"Polling FW ready fail!! REG_MCUFWDL:0x%08x\n",
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rtl_read_dword(rtlpriv, REG_MCUFWDL));
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return -1;
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}
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EXPORT_SYMBOL_GPL(rtl92d_fw_init);
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static bool _rtl92d_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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u8 val_hmetfr;
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bool result = false;
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val_hmetfr = rtl_read_byte(rtlpriv, REG_HMETFR);
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if (((val_hmetfr >> boxnum) & BIT(0)) == 0)
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result = true;
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return result;
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}
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void rtl92d_fill_h2c_cmd(struct ieee80211_hw *hw,
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u8 element_id, u32 cmd_len, u8 *cmdbuffer)
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{
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struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
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struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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u8 boxcontent[4], boxextcontent[2];
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u16 box_reg = 0, box_extreg = 0;
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u8 wait_writeh2c_limmit = 100;
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bool bwrite_success = false;
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u8 wait_h2c_limmit = 100;
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u32 h2c_waitcounter = 0;
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bool isfw_read = false;
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unsigned long flag;
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u8 u1b_tmp;
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u8 boxnum;
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u8 idx;
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if (ppsc->rfpwr_state == ERFOFF || ppsc->inactive_pwrstate == ERFOFF) {
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rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
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"Return as RF is off!!!\n");
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return;
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}
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rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "come in\n");
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while (true) {
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spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
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if (rtlhal->h2c_setinprogress) {
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rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
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"H2C set in progress! Wait to set..element_id(%d)\n",
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element_id);
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while (rtlhal->h2c_setinprogress) {
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spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock,
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flag);
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h2c_waitcounter++;
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rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
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"Wait 100 us (%d times)...\n",
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h2c_waitcounter);
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udelay(100);
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if (h2c_waitcounter > 1000)
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return;
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spin_lock_irqsave(&rtlpriv->locks.h2c_lock,
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flag);
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}
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spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
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} else {
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rtlhal->h2c_setinprogress = true;
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spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
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break;
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}
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}
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while (!bwrite_success) {
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wait_writeh2c_limmit--;
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if (wait_writeh2c_limmit == 0) {
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pr_err("Write H2C fail because no trigger for FW INT!\n");
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break;
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}
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boxnum = rtlhal->last_hmeboxnum;
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if (boxnum > 3) {
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pr_err("boxnum %#x too big\n", boxnum);
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break;
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}
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box_reg = REG_HMEBOX_0 + boxnum * SIZE_OF_REG_HMEBOX;
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box_extreg = REG_HMEBOX_EXT_0 + boxnum * SIZE_OF_REG_HMEBOX_EXT;
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isfw_read = _rtl92d_check_fw_read_last_h2c(hw, boxnum);
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while (!isfw_read) {
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wait_h2c_limmit--;
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if (wait_h2c_limmit == 0) {
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rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
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"Waiting too long for FW read clear HMEBox(%d)!\n",
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boxnum);
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break;
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}
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udelay(10);
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isfw_read = _rtl92d_check_fw_read_last_h2c(hw, boxnum);
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u1b_tmp = rtl_read_byte(rtlpriv, 0x1BF);
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rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
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"Waiting for FW read clear HMEBox(%d)!!! 0x1BF = %2x\n",
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boxnum, u1b_tmp);
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}
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if (!isfw_read) {
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rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
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"Write H2C register BOX[%d] fail!!!!! Fw do not read.\n",
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boxnum);
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break;
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}
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memset(boxcontent, 0, sizeof(boxcontent));
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memset(boxextcontent, 0, sizeof(boxextcontent));
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boxcontent[0] = element_id;
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rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
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"Write element_id box_reg(%4x) = %2x\n",
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box_reg, element_id);
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switch (cmd_len) {
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case 1 ... 3:
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/* BOX: | ID | A0 | A1 | A2 |
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* BOX_EXT: --- N/A ------
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*/
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boxcontent[0] &= ~BIT(7);
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memcpy(boxcontent + 1, cmdbuffer, cmd_len);
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for (idx = 0; idx < 4; idx++)
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rtl_write_byte(rtlpriv, box_reg + idx,
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boxcontent[idx]);
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break;
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case 4 ... 5:
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/* * ID ext = ID | BIT(7)
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* BOX: | ID ext | A2 | A3 | A4 |
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* BOX_EXT: | A0 | A1 |
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*/
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boxcontent[0] |= BIT(7);
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memcpy(boxextcontent, cmdbuffer, 2);
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memcpy(boxcontent + 1, cmdbuffer + 2, cmd_len - 2);
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for (idx = 0; idx < 2; idx++)
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rtl_write_byte(rtlpriv, box_extreg + idx,
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boxextcontent[idx]);
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for (idx = 0; idx < 4; idx++)
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rtl_write_byte(rtlpriv, box_reg + idx,
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boxcontent[idx]);
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break;
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default:
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pr_err("switch case %#x not processed\n", cmd_len);
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break;
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}
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bwrite_success = true;
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rtlhal->last_hmeboxnum = boxnum + 1;
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if (rtlhal->last_hmeboxnum == 4)
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rtlhal->last_hmeboxnum = 0;
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rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
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"pHalData->last_hmeboxnum = %d\n",
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rtlhal->last_hmeboxnum);
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}
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spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
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rtlhal->h2c_setinprogress = false;
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spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
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rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "go out\n");
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}
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EXPORT_SYMBOL_GPL(rtl92d_fill_h2c_cmd);
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void rtl92d_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus)
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{
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u8 u1_joinbssrpt_parm[1] = {0};
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u1_joinbssrpt_parm[0] = mstatus;
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rtl92d_fill_h2c_cmd(hw, H2C_JOINBSSRPT, 1, u1_joinbssrpt_parm);
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}
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EXPORT_SYMBOL_GPL(rtl92d_set_fw_joinbss_report_cmd);
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