120 lines
3.4 KiB
C
120 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright(c) 2024 Realtek Corporation.*/
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#include "../wifi.h"
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#include "../core.h"
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#include "../rtl8192d/reg.h"
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#include "../rtl8192d/def.h"
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#include "../rtl8192d/dm_common.h"
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#include "../rtl8192d/fw_common.h"
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#include "dm.h"
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static void rtl92du_dm_init_1r_cca(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
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dm_pstable->pre_ccastate = CCA_MAX;
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dm_pstable->cur_ccasate = CCA_MAX;
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}
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static void rtl92du_dm_1r_cca(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
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struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
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int pwdb = rtlpriv->dm_digtable.min_undec_pwdb_for_dm;
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if (rtlhal->macphymode != SINGLEMAC_SINGLEPHY ||
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rtlhal->current_bandtype != BAND_ON_5G)
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return;
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if (pwdb != 0) {
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if (dm_pstable->pre_ccastate == CCA_2R ||
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dm_pstable->pre_ccastate == CCA_MAX)
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dm_pstable->cur_ccasate = (pwdb >= 35) ? CCA_1R : CCA_2R;
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else
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dm_pstable->cur_ccasate = (pwdb <= 30) ? CCA_2R : CCA_1R;
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} else {
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dm_pstable->cur_ccasate = CCA_MAX;
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}
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if (dm_pstable->pre_ccastate == dm_pstable->cur_ccasate)
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return;
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rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_TRACE,
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"Old CCA state: %d new CCA state: %d\n",
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dm_pstable->pre_ccastate, dm_pstable->cur_ccasate);
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if (dm_pstable->cur_ccasate == CCA_1R) {
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if (rtlpriv->phy.rf_type == RF_2T2R)
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rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x13);
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else /* Is this branch reachable? */
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rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23);
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} else { /* CCA_2R or CCA_MAX */
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rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33);
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}
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}
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static void rtl92du_dm_pwdb_monitor(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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const u32 max_macid = 32;
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u32 temp;
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/* AP & ADHOC & MESH will return tmp */
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if (rtlpriv->mac80211.opmode != NL80211_IFTYPE_STATION)
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return;
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/* Indicate Rx signal strength to FW. */
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if (rtlpriv->dm.useramask) {
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temp = rtlpriv->dm.undec_sm_pwdb << 16;
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temp |= max_macid << 8;
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rtl92d_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, (u8 *)(&temp));
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} else {
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rtl_write_byte(rtlpriv, 0x4fe, (u8)rtlpriv->dm.undec_sm_pwdb);
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}
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}
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void rtl92du_dm_init(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
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rtl_dm_diginit(hw, 0x20);
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rtlpriv->dm_digtable.rx_gain_max = DM_DIG_FA_UPPER;
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rtlpriv->dm_digtable.rx_gain_min = DM_DIG_FA_LOWER;
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rtl92d_dm_init_edca_turbo(hw);
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rtl92du_dm_init_1r_cca(hw);
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rtl92d_dm_init_rate_adaptive_mask(hw);
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rtl92d_dm_initialize_txpower_tracking(hw);
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}
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void rtl92du_dm_watchdog(struct ieee80211_hw *hw)
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{
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struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
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bool fw_current_inpsmode = false;
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bool fwps_awake = true;
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/* 1. RF is OFF. (No need to do DM.)
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* 2. Fw is under power saving mode for FwLPS.
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* (Prevent from SW/FW I/O racing.)
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* 3. IPS workitem is scheduled. (Prevent from IPS sequence
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* to be swapped with DM.
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* 4. RFChangeInProgress is TRUE.
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* (Prevent from broken by IPS/HW/SW Rf off.)
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*/
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if (ppsc->rfpwr_state != ERFON || fw_current_inpsmode ||
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!fwps_awake || ppsc->rfchange_inprogress)
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return;
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rtl92du_dm_pwdb_monitor(hw);
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rtl92d_dm_false_alarm_counter_statistics(hw);
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rtl92d_dm_find_minimum_rssi(hw);
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rtl92d_dm_dig(hw);
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rtl92d_dm_check_txpower_tracking_thermal_meter(hw);
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rtl92d_dm_check_edca_turbo(hw);
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rtl92du_dm_1r_cca(hw);
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}
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