315 lines
9.8 KiB
C
315 lines
9.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/compiler.h>
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static struct ins_ops *powerpc__associate_instruction_ops(struct arch *arch, const char *name)
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{
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int i;
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struct ins_ops *ops;
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/*
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* - Interested only if instruction starts with 'b'.
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* - Few start with 'b', but aren't branch instructions.
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*/
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if (name[0] != 'b' ||
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!strncmp(name, "bcd", 3) ||
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!strncmp(name, "brinc", 5) ||
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!strncmp(name, "bper", 4))
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return NULL;
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ops = &jump_ops;
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i = strlen(name) - 1;
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if (i < 0)
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return NULL;
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/* ignore optional hints at the end of the instructions */
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if (name[i] == '+' || name[i] == '-')
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i--;
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if (name[i] == 'l' || (name[i] == 'a' && name[i-1] == 'l')) {
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/*
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* if the instruction ends up with 'l' or 'la', then
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* those are considered 'calls' since they update LR.
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* ... except for 'bnl' which is branch if not less than
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* and the absolute form of the same.
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*/
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if (strcmp(name, "bnl") && strcmp(name, "bnl+") &&
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strcmp(name, "bnl-") && strcmp(name, "bnla") &&
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strcmp(name, "bnla+") && strcmp(name, "bnla-"))
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ops = &call_ops;
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}
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if (name[i] == 'r' && name[i-1] == 'l')
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/*
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* instructions ending with 'lr' are considered to be
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* return instructions
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*/
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ops = &ret_ops;
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arch__associate_ins_ops(arch, name, ops);
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return ops;
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}
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#define PPC_OP(op) (((op) >> 26) & 0x3F)
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#define PPC_21_30(R) (((R) >> 1) & 0x3ff)
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#define PPC_22_30(R) (((R) >> 1) & 0x1ff)
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struct insn_offset {
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const char *name;
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int value;
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};
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/*
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* There are memory instructions with opcode 31 which are
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* of X Form, Example:
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* ldx RT,RA,RB
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* ______________________________________
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* | 31 | RT | RA | RB | 21 |/|
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* --------------------------------------
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* 0 6 11 16 21 30 31
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*
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* But all instructions with opcode 31 are not memory.
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* Example: add RT,RA,RB
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*
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* Use bits 21 to 30 to check memory insns with 31 as opcode.
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* In ins_array below, for ldx instruction:
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* name => OP_31_XOP_LDX
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* value => 21
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*/
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static struct insn_offset ins_array[] = {
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{ .name = "OP_31_XOP_LXSIWZX", .value = 12, },
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{ .name = "OP_31_XOP_LWARX", .value = 20, },
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{ .name = "OP_31_XOP_LDX", .value = 21, },
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{ .name = "OP_31_XOP_LWZX", .value = 23, },
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{ .name = "OP_31_XOP_LDUX", .value = 53, },
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{ .name = "OP_31_XOP_LWZUX", .value = 55, },
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{ .name = "OP_31_XOP_LXSIWAX", .value = 76, },
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{ .name = "OP_31_XOP_LDARX", .value = 84, },
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{ .name = "OP_31_XOP_LBZX", .value = 87, },
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{ .name = "OP_31_XOP_LVX", .value = 103, },
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{ .name = "OP_31_XOP_LBZUX", .value = 119, },
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{ .name = "OP_31_XOP_STXSIWX", .value = 140, },
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{ .name = "OP_31_XOP_STDX", .value = 149, },
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{ .name = "OP_31_XOP_STWX", .value = 151, },
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{ .name = "OP_31_XOP_STDUX", .value = 181, },
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{ .name = "OP_31_XOP_STWUX", .value = 183, },
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{ .name = "OP_31_XOP_STBX", .value = 215, },
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{ .name = "OP_31_XOP_STVX", .value = 231, },
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{ .name = "OP_31_XOP_STBUX", .value = 247, },
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{ .name = "OP_31_XOP_LHZX", .value = 279, },
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{ .name = "OP_31_XOP_LHZUX", .value = 311, },
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{ .name = "OP_31_XOP_LXVDSX", .value = 332, },
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{ .name = "OP_31_XOP_LWAX", .value = 341, },
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{ .name = "OP_31_XOP_LHAX", .value = 343, },
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{ .name = "OP_31_XOP_LWAUX", .value = 373, },
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{ .name = "OP_31_XOP_LHAUX", .value = 375, },
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{ .name = "OP_31_XOP_STHX", .value = 407, },
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{ .name = "OP_31_XOP_STHUX", .value = 439, },
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{ .name = "OP_31_XOP_LXSSPX", .value = 524, },
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{ .name = "OP_31_XOP_LDBRX", .value = 532, },
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{ .name = "OP_31_XOP_LSWX", .value = 533, },
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{ .name = "OP_31_XOP_LWBRX", .value = 534, },
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{ .name = "OP_31_XOP_LFSUX", .value = 567, },
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{ .name = "OP_31_XOP_LXSDX", .value = 588, },
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{ .name = "OP_31_XOP_LSWI", .value = 597, },
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{ .name = "OP_31_XOP_LFDX", .value = 599, },
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{ .name = "OP_31_XOP_LFDUX", .value = 631, },
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{ .name = "OP_31_XOP_STXSSPX", .value = 652, },
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{ .name = "OP_31_XOP_STDBRX", .value = 660, },
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{ .name = "OP_31_XOP_STXWX", .value = 661, },
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{ .name = "OP_31_XOP_STWBRX", .value = 662, },
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{ .name = "OP_31_XOP_STFSX", .value = 663, },
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{ .name = "OP_31_XOP_STFSUX", .value = 695, },
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{ .name = "OP_31_XOP_STXSDX", .value = 716, },
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{ .name = "OP_31_XOP_STSWI", .value = 725, },
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{ .name = "OP_31_XOP_STFDX", .value = 727, },
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{ .name = "OP_31_XOP_STFDUX", .value = 759, },
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{ .name = "OP_31_XOP_LXVW4X", .value = 780, },
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{ .name = "OP_31_XOP_LHBRX", .value = 790, },
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{ .name = "OP_31_XOP_LXVD2X", .value = 844, },
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{ .name = "OP_31_XOP_LFIWAX", .value = 855, },
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{ .name = "OP_31_XOP_LFIWZX", .value = 887, },
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{ .name = "OP_31_XOP_STXVW4X", .value = 908, },
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{ .name = "OP_31_XOP_STHBRX", .value = 918, },
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{ .name = "OP_31_XOP_STXVD2X", .value = 972, },
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{ .name = "OP_31_XOP_STFIWX", .value = 983, },
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};
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/*
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* Arithmetic instructions which are having opcode as 31.
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* These instructions are tracked to save the register state
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* changes. Example:
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*
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* lwz r10,264(r3)
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* add r31, r3, r3
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* lwz r9, 0(r31)
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*
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* Here instruction tracking needs to identify the "add"
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* instruction and save data type of r3 to r31. If a sample
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* is hit at next "lwz r9, 0(r31)", by this instruction tracking,
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* data type of r31 can be resolved.
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*/
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static struct insn_offset arithmetic_ins_op_31[] = {
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{ .name = "SUB_CARRY_XO_FORM", .value = 8, },
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{ .name = "MUL_HDW_XO_FORM1", .value = 9, },
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{ .name = "ADD_CARRY_XO_FORM", .value = 10, },
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{ .name = "MUL_HW_XO_FORM1", .value = 11, },
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{ .name = "SUB_XO_FORM", .value = 40, },
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{ .name = "MUL_HDW_XO_FORM", .value = 73, },
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{ .name = "MUL_HW_XO_FORM", .value = 75, },
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{ .name = "SUB_EXT_XO_FORM", .value = 136, },
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{ .name = "ADD_EXT_XO_FORM", .value = 138, },
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{ .name = "SUB_ZERO_EXT_XO_FORM", .value = 200, },
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{ .name = "ADD_ZERO_EXT_XO_FORM", .value = 202, },
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{ .name = "SUB_EXT_XO_FORM2", .value = 232, },
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{ .name = "MUL_DW_XO_FORM", .value = 233, },
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{ .name = "ADD_EXT_XO_FORM2", .value = 234, },
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{ .name = "MUL_W_XO_FORM", .value = 235, },
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{ .name = "ADD_XO_FORM", .value = 266, },
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{ .name = "DIV_DW_XO_FORM1", .value = 457, },
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{ .name = "DIV_W_XO_FORM1", .value = 459, },
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{ .name = "DIV_DW_XO_FORM", .value = 489, },
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{ .name = "DIV_W_XO_FORM", .value = 491, },
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};
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static struct insn_offset arithmetic_two_ops[] = {
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{ .name = "mulli", .value = 7, },
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{ .name = "subfic", .value = 8, },
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{ .name = "addic", .value = 12, },
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{ .name = "addic.", .value = 13, },
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{ .name = "addi", .value = 14, },
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{ .name = "addis", .value = 15, },
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};
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static int cmp_offset(const void *a, const void *b)
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{
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const struct insn_offset *val1 = a;
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const struct insn_offset *val2 = b;
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return (val1->value - val2->value);
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}
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static struct ins_ops *check_ppc_insn(struct disasm_line *dl)
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{
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int raw_insn = dl->raw.raw_insn;
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int opcode = PPC_OP(raw_insn);
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int mem_insn_31 = PPC_21_30(raw_insn);
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struct insn_offset *ret;
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struct insn_offset mem_insns_31_opcode = {
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"OP_31_INSN",
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mem_insn_31
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};
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char name_insn[32];
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/*
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* Instructions with opcode 32 to 63 are memory
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* instructions in powerpc
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*/
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if ((opcode & 0x20)) {
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/*
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* Set name in case of raw instruction to
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* opcode to be used in insn-stat
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*/
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if (!strlen(dl->ins.name)) {
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sprintf(name_insn, "%d", opcode);
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dl->ins.name = strdup(name_insn);
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}
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return &load_store_ops;
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} else if (opcode == 31) {
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/* Check for memory instructions with opcode 31 */
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ret = bsearch(&mem_insns_31_opcode, ins_array, ARRAY_SIZE(ins_array), sizeof(ins_array[0]), cmp_offset);
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if (ret) {
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if (!strlen(dl->ins.name))
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dl->ins.name = strdup(ret->name);
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return &load_store_ops;
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} else {
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mem_insns_31_opcode.value = PPC_22_30(raw_insn);
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ret = bsearch(&mem_insns_31_opcode, arithmetic_ins_op_31, ARRAY_SIZE(arithmetic_ins_op_31),
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sizeof(arithmetic_ins_op_31[0]), cmp_offset);
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if (ret != NULL)
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return &arithmetic_ops;
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/* Bits 21 to 30 has value 444 for "mr" insn ie, OR X form */
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if (PPC_21_30(raw_insn) == 444)
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return &arithmetic_ops;
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}
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} else {
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mem_insns_31_opcode.value = opcode;
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ret = bsearch(&mem_insns_31_opcode, arithmetic_two_ops, ARRAY_SIZE(arithmetic_two_ops),
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sizeof(arithmetic_two_ops[0]), cmp_offset);
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if (ret != NULL)
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return &arithmetic_ops;
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}
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return NULL;
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}
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/*
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* Instruction tracking function to track register state moves.
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* Example sequence:
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* ld r10,264(r3)
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* mr r31,r3
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* <<after some sequence>
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* ld r9,312(r31)
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*
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* Previous instruction sequence shows that register state of r3
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* is moved to r31. update_insn_state_powerpc tracks these state
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* changes
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*/
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#ifdef HAVE_DWARF_SUPPORT
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static void update_insn_state_powerpc(struct type_state *state,
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struct data_loc_info *dloc, Dwarf_Die * cu_die __maybe_unused,
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struct disasm_line *dl)
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{
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struct annotated_insn_loc loc;
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struct annotated_op_loc *src = &loc.ops[INSN_OP_SOURCE];
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struct annotated_op_loc *dst = &loc.ops[INSN_OP_TARGET];
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struct type_state_reg *tsr;
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u32 insn_offset = dl->al.offset;
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if (annotate_get_insn_location(dloc->arch, dl, &loc) < 0)
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return;
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/*
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* Value 444 for bits 21:30 is for "mr"
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* instruction. "mr" is extended OR. So set the
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* source and destination reg correctly
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*/
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if (PPC_21_30(dl->raw.raw_insn) == 444) {
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int src_reg = src->reg1;
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src->reg1 = dst->reg1;
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dst->reg1 = src_reg;
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}
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if (!has_reg_type(state, dst->reg1))
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return;
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tsr = &state->regs[dst->reg1];
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if (!has_reg_type(state, src->reg1) ||
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!state->regs[src->reg1].ok) {
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tsr->ok = false;
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return;
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}
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tsr->type = state->regs[src->reg1].type;
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tsr->kind = state->regs[src->reg1].kind;
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tsr->ok = true;
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pr_debug_dtp("mov [%x] reg%d -> reg%d",
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insn_offset, src->reg1, dst->reg1);
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pr_debug_type_name(&tsr->type, tsr->kind);
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}
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#endif /* HAVE_DWARF_SUPPORT */
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static int powerpc__annotate_init(struct arch *arch, char *cpuid __maybe_unused)
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{
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if (!arch->initialized) {
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arch->initialized = true;
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arch->associate_instruction_ops = powerpc__associate_instruction_ops;
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arch->objdump.comment_char = '#';
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annotate_opts.show_asm_raw = true;
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}
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return 0;
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}
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