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Adding upstream version 1:10.0.2+ds.

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Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
This commit is contained in:
Daniel Baumann 2025-06-22 14:27:05 +02:00
parent bf2768bd0f
commit ea34ddeea6
Signed by: daniel.baumann
GPG key ID: BCC918A2ABD66424
37998 changed files with 9510514 additions and 0 deletions
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57
include/hw/adc/aspeed_adc.h Normal file
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/*
* Aspeed ADC
*
* Copyright 2017-2021 IBM Corp.
*
* Andrew Jeffery <andrew@aj.id.au>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef HW_ADC_ASPEED_ADC_H
#define HW_ADC_ASPEED_ADC_H
#include "hw/sysbus.h"
#define TYPE_ASPEED_ADC "aspeed.adc"
#define TYPE_ASPEED_2400_ADC TYPE_ASPEED_ADC "-ast2400"
#define TYPE_ASPEED_2500_ADC TYPE_ASPEED_ADC "-ast2500"
#define TYPE_ASPEED_2600_ADC TYPE_ASPEED_ADC "-ast2600"
#define TYPE_ASPEED_1030_ADC TYPE_ASPEED_ADC "-ast1030"
#define TYPE_ASPEED_2700_ADC TYPE_ASPEED_ADC "-ast2700"
OBJECT_DECLARE_TYPE(AspeedADCState, AspeedADCClass, ASPEED_ADC)
#define TYPE_ASPEED_ADC_ENGINE "aspeed.adc.engine"
OBJECT_DECLARE_SIMPLE_TYPE(AspeedADCEngineState, ASPEED_ADC_ENGINE)
#define ASPEED_ADC_NR_CHANNELS 16
#define ASPEED_ADC_NR_REGS (0xD0 >> 2)
struct AspeedADCEngineState {
/* <private> */
SysBusDevice parent;
MemoryRegion mmio;
qemu_irq irq;
uint32_t engine_id;
uint32_t nr_channels;
uint32_t regs[ASPEED_ADC_NR_REGS];
};
struct AspeedADCState {
/* <private> */
SysBusDevice parent;
MemoryRegion mmio;
qemu_irq irq;
AspeedADCEngineState engines[2];
};
struct AspeedADCClass {
SysBusDeviceClass parent_class;
uint32_t nr_engines;
};
#endif /* HW_ADC_ASPEED_ADC_H */

68
include/hw/adc/npcm7xx_adc.h Normal file
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/*
* Nuvoton NPCM7xx ADC Module
*
* Copyright 2020 Google LLC
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#ifndef NPCM7XX_ADC_H
#define NPCM7XX_ADC_H
#include "hw/clock.h"
#include "hw/irq.h"
#include "hw/sysbus.h"
#include "qemu/timer.h"
#define NPCM7XX_ADC_NUM_INPUTS 8
/**
* This value should not be changed unless write_adc_calibration function in
* hw/arm/npcm7xx.c is also changed.
*/
#define NPCM7XX_ADC_NUM_CALIB 2
/**
* struct NPCM7xxADCState - Analog to Digital Converter Module device state.
* @parent: System bus device.
* @iomem: Memory region through which registers are accessed.
* @conv_timer: The timer counts down remaining cycles for the conversion.
* @irq: GIC interrupt line to fire on expiration (if enabled).
* @con: The Control Register.
* @data: The Data Buffer.
* @clock: The ADC Clock.
* @adci: The input voltage in units of uV. 1uv = 1e-6V.
* @vref: The external reference voltage.
* @iref: The internal reference voltage, initialized at launch time.
* @rv: The calibrated output values of 0.5V and 1.5V for the ADC.
*/
struct NPCM7xxADCState {
SysBusDevice parent;
MemoryRegion iomem;
QEMUTimer conv_timer;
qemu_irq irq;
uint32_t con;
uint32_t data;
Clock *clock;
/* Voltages are in unit of uV. 1V = 1000000uV. */
uint32_t adci[NPCM7XX_ADC_NUM_INPUTS];
uint32_t vref;
uint32_t iref;
uint16_t calibration_r_values[NPCM7XX_ADC_NUM_CALIB];
};
#define TYPE_NPCM7XX_ADC "npcm7xx-adc"
OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxADCState, NPCM7XX_ADC)
#endif /* NPCM7XX_ADC_H */

89
include/hw/adc/stm32f2xx_adc.h Normal file
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/*
* STM32F2XX ADC
*
* Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef HW_STM32F2XX_ADC_H
#define HW_STM32F2XX_ADC_H
#include "hw/sysbus.h"
#include "qom/object.h"
#define ADC_SR 0x00
#define ADC_CR1 0x04
#define ADC_CR2 0x08
#define ADC_SMPR1 0x0C
#define ADC_SMPR2 0x10
#define ADC_JOFR1 0x14
#define ADC_JOFR2 0x18
#define ADC_JOFR3 0x1C
#define ADC_JOFR4 0x20
#define ADC_HTR 0x24
#define ADC_LTR 0x28
#define ADC_SQR1 0x2C
#define ADC_SQR2 0x30
#define ADC_SQR3 0x34
#define ADC_JSQR 0x38
#define ADC_JDR1 0x3C
#define ADC_JDR2 0x40
#define ADC_JDR3 0x44
#define ADC_JDR4 0x48
#define ADC_DR 0x4C
#define ADC_CR2_ADON 0x01
#define ADC_CR2_CONT 0x02
#define ADC_CR2_ALIGN 0x800
#define ADC_CR2_SWSTART 0x40000000
#define ADC_CR1_RES 0x3000000
#define ADC_COMMON_ADDRESS 0x100
#define TYPE_STM32F2XX_ADC "stm32f2xx-adc"
OBJECT_DECLARE_SIMPLE_TYPE(STM32F2XXADCState, STM32F2XX_ADC)
struct STM32F2XXADCState {
/* <private> */
SysBusDevice parent_obj;
/* <public> */
MemoryRegion mmio;
uint32_t adc_sr;
uint32_t adc_cr1;
uint32_t adc_cr2;
uint32_t adc_smpr1;
uint32_t adc_smpr2;
uint32_t adc_jofr[4];
uint32_t adc_htr;
uint32_t adc_ltr;
uint32_t adc_sqr1;
uint32_t adc_sqr2;
uint32_t adc_sqr3;
uint32_t adc_jsqr;
uint32_t adc_jdr[4];
uint32_t adc_dr;
qemu_irq irq;
};
#endif /* HW_STM32F2XX_ADC_H */

45
include/hw/adc/zynq-xadc.h Normal file
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/*
* Device model for Zynq ADC controller
*
* Copyright (c) 2015 Guenter Roeck <linux@roeck-us.net>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef ZYNQ_XADC_H
#define ZYNQ_XADC_H
#include "hw/sysbus.h"
#include "qom/object.h"
#define ZYNQ_XADC_MMIO_SIZE 0x0020
#define ZYNQ_XADC_NUM_IO_REGS (ZYNQ_XADC_MMIO_SIZE / 4)
#define ZYNQ_XADC_NUM_ADC_REGS 128
#define ZYNQ_XADC_FIFO_DEPTH 15
#define TYPE_ZYNQ_XADC "xlnx-zynq-xadc"
OBJECT_DECLARE_SIMPLE_TYPE(ZynqXADCState, ZYNQ_XADC)
struct ZynqXADCState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
uint32_t regs[ZYNQ_XADC_NUM_IO_REGS];
uint16_t xadc_regs[ZYNQ_XADC_NUM_ADC_REGS];
uint16_t xadc_read_reg_previous;
uint16_t xadc_dfifo[ZYNQ_XADC_FIFO_DEPTH];
uint16_t xadc_dfifo_entries;
qemu_irq irq;
};
#endif /* ZYNQ_XADC_H */