20 lines
380 B
C
20 lines
380 B
C
/*
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* Riscv64 general target stuff that's common to all aarch details
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*
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* Copyright (c) 2022 M. Warner Losh <imp@bsdimp.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef TARGET_H
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#define TARGET_H
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/*
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* riscv64 ABI does not 'lump' the registers for 64-bit args.
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*/
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static inline bool regpairs_aligned(void *cpu_env)
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{
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return false;
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}
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#endif /* TARGET_H */
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