407 lines
12 KiB
C
407 lines
12 KiB
C
/*
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* QEMU model of the Xilinx Ethernet Lite MAC.
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*
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* Copyright (c) 2009 Edgar E. Iglesias.
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* Copyright (c) 2024 Linaro, Ltd
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*
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* DS580: https://docs.amd.com/v/u/en-US/xps_ethernetlite
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* LogiCORE IP XPS Ethernet Lite Media Access Controller
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/module.h"
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#include "qemu/bitops.h"
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#include "qom/object.h"
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#include "qapi/error.h"
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#include "hw/sysbus.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-properties-system.h"
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#include "hw/misc/unimp.h"
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#include "net/net.h"
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#include "trace.h"
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#define BUFSZ_MAX 0x07e4
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#define A_MDIO_BASE 0x07e4
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#define A_TX_BASE0 0x07f4
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#define A_TX_BASE1 0x0ff4
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#define A_RX_BASE0 0x17fc
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#define A_RX_BASE1 0x1ffc
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enum {
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TX_LEN = 0,
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TX_GIE = 1,
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TX_CTRL = 2,
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TX_MAX
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};
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enum {
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RX_CTRL = 0,
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RX_MAX
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};
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#define GIE_GIE 0x80000000
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#define CTRL_I 0x8
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#define CTRL_P 0x2
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#define CTRL_S 0x1
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typedef struct XlnxXpsEthLitePort {
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MemoryRegion txio;
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MemoryRegion rxio;
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MemoryRegion txbuf;
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MemoryRegion rxbuf;
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struct {
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uint32_t tx_len;
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uint32_t tx_gie;
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uint32_t tx_ctrl;
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uint32_t rx_ctrl;
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} reg;
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} XlnxXpsEthLitePort;
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#define TYPE_XILINX_ETHLITE "xlnx.xps-ethernetlite"
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OBJECT_DECLARE_SIMPLE_TYPE(XlnxXpsEthLite, XILINX_ETHLITE)
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struct XlnxXpsEthLite
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{
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SysBusDevice parent_obj;
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EndianMode model_endianness;
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MemoryRegion container;
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qemu_irq irq;
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NICState *nic;
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NICConf conf;
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uint32_t c_tx_pingpong;
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uint32_t c_rx_pingpong;
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unsigned int port_index; /* dual port RAM index */
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UnimplementedDeviceState rsvd;
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UnimplementedDeviceState mdio;
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XlnxXpsEthLitePort port[2];
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};
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static inline void eth_pulse_irq(XlnxXpsEthLite *s)
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{
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/* Only the first gie reg is active. */
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if (s->port[0].reg.tx_gie & GIE_GIE) {
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qemu_irq_pulse(s->irq);
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}
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}
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static unsigned addr_to_port_index(hwaddr addr)
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{
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return extract64(addr, 11, 1);
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}
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static void *txbuf_ptr(XlnxXpsEthLite *s, unsigned port_index)
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{
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return memory_region_get_ram_ptr(&s->port[port_index].txbuf);
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}
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static void *rxbuf_ptr(XlnxXpsEthLite *s, unsigned port_index)
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{
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return memory_region_get_ram_ptr(&s->port[port_index].rxbuf);
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}
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static uint64_t port_tx_read(void *opaque, hwaddr addr, unsigned int size)
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{
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XlnxXpsEthLite *s = opaque;
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unsigned port_index = addr_to_port_index(addr);
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uint32_t r = 0;
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switch (addr >> 2) {
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case TX_LEN:
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r = s->port[port_index].reg.tx_len;
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break;
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case TX_GIE:
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r = s->port[port_index].reg.tx_gie;
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break;
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case TX_CTRL:
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r = s->port[port_index].reg.tx_ctrl;
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break;
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default:
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g_assert_not_reached();
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}
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return r;
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}
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static void port_tx_write(void *opaque, hwaddr addr, uint64_t value,
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unsigned int size)
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{
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XlnxXpsEthLite *s = opaque;
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unsigned port_index = addr_to_port_index(addr);
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switch (addr >> 2) {
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case TX_LEN:
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s->port[port_index].reg.tx_len = value;
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break;
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case TX_GIE:
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s->port[port_index].reg.tx_gie = value;
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break;
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case TX_CTRL:
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if ((value & (CTRL_P | CTRL_S)) == CTRL_S) {
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qemu_send_packet(qemu_get_queue(s->nic),
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txbuf_ptr(s, port_index),
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s->port[port_index].reg.tx_len);
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if (s->port[port_index].reg.tx_ctrl & CTRL_I) {
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eth_pulse_irq(s);
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}
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} else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) {
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memcpy(&s->conf.macaddr.a[0], txbuf_ptr(s, port_index), 6);
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if (s->port[port_index].reg.tx_ctrl & CTRL_I) {
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eth_pulse_irq(s);
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}
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}
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/*
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* We are fast and get ready pretty much immediately
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* so we actually never flip the S nor P bits to one.
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*/
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s->port[port_index].reg.tx_ctrl = value & ~(CTRL_P | CTRL_S);
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break;
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default:
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g_assert_not_reached();
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}
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}
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static const MemoryRegionOps eth_porttx_ops[2] = {
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[0 ... 1] = {
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.read = port_tx_read,
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.write = port_tx_write,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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},
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[0].endianness = DEVICE_LITTLE_ENDIAN,
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[1].endianness = DEVICE_BIG_ENDIAN,
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};
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static uint64_t port_rx_read(void *opaque, hwaddr addr, unsigned int size)
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{
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XlnxXpsEthLite *s = opaque;
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unsigned port_index = addr_to_port_index(addr);
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uint32_t r = 0;
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switch (addr >> 2) {
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case RX_CTRL:
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r = s->port[port_index].reg.rx_ctrl;
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break;
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default:
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g_assert_not_reached();
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}
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return r;
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}
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static void port_rx_write(void *opaque, hwaddr addr, uint64_t value,
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unsigned int size)
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{
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XlnxXpsEthLite *s = opaque;
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unsigned port_index = addr_to_port_index(addr);
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switch (addr >> 2) {
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case RX_CTRL:
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if (!(value & CTRL_S)) {
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qemu_flush_queued_packets(qemu_get_queue(s->nic));
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}
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s->port[port_index].reg.rx_ctrl = value;
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break;
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default:
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g_assert_not_reached();
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}
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}
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static const MemoryRegionOps eth_portrx_ops[2] = {
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[0 ... 1] = {
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.read = port_rx_read,
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.write = port_rx_write,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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},
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[0].endianness = DEVICE_LITTLE_ENDIAN,
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[1].endianness = DEVICE_BIG_ENDIAN,
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};
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static bool eth_can_rx(NetClientState *nc)
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{
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XlnxXpsEthLite *s = qemu_get_nic_opaque(nc);
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return !(s->port[s->port_index].reg.rx_ctrl & CTRL_S);
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}
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static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
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{
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XlnxXpsEthLite *s = qemu_get_nic_opaque(nc);
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unsigned int port_index = s->port_index;
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/* DA filter. */
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if (!(buf[0] & 0x80) && memcmp(&s->conf.macaddr.a[0], buf, 6))
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return size;
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if (s->port[port_index].reg.rx_ctrl & CTRL_S) {
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trace_ethlite_pkt_lost(s->port[port_index].reg.rx_ctrl);
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return -1;
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}
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if (size >= BUFSZ_MAX) {
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trace_ethlite_pkt_size_too_big(size);
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return -1;
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}
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memcpy(rxbuf_ptr(s, port_index), buf, size);
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s->port[port_index].reg.rx_ctrl |= CTRL_S;
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if (s->port[port_index].reg.rx_ctrl & CTRL_I) {
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eth_pulse_irq(s);
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}
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/* If c_rx_pingpong was set flip buffers. */
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s->port_index ^= s->c_rx_pingpong;
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return size;
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}
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static void xilinx_ethlite_reset(DeviceState *dev)
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{
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XlnxXpsEthLite *s = XILINX_ETHLITE(dev);
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s->port_index = 0;
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}
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static NetClientInfo net_xilinx_ethlite_info = {
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.type = NET_CLIENT_DRIVER_NIC,
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.size = sizeof(NICState),
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.can_receive = eth_can_rx,
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.receive = eth_rx,
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};
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static void xilinx_ethlite_realize(DeviceState *dev, Error **errp)
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{
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XlnxXpsEthLite *s = XILINX_ETHLITE(dev);
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unsigned ops_index;
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if (s->model_endianness == ENDIAN_MODE_UNSPECIFIED) {
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error_setg(errp, TYPE_XILINX_ETHLITE " property 'endianness'"
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" must be set to 'big' or 'little'");
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return;
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}
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ops_index = s->model_endianness == ENDIAN_MODE_BIG ? 1 : 0;
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memory_region_init(&s->container, OBJECT(dev),
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"xlnx.xps-ethernetlite", 0x2000);
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object_initialize_child(OBJECT(dev), "ethlite.reserved", &s->rsvd,
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TYPE_UNIMPLEMENTED_DEVICE);
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qdev_prop_set_string(DEVICE(&s->rsvd), "name", "ethlite.reserved");
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qdev_prop_set_uint64(DEVICE(&s->rsvd), "size",
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memory_region_size(&s->container));
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sysbus_realize(SYS_BUS_DEVICE(&s->rsvd), &error_fatal);
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memory_region_add_subregion_overlap(&s->container, 0,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rsvd), 0),
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-1);
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object_initialize_child(OBJECT(dev), "ethlite.mdio", &s->mdio,
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TYPE_UNIMPLEMENTED_DEVICE);
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qdev_prop_set_string(DEVICE(&s->mdio), "name", "ethlite.mdio");
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qdev_prop_set_uint64(DEVICE(&s->mdio), "size", 4 * 4);
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sysbus_realize(SYS_BUS_DEVICE(&s->mdio), &error_fatal);
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memory_region_add_subregion(&s->container, A_MDIO_BASE,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mdio), 0));
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for (unsigned i = 0; i < 2; i++) {
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memory_region_init_ram(&s->port[i].txbuf, OBJECT(dev),
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i ? "ethlite.tx[1]buf" : "ethlite.tx[0]buf",
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BUFSZ_MAX, &error_abort);
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memory_region_add_subregion(&s->container, 0x0800 * i, &s->port[i].txbuf);
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memory_region_init_io(&s->port[i].txio, OBJECT(dev),
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ð_porttx_ops[ops_index], s,
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i ? "ethlite.tx[1]io" : "ethlite.tx[0]io",
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4 * TX_MAX);
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memory_region_add_subregion(&s->container, i ? A_TX_BASE1 : A_TX_BASE0,
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&s->port[i].txio);
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memory_region_init_ram(&s->port[i].rxbuf, OBJECT(dev),
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i ? "ethlite.rx[1]buf" : "ethlite.rx[0]buf",
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BUFSZ_MAX, &error_abort);
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memory_region_add_subregion(&s->container, 0x1000 + 0x0800 * i,
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&s->port[i].rxbuf);
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memory_region_init_io(&s->port[i].rxio, OBJECT(dev),
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ð_portrx_ops[ops_index], s,
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i ? "ethlite.rx[1]io" : "ethlite.rx[0]io",
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4 * RX_MAX);
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memory_region_add_subregion(&s->container, i ? A_RX_BASE1 : A_RX_BASE0,
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&s->port[i].rxio);
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}
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qemu_macaddr_default_if_unset(&s->conf.macaddr);
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s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf,
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object_get_typename(OBJECT(dev)), dev->id,
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&dev->mem_reentrancy_guard, s);
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qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
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}
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static void xilinx_ethlite_init(Object *obj)
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{
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XlnxXpsEthLite *s = XILINX_ETHLITE(obj);
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sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container);
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}
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static const Property xilinx_ethlite_properties[] = {
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DEFINE_PROP_ENDIAN_NODEFAULT("endianness", XlnxXpsEthLite, model_endianness),
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DEFINE_PROP_UINT32("tx-ping-pong", XlnxXpsEthLite, c_tx_pingpong, 1),
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DEFINE_PROP_UINT32("rx-ping-pong", XlnxXpsEthLite, c_rx_pingpong, 1),
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DEFINE_NIC_PROPERTIES(XlnxXpsEthLite, conf),
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};
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static void xilinx_ethlite_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = xilinx_ethlite_realize;
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device_class_set_legacy_reset(dc, xilinx_ethlite_reset);
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device_class_set_props(dc, xilinx_ethlite_properties);
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}
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static const TypeInfo xilinx_ethlite_types[] = {
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{
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.name = TYPE_XILINX_ETHLITE,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(XlnxXpsEthLite),
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.instance_init = xilinx_ethlite_init,
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.class_init = xilinx_ethlite_class_init,
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},
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};
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DEFINE_TYPES(xilinx_ethlite_types)
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