286 lines
9.8 KiB
C
286 lines
9.8 KiB
C
/*
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* Common CPU TLB handling
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef CPUTLB_H
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#define CPUTLB_H
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#include "exec/cpu-common.h"
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#include "exec/hwaddr.h"
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#include "exec/memattrs.h"
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#include "exec/vaddr.h"
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#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
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void tlb_protect_code(ram_addr_t ram_addr);
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void tlb_unprotect_code(ram_addr_t ram_addr);
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#endif
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#ifndef CONFIG_USER_ONLY
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void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
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void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length);
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#endif
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/**
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* tlb_set_page_full:
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* @cpu: CPU context
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* @mmu_idx: mmu index of the tlb to modify
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* @addr: virtual address of the entry to add
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* @full: the details of the tlb entry
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*
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* Add an entry to @cpu tlb index @mmu_idx. All of the fields of
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* @full must be filled, except for xlat_section, and constitute
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* the complete description of the translated page.
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*
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* This is generally called by the target tlb_fill function after
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* having performed a successful page table walk to find the physical
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* address and attributes for the translation.
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*
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* At most one entry for a given virtual address is permitted. Only a
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* single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only
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* used by tlb_flush_page.
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*/
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void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr,
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CPUTLBEntryFull *full);
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/**
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* tlb_set_page_with_attrs:
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* @cpu: CPU to add this TLB entry for
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* @addr: virtual address of page to add entry for
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* @paddr: physical address of the page
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* @attrs: memory transaction attributes
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* @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits)
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* @mmu_idx: MMU index to insert TLB entry for
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* @size: size of the page in bytes
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*
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* Add an entry to this CPU's TLB (a mapping from virtual address
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* @addr to physical address @paddr) with the specified memory
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* transaction attributes. This is generally called by the target CPU
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* specific code after it has been called through the tlb_fill()
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* entry point and performed a successful page table walk to find
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* the physical address and attributes for the virtual address
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* which provoked the TLB miss.
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*
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* At most one entry for a given virtual address is permitted. Only a
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* single TARGET_PAGE_SIZE region is mapped; the supplied @size is only
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* used by tlb_flush_page.
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*/
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void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr,
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hwaddr paddr, MemTxAttrs attrs,
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int prot, int mmu_idx, vaddr size);
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/**
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* tlb_set_page:
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*
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* This function is equivalent to calling tlb_set_page_with_attrs()
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* with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided
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* as a convenience for CPUs which don't use memory transaction attributes.
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*/
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void tlb_set_page(CPUState *cpu, vaddr addr,
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hwaddr paddr, int prot,
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int mmu_idx, vaddr size);
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#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
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/**
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* tlb_flush_page:
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* @cpu: CPU whose TLB should be flushed
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* @addr: virtual address of page to be flushed
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*
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* Flush one page from the TLB of the specified CPU, for all
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* MMU indexes.
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*/
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void tlb_flush_page(CPUState *cpu, vaddr addr);
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/**
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* tlb_flush_page_all_cpus_synced:
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* @cpu: src CPU of the flush
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* @addr: virtual address of page to be flushed
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*
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* Flush one page from the TLB of all CPUs, for all
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* MMU indexes.
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*
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* When this function returns, no CPUs will subsequently perform
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* translations using the flushed TLBs.
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*/
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void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr);
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/**
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* tlb_flush:
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* @cpu: CPU whose TLB should be flushed
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*
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* Flush the entire TLB for the specified CPU. Most CPU architectures
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* allow the implementation to drop entries from the TLB at any time
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* so this is generally safe. If more selective flushing is required
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* use one of the other functions for efficiency.
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*/
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void tlb_flush(CPUState *cpu);
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/**
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* tlb_flush_all_cpus_synced:
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* @cpu: src CPU of the flush
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*
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* Flush the entire TLB for all CPUs, for all MMU indexes.
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*
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* When this function returns, no CPUs will subsequently perform
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* translations using the flushed TLBs.
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*/
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void tlb_flush_all_cpus_synced(CPUState *src_cpu);
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/**
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* tlb_flush_page_by_mmuidx:
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* @cpu: CPU whose TLB should be flushed
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* @addr: virtual address of page to be flushed
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* @idxmap: bitmap of MMU indexes to flush
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*
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* Flush one page from the TLB of the specified CPU, for the specified
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* MMU indexes.
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*/
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void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr,
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uint16_t idxmap);
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/**
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* tlb_flush_page_by_mmuidx_all_cpus_synced:
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* @cpu: Originating CPU of the flush
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* @addr: virtual address of page to be flushed
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* @idxmap: bitmap of MMU indexes to flush
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*
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* Flush one page from the TLB of all CPUs, for the specified
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* MMU indexes.
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*
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* When this function returns, no CPUs will subsequently perform
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* translations using the flushed TLBs.
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*/
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void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
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uint16_t idxmap);
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/**
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* tlb_flush_by_mmuidx:
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* @cpu: CPU whose TLB should be flushed
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* @wait: If true ensure synchronisation by exiting the cpu_loop
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* @idxmap: bitmap of MMU indexes to flush
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*
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* Flush all entries from the TLB of the specified CPU, for the specified
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* MMU indexes.
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*/
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void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap);
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/**
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* tlb_flush_by_mmuidx_all_cpus_synced:
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* @cpu: Originating CPU of the flush
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* @idxmap: bitmap of MMU indexes to flush
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*
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* Flush all entries from the TLB of all CPUs, for the specified
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* MMU indexes.
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*
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* When this function returns, no CPUs will subsequently perform
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* translations using the flushed TLBs.
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*/
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void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap);
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/**
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* tlb_flush_page_bits_by_mmuidx
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* @cpu: CPU whose TLB should be flushed
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* @addr: virtual address of page to be flushed
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* @idxmap: bitmap of mmu indexes to flush
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* @bits: number of significant bits in address
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*
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* Similar to tlb_flush_page_mask, but with a bitmap of indexes.
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*/
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void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr,
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uint16_t idxmap, unsigned bits);
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/* Similarly, with broadcast and syncing. */
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void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
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uint16_t idxmap,
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unsigned bits);
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/**
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* tlb_flush_range_by_mmuidx
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* @cpu: CPU whose TLB should be flushed
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* @addr: virtual address of the start of the range to be flushed
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* @len: length of range to be flushed
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* @idxmap: bitmap of mmu indexes to flush
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* @bits: number of significant bits in address
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*
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* For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len),
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* comparing only the low @bits worth of each virtual page.
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*/
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void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
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vaddr len, uint16_t idxmap,
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unsigned bits);
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/* Similarly, with broadcast and syncing. */
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void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
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vaddr addr,
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vaddr len,
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uint16_t idxmap,
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unsigned bits);
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#else
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static inline void tlb_flush_page(CPUState *cpu, vaddr addr)
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{
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}
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static inline void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr)
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{
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}
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static inline void tlb_flush(CPUState *cpu)
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{
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}
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static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu)
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{
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}
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static inline void tlb_flush_page_by_mmuidx(CPUState *cpu,
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vaddr addr, uint16_t idxmap)
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{
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}
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static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap)
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{
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}
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static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu,
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vaddr addr,
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uint16_t idxmap)
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{
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}
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static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
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uint16_t idxmap)
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{
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}
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static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu,
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vaddr addr,
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uint16_t idxmap,
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unsigned bits)
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{
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}
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static inline void
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tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
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uint16_t idxmap, unsigned bits)
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{
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}
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static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
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vaddr len, uint16_t idxmap,
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unsigned bits)
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{
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}
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static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
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vaddr addr,
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vaddr len,
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uint16_t idxmap,
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unsigned bits)
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{
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}
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#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
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#endif /* CPUTLB_H */
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