240 lines
8 KiB
C
240 lines
8 KiB
C
/*
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* internal execution defines for qemu
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef EXEC_ALL_H
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#define EXEC_ALL_H
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#include "cpu.h"
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#if defined(CONFIG_USER_ONLY)
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#include "exec/cpu_ldst.h"
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#endif
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#include "exec/mmu-access-type.h"
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#include "exec/translation-block.h"
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#if defined(CONFIG_TCG)
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#include "accel/tcg/getpc.h"
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/**
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* probe_access:
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* @env: CPUArchState
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* @addr: guest virtual address to look up
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* @size: size of the access
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* @access_type: read, write or execute permission
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* @mmu_idx: MMU index to use for lookup
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* @retaddr: return address for unwinding
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*
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* Look up the guest virtual address @addr. Raise an exception if the
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* page does not satisfy @access_type. Raise an exception if the
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* access (@addr, @size) hits a watchpoint. For writes, mark a clean
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* page as dirty.
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*
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* Finally, return the host address for a page that is backed by RAM,
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* or NULL if the page requires I/O.
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*/
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void *probe_access(CPUArchState *env, vaddr addr, int size,
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MMUAccessType access_type, int mmu_idx, uintptr_t retaddr);
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static inline void *probe_write(CPUArchState *env, vaddr addr, int size,
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int mmu_idx, uintptr_t retaddr)
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{
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return probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, retaddr);
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}
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static inline void *probe_read(CPUArchState *env, vaddr addr, int size,
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int mmu_idx, uintptr_t retaddr)
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{
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return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr);
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}
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/**
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* probe_access_flags:
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* @env: CPUArchState
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* @addr: guest virtual address to look up
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* @size: size of the access
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* @access_type: read, write or execute permission
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* @mmu_idx: MMU index to use for lookup
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* @nonfault: suppress the fault
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* @phost: return value for host address
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* @retaddr: return address for unwinding
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*
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* Similar to probe_access, loosely returning the TLB_FLAGS_MASK for
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* the page, and storing the host address for RAM in @phost.
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*
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* If @nonfault is set, do not raise an exception but return TLB_INVALID_MASK.
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* Do not handle watchpoints, but include TLB_WATCHPOINT in the returned flags.
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* Do handle clean pages, so exclude TLB_NOTDIRY from the returned flags.
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* For simplicity, all "mmio-like" flags are folded to TLB_MMIO.
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*/
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int probe_access_flags(CPUArchState *env, vaddr addr, int size,
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MMUAccessType access_type, int mmu_idx,
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bool nonfault, void **phost, uintptr_t retaddr);
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#ifndef CONFIG_USER_ONLY
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/**
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* probe_access_full:
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* Like probe_access_flags, except also return into @pfull.
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*
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* The CPUTLBEntryFull structure returned via @pfull is transient
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* and must be consumed or copied immediately, before any further
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* access or changes to TLB @mmu_idx.
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*
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* This function will not fault if @nonfault is set, but will
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* return TLB_INVALID_MASK if the page is not mapped, or is not
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* accessible with @access_type.
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*
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* This function will return TLB_MMIO in order to force the access
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* to be handled out-of-line if plugins wish to instrument the access.
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*/
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int probe_access_full(CPUArchState *env, vaddr addr, int size,
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MMUAccessType access_type, int mmu_idx,
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bool nonfault, void **phost,
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CPUTLBEntryFull **pfull, uintptr_t retaddr);
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/**
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* probe_access_full_mmu:
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* Like probe_access_full, except:
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*
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* This function is intended to be used for page table accesses by
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* the target mmu itself. Since such page walking happens while
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* handling another potential mmu fault, this function never raises
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* exceptions (akin to @nonfault true for probe_access_full).
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* Likewise this function does not trigger plugin instrumentation.
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*/
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int probe_access_full_mmu(CPUArchState *env, vaddr addr, int size,
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MMUAccessType access_type, int mmu_idx,
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void **phost, CPUTLBEntryFull **pfull);
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#endif /* !CONFIG_USER_ONLY */
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#endif /* CONFIG_TCG */
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static inline tb_page_addr_t tb_page_addr0(const TranslationBlock *tb)
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{
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#ifdef CONFIG_USER_ONLY
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return tb->itree.start;
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#else
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return tb->page_addr[0];
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#endif
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}
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static inline tb_page_addr_t tb_page_addr1(const TranslationBlock *tb)
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{
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#ifdef CONFIG_USER_ONLY
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tb_page_addr_t next = tb->itree.last & TARGET_PAGE_MASK;
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return next == (tb->itree.start & TARGET_PAGE_MASK) ? -1 : next;
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#else
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return tb->page_addr[1];
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#endif
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}
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static inline void tb_set_page_addr0(TranslationBlock *tb,
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tb_page_addr_t addr)
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{
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#ifdef CONFIG_USER_ONLY
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tb->itree.start = addr;
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/*
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* To begin, we record an interval of one byte. When the translation
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* loop encounters a second page, the interval will be extended to
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* include the first byte of the second page, which is sufficient to
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* allow tb_page_addr1() above to work properly. The final corrected
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* interval will be set by tb_page_add() from tb->size before the
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* node is added to the interval tree.
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*/
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tb->itree.last = addr;
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#else
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tb->page_addr[0] = addr;
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#endif
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}
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static inline void tb_set_page_addr1(TranslationBlock *tb,
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tb_page_addr_t addr)
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{
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#ifdef CONFIG_USER_ONLY
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/* Extend the interval to the first byte of the second page. See above. */
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tb->itree.last = addr;
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#else
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tb->page_addr[1] = addr;
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#endif
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}
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/* TranslationBlock invalidate API */
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void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
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void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t last);
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void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr);
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#if !defined(CONFIG_USER_ONLY)
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/**
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* iotlb_to_section:
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* @cpu: CPU performing the access
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* @index: TCG CPU IOTLB entry
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*
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* Given a TCG CPU IOTLB entry, return the MemoryRegionSection that
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* it refers to. @index will have been initially created and returned
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* by memory_region_section_get_iotlb().
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*/
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struct MemoryRegionSection *iotlb_to_section(CPUState *cpu,
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hwaddr index, MemTxAttrs attrs);
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#endif
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/**
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* get_page_addr_code_hostp()
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* @env: CPUArchState
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* @addr: guest virtual address of guest code
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*
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* See get_page_addr_code() (full-system version) for documentation on the
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* return value.
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*
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* Sets *@hostp (when @hostp is non-NULL) as follows.
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* If the return value is -1, sets *@hostp to NULL. Otherwise, sets *@hostp
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* to the host address where @addr's content is kept.
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*
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* Note: this function can trigger an exception.
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*/
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tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, vaddr addr,
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void **hostp);
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/**
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* get_page_addr_code()
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* @env: CPUArchState
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* @addr: guest virtual address of guest code
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*
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* If we cannot translate and execute from the entire RAM page, or if
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* the region is not backed by RAM, returns -1. Otherwise, returns the
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* ram_addr_t corresponding to the guest code at @addr.
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*
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* Note: this function can trigger an exception.
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*/
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static inline tb_page_addr_t get_page_addr_code(CPUArchState *env,
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vaddr addr)
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{
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return get_page_addr_code_hostp(env, addr, NULL);
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}
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#if !defined(CONFIG_USER_ONLY)
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MemoryRegionSection *
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address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
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hwaddr *xlat, hwaddr *plen,
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MemTxAttrs attrs, int *prot);
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hwaddr memory_region_section_get_iotlb(CPUState *cpu,
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MemoryRegionSection *section);
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#endif
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#endif
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