194 lines
5.3 KiB
C
194 lines
5.3 KiB
C
/* Memory layout and register descriptions for the TSUNAMI/TYPHOON chipset.
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Copyright (C) 2011 Richard Henderson
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This file is part of QEMU PALcode.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the text
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of the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING. If not see
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<http://www.gnu.org/licenses/>. */
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#ifndef TYPHOON_H
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#define TYPHOON_H 1
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/* Assume a 43-bit KSEG for now. */
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#define PIO_PHYS_ADDR 0x80000000000
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#define PIO_KSEG_ADDR (0xfffffc0000000000 + 0x10000000000)
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/* CCHIP REGISTERS */
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#define TYPHOON_CCHIP 0x1a0000000
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#define TYPHOON_CCHIP_CSC 0x0000
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#define TYPHOON_CCHIP_MTR 0x0040
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#define TYPHOON_CCHIP_MISC 0x0080
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#define TYPHOON_CCHIP_MPD 0x00c0
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#define TYPHOON_CCHIP_AAR0 0x0100
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#define TYPHOON_CCHIP_AAR1 0x0140
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#define TYPHOON_CCHIP_AAR2 0x0180
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#define TYPHOON_CCHIP_AAR3 0x01c0
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#define TYPHOON_CCHIP_DIM0 0x0200
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#define TYPHOON_CCHIP_DIM1 0x0240
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#define TYPHOON_CCHIP_DIR0 0x0280
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#define TYPHOON_CCHIP_DIR1 0x02c0
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#define TYPHOON_CCHIP_DRIR 0x0300
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#define TYPHOON_CCHIP_PRBEN 0x0340
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#define TYPHOON_CCHIP_IIC0 0x0380
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#define TYPHOON_CCHIP_IIC1 0x03c0
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#define TYPHOON_CCHIP_MPR0 0x0400
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#define TYPHOON_CCHIP_MPR1 0x0440
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#define TYPHOON_CCHIP_MPR2 0x0480
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#define TYPHOON_CCHIP_MPR3 0x04c0
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#define TYPHOON_CCHIP_TTR 0x0580
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#define TYPHOON_CCHIP_TDR 0x05c0
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#define TYPHOON_CCHIP_DIM2 0x0600
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#define TYPHOON_CCHIP_DIM3 0x0640
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#define TYPHOON_CCHIP_DIR2 0x0680
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#define TYPHOON_CCHIP_DIR3 0x06c0
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#define TYPHOON_CCHIP_IIC2 0x0700
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#define TYPHOON_CCHIP_IIC3 0x0740
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#define TYPHOON_CCHIP_PWR 0x0780
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#define TYPHOON_CCHIP_CMONCTLA 0x0c00
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#define TYPHOON_CCHIP_CMONCTLB 0x0c40
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#define TYPHOON_CCHIP_CMONCNT01 0x0c80
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#define TYPHOON_CCHIP_CMONCNT23 0x0cc0
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/* DCHIP REGISTERS */
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#define TYPHOON_DCHIP 0x1b0000000
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#define TYPHOON_DCHIP_DSC 0x0800
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#define TYPHOON_DCHIP_STR 0x0840
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#define TYPHOON_DCHIP_DREV 0x0880
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#define TYPHOON_DCHIP_DSC2 0x08c0
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/* PCHIP REGISTERS */
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#define TYPHOON_PCHIP0 0x180000000
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#define TYPHOON_PCHIP1 0x380000000
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#define TYPHOON_PCHIP_WSBA0 0x0000
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#define TYPHOON_PCHIP_WSBA1 0x0040
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#define TYPHOON_PCHIP_WSBA2 0x0080
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#define TYPHOON_PCHIP_WSBA3 0x00c0
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#define TYPHOON_PCHIP_WSM0 0x0100
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#define TYPHOON_PCHIP_WSM1 0x0140
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#define TYPHOON_PCHIP_WSM2 0x0180
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#define TYPHOON_PCHIP_WSM3 0x01c0
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#define TYPHOON_PCHIP_TBA0 0x0200
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#define TYPHOON_PCHIP_TBA1 0x0240
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#define TYPHOON_PCHIP_TBA2 0x0280
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#define TYPHOON_PCHIP_TBA3 0x02c0
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#define TYPHOON_PCHIP_PCTL 0x0300
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#define TYPHOON_PCHIP_PLAT 0x0340
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#define TYPHOON_PCHIP_PERROR 0x03c0
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#define TYPHOON_PCHIP_PERRMASK 0x0400
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#define TYPHOON_PCHIP_PERRSET 0x0440
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#define TYPHOON_PCHIP_TLBIV 0x0480
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#define TYPHOON_PCHIP_TLBIA 0x04c0
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#define TYPHOON_PCHIP_PMONCTL 0x0500
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#define TYPHOON_PCHIP_PMONCNT 0x0540
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#define TYPHOON_PCHIP_SPRST 0x0800
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/* PCI ADDRESSES */
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#define TYPHOON_PCHIP0_PCI_MEM 0
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#define TYPHOON_PCHIP0_PCI_IO 0x1fc000000
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#define TYPHOON_PCHIP0_PCI_CONF 0x1fe000000
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#define TYPHOON_PCHIP0_PCI_IACK 0x1f8000000
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#ifdef __ASSEMBLER__
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#include "pal.h"
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#define ptCpuDIR ptSys0
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#define ptCpuIIC ptSys1
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/* Unfortunately, GAS doesn't attempt any interesting constructions of
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64-bit constants, dropping them all into the .lit8 section. It is
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better for us to build these by hand. */
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.macro LOAD_PHYS_CCHIP ret
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lda \ret, (PIO_PHYS_ADDR + TYPHOON_CCHIP) >> 29
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sll \ret, 29, \ret
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.endm
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.macro LOAD_PHYS_PCHIP0 ret
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lda \ret, (PIO_PHYS_ADDR + TYPHOON_PCHIP0) >> 29
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sll \ret, 29, \ret
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.endm
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.macro LOAD_PHYS_PCHIP0_IACK ret
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.set macro
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lda \ret, (PIO_PHYS_ADDR + TYPHOON_PCHIP0_PCI_IACK) >> 24
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.set nomacro
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sll \ret, 24, \ret
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.endm
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.macro LOAD_KSEG_PCI_IO ret
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.set macro
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// Note that GAS shifts are logical. Force arithmetic shift style
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// results by negating before and after the shift.
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lda \ret, -(-(PIO_KSEG_ADDR + TYPHOON_PCHIP0_PCI_IO) >> 20)
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.set nomacro
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sll \ret, 20, \ret
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.endm
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.macro LOAD_KSEG_PCI_CONF ret
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.set macro
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// Note that GAS shifts are logical. Force arithmetic shift style
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// results by negating before and after the shift.
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lda \ret, -(-(PIO_KSEG_ADDR + TYPHOON_PCHIP0_PCI_CONF) >> 20)
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.set nomacro
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sll \ret, 20, \ret
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.endm
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.macro SYS_WHAMI ret
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LOAD_PHYS_CCHIP \ret
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ldq_p \ret, TYPHOON_CCHIP_MISC(\ret)
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and \ret, 3, \ret
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.endm
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/* ACK the Interprocessor Interrupt. */
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.macro SYS_ACK_SMP t0, t1, t2
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LOAD_PHYS_CCHIP \t0
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ldq_p \t1, TYPHOON_CCHIP_MISC(\t0)
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and \t1, 3, \t1
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addq \t1, 8, \t1
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lda \t2, 1
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sll \t2, \t1, \t2
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stq_p \t2, TYPHOON_CCHIP_MISC(\t0)
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.endm
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/* ACK the Clock Interrupt. */
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.macro SYS_ACK_CLK t0, t1, t2
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LOAD_PHYS_CCHIP \t0
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ldq_p \t1, TYPHOON_CCHIP_MISC(\t0)
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and \t1, 3, \t1
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addq \t1, 4, \t1
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lda \t2, 1
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sll \t2, \t1, \t2
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stq_p \t2, TYPHOON_CCHIP_MISC(\t0)
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.endm
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/* Interrupt another CPU. */
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.macro SYS_WRIPIR target, t0, t1, t2
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LOAD_PHYS_CCHIP \t0
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mov 1, \t1
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and \target, 3, \t2
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addq \t2, 12, \t2
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sll \t1, \t2, \t1
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stq_p \t1, TYPHOON_CCHIP_MISC(\t0)
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.endm
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#endif /* ASSEMBLER */
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#endif /* TYPHOON_H */
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