135 lines
3.7 KiB
C
135 lines
3.7 KiB
C
// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
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/*
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* Deal with PCI device quirks
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*
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* Copyright 2017-2018 IBM Corp.
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*/
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#define pr_fmt(fmt) "PCI-QUIRK: " fmt
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#include <skiboot.h>
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#include <pci.h>
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#include <pci-cfg.h>
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#include <pci-quirk.h>
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#include <platform.h>
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#include <ast.h>
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static int64_t cfg_block_filter(void *dev __unused,
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struct pci_cfg_reg_filter *pcrf __unused,
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uint32_t offset __unused, uint32_t len,
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uint32_t *data, bool write)
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{
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if (write)
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return OPAL_SUCCESS;
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switch (len) {
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case 4:
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*data = 0x0;
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return OPAL_SUCCESS;
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case 2:
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*((uint16_t *)data) = 0x0;
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return OPAL_SUCCESS;
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case 1:
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*((uint8_t *)data) = 0x0;
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return OPAL_SUCCESS;
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}
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return OPAL_PARAMETER; /* should never happen */
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}
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/* blocks config accesses to registers in the range: [start, end] */
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#define BLOCK_CFG_RANGE(pd, start, end) \
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pci_add_cfg_reg_filter(pd, start, end - start + 1, \
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PCI_REG_FLAG_WRITE | PCI_REG_FLAG_READ, \
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cfg_block_filter);
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static void quirk_microsemi_gen4_sw(struct phb *phb, struct pci_device *pd)
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{
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uint8_t data;
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bool frozen;
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int offset;
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int start;
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pci_check_clear_freeze(phb);
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/*
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* Reading from 0xff should trigger a UR on the affected switches.
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* If we don't get a freeze then we don't need the workaround
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*/
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pci_cfg_read8(phb, pd->bdfn, 0xff, &data);
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frozen = pci_check_clear_freeze(phb);
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if (!frozen)
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return;
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for (start = -1, offset = 0; offset < 4096; offset++) {
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pci_cfg_read8(phb, pd->bdfn, offset, &data);
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frozen = pci_check_clear_freeze(phb);
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if (start < 0 && frozen) { /* new UR range */
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start = offset;
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} else if (start >= 0 && !frozen) { /* end of range */
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BLOCK_CFG_RANGE(pd, start, offset - 1);
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PCINOTICE(phb, pd->bdfn, "Applied UR workaround to [%03x..%03x]\n", start, offset - 1);
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start = -1;
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}
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}
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/* range lasted until the end of config space */
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if (start >= 0) {
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BLOCK_CFG_RANGE(pd, start, 0xfff);
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PCINOTICE(phb, pd->bdfn, "Applied UR workaround to [%03x..fff]\n", start);
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}
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}
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static void quirk_astbmc_vga(struct phb *phb __unused,
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struct pci_device *pd)
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{
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struct dt_node *np = pd->dn;
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uint32_t revision, mcr_configuration, mcr_scu_mpll, mcr_scu_strap;
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if (ast_sio_is_enabled()) {
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revision = ast_ahb_readl(SCU_REVISION_ID);
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mcr_configuration = ast_ahb_readl(MCR_CONFIGURATION);
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mcr_scu_mpll = ast_ahb_readl(MCR_SCU_MPLL);
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mcr_scu_strap = ast_ahb_readl(MCR_SCU_STRAP);
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} else {
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/* Previously we would warn, now SIO disabled by design */
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prlog(PR_INFO, "Assumed platform default parameters for %s\n",
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__func__);
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revision = bmc_platform->hw->scu_revision_id;
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mcr_configuration = bmc_platform->hw->mcr_configuration;
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mcr_scu_mpll = bmc_platform->hw->mcr_scu_mpll;
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mcr_scu_strap = bmc_platform->hw->mcr_scu_strap;
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}
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dt_add_property_cells(np, "aspeed,scu-revision-id", revision);
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dt_add_property_cells(np, "aspeed,mcr-configuration", mcr_configuration);
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dt_add_property_cells(np, "aspeed,mcr-scu-mpll", mcr_scu_mpll);
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dt_add_property_cells(np, "aspeed,mcr-scu-strap", mcr_scu_strap);
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}
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/* Quirks are: {fixup function, vendor ID, (device ID or PCI_ANY_ID)} */
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static const struct pci_quirk quirk_table[] = {
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/* ASPEED 2400 VGA device */
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{ 0x1a03, 0x2000, &quirk_astbmc_vga },
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{ 0x11f8, 0x4052, &quirk_microsemi_gen4_sw },
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{ 0, 0, NULL }
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};
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static void __pci_handle_quirk(struct phb *phb, struct pci_device *pd,
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const struct pci_quirk *quirks)
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{
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while (quirks->vendor_id) {
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if (quirks->vendor_id == PCI_VENDOR_ID(pd->vdid) &&
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(quirks->device_id == PCI_ANY_ID ||
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quirks->device_id == PCI_DEVICE_ID(pd->vdid)))
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quirks->fixup(phb, pd);
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quirks++;
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}
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}
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void pci_handle_quirk(struct phb *phb, struct pci_device *pd)
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{
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__pci_handle_quirk(phb, pd, quirk_table);
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}
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