149 lines
4.9 KiB
C
149 lines
4.9 KiB
C
// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
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/* Copyright 2013-2019 IBM Corp. */
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#ifndef __MEM_MAP_H
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#define __MEM_MAP_H
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/* This is our main offset for relocation. All our buffers
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* are offset from that and our code relocates itself to
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* that location
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*/
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#define SKIBOOT_BASE 0x30000000
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/* Stack size set to 32K, 16K for general stack and 16K for an emergency
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* stack.
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*/
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#define STACK_SHIFT 15
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#define STACK_SIZE (1 << STACK_SHIFT)
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/* End of the exception region we copy from 0x0. 0x0-0x100 will have
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* IPL data and is not actually for exception vectors.
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*/
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#define EXCEPTION_VECTORS_END 0x3000
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#define NACA_OFF 0x4000
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/* The NACA and other stuff in head.S need to be at the start: we
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* give it 64k before placing the SPIRA and related data.
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*/
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#define SPIRAH_OFF 0x00010000
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#define SPIRAH_SIZE 0x300
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#define PROC_DUMP_AREA_OFF (SPIRAH_OFF + SPIRAH_SIZE)
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#define PROC_DUMP_AREA_SIZE 0x100
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/*
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* SPIRA-H is lesser than 768 bytes (presently we use 288 bytes)
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* Use 768 bytes for SPIRAH.
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*
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* Use 256 bytes for processor dump area. (presently we use
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* sizeof(proc_dump_area) = 0x30 bytes).
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*
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* Then follow with for proc_init_data (aka PROCIN).
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* These need to be at fixed addresses in case we're ever little
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* endian: linker can't endian reverse a pointer for us. Text, data
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* et. al. follows this.
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*/
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#define PROCIN_OFF (PROC_DUMP_AREA_OFF + PROC_DUMP_AREA_SIZE)
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#define PROCIN_SIZE 0x800
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/* Initial MDST and MDDT tables like PROCIN, we need fixed addresses,
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* we leave a 2k gap for PROCIN
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*/
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#define MDST_TABLE_OFF (PROCIN_OFF + PROCIN_SIZE)
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#define MDST_TABLE_SIZE 0x400
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#define MDDT_TABLE_OFF (MDST_TABLE_OFF + MDST_TABLE_SIZE)
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#define MDDT_TABLE_SIZE 0x400
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/* Like MDST and MDDT, we need fixed address for CPU control header.
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* We leave a 2k gap for MDST. CPU_CTL table is of size ~4k, give it 8k.
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*/
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#define CPU_CTL_OFF (MDDT_TABLE_OFF + MDDT_TABLE_SIZE)
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#define CPU_CTL_SIZE 0x2000
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/* We keep a gap of 5M for skiboot text & bss for now. We will
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* then we have our heap which goes up to base + 14M (so 11M for
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* now, though we can certainly reduce that a lot).
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*
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* Ideally, we should fix the heap end and use _end to basically
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* initialize our heap so that it covers anything from _end to
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* that heap end, avoiding wasted space.
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*
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* That's made a bit tricky however due to how we create those
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* regions statically in mem_region.c, but still on the list of
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* things to improve.
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*
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* As of A Long Time Ago (2014/4/6), we used approc 512K for skiboot
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* core and 2M of heap on a 1 socket machine.
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*
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* As of still a Long Time Ago (2015/5/7) we used approx 800k for skiboot,
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* 500k HEAP for mambo boot.
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*
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* As of mid-2019, a 2 socket Romulus uses ~4MB heap.
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*/
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#define HEAP_BASE (SKIBOOT_BASE + 0x00600000)
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#define HEAP_SIZE 0x00a00000
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/* This is the location of our console buffer at base + 16M */
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#define INMEM_CON_START (SKIBOOT_BASE + 0x01000000)
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#define INMEM_CON_LEN 0x100000
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/* This is the location of HBRT console buffer at base + 17M */
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#define HBRT_CON_START (SKIBOOT_BASE + 0x01100000)
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#define HBRT_CON_LEN 0x100000
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/* Tell FSP to put the init data at base + 20M, allocate 8M */
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#define SPIRA_HEAP_BASE (SKIBOOT_BASE + 0x01200000)
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#define SPIRA_HEAP_SIZE 0x00800000
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/* This is our PSI TCE table. It's 256K entries on P8 */
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#define PSI_TCE_TABLE_BASE (SKIBOOT_BASE + 0x01a00000)
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#define PSI_TCE_TABLE_SIZE 0x00200000UL
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/* This is our dump result table after MPIPL. Hostboot will write to this
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* memory after moving memory content from source to destination memory.
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*/
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#define MDRT_TABLE_BASE (SKIBOOT_BASE + 0x01c00000)
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#define MDRT_TABLE_SIZE 0x00008000
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/* This is our dump metadata area. We will use this memory to save metadata
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* (like crashing CPU details, payload tags) before triggering MPIPL.
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*/
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#define DUMP_METADATA_AREA_BASE (SKIBOOT_BASE + 0x01c08000)
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#define DUMP_METADATA_AREA_SIZE 0x8000
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/* Total size of the above area
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*
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* (Ensure this has at least a 64k alignment)
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*/
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#define SKIBOOT_SIZE 0x01c10000
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/* We start laying out the CPU stacks from here, indexed by PIR
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* each stack is STACK_SIZE in size (naturally aligned power of
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* two) and the bottom of the stack contains the cpu thread
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* structure for the processor, so it can be obtained by a simple
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* bit mask from the stack pointer. Within the CPU stack is divided
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* into a normal and emergency stack to cope with a single level of
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* re-entrancy.
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*
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* The size of this array is dynamically determined at boot time
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*/
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#define CPU_STACKS_BASE (SKIBOOT_BASE + SKIBOOT_SIZE)
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/*
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* Address at which we load the kernel LID. This is also where
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* we expect a passed-in kernel if booting without FSP and
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* without a built-in kernel.
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*/
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#define KERNEL_LOAD_BASE ((void *)0x20000000)
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#define KERNEL_LOAD_SIZE 0x08000000
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#define INITRAMFS_LOAD_BASE KERNEL_LOAD_BASE + KERNEL_LOAD_SIZE
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#define INITRAMFS_LOAD_SIZE 0x08000000
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/* Size allocated to build the device-tree */
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#define DEVICE_TREE_MAX_SIZE 0x80000
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#endif /* __MEM_MAP_H */
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