72 lines
2.3 KiB
C
72 lines
2.3 KiB
C
// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
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/* Copyright 2013-2016 IBM Corp. */
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#ifndef __PCI_VIRT_H
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#define __PCI_VIRT_H
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#include <ccan/list/list.h>
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enum {
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PCI_VIRT_CFG_NORMAL,
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PCI_VIRT_CFG_RDONLY,
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PCI_VIRT_CFG_W1CLR,
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PCI_VIRT_CFG_MAX
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};
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struct pci_virt_device {
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uint32_t bdfn;
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uint32_t cfg_size;
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uint8_t *config[PCI_VIRT_CFG_MAX];
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struct list_head pcrf;
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struct list_node node;
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void *data;
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};
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extern void pci_virt_cfg_read_raw(struct pci_virt_device *pvd,
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uint32_t space, uint32_t offset,
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uint32_t size, uint32_t *data);
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extern void pci_virt_cfg_write_raw(struct pci_virt_device *pvd,
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uint32_t space, uint32_t offset,
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uint32_t size, uint32_t data);
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extern struct pci_cfg_reg_filter *pci_virt_add_filter(
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struct pci_virt_device *pvd,
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uint32_t start, uint32_t len,
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uint32_t flags, pci_cfg_reg_func func,
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void *data);
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extern int64_t pci_virt_cfg_read(struct phb *phb, uint32_t bdfn,
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uint32_t offset, uint32_t size,
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uint32_t *data);
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extern int64_t pci_virt_cfg_write(struct phb *phb, uint32_t bdfn,
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uint32_t offset, uint32_t size,
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uint32_t data);
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extern struct pci_virt_device *pci_virt_find_device(struct phb *phb,
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uint32_t bdfn);
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extern struct pci_virt_device *pci_virt_add_device(struct phb *phb,
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uint32_t bdfn,
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uint32_t cfg_size,
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void *data);
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/* Config space accessors */
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#define PCI_VIRT_CFG_NORMAL_RD(d, o, s, v) \
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pci_virt_cfg_read_raw(d, PCI_VIRT_CFG_NORMAL, o, s, v)
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#define PCI_VIRT_CFG_NORMAL_WR(d, o, s, v) \
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pci_virt_cfg_write_raw(d, PCI_VIRT_CFG_NORMAL, o, s, v)
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#define PCI_VIRT_CFG_RDONLY_RD(d, o, s, v) \
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pci_virt_cfg_read_raw(d, PCI_VIRT_CFG_RDONLY, o, s, v)
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#define PCI_VIRT_CFG_RDONLY_WR(d, o, s, v) \
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pci_virt_cfg_write_raw(d, PCI_VIRT_CFG_RDONLY, o, s, v)
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#define PCI_VIRT_CFG_W1CLR_RD(d, o, s, v) \
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pci_virt_cfg_read_raw(d, PCI_VIRT_CFG_W1CLR, o, s, v)
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#define PCI_VIRT_CFG_W1CLR_WR(d, o, s, v) \
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pci_virt_cfg_write_raw(d, PCI_VIRT_CFG_W1CLR, o, s, v)
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#define PCI_VIRT_CFG_INIT(d, o, s, v, r, w) \
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do { \
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PCI_VIRT_CFG_NORMAL_WR(d, o, s, v); \
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PCI_VIRT_CFG_RDONLY_WR(d, o, s, r); \
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PCI_VIRT_CFG_W1CLR_WR(d, o, s, w); \
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} while (0)
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#define PCI_VIRT_CFG_INIT_RO(d, o, s, v) \
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PCI_VIRT_CFG_INIT(d, o, s, v, 0xffffffff, 0)
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#endif /* __VIRT_PCI_H */
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