256 lines
8.7 KiB
C
256 lines
8.7 KiB
C
// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
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/*
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* IBM System P PSI (Processor Service Interface)
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*
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* Copyright 2013-2019 IBM Corp.
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*/
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#ifndef __PSI_H
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#define __PSI_H
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#include <skiboot.h>
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/*
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* PSI Host Bridge Registers (MMIO)
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*
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* The PSI interface is the bridge to the FPS, it has its own
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* registers. The FSP registers appear at an offset within the
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* aperture defined by the PSI_FSPBAR
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*/
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/* Base address of the PSI MMIO space and LSB is the enable/valid bit */
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#define PSIHB_BBAR 0x00
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/* FSP MMIO region -- this is where the mbx regs are (offset defined below) */
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#define PSIHB_FSPBAR 0x08
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/* FSP MMIO region mask register -- determines size of region */
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#define PSIHB_FSPMMR 0x10
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/* TCE address register */
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#define PSIHB_TAR 0x18
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#define PSIHB_TAR_8K_ENTRIES 0
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#define PSIHB_TAR_16K_ENTRIES 1
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#define PSIHB_TAR_256K_ENTRIES 2 /* P8 only */
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#define PSIHB_TAR_512K_ENTRIES 4 /* P8 only */
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/* PSI Host Bridge Control Register */
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#define PSIHB_CR 0x20
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#define PSIHB_CR_FSP_CMD_ENABLE PPC_BIT(0)
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#define PSIHB_CR_FSP_MMIO_ENABLE PPC_BIT(1)
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#define PSIHB_CR_FSP_IRQ_ENABLE PPC_BIT(3)
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#define PSIHB_CR_FSP_ERR_RSP_ENABLE PPC_BIT(4)
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#define PSIHB_CR_PSI_LINK_ENABLE PPC_BIT(5)
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#define PSIHB_CR_FSP_RESET PPC_BIT(6)
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#define PSIHB_CR_PSIHB_RESET PPC_BIT(7)
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#define PSIHB10_CR_STORE_EOI PPC_BIT(12)
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#define PSIHB_CR_PSI_IRQ PPC_BIT(16) /* PSIHB interrupt */
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#define PSIHB_CR_FSP_IRQ PPC_BIT(17) /* FSP interrupt */
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#define PSIHB_CR_FSP_LINK_ACTIVE PPC_BIT(18) /* FSP link active */
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/* Error conditions in the GXHB */
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#define PSIHB_CR_PSI_ERROR PPC_BIT(32) /* PSI error */
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#define PSIHB_CR_PSI_LINK_INACTIVE PPC_BIT(33) /* Link inactive */
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#define PSIHB_CR_FSP_ACK_TIMEOUT PPC_BIT(34) /* FSP ack timeout */
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#define PSIHB_CR_MMIO_LOAD_TIMEOUT PPC_BIT(35) /* MMIO load timeout */
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#define PSIHB_CR_MMIO_LENGTH_ERROR PPC_BIT(36) /* MMIO length error */
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#define PSIHB_CR_MMIO_ADDRESS_ERROR PPC_BIT(37) /* MMIO address error */
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#define PSIHB_CR_MMIO_TYPE_ERROR PPC_BIT(38) /* MMIO type error */
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#define PSIHB_CR_UE PPC_BIT(39) /* UE detected */
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#define PSIHB_CR_PARITY_ERROR PPC_BIT(40) /* Parity error */
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#define PSIHB_CR_SYNC_ERR_ALERT1 PPC_BIT(41) /* Sync alert 1 */
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#define PSIHB_CR_SYNC_ERR_ALERT2 PPC_BIT(42) /* Sync alert 2 */
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#define PSIHB_CR_FSP_COMMAND_ERROR PPC_BIT(43) /* FSP cmd error */
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/* PSI Status / Error Mask Register */
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#define PSIHB_SEMR 0x28
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/* XIVR and BUID used for PSI interrupts on P8 */
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#define PSIHB_XIVR_FSP 0x30
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#define PSIHB_XIVR_OCC 0x60
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#define PSIHB_XIVR_FSI 0x68
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#define PSIHB_XIVR_LPC 0x70
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#define PSIHB_XIVR_LOCAL_ERR 0x78
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#define PSIHB_XIVR_HOST_ERR 0x80
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#define PSIHB_IRSN 0x88
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#define PSIHB_IRSN_COMP PPC_BITMASK(0,18)
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#define PSIHB_IRSN_IRQ_MUX PPC_BIT(28)
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#define PSIHB_IRSN_IRQ_RESET PPC_BIT(29)
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#define PSIHB_IRSN_DOWNSTREAM_EN PPC_BIT(30)
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#define PSIHB_IRSN_UPSTREAM_EN PPC_BIT(31)
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#define PSIHB_IRSN_MASK PPC_BITMASK(32,50)
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#define PSIHB_IRQ_STATUS 0x58
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#define PSIHB_IRQ_STAT_OCC PPC_BIT(27)
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#define PSIHB_IRQ_STAT_FSI PPC_BIT(28)
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#define PSIHB_IRQ_STAT_LPC PPC_BIT(29)
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#define PSIHB_IRQ_STAT_LOCAL_ERR PPC_BIT(30)
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#define PSIHB_IRQ_STAT_HOST_ERR PPC_BIT(31)
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/* Secure version of CR for P8 and P9 (TCE enable bit) */
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#define PSIHB_PHBSCR 0x90
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#define PSIHB_PHBSCR_TCE_ENABLE PPC_BIT(2)
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/* P9 registers */
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#define PSIHB_INTERRUPT_CONTROL 0x58
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#define PSIHB_IRQ_METHOD PPC_BIT(0)
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#define PSIHB_IRQ_RESET PPC_BIT(1)
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#define PSIHB_ESB_CI_BASE 0x60
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#define PSIHB10_ESB_CI_64K PPC_BIT(1)
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#define PSIHB_ESB_CI_VALID PPC_BIT(63)
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#define PSIHB_ESB_NOTIF_ADDR 0x68
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#define PSIHB_ESB_NOTIF_VALID PPC_BIT(63)
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#define PSIHB_IVT_OFFSET 0x70
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#define PSIHB_IVT_OFF_SHIFT 32
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/*
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* PSI Host Bridge Registers (XSCOM)
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*/
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#define PSIHB_XSCOM_P8_BASE 0xa
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#define PSIHB_XSCOM_P8_HBBAR_EN PPC_BIT(63)
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#define PSIHB_XSCOM_P8_HBCSR 0xe
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#define PSIHB_XSCOM_P8_HBCSR_SET 0x12
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#define PSIHB_XSCOM_P8_HBCSR_CLR 0x13
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#define PSIHB_XSCOM_P8_HBSCR_FSP_IRQ PPC_BIT(17)
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#define PSIHB_XSCOM_P9_BASE 0xa
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#define PSIHB_XSCOM_P9_HBBAR_EN PPC_BIT(63)
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#define PSIHB_XSCOM_P9_HBCSR 0xe
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#define PSIHB_XSCOM_P9_HBCSR_SET 0x12
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#define PSIHB_XSCOM_P9_HBCSR_CLR 0x13
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#define PSIHB_XSCOM_P9_HBSCR_FSP_IRQ PPC_BIT(17)
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#define PSIHB_XSCOM_P10_BASE 0xa
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#define PSIHB_XSCOM_P10_HBBAR_EN PPC_BIT(63)
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#define PSIHB_XSCOM_P10_HBCSR 0xe
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#define PSIHB_XSCOM_P10_HBCSR_SET 0x12
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#define PSIHB_XSCOM_P10_HBCSR_CLR 0x13
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#define PSIHB_XSCOM_P10_HBSCR_FSP_IRQ PPC_BIT(17)
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/* P9 PSI Interrupts */
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#define P9_PSI_IRQ_PSI 0
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#define P9_PSI_IRQ_OCC 1
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#define P9_PSI_IRQ_FSI 2
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#define P9_PSI_IRQ_LPCHC 3
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#define P9_PSI_IRQ_LOCAL_ERR 4
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#define P9_PSI_IRQ_GLOBAL_ERR 5
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#define P9_PSI_IRQ_EXTERNAL 6
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#define P9_PSI_IRQ_LPC_SIRQ0 7
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#define P9_PSI_IRQ_LPC_SIRQ1 8
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#define P9_PSI_IRQ_LPC_SIRQ2 9
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#define P9_PSI_IRQ_LPC_SIRQ3 10
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#define P9_PSI_IRQ_SBE_I2C 11
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#define P9_PSI_IRQ_DIO 12
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#define P9_PSI_IRQ_PSU 13
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#define P9_PSI_NUM_IRQS 14
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/*
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* Layout of the PSI DMA address space
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*
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* We use a larger mapping of 256K TCEs which provides us with a 1G window in
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* order to fit the trace buffers
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*
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* Currently we have:
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*
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* - 4x256K serial areas (each divided in 2: in and out buffers)
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* - 1M region for inbound buffers
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* - 2M region for generic data fetches
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*/
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#define PSI_DMA_SER0_BASE 0x00000000
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#define PSI_DMA_SER0_SIZE 0x00040000
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#define PSI_DMA_SER1_BASE 0x00040000
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#define PSI_DMA_SER1_SIZE 0x00040000
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#define PSI_DMA_SER2_BASE 0x00080000
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#define PSI_DMA_SER2_SIZE 0x00040000
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#define PSI_DMA_SER3_BASE 0x000c0000
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#define PSI_DMA_SER3_SIZE 0x00040000
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#define PSI_DMA_INBOUND_BUF 0x00100000
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#define PSI_DMA_INBOUND_SIZE 0x00100000
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#define PSI_DMA_FETCH 0x00200000
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#define PSI_DMA_FETCH_SIZE 0x00800000
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#define PSI_DMA_NVRAM_BODY 0x00a00000
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#define PSI_DMA_NVRAM_BODY_SZ 0x00100000
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#define PSI_DMA_NVRAM_TRIPL 0x00b00000
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#define PSI_DMA_NVRAM_TRIPL_SZ 0x00001000
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#define PSI_DMA_OP_PANEL_MISC 0x00b01000
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#define PSI_DMA_OP_PANEL_SIZE 0x00001000
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#define PSI_DMA_GET_SYSPARAM 0x00b02000
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#define PSI_DMA_GET_SYSPARAM_SZ 0x00001000
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#define PSI_DMA_SET_SYSPARAM 0x00b03000
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#define PSI_DMA_SET_SYSPARAM_SZ 0x00001000
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#define PSI_DMA_ERRLOG_READ_BUF 0x00b04000
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#define PSI_DMA_ERRLOG_READ_BUF_SZ 0x00040000
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#define PSI_DMA_ELOG_PANIC_WRITE_BUF 0x00b44000
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#define PSI_DMA_ELOG_PANIC_WRITE_BUF_SZ 0x00010000
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#define PSI_DMA_ERRLOG_WRITE_BUF 0x00b54000
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#define PSI_DMA_ERRLOG_WRITE_BUF_SZ 0x00040000
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#define PSI_DMA_ELOG_WR_TO_HOST_BUF 0x00b94000 /* Unused */
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#define PSI_DMA_ELOG_WR_TO_HOST_BUF_SZ 0x00010000
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#define PSI_DMA_HBRT_LOG_WRITE_BUF 0x00ba4000
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#define PSI_DMA_HBRT_LOG_WRITE_BUF_SZ 0x00001000
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#define PSI_DMA_CODE_UPD 0x00c04000
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#define PSI_DMA_CODE_UPD_SIZE 0x01001000
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#define PSI_DMA_DUMP_DATA 0x01c05000
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#define PSI_DMA_DUMP_DATA_SIZE 0x00500000
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#define PSI_DMA_SENSOR_BUF 0x02105000
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#define PSI_DMA_SENSOR_BUF_SZ 0x00080000
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#define PSI_DMA_MDST_TABLE 0x02185000
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#define PSI_DMA_MDST_TABLE_SIZE 0x00001000
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#define PSI_DMA_HYP_DUMP 0x02186000
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#define PSI_DMA_HYP_DUMP_SIZE 0x01000000
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#define PSI_DMA_PCIE_INVENTORY 0x03186000
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#define PSI_DMA_PCIE_INVENTORY_SIZE 0x00010000
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#define PSI_DMA_LED_BUF 0x03196000
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#define PSI_DMA_LED_BUF_SZ 0x00001000
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#define PSI_DMA_LOC_COD_BUF 0x03197000
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#define PSI_DMA_LOC_COD_BUF_SZ 0x00008000
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#define PSI_DMA_MEMCONS 0x0319f000
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#define PSI_DMA_MEMCONS_SZ 0x00001000
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#define PSI_DMA_LOG_BUF 0x03200000
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#define PSI_DMA_LOG_BUF_SZ 0x00100000 /* INMEM_CON_LEN */
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#define PSI_DMA_PLAT_REQ_BUF 0x03300000
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#define PSI_DMA_PLAT_REQ_BUF_SIZE 0x00001000
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#define PSI_DMA_PLAT_RESP_BUF 0x03301000
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#define PSI_DMA_PLAT_RESP_BUF_SIZE 0x00001000
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/*
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* Our PRD interface can handle upto 64KB data transfer between
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* OPAL - opal-prd. Hence adding TCE size as 68KB. If we increase
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* OPAL - opal-prd message size, then we have to fix this.
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*/
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#define PSI_DMA_HBRT_FSP_MSG 0x03302000
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#define PSI_DMA_HBRT_FSP_MSG_SIZE 0x00011000
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#define PSI_DMA_TRACE_BASE 0x04000000
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struct psi {
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struct list_node list;
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uint64_t xscom_base;
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void *regs;
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void *esb_mmio;
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unsigned int chip_id;
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unsigned int interrupt;
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bool active;
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bool no_lpc_irqs;
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struct dt_node *node;
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};
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extern void psi_set_link_polling(bool active);
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extern struct psi *first_psi;
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extern void psi_init(void);
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extern struct psi *psi_find_link(uint32_t chip_id);
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extern void psi_init_for_fsp(struct psi *psi);
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extern void psi_disable_link(struct psi *psi);
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extern void psi_reset_fsp(struct psi *psi);
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extern bool psi_check_link_active(struct psi *psi);
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extern bool psi_poll_fsp_interrupt(struct psi *psi);
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extern struct psi *psi_find_functional_chip(void);
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/* Interrupts */
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extern void psi_irq_reset(void);
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extern void psi_enable_fsp_interrupt(struct psi *psi);
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extern void psi_fsp_link_in_use(struct psi *psi);
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extern struct lock psi_lock;
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#endif /* __PSI_H */
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