103 lines
3.3 KiB
C
103 lines
3.3 KiB
C
// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
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/*
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* XIVE: eXternal Interrupt Virtualization Engine. POWER9 interrupt
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* controller
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*
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* Copyright (c) 2016-2019, IBM Corporation.
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*/
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#ifndef XIVE_H
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#define XIVE_H
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/* Internal APIs to other modules */
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/* IRQ allocators return this on failure */
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#define XIVE_IRQ_ERROR 0xffffffff
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void init_xive(void);
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int64_t xive_reset(void);
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/* Allocate a chunk of HW sources */
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uint32_t xive_alloc_hw_irqs(uint32_t chip_id, uint32_t count, uint32_t align);
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/* Allocate a chunk of IPI sources */
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uint32_t xive_alloc_ipi_irqs(uint32_t chip_id, uint32_t count, uint32_t align);
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/* Get notification port address for a HW source entity */
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#define XIVE_HW_SRC_PHBn(__n) (__n)
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#define XIVE_HW_SRC_PSI 8
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uint64_t xive_get_notify_port(uint32_t chip_id, uint32_t ent);
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__attrconst uint32_t xive_get_notify_base(uint32_t girq);
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/* XIVE feature flag to de/activate store EOI */
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#define XIVE_STORE_EOI_ENABLED 0
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/* Internal IRQ flags */
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#define XIVE_SRC_TRIGGER_PAGE 0x01 /* Trigger page exist (either separate
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* or not, so different from the OPAL
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* flag which is only set when the
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* trigger page is separate).
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*/
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#define XIVE_SRC_EOI_PAGE1 0x02 /* EOI on the second page */
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#define XIVE_SRC_STORE_EOI 0x04 /* EOI using stores supported */
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#define XIVE_SRC_LSI 0x08 /* Interrupt is an LSI */
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struct irq_source_ops;
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void xive_register_hw_source(uint32_t base, uint32_t count, uint32_t shift,
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void *mmio, uint32_t flags, void *data,
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const struct irq_source_ops *ops);
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void xive_register_ipi_source(uint32_t base, uint32_t count, void *data,
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const struct irq_source_ops *ops);
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void xive_cpu_callin(struct cpu_thread *cpu);
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/* Get the trigger page address for an interrupt allocated with
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* xive_alloc_ipi_irqs()
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*/
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void *xive_get_trigger_port(uint32_t girq);
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/* To be used by PSI to prevent asserted LSI to constantly re-fire */
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struct irq_source;
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void xive_source_mask(struct irq_source *is, uint32_t isn);
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void xive_cpu_reset(void);
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void xive_late_init(void);
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/*
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* POWER10
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*/
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/*
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* StoreEOI requires the OS to enforce load-after-store ordering and
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* the PHB5 should be configured in Address-based trigger mode with PQ
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* state bit offloading.
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*/
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#define XIVE2_STORE_EOI_ENABLED xive2_cap_store_eoi()
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void xive2_init(void);
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bool xive2_cap_phb_pq_disable(void);
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bool xive2_cap_phb_abt(void);
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bool xive2_cap_store_eoi(void);
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int64_t xive2_reset(void);
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uint32_t xive2_get_phandle(void);
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uint32_t xive2_alloc_hw_irqs(uint32_t chip_id, uint32_t count, uint32_t align);
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uint32_t xive2_alloc_ipi_irqs(uint32_t chip_id, uint32_t count, uint32_t align);
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uint64_t xive2_get_notify_port(uint32_t chip_id, uint32_t ent);
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__attrconst uint32_t xive2_get_notify_base(uint32_t girq);
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void xive2_register_hw_source(uint32_t base, uint32_t count, uint32_t shift,
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void *mmio, uint32_t flags, void *data,
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const struct irq_source_ops *ops);
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void xive2_register_ipi_source(uint32_t base, uint32_t count, void *data,
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const struct irq_source_ops *ops);
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void xive2_register_esb_source(uint32_t base, uint32_t count);
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uint64_t xive2_get_esb_base(uint32_t girq);
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void xive2_cpu_callin(struct cpu_thread *cpu);
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void *xive2_get_trigger_port(uint32_t girq);
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void xive2_source_mask(struct irq_source *is, uint32_t isn);
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void xive2_cpu_reset(void);
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void xive2_late_init(void);
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#endif /* XIVE_H */
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