202 lines
6.8 KiB
C++
202 lines
6.8 KiB
C++
/* IBM_PROLOG_BEGIN_TAG */
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/* This is an automatically generated prolog. */
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/* */
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/* $Source: src/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H $ */
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/* */
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/* OpenPOWER HostBoot Project */
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/* */
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/* Contributors Listed Below - COPYRIGHT 2015,2018 */
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/* [+] International Business Machines Corp. */
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/* */
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/* */
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/* Licensed under the Apache License, Version 2.0 (the "License"); */
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/* you may not use this file except in compliance with the License. */
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/* You may obtain a copy of the License at */
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/* */
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/* http://www.apache.org/licenses/LICENSE-2.0 */
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/* */
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/* Unless required by applicable law or agreed to in writing, software */
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/* distributed under the License is distributed on an "AS IS" BASIS, */
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/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
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/* implied. See the License for the specific language governing */
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/* permissions and limitations under the License. */
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/* */
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/* IBM_PROLOG_END_TAG */
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///
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/// @file p9_stop_data_struct.H
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/// @brief describes data structures internal to STOP API.
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///
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// *HWP HW Owner : Greg Still <stillgs@us.ibm.com>
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// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com>
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// *HWP Team : PM
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// *HWP Level : 2
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// *HWP Consumed by : HB:HYP
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#ifndef __STOP_DATA_STRUCT_
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#define __STOP_DATA_STRUCT_
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#include "p9_hcd_memmap_base.H"
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#ifdef __SKIBOOT__
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#include <skiboot.h>
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#endif
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#ifdef __FAPI_2_
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#include <fapi2.H>
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#endif
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#ifdef PPC_HYP
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#define STATIC
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#else
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#define STATIC static
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#endif
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#ifdef __cplusplus
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extern "C" {
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namespace stopImageSection
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{
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#endif
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enum
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{
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MAX_SPR_RESTORE_INST = 0x08,
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SIZE_PER_SPR_RESTORE_INST = ((4 * sizeof(uint8_t)) / sizeof(uint32_t)),
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MAX_THREAD_LEVEL_SPRS = 11,
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MAX_CORE_LEVEL_SPRS = 6,
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MAX_SPR_BIT_POS = 31,
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SPR_BIT_POS_8 = 8,
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SPR_BIT_POS_19 = 19,
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SPR_BIT_POS_25 = 25,
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SPR_BIT_POS_27 = 27,
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};
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enum SprEntryUpdateMode
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{
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INIT_SPR_REGION = 0x01,
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UPDATE_SPR_ENTRY = 0x02,
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};
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typedef struct
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{
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uint32_t scomEntryHeader;
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uint32_t scomEntryAddress;
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uint64_t scomEntryData;
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} ScomEntry_t;
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/**
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* @brief models a CPU register restoration area in STOP section of homer image.
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*/
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typedef struct
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{
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uint8_t iv_threadRestoreArea[MAX_THREADS_PER_CORE][SMF_CORE_RESTORE_THREAD_AREA_SIZE];
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uint8_t iv_threadSaveArea[MAX_THREADS_PER_CORE][SMF_SELF_SAVE_THREAD_AREA_SIZE];
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uint8_t iv_coreRestoreArea[SMF_CORE_RESTORE_CORE_AREA_SIZE];
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uint8_t iv_coreSaveArea[SMF_CORE_SAVE_CORE_AREA_SIZE];
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} SmfSprRestoreArea_t;
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typedef struct
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{
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uint8_t iv_threadArea[CORE_RESTORE_THREAD_AREA_SIZE];
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uint8_t iv_coreArea[CORE_RESTORE_CORE_AREA_SIZE];
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} SprRestoreArea_t;
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/**
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* @brief models homer image of a chip.
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* @note sections not relevant for CPU register restoration have been
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* abstracted using field 'reserve'.
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*/
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typedef struct
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{
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uint8_t iv_occ_host_sgpe_area[ TWO_MB ]; // CPU restore area starts at an offset of 2MB from chip HOMER
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uint8_t iv_interrruptHandler[SELF_RESTORE_INT_SIZE];
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uint8_t iv_threadLauncher[THREAD_LAUNCHER_SIZE];
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SprRestoreArea_t iv_coreThreadRestore[MAX_CORES_PER_CHIP][MAX_THREADS_PER_CORE];
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uint8_t reserve[(ONE_KB * ONE_KB) - SELF_RESTORE_SIZE_TOTAL];
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} HomerSection_t;
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/**
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* @brief models homer image of a chip that supports SMF.
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* @note sections not relevant for CPU register restoration have been
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* abstracted using field 'reserve'.
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*/
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typedef struct
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{
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uint8_t iv_occ_host_sgpe_area[ TWO_MB ];
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uint8_t iv_interrruptHandler[SELF_RESTORE_INT_SIZE];
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uint8_t iv_threadLauncher[SMF_THREAD_LAUNCHER_SIZE];
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SmfSprRestoreArea_t iv_coreThreadRestore[MAX_CORES_PER_CHIP];
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uint8_t reserve[(ONE_KB * ONE_KB) - SMF_SELF_RESTORE_SIZE_TOTAL];
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} SmfHomerSection_t;
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/**
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* @brief models cache subsection in STOP section of a given homer image.
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* @note given the start of cache subsection associated with a given core,
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* the structure below represents what a cache subsection would look
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* like. Based on known start address, quick traversing can be done
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* within the cache subsection.
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*/
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typedef struct
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{
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ScomEntry_t nonCacheArea[MAX_EQ_SCOM_ENTRIES];
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ScomEntry_t l2CacheArea[MAX_L2_SCOM_ENTRIES];
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ScomEntry_t l3CacheArea[MAX_L3_SCOM_ENTRIES];
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} StopCacheSection_t;
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/**
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* @brief summarizes attributes associated with a SPR register.
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*/
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typedef struct
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{
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uint32_t iv_sprId;
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bool iv_isThreadScope;
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uint32_t iv_saveMaskPos;
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} StopSprReg_t;
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enum
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{
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SIZE_SCOM_ENTRY = sizeof( ScomEntry_t ),
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SCOM_ENTRY_START = 0xDEADDEAD,
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BAD_SAVE_MASK = 0x007FF000,
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MAX_SPR_INDEX = 31,
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TEST_BIT_PATTERN = 0x80000000,
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};
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#ifdef __FAPI_2_
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#define MY_ERR( _fmt_, _args_...) FAPI_ERR(_fmt_, ##_args_)
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#define MY_INF(_fmt_, _args_...) FAPI_INF(_fmt_, ##_args_)
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#else
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#define MY_ERR( _fmt_, _args_...)
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#define MY_INF(_fmt_, _args_...)
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#endif
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#define CORE_ID_SCOM_START(io_image,\
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i_chipletId) \
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((ScomEntry_t*)(((uint8_t*)(io_image)) + CORE_SCOM_RESTORE_HOMER_OFFSET +\
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((i_chipletId - CORE_CHIPLET_ID_MIN) * \
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CORE_SCOM_RESTORE_SIZE_PER_CORE)));
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#define CACHE_SECTN_START(io_image,\
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i_chipletId) \
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((StopCacheSection_t *)(((uint8_t *)(io_image)) + QUAD_SCOM_RESTORE_HOMER_OFFSET +\
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((i_chipletId - CACHE_CHIPLET_ID_MIN) * \
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QUAD_SCOM_RESTORE_SIZE_PER_QUAD)));
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#define CACHE_SCOM_ADDR(io_image,\
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i_chipletId,\
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i_maxScomEntry)\
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((ScomEntry_t *)(((uint8_t *)(io_image)) + QUAD_SCOM_RESTORE_HOMER_OFFSET +\
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((i_chipletId - CACHE_CHIPLET_ID_MIN) * \
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((i_maxScomEntry + 1) * 16 ))));
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#ifdef __cplusplus
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} // extern "C"
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} //namespace stopImageSection ends
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#endif //__cplusplus
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#endif
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