453 lines
16 KiB
Python
453 lines
16 KiB
Python
#
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# Copyright (c) 2021 Nutanix Inc. All rights reserved.
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#
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# Authors: John Levon <john.levon@nutanix.com>
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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# * Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# * Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution.
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# * Neither the name of Nutanix nor the names of its contributors may be
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# used to endorse or promote products derived from this software without
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# specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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# DAMAGE.
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#
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from unittest.mock import patch
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from libvfio_user import *
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import ctypes as c
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import errno
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ctx = None
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def setup_function(function):
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global ctx
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ctx = vfu_create_ctx(flags=LIBVFIO_USER_FLAG_ATTACH_NB)
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assert ctx is not None
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ret = vfu_setup_device_reset_cb(ctx)
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assert ret == 0
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vfu_setup_device_quiesce_cb(ctx)
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def teardown_function(function):
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vfu_destroy_ctx(ctx)
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def setup_pci_dev(config_space=True, realize=False):
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global ctx
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ret = vfu_pci_init(ctx, pci_type=VFU_PCI_TYPE_CONVENTIONAL)
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assert ret == 0
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if config_space:
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ret = vfu_setup_region(ctx, index=VFU_PCI_DEV_CFG_REGION_IDX,
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size=PCI_CFG_SPACE_SIZE,
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flags=VFU_REGION_FLAG_RW)
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assert ret == 0
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if realize:
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ret = vfu_realize_ctx(ctx)
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assert ret == 0
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def test_pci_cap_bad_flags():
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"""Tests adding a PCI capability with bad VFU_CAP_FLAG_ flags."""
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setup_pci_dev()
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pos = vfu_pci_add_capability(ctx, pos=0, flags=999,
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data=struct.pack("ccHH", to_byte(PCI_CAP_ID_PM), b'\0', 0, 0))
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assert pos == -1
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assert c.get_errno() == errno.EINVAL
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def test_pci_cap_no_cb():
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"""
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Tests adding a PCI capability VFU_CAP_FLAG_CALLBACK without a callback.
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"""
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setup_pci_dev(config_space=False)
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pos = vfu_pci_add_capability(ctx, pos=0, flags=VFU_CAP_FLAG_CALLBACK,
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data=struct.pack("ccHH", to_byte(PCI_CAP_ID_PM), b'\0', 0, 0))
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assert pos == -1
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assert c.get_errno() == errno.EINVAL
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def test_pci_cap_unknown_cap():
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"""Tests adding an unknown PCI capability."""
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setup_pci_dev()
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pos = vfu_pci_add_capability(ctx, pos=0, flags=0,
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data=struct.pack("ccHH", b'\x81', b'\0', 0, 0))
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assert pos == -1
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assert c.get_errno() == errno.ENOTSUP
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def test_pci_cap_bad_pos():
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"""Tests adding a PCI capability at an invalid position."""
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setup_pci_dev()
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pos = vfu_pci_add_capability(ctx, pos=PCI_CFG_SPACE_SIZE, flags=0,
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data=struct.pack("ccHH", to_byte(PCI_CAP_ID_PM), b'\0', 0, 0))
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assert pos == -1
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assert c.get_errno() == errno.EINVAL
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def __pci_region_cb(ctx, buf, count, offset, is_write):
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if not is_write:
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return read_pci_cfg_space(ctx, buf, count, offset)
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return write_pci_cfg_space(ctx, buf, count, offset)
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cap_offsets = (
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PCI_STD_HEADER_SIZEOF,
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PCI_STD_HEADER_SIZEOF + PCI_PM_SIZEOF,
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# NB: note 4-byte alignment of vsc2
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PCI_STD_HEADER_SIZEOF + PCI_PM_SIZEOF + 8,
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0x80,
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0x90,
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0xa0
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)
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@patch("libvfio_user.pci_region_cb", side_effect=__pci_region_cb)
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def test_add_caps(mock_pci_region_cb):
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setup_pci_dev()
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pos = vfu_pci_add_capability(ctx, pos=0, flags=0,
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data=struct.pack("ccHH", to_byte(PCI_CAP_ID_PM), b'\0', 0, 0))
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assert pos == cap_offsets[0]
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data = b"abc"
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cap = struct.pack("ccc%ds" % len(data), to_byte(PCI_CAP_ID_VNDR), b'\0',
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to_byte(3 + len(data)), data)
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pos = vfu_pci_add_capability(ctx, pos=0, flags=VFU_CAP_FLAG_READONLY,
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data=cap)
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assert pos == cap_offsets[1]
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data = b"Hello world."
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cap = struct.pack("ccc%ds" % len(data), to_byte(PCI_CAP_ID_VNDR), b'\0',
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to_byte(3 + len(data)), data)
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pos = vfu_pci_add_capability(ctx, pos=0, flags=VFU_CAP_FLAG_CALLBACK,
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data=cap)
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assert pos == cap_offsets[2]
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pos = vfu_pci_add_capability(ctx, pos=cap_offsets[3], flags=0, data=cap)
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assert pos == cap_offsets[3]
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pos = vfu_pci_add_capability(ctx, pos=cap_offsets[4], flags=0, data=cap)
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assert pos == cap_offsets[4]
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ret = vfu_realize_ctx(ctx)
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assert ret == 0
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__test_find_caps()
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sock = connect_client(ctx)
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__test_pci_cap_write_hdr(sock)
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__test_pci_cap_readonly(sock)
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__test_pci_cap_callback(sock)
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__test_pci_cap_write_pmcs(sock)
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def __test_find_caps():
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offset = vfu_pci_find_capability(ctx, False, PCI_CAP_ID_PM)
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assert offset == cap_offsets[0]
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space = get_pci_cfg_space(ctx)
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assert space[offset] == PCI_CAP_ID_PM
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assert space[offset + PCI_CAP_LIST_NEXT] == cap_offsets[1]
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offset = vfu_pci_find_next_capability(ctx, False, offset, PCI_CAP_ID_PM)
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assert offset == 0
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offset = vfu_pci_find_capability(ctx, False, PCI_CAP_ID_VNDR)
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assert offset == cap_offsets[1]
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assert space[offset] == PCI_CAP_ID_VNDR
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assert space[offset + PCI_CAP_LIST_NEXT] == cap_offsets[2]
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offset = vfu_pci_find_next_capability(ctx, False, offset, PCI_CAP_ID_PM)
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assert offset == 0
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offset = vfu_pci_find_next_capability(ctx, False, 0, PCI_CAP_ID_VNDR)
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assert offset == cap_offsets[1]
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assert space[offset] == PCI_CAP_ID_VNDR
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assert space[offset + PCI_CAP_LIST_NEXT] == cap_offsets[2]
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offset = vfu_pci_find_next_capability(ctx, False, offset, PCI_CAP_ID_VNDR)
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assert offset == cap_offsets[2]
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assert space[offset] == PCI_CAP_ID_VNDR
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assert space[offset + PCI_CAP_LIST_NEXT] == cap_offsets[3]
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offset = vfu_pci_find_next_capability(ctx, False, offset, PCI_CAP_ID_VNDR)
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assert offset == cap_offsets[3]
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offset = vfu_pci_find_next_capability(ctx, False, offset, PCI_CAP_ID_VNDR)
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assert offset == cap_offsets[4]
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offset = vfu_pci_find_next_capability(ctx, False, offset, PCI_CAP_ID_VNDR)
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assert offset == 0
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# check for invalid offsets
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offset = vfu_pci_find_next_capability(ctx, False, 8192, PCI_CAP_ID_PM)
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assert offset == 0
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assert c.get_errno() == errno.EINVAL
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offset = vfu_pci_find_next_capability(ctx, False, 256, PCI_CAP_ID_PM)
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assert offset == 0
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assert c.get_errno() == errno.EINVAL
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offset = vfu_pci_find_next_capability(ctx, False, 255, PCI_CAP_ID_PM)
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assert offset == 0
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assert c.get_errno() == errno.EINVAL
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offset = vfu_pci_find_next_capability(ctx, False,
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PCI_STD_HEADER_SIZEOF +
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PCI_PM_SIZEOF + 1,
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PCI_CAP_ID_VNDR)
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assert offset == 0
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assert c.get_errno() == errno.ENOENT
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def __test_pci_cap_write_hdr(sock):
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# offset of struct cap_hdr
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offset = cap_offsets[0]
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data = b'\x01'
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write_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX, offset=offset,
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count=len(data), data=data, expect=errno.EPERM)
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def __test_pci_cap_readonly(sock):
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# start of vendor payload
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offset = cap_offsets[1] + 2
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data = b'\x01'
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write_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX, offset=offset,
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count=len(data), data=data, expect=errno.EPERM)
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# offsetof(struct vsc, data)
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offset = cap_offsets[1] + 3
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payload = read_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX, offset=offset,
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count=3)
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assert payload == b'abc'
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def __test_pci_cap_callback(sock):
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# offsetof(struct vsc, data)
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offset = cap_offsets[2] + 3
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data = b"Hello world."
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payload = read_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX, offset=offset,
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count=len(data))
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assert payload == data
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data = b"Bye world."
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write_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX, offset=offset,
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count=len(data), data=data)
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payload = read_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX, offset=offset,
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count=len(data))
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assert payload == data
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def __test_pci_cap_write_pmcs(sock):
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# struct pc
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offset = cap_offsets[0] + 3
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data = b'\x01\x02'
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write_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX, offset=offset,
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count=len(data), data=data, expect=errno.EINVAL)
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offset = cap_offsets[0] + 2
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data = b'\x01'
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write_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX, offset=offset,
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count=len(data), data=data, expect=errno.EINVAL)
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offset = cap_offsets[0] + 2
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data = b'\x01\x02'
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write_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX, offset=offset,
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count=len(data), data=data, expect=errno.ENOTSUP)
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# struct pmcs
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offset = cap_offsets[0] + 5
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data = b'\x01\x02'
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write_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX, offset=offset,
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count=len(data), data=data, expect=errno.EINVAL)
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offset = cap_offsets[0] + 4
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data = b'\x01'
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write_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX, offset=offset,
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count=len(data), data=data, expect=errno.EINVAL)
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offset = cap_offsets[0] + 4
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data = b'\x01\x02'
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write_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX, offset=offset,
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count=len(data), data=data)
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assert get_pci_cfg_space(ctx)[offset:offset+2] == data
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# pmcsr_se
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offset = cap_offsets[0] + 6
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data = b'\x01'
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write_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX, offset=offset,
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count=len(data), data=data, expect=errno.ENOTSUP)
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# data
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offset = cap_offsets[0] + 7
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data = b'\x01'
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write_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX, offset=offset,
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count=len(data), data=data, expect=errno.ENOTSUP)
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def _setup_flrc(ctx):
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# flrc
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cap = struct.pack("ccHHcc52c", to_byte(PCI_CAP_ID_EXP), b'\0', 0, 0, b'\0',
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b'\x10', *[b'\0' for _ in range(52)])
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# FIXME adding capability after we've realized the device only works
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# because of bug #618.
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pos = vfu_pci_add_capability(ctx, pos=0, flags=0, data=cap)
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assert pos == PCI_STD_HEADER_SIZEOF
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@patch("libvfio_user.reset_cb", return_value=0)
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@patch('libvfio_user.quiesce_cb')
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def test_pci_cap_write_px(mock_quiesce, mock_reset):
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"""
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Tests function level reset.
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"""
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setup_pci_dev(realize=True)
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sock = connect_client(ctx)
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_setup_flrc(ctx)
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# iflr
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offset = PCI_STD_HEADER_SIZEOF + 8
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data = b'\x00\x80'
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write_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX, offset=offset,
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count=len(data), data=data)
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mock_quiesce.assert_called_once_with(ctx)
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mock_reset.assert_called_once_with(ctx, VFU_RESET_PCI_FLR)
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# bad access
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for _off in (-1, +1):
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for _len in (-1, +1):
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write_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX,
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offset=offset+_off, count=len(data)+_len, data=data,
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expect=errno.EINVAL)
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def to_bytes_le(n, length=1):
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return n.to_bytes(length, 'little')
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def test_pci_cap_write_msix():
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setup_pci_dev(realize=True)
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sock = connect_client(ctx)
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flags = PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE
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pos = vfu_pci_add_capability(ctx, pos=0, flags=0,
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data=struct.pack("ccHII",
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to_byte(PCI_CAP_ID_MSIX),
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b'\0', 0, 0, 0))
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assert pos == cap_offsets[0]
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offset = vfu_pci_find_capability(ctx, False, PCI_CAP_ID_MSIX)
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# write exactly to Message Control: mask all vectors and enable MSI-X
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data = b'\xff\xff'
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write_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX,
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offset=offset + PCI_MSIX_FLAGS,
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count=len(data), data=data)
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data = b'\xff\xff' + to_bytes_le(flags, 2)
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payload = read_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX, offset=offset,
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count=len(data))
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expected = to_bytes_le(PCI_CAP_ID_MSIX) + b'\x00' + \
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to_bytes_le(PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE, 2)
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assert expected == payload
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# reset
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data = b'\x00\x00'
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write_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX,
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offset=offset + PCI_MSIX_FLAGS,
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count=len(data), data=data)
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expected = to_bytes_le(PCI_CAP_ID_MSIX) + b'\x00\x00'
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payload = read_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX, offset=offset,
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count=len(expected))
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assert expected == payload
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# write 2 bytes to Message Control + 1: mask all vectors and enable MSI-X
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# This looks bizarre, but some versions of QEMU do this.
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data = to_bytes_le(flags >> 8) + b'\xff'
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write_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX,
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offset=offset + PCI_MSIX_FLAGS + 1,
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count=len(data), data=data)
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# read back entire MSI-X
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expected = to_bytes_le(PCI_CAP_ID_MSIX) + b'\x00' + \
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to_bytes_le(flags, 2) + b'\x00\x00\x00\x00' + b'\x00\x00\x00\x00'
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payload = read_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX, offset=offset,
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count=PCI_CAP_MSIX_SIZEOF)
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assert expected == payload
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# reset with MSI-X enabled
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data = to_bytes_le(PCI_MSIX_FLAGS_ENABLE, 2)
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write_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX,
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offset=offset + PCI_MSIX_FLAGS,
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count=len(data), data=data)
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# write 1 byte past Message Control, MSI-X should still be enabled
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data = b'\x00'
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write_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX,
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offset=offset + PCI_MSIX_TABLE,
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count=len(data), data=data)
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payload = read_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX,
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offset=offset + PCI_MSIX_FLAGS, count=2)
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assert payload == to_bytes_le(PCI_MSIX_FLAGS_ENABLE, 2)
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def test_pci_cap_write_pxdc2():
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setup_pci_dev(realize=True)
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sock = connect_client(ctx)
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_setup_flrc(ctx)
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offset = (vfu_pci_find_capability(ctx, False, PCI_CAP_ID_EXP) +
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PCI_EXP_DEVCTL2)
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data = b'\xde\xad'
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write_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX, offset=offset,
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count=len(data), data=data)
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payload = read_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX, offset=offset,
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count=len(data))
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assert payload == data
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def test_pci_cap_write_pxlc2():
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setup_pci_dev(realize=True)
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_setup_flrc(ctx)
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sock = connect_client(ctx)
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offset = (vfu_pci_find_capability(ctx, False, PCI_CAP_ID_EXP) +
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PCI_EXP_LNKCTL2)
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data = b'\xbe\xef'
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write_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX, offset=offset,
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count=len(data), data=data)
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payload = read_region(ctx, sock, VFU_PCI_DEV_CFG_REGION_IDX, offset=offset,
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count=len(data))
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assert payload == data
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# ex: set tabstop=4 shiftwidth=4 softtabstop=4 expandtab: #
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