Adding upstream version 2:9.1.1230.
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
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132
runtime/syntax/verilogams.vim
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132
runtime/syntax/verilogams.vim
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" Vim syntax file
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" Language: Verilog-AMS
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" Maintainer: S. Myles Prather <smprather@gmail.com>
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"
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" Version 1.1 S. Myles Prather <smprather@gmail.com>
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" Moved some keywords to the type category.
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" Added the metrix suffixes to the number matcher.
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" Version 1.2 Prasanna Tamhankar <pratam@gmail.com>
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" Minor reserved keyword updates.
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" Last Update: Thursday September 15 15:36:03 CST 2005
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" quit when a syntax file was already loaded
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if exists("b:current_syntax")
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finish
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endif
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" Set the local value of the 'iskeyword' option
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setlocal iskeyword=@,48-57,_,192-255
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" Annex B.1 'All keywords'
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syn keyword verilogamsStatement above abs absdelay acos acosh ac_stim
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syn keyword verilogamsStatement always analog analysis and asin
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syn keyword verilogamsStatement asinh assign atan atan2 atanh
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syn keyword verilogamsStatement buf bufif0 bufif1 ceil cmos connectmodule
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syn keyword verilogamsStatement connectrules cos cosh cross ddt ddx deassign
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syn keyword verilogamsStatement defparam disable discipline
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syn keyword verilogamsStatement driver_update edge enddiscipline
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syn keyword verilogamsStatement endconnectrules endmodule endfunction endgenerate
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syn keyword verilogamsStatement endnature endparamset endprimitive endspecify
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syn keyword verilogamsStatement endtable endtask event exp final_step
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syn keyword verilogamsStatement flicker_noise floor flow force fork
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syn keyword verilogamsStatement function generate highz0
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syn keyword verilogamsStatement highz1 hypot idt idtmod if ifnone inf initial
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syn keyword verilogamsStatement initial_step inout input join
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syn keyword verilogamsStatement laplace_nd laplace_np laplace_zd laplace_zp
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syn keyword verilogamsStatement large last_crossing limexp ln localparam log
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syn keyword verilogamsStatement macromodule max medium min module nand nature
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syn keyword verilogamsStatement negedge net_resolution nmos noise_table nor not
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syn keyword verilogamsStatement notif0 notif1 or output paramset pmos
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syn keyword verilogamsType parameter real integer electrical input output
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syn keyword verilogamsType inout reg tri tri0 tri1 triand trior trireg
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syn keyword verilogamsType string from exclude aliasparam ground genvar
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syn keyword verilogamsType branch time realtime
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syn keyword verilogamsStatement posedge potential pow primitive pull0 pull1
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syn keyword verilogamsStatement pullup pulldown rcmos release
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syn keyword verilogamsStatement rnmos rpmos rtran rtranif0 rtranif1
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syn keyword verilogamsStatement scalared sin sinh slew small specify specparam
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syn keyword verilogamsStatement sqrt strong0 strong1 supply0 supply1
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syn keyword verilogamsStatement table tan tanh task timer tran tranif0
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syn keyword verilogamsStatement tranif1 transition
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syn keyword verilogamsStatement vectored wait wand weak0 weak1
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syn keyword verilogamsStatement white_noise wire wor wreal xnor xor zi_nd
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syn keyword verilogamsStatement zi_np zi_zd zi_zp
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syn keyword verilogamsRepeat forever repeat while for
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syn keyword verilogamsLabel begin end
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syn keyword verilogamsConditional if else case casex casez default endcase
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syn match verilogamsConstant ":inf"lc=1
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syn match verilogamsConstant "-inf"lc=1
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" Annex B.2 Discipline/nature
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syn keyword verilogamsStatement abstol access continuous ddt_nature discrete
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syn keyword verilogamsStatement domain idt_nature units
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" Annex B.3 Connect Rules
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syn keyword verilogamsStatement connect merged resolveto split
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syn match verilogamsOperator "[&|~><!)(*#%@+/=?:;}{,.\^\-\[\]]"
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syn match verilogamsOperator "<+"
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syn match verilogamsStatement "[vV]("me=e-1
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syn match verilogamsStatement "[iI]("me=e-1
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syn keyword verilogamsTodo contained TODO
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syn region verilogamsComment start="/\*" end="\*/" contains=verilogamsTodo
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syn match verilogamsComment "//.*" contains=verilogamsTodo
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syn match verilogamsGlobal "`celldefine"
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syn match verilogamsGlobal "`default_nettype"
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syn match verilogamsGlobal "`define"
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syn match verilogamsGlobal "`else"
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syn match verilogamsGlobal "`elsif"
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syn match verilogamsGlobal "`endcelldefine"
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syn match verilogamsGlobal "`endif"
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syn match verilogamsGlobal "`ifdef"
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syn match verilogamsGlobal "`ifndef"
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syn match verilogamsGlobal "`include"
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syn match verilogamsGlobal "`line"
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syn match verilogamsGlobal "`nounconnected_drive"
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syn match verilogamsGlobal "`resetall"
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syn match verilogamsGlobal "`timescale"
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syn match verilogamsGlobal "`unconnected_drive"
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syn match verilogamsGlobal "`undef"
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syn match verilogamsSystask "$[a-zA-Z0-9_]\+\>"
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syn match verilogamsConstant "\<[A-Z][A-Z0-9_]\+\>"
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syn match verilogamsNumber "\(\<\d\+\|\)'[bB]\s*[0-1_xXzZ?]\+\>"
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syn match verilogamsNumber "\(\<\d\+\|\)'[oO]\s*[0-7_xXzZ?]\+\>"
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syn match verilogamsNumber "\(\<\d\+\|\)'[dD]\s*[0-9_xXzZ?]\+\>"
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syn match verilogamsNumber "\(\<\d\+\|\)'[hH]\s*[0-9a-fA-F_xXzZ?]\+\>"
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syn match verilogamsNumber "\<[+-]\=[0-9_]\+\(\.[0-9_]*\|\)\(e[0-9_]*\|\)[TGMKkmunpfa]\=\>"
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syn region verilogamsString start=+"+ skip=+\\"+ end=+"+ contains=verilogamsEscape
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syn match verilogamsEscape +\\[nt"\\]+ contained
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syn match verilogamsEscape "\\\o\o\=\o\=" contained
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"Modify the following as needed. The trade-off is performance versus
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"functionality.
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syn sync lines=50
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" Define the default highlighting.
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" Only when an item doesn't have highlighting yet
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" The default highlighting.
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hi def link verilogamsCharacter Character
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hi def link verilogamsConditional Conditional
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hi def link verilogamsRepeat Repeat
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hi def link verilogamsString String
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hi def link verilogamsTodo Todo
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hi def link verilogamsComment Comment
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hi def link verilogamsConstant Constant
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hi def link verilogamsLabel Label
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hi def link verilogamsNumber Number
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hi def link verilogamsOperator Special
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hi def link verilogamsStatement Statement
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hi def link verilogamsGlobal Define
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hi def link verilogamsDirective SpecialComment
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hi def link verilogamsEscape Special
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hi def link verilogamsType Type
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hi def link verilogamsSystask Function
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let b:current_syntax = "verilogams"
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" vim: ts=8
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