422 lines
22 KiB
C
422 lines
22 KiB
C
/** @file
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* IEM - Interpreted Execution Manager.
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*/
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/*
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* Copyright (C) 2011-2023 Oracle and/or its affiliates.
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*
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* This file is part of VirtualBox base platform packages, as
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* available from https://www.virtualbox.org.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, in version 3 of the
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* License.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <https://www.gnu.org/licenses>.
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*
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* The contents of this file may alternatively be used under the terms
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* of the Common Development and Distribution License Version 1.0
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* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
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* in the VirtualBox distribution, in which case the provisions of the
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* CDDL are applicable instead of those of the GPL.
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*
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* You may elect to license modified versions of this file under the
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* terms and conditions of either the GPL or the CDDL or both.
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*
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* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
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*/
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#ifndef VBOX_INCLUDED_vmm_iem_h
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#define VBOX_INCLUDED_vmm_iem_h
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#ifndef RT_WITHOUT_PRAGMA_ONCE
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# pragma once
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#endif
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#include <VBox/types.h>
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#include <VBox/vmm/trpm.h>
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#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
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# include <VBox/vmm/hm_vmx.h>
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#endif
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#include <iprt/assert.h>
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RT_C_DECLS_BEGIN
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/** @defgroup grp_iem The Interpreted Execution Manager API.
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* @ingroup grp_vmm
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* @{
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*/
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/** @name IEMXCPTRAISEINFO_XXX - Extra info. on a recursive exception situation.
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*
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* This is primarily used by HM for working around a PGM limitation (see
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* @bugref{6607}) and special NMI/IRET handling. In the future, this may be
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* used for diagnostics.
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*
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* @{
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*/
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typedef uint32_t IEMXCPTRAISEINFO;
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/** Pointer to a IEMXCPTINFO type. */
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typedef IEMXCPTRAISEINFO *PIEMXCPTRAISEINFO;
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/** No addition info. available. */
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#define IEMXCPTRAISEINFO_NONE RT_BIT_32(0)
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/** Delivery of a \#AC caused another \#AC. */
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#define IEMXCPTRAISEINFO_AC_AC RT_BIT_32(1)
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/** Delivery of a \#PF caused another \#PF. */
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#define IEMXCPTRAISEINFO_PF_PF RT_BIT_32(2)
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/** Delivery of a \#PF caused some contributory exception. */
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#define IEMXCPTRAISEINFO_PF_CONTRIBUTORY_XCPT RT_BIT_32(3)
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/** Delivery of an external interrupt caused an exception. */
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#define IEMXCPTRAISEINFO_EXT_INT_XCPT RT_BIT_32(4)
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/** Delivery of an external interrupt caused an \#PF. */
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#define IEMXCPTRAISEINFO_EXT_INT_PF RT_BIT_32(5)
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/** Delivery of a software interrupt caused an exception. */
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#define IEMXCPTRAISEINFO_SOFT_INT_XCPT RT_BIT_32(6)
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/** Delivery of an NMI caused an exception. */
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#define IEMXCPTRAISEINFO_NMI_XCPT RT_BIT_32(7)
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/** Delivery of an NMI caused a \#PF. */
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#define IEMXCPTRAISEINFO_NMI_PF RT_BIT_32(8)
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/** Can re-execute the instruction at CS:RIP. */
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#define IEMXCPTRAISEINFO_CAN_REEXEC_INSTR RT_BIT_32(9)
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/** @} */
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/** @name IEMXCPTRAISE_XXX - Ways to handle a recursive exception condition.
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* @{ */
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typedef enum IEMXCPTRAISE
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{
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/** Raise the current (second) exception. */
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IEMXCPTRAISE_CURRENT_XCPT = 0,
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/** Re-raise the previous (first) event (for HM, unused by IEM). */
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IEMXCPTRAISE_PREV_EVENT,
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/** Re-execute instruction at CS:RIP (for HM, unused by IEM). */
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IEMXCPTRAISE_REEXEC_INSTR,
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/** Raise a \#DF exception. */
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IEMXCPTRAISE_DOUBLE_FAULT,
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/** Raise a triple fault. */
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IEMXCPTRAISE_TRIPLE_FAULT,
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/** Cause a CPU hang. */
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IEMXCPTRAISE_CPU_HANG,
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/** Invalid sequence of events. */
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IEMXCPTRAISE_INVALID = 0x7fffffff
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} IEMXCPTRAISE;
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/** Pointer to a IEMXCPTRAISE type. */
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typedef IEMXCPTRAISE *PIEMXCPTRAISE;
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/** @} */
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/** @name Operand or addressing mode.
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* @{ */
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typedef uint8_t IEMMODE;
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#define IEMMODE_16BIT 0
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#define IEMMODE_32BIT 1
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#define IEMMODE_64BIT 2
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/** @} */
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/** @name IEM_XCPT_FLAGS_XXX - flags for iemRaiseXcptOrInt.
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* @{ */
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/** CPU exception. */
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#define IEM_XCPT_FLAGS_T_CPU_XCPT RT_BIT_32(0)
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/** External interrupt (from PIC, APIC, whatever). */
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#define IEM_XCPT_FLAGS_T_EXT_INT RT_BIT_32(1)
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/** Software interrupt (int or into, not bound).
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* Returns to the following instruction */
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#define IEM_XCPT_FLAGS_T_SOFT_INT RT_BIT_32(2)
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/** Takes an error code. */
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#define IEM_XCPT_FLAGS_ERR RT_BIT_32(3)
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/** Takes a CR2. */
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#define IEM_XCPT_FLAGS_CR2 RT_BIT_32(4)
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/** Generated by the breakpoint instruction. */
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#define IEM_XCPT_FLAGS_BP_INSTR RT_BIT_32(5)
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/** Generated by a DRx instruction breakpoint and RF should be cleared. */
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#define IEM_XCPT_FLAGS_DRx_INSTR_BP RT_BIT_32(6)
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/** Generated by the icebp instruction. */
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#define IEM_XCPT_FLAGS_ICEBP_INSTR RT_BIT_32(7)
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/** Generated by the overflow instruction. */
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#define IEM_XCPT_FLAGS_OF_INSTR RT_BIT_32(8)
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/** @} */
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/** @name IEMTARGETCPU_XXX - IEM target CPU specification.
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*
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* This is a gross simpliciation of CPUMMICROARCH for dealing with really old
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* CPUs which didn't have much in the way of hinting at supported instructions
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* and features. This slowly changes with the introduction of CPUID with the
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* Intel Pentium.
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*
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* @{
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*/
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/** The dynamic target CPU mode is for getting thru the BIOS and then use
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* the debugger or modifying instruction behaviour (e.g. HLT) to switch to a
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* different target CPU. */
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#define IEMTARGETCPU_DYNAMIC UINT32_C(0)
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/** Intel 8086/8088. */
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#define IEMTARGETCPU_8086 UINT32_C(1)
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/** NEC V20/V30.
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* @remarks must be between 8086 and 80186. */
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#define IEMTARGETCPU_V20 UINT32_C(2)
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/** Intel 80186/80188. */
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#define IEMTARGETCPU_186 UINT32_C(3)
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/** Intel 80286. */
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#define IEMTARGETCPU_286 UINT32_C(4)
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/** Intel 80386. */
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#define IEMTARGETCPU_386 UINT32_C(5)
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/** Intel 80486. */
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#define IEMTARGETCPU_486 UINT32_C(6)
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/** Intel Pentium . */
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#define IEMTARGETCPU_PENTIUM UINT32_C(7)
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/** Intel PentiumPro. */
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#define IEMTARGETCPU_PPRO UINT32_C(8)
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/** A reasonably current CPU, probably newer than the pentium pro when it comes
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* to the feature set and behaviour. Generally the CPUID info and CPU vendor
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* dicates the behaviour here. */
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#define IEMTARGETCPU_CURRENT UINT32_C(9)
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/** @} */
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/** @name IEM status codes.
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*
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* Not quite sure how this will play out in the end, just aliasing safe status
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* codes for now.
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*
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* @{ */
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#define VINF_IEM_RAISED_XCPT VINF_EM_RESCHEDULE
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/** @} */
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/** The CPUMCTX_EXTRN_XXX mask required to be cleared when interpreting anything.
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* IEM will ASSUME the caller of IEM APIs has ensured these are already present. */
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#define IEM_CPUMCTX_EXTRN_MUST_MASK ( CPUMCTX_EXTRN_GPRS_MASK \
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| CPUMCTX_EXTRN_RIP \
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| CPUMCTX_EXTRN_RFLAGS \
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| CPUMCTX_EXTRN_SS \
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| CPUMCTX_EXTRN_CS \
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| CPUMCTX_EXTRN_CR0 \
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| CPUMCTX_EXTRN_CR3 \
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| CPUMCTX_EXTRN_CR4 \
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| CPUMCTX_EXTRN_APIC_TPR \
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| CPUMCTX_EXTRN_EFER \
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| CPUMCTX_EXTRN_DR7 )
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/** The CPUMCTX_EXTRN_XXX mask needed when injecting an exception/interrupt.
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* IEM will import missing bits, callers are encouraged to make these registers
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* available prior to injection calls if fetching state anyway. */
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#define IEM_CPUMCTX_EXTRN_XCPT_MASK ( IEM_CPUMCTX_EXTRN_MUST_MASK \
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| CPUMCTX_EXTRN_CR2 \
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| CPUMCTX_EXTRN_SREG_MASK \
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| CPUMCTX_EXTRN_TABLE_MASK )
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/** The CPUMCTX_EXTRN_XXX mask required to be cleared when calling any
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* IEMExecDecoded API not using memory. IEM will ASSUME the caller of IEM
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* APIs has ensured these are already present.
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* @note ASSUMES execution engine has checked for instruction breakpoints
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* during decoding. */
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#define IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK ( CPUMCTX_EXTRN_RIP \
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| CPUMCTX_EXTRN_RFLAGS \
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| CPUMCTX_EXTRN_SS /* for CPL */ \
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| CPUMCTX_EXTRN_CS /* for mode */ \
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| CPUMCTX_EXTRN_CR0 /* for mode */ \
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| CPUMCTX_EXTRN_EFER /* for mode */ )
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/** The CPUMCTX_EXTRN_XXX mask required to be cleared when calling any
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* IEMExecDecoded API using memory. IEM will ASSUME the caller of IEM
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* APIs has ensured these are already present.
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* @note ASSUMES execution engine has checked for instruction breakpoints
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* during decoding. */
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#define IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK ( IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \
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| CPUMCTX_EXTRN_CR3 /* for page tables */ \
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| CPUMCTX_EXTRN_CR4 /* for mode paging mode */ \
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| CPUMCTX_EXTRN_DR7 /* for memory breakpoints */ )
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#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
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/** The CPUMCTX_EXTRN_XXX mask needed when calling IEMExecDecodedVmlaunchVmresume().
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* IEM will ASSUME the caller has ensured these are already present. */
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# define IEM_CPUMCTX_EXTRN_VMX_VMENTRY_MASK ( IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \
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| CPUMCTX_EXTRN_CR2 \
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| CPUMCTX_EXTRN_HWVIRT )
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/** The CPUMCTX_EXTRN_XXX mask that the IEM VM-exit code will import on-demand when
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* needed, primarily because there are several IEM VM-exit interface functions and
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* some of which may not cause a VM-exit at all.
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*
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* This is currently unused, but keeping it here in case we can get away a bit more
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* fine-grained state handling.
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*
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* @note Update HM_CHANGED_VMX_VMEXIT_MASK if something here changes. */
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# define IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK ( CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 \
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| CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_DR6 \
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| CPUMCTX_EXTRN_EFER \
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| CPUMCTX_EXTRN_SYSENTER_MSRS \
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| CPUMCTX_EXTRN_OTHER_MSRS /* for PAT MSR */ \
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| CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_RFLAGS \
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| CPUMCTX_EXTRN_SREG_MASK \
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| CPUMCTX_EXTRN_TR \
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| CPUMCTX_EXTRN_LDTR | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_IDTR \
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| CPUMCTX_EXTRN_HWVIRT )
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#endif
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#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
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/** The CPUMCTX_EXTRN_XXX mask needed when calling IEMExecSvmVmexit().
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* IEM will ASSUME the caller has ensured these are already present. */
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# define IEM_CPUMCTX_EXTRN_SVM_VMEXIT_MASK ( CPUMCTX_EXTRN_RSP \
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| CPUMCTX_EXTRN_RAX \
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| CPUMCTX_EXTRN_RIP \
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| CPUMCTX_EXTRN_RFLAGS \
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| CPUMCTX_EXTRN_CS \
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| CPUMCTX_EXTRN_SS \
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| CPUMCTX_EXTRN_DS \
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| CPUMCTX_EXTRN_ES \
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| CPUMCTX_EXTRN_GDTR \
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| CPUMCTX_EXTRN_IDTR \
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| CPUMCTX_EXTRN_CR_MASK \
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| CPUMCTX_EXTRN_EFER \
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| CPUMCTX_EXTRN_DR6 \
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| CPUMCTX_EXTRN_DR7 \
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| CPUMCTX_EXTRN_OTHER_MSRS \
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| CPUMCTX_EXTRN_HWVIRT \
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| CPUMCTX_EXTRN_APIC_TPR \
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| CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ)
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/** The CPUMCTX_EXTRN_XXX mask needed when calling IEMExecDecodedVmrun().
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* IEM will ASSUME the caller has ensured these are already present. */
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# define IEM_CPUMCTX_EXTRN_SVM_VMRUN_MASK IEM_CPUMCTX_EXTRN_SVM_VMEXIT_MASK
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#endif
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VMMDECL(VBOXSTRICTRC) IEMExecOne(PVMCPUCC pVCpu);
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VMMDECL(VBOXSTRICTRC) IEMExecOneEx(PVMCPUCC pVCpu, uint32_t *pcbWritten);
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VMMDECL(VBOXSTRICTRC) IEMExecOneWithPrefetchedByPC(PVMCPUCC pVCpu, uint64_t OpcodeBytesPC,
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const void *pvOpcodeBytes, size_t cbOpcodeBytes);
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VMMDECL(VBOXSTRICTRC) IEMExecOneBypassEx(PVMCPUCC pVCpu, uint32_t *pcbWritten);
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VMMDECL(VBOXSTRICTRC) IEMExecOneBypassWithPrefetchedByPC(PVMCPUCC pVCpu, uint64_t OpcodeBytesPC,
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const void *pvOpcodeBytes, size_t cbOpcodeBytes);
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VMMDECL(VBOXSTRICTRC) IEMExecOneIgnoreLock(PVMCPUCC pVCpu);
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VMMDECL(VBOXSTRICTRC) IEMExecLots(PVMCPUCC pVCpu, uint32_t cMaxInstructions, uint32_t cPollRate, uint32_t *pcInstructions);
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/** Statistics returned by IEMExecForExits. */
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typedef struct IEMEXECFOREXITSTATS
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{
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uint32_t cInstructions;
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uint32_t cExits;
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uint32_t cMaxExitDistance;
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uint32_t cReserved;
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} IEMEXECFOREXITSTATS;
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/** Pointer to statistics returned by IEMExecForExits. */
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typedef IEMEXECFOREXITSTATS *PIEMEXECFOREXITSTATS;
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VMMDECL(VBOXSTRICTRC) IEMExecForExits(PVMCPUCC pVCpu, uint32_t fWillExit, uint32_t cMinInstructions, uint32_t cMaxInstructions,
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uint32_t cMaxInstructionsWithoutExits, PIEMEXECFOREXITSTATS pStats);
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VMMDECL(VBOXSTRICTRC) IEMInjectTrpmEvent(PVMCPUCC pVCpu);
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VMM_INT_DECL(VBOXSTRICTRC) IEMInjectTrap(PVMCPUCC pVCpu, uint8_t u8TrapNo, TRPMEVENT enmType, uint16_t uErrCode, RTGCPTR uCr2,
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uint8_t cbInstr);
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VMM_INT_DECL(int) IEMBreakpointSet(PVM pVM, RTGCPTR GCPtrBp);
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VMM_INT_DECL(int) IEMBreakpointClear(PVM pVM, RTGCPTR GCPtrBp);
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VMM_INT_DECL(void) IEMTlbInvalidateAll(PVMCPUCC pVCpu);
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VMM_INT_DECL(void) IEMTlbInvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCPtr);
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VMM_INT_DECL(void) IEMTlbInvalidateAllPhysical(PVMCPUCC pVCpu);
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VMM_INT_DECL(void) IEMTlbInvalidateAllPhysicalAllCpus(PVMCC pVM, VMCPUID idCpuCaller);
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VMM_INT_DECL(bool) IEMGetCurrentXcpt(PVMCPUCC pVCpu, uint8_t *puVector, uint32_t *pfFlags, uint32_t *puErr,
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uint64_t *puCr2);
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VMM_INT_DECL(IEMXCPTRAISE) IEMEvaluateRecursiveXcpt(PVMCPUCC pVCpu, uint32_t fPrevFlags, uint8_t uPrevVector, uint32_t fCurFlags,
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uint8_t uCurVector, PIEMXCPTRAISEINFO pXcptRaiseInfo);
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/** @name Given Instruction Interpreters
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* @{ */
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecStringIoWrite(PVMCPUCC pVCpu, uint8_t cbValue, IEMMODE enmAddrMode,
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bool fRepPrefix, uint8_t cbInstr, uint8_t iEffSeg, bool fIoChecked);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecStringIoRead(PVMCPUCC pVCpu, uint8_t cbValue, IEMMODE enmAddrMode,
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bool fRepPrefix, uint8_t cbInstr, bool fIoChecked);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedOut(PVMCPUCC pVCpu, uint8_t cbInstr, uint16_t u16Port, bool fImm, uint8_t cbReg);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedIn(PVMCPUCC pVCpu, uint8_t cbInstr, uint16_t u16Port, bool fImm, uint8_t cbReg);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMovCRxWrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iCrReg, uint8_t iGReg);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMovCRxRead(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iGReg, uint8_t iCrReg);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMovDRxWrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iDrReg, uint8_t iGReg);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMovDRxRead(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iGReg, uint8_t iDrReg);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedClts(PVMCPUCC pVCpu, uint8_t cbInstr);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedLmsw(PVMCPUCC pVCpu, uint8_t cbInstr, uint16_t uValue, RTGCPTR GCPtrEffDst);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedXsetbv(PVMCPUCC pVCpu, uint8_t cbInstr);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedWbinvd(PVMCPUCC pVCpu, uint8_t cbInstr);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvd(PVMCPUCC pVCpu, uint8_t cbInstr);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvlpg(PVMCPUCC pVCpu, uint8_t cbInstr, RTGCPTR GCPtrPage);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvpcid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDesc,
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uint64_t uType);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedCpuid(PVMCPUCC pVCpu, uint8_t cbInstr);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdpmc(PVMCPUCC pVCpu, uint8_t cbInstr);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdtsc(PVMCPUCC pVCpu, uint8_t cbInstr);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdtscp(PVMCPUCC pVCpu, uint8_t cbInstr);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdmsr(PVMCPUCC pVCpu, uint8_t cbInstr);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedWrmsr(PVMCPUCC pVCpu, uint8_t cbInstr);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMonitor(PVMCPUCC pVCpu, uint8_t cbInstr);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMwait(PVMCPUCC pVCpu, uint8_t cbInstr);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedHlt(PVMCPUCC pVCpu, uint8_t cbInstr);
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#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedClgi(PVMCPUCC pVCpu, uint8_t cbInstr);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedStgi(PVMCPUCC pVCpu, uint8_t cbInstr);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmload(PVMCPUCC pVCpu, uint8_t cbInstr);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmsave(PVMCPUCC pVCpu, uint8_t cbInstr);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvlpga(PVMCPUCC pVCpu, uint8_t cbInstr);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmrun(PVMCPUCC pVCpu, uint8_t cbInstr);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2);
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#endif
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#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
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VMM_INT_DECL(void) IEMReadVmxVmcsField(PCVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t *pu64Dst);
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VMM_INT_DECL(void) IEMWriteVmxVmcsField(PVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t u64Val);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVirtApicAccessMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Val, bool fWrite);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicWrite(PVMCPUCC pVCpu);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitPreemptTimer(PVMCPUCC pVCpu);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcpt(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcptNmi(PVMCPUCC pVCpu);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTripleFault(PVMCPUCC pVCpu);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitStartupIpi(PVMCPUCC pVCpu, uint8_t uVector);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTrapLike(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTaskSwitch(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicAccess(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t uExitQual);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmread(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmwrite(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrld(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrst(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmclear(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxon(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxoff(PVMCPUCC pVCpu, uint8_t cbInstr);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvvpid(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
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# ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvept(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitEptViolation(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo);
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VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitEptMisconfig(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr, PCVMXVEXITEVENTINFO pExitEventInfo);
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# endif
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#endif
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/** @} */
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/** @defgroup grp_iem_r3 The IEM Host Context Ring-3 API.
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* @{
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*/
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VMMR0_INT_DECL(int) IEMR0InitVM(PGVM pGVM);
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/** @} */
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/** @defgroup grp_iem_r3 The IEM Host Context Ring-3 API.
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* @{
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*/
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VMMR3DECL(int) IEMR3Init(PVM pVM);
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VMMR3DECL(int) IEMR3Term(PVM pVM);
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VMMR3DECL(void) IEMR3Relocate(PVM pVM);
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VMMR3_INT_DECL(VBOXSTRICTRC) IEMR3ProcessForceFlag(PVM pVM, PVMCPUCC pVCpu, VBOXSTRICTRC rcStrict);
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/** @} */
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/** @} */
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RT_C_DECLS_END
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#endif /* !VBOX_INCLUDED_vmm_iem_h */
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