summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--data/amdgpu.ids61
-rw-r--r--debian/changelog30
-rw-r--r--debian/control14
-rw-r--r--debian/patches/hurd-port.diff177
-rw-r--r--debian/patches/series1
-rwxr-xr-xdebian/rules2
-rw-r--r--include/drm/amdgpu_drm.h29
-rw-r--r--intel/i915_pciids.h21
-rw-r--r--intel/intel_chipset.c2
-rw-r--r--man/drm-kms.xml3
-rw-r--r--man/drm-memory.xml3
-rw-r--r--man/drm.xml3
-rw-r--r--man/drmAvailable.xml3
-rw-r--r--man/drmHandleEvent.xml3
-rw-r--r--man/drmModeGetResources.xml3
-rw-r--r--meson.build2
-rw-r--r--tests/amdgpu/amdgpu_test.c13
-rw-r--r--tests/amdgpu/amdgpu_test.h53
-rw-r--r--tests/amdgpu/basic_tests.c224
-rw-r--r--tests/amdgpu/cs_tests.c6
-rw-r--r--tests/amdgpu/deadlock_tests.c10
-rw-r--r--tests/amdgpu/decode_messages.h4
-rw-r--r--tests/amdgpu/meson.build2
-rw-r--r--tests/amdgpu/security_tests.c481
-rw-r--r--tests/amdgpu/vce_tests.c6
-rw-r--r--tests/amdgpu/vcn_tests.c49
-rw-r--r--tests/amdgpu/vm_tests.c12
-rw-r--r--tests/util/kms.c2
-rw-r--r--xf86drm.c30
29 files changed, 1179 insertions, 70 deletions
diff --git a/data/amdgpu.ids b/data/amdgpu.ids
index 6fc6858..d0de378 100644
--- a/data/amdgpu.ids
+++ b/data/amdgpu.ids
@@ -4,10 +4,67 @@
# device_id, revision_id, product_name <-- single tab after comma
1.0.0
+15DD, C3, AMD Radeon(TM) Vega 3 Graphics
+15DD, CB, AMD Radeon(TM) Vega 3 Graphics
+15DD, CE, AMD Radeon(TM) Vega 3 Graphics
+15DD, D8, AMD Radeon(TM) Vega 3 Graphics
+15DD, CC, AMD Radeon(TM) Vega 6 Graphics
+15DD, D9, AMD Radeon(TM) Vega 6 Graphics
+15DD, C2, AMD Radeon(TM) Vega 8 Graphics
+15DD, C4, AMD Radeon(TM) Vega 8 Graphics
+15DD, C8, AMD Radeon(TM) Vega 8 Graphics
+15DD, CA, AMD Radeon(TM) Vega 8 Graphics
+15DD, D1, AMD Radeon(TM) Vega 8 Graphics
+15DD, D5, AMD Radeon(TM) Vega 8 Graphics
+15DD, D7, AMD Radeon(TM) Vega 8 Graphics
+15DD, C3, AMD Radeon(TM) Vega 10 Graphics
+15DD, D0, AMD Radeon(TM) Vega 10 Graphics
+15DD, C1, AMD Radeon(TM) Vega 11 Graphics
+15DD, C6, AMD Radeon(TM) Vega 11 Graphics
+15DD, C9, AMD Radeon(TM) Vega 11 Graphics
+15DD, D3, AMD Radeon(TM) Vega 11 Graphics
+15DD, D6, AMD Radeon(TM) Vega 11 Graphics
15DD, 81, AMD Ryzen Embedded V1807B with Radeon Vega Gfx
15DD, 82, AMD Ryzen Embedded V1756B with Radeon Vega Gfx
15DD, 83, AMD Ryzen Embedded V1605B with Radeon Vega Gfx
15DD, 85, AMD Ryzen Embedded V1202B with Radeon Vega Gfx
+15D8, 93, AMD Radeon(TM) Vega 1 Graphics
+15D8, C4, AMD Radeon(TM) Vega 3 Graphics
+15D8, C5, AMD Radeon(TM) Vega 3 Graphics
+15D8, CC, AMD Radeon(TM) Vega 3 Graphics
+15D8, CE, AMD Radeon(TM) Vega 3 Graphics
+15D8, CF, AMD Radeon(TM) Vega 3 Graphics
+15D8, D4, AMD Radeon(TM) Vega 3 Graphics
+15D8, DC, AMD Radeon(TM) Vega 3 Graphics
+15D8, DD, AMD Radeon(TM) Vega 3 Graphics
+15D8, DE, AMD Radeon(TM) Vega 3 Graphics
+15D8, DF, AMD Radeon(TM) Vega 3 Graphics
+15D8, E3, AMD Radeon(TM) Vega 3 Graphics
+15D8, E4, AMD Radeon(TM) Vega 3 Graphics
+15D8, A3, AMD Radeon(TM) Vega 6 Graphics
+15D8, B3, AMD Radeon(TM) Vega 6 Graphics
+15D8, C3, AMD Radeon(TM) Vega 6 Graphics
+15D8, D3, AMD Radeon(TM) Vega 6 Graphics
+15D8, A2, AMD Radeon(TM) Vega 8 Graphics
+15D8, B2, AMD Radeon(TM) Vega 8 Graphics
+15D8, C2, AMD Radeon(TM) Vega 8 Graphics
+15D8, C9, AMD Radeon(TM) Vega 8 Graphics
+15D8, CB, AMD Radeon(TM) Vega 8 Graphics
+15D8, D2, AMD Radeon(TM) Vega 8 Graphics
+15D8, D9, AMD Radeon(TM) Vega 8 Graphics
+15D8, DB, AMD Radeon(TM) Vega 8 Graphics
+15D8, A1, AMD Radeon(TM) Vega 10 Graphics
+15D8, B1, AMD Radeon(TM) Vega 10 Graphics
+15D8, C1, AMD Radeon(TM) Vega 10 Graphics
+15D8, D1, AMD Radeon(TM) Vega 10 Graphics
+15D8, C8, AMD Radeon(TM) Vega 11 Graphics
+15D8, CA, AMD Radeon(TM) Vega 11 Graphics
+15D8, D8, AMD Radeon(TM) Vega 11 Graphics
+15D8, DA, AMD Radeon(TM) Vega 11 Graphics
+15D8, 91, AMD Ryzen Embedded R1606G with Radeon Vega Gfx
+15D8, 92, AMD Ryzen Embedded R1505G with Radeon Vega Gfx
+15D8, CF, AMD Ryzen Embedded R1305G with Radeon Vega Gfx
+15D8, E4, AMD Ryzen Embedded R1102G with Radeon Vega Gfx
6600, 0, AMD Radeon HD 8600/8700M
6600, 81, AMD Radeon (TM) R7 M370
6601, 0, AMD Radeon (TM) HD 8500M/8700M
@@ -45,6 +102,7 @@
6665, 83, AMD Radeon (TM) R5 M320
6667, 0, AMD Radeon R5 M200 Series
666F, 0, AMD Radeon HD 8500M
+66A1, 06, AMD Radeon (TM) Pro VII
66AF, C1, AMD Radeon VII
6780, 0, ATI FirePro V (FireGL V) Graphics Adapter
678A, 0, ATI FirePro V (FireGL V) Graphics Adapter
@@ -181,6 +239,7 @@
6985, 00, AMD Radeon Pro WX3100
6987, 80, AMD Embedded Radeon E9171
6987, C0, Radeon 550X Series
+6987, C1, AMD Radeon RX 640
6987, C3, Radeon 540X Series
6995, 00, AMD Radeon Pro WX2100
6997, 00, Radeon Pro WX2100
@@ -206,6 +265,7 @@
7340, C1, Radeon RX 5500M
7340, C5, Radeon RX 5500 XT
7340, C7, Radeon RX 5500
+7340, CF, Radeon RX 5300
7341, 00, AMD Radeon Pro W5500
7347, 00, AMD Radeon Pro W5500M
9874, C4, AMD Radeon R7 Graphics
@@ -217,4 +277,5 @@
9874, 87, AMD Radeon R5 Graphics
9874, 85, AMD Radeon R6 Graphics
9874, 84, AMD Radeon R7 Graphics
+6FDF, E7, AMD Radeon RX 590 GME
6FDF, EF, AMD Radeon RX 580 2048SP
diff --git a/debian/changelog b/debian/changelog
index e39c2c9..020abfd 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,33 @@
+libdrm (2.4.103-1~progress5+u1) engywuck-backports; urgency=medium
+
+ * Uploading to engywuck-backports, remaining changes:
+ - Updating maintainer field.
+ - Updating uploaders field.
+ - Updating bugs field.
+ - Updating vcs fields.
+ * Merging upstream version 2.4.103.
+ * Merging debian version 2.4.103-1.
+
+ -- Daniel Baumann <daniel.baumann@progress-linux.org> Wed, 11 Nov 2020 07:13:24 +0100
+
+libdrm (2.4.103-1) unstable; urgency=medium
+
+ * New upstream release. (Closes: #970304)
+ * control, rules, hurd-port.diff: Add support for Hurd. (Closes:
+ #909436)
+
+ -- Timo Aaltonen <tjaalton@debian.org> Tue, 10 Nov 2020 19:51:20 +0200
+
+libdrm (2.4.102-1~progress5+u1) engywuck-backports; urgency=medium
+
+ * Uploading to engywuck-backports.
+ * Updating maintainer field.
+ * Updating uploaders field.
+ * Updating bugs field.
+ * Updating vcs fields.
+
+ -- Daniel Baumann <daniel.baumann@progress-linux.org> Tue, 01 Sep 2020 20:20:22 +0200
+
libdrm (2.4.102-1) unstable; urgency=medium
* New upstream release.
diff --git a/debian/control b/debian/control
index 2df4edf..2accbb6 100644
--- a/debian/control
+++ b/debian/control
@@ -27,10 +27,10 @@ Homepage: https://cgit.freedesktop.org/mesa/drm/
Package: libdrm-dev
Section: libdevel
-Architecture: linux-any kfreebsd-any
+Architecture: linux-any kfreebsd-any hurd-any
Depends:
libdrm2 (= ${binary:Version}),
- libdrm-intel1 (= ${binary:Version}) [amd64 i386 kfreebsd-amd64 kfreebsd-i386 x32],
+ libdrm-intel1 (= ${binary:Version}) [amd64 i386 kfreebsd-amd64 kfreebsd-i386 hurd-i386 x32],
libdrm-radeon1 (= ${binary:Version}),
libdrm-nouveau2 (= ${binary:Version}) [linux-any],
libdrm-amdgpu1 (= ${binary:Version}),
@@ -51,7 +51,7 @@ Description: Userspace interface to kernel DRM services -- development files
This package provides the development environment for libdrm.
Package: libdrm2
-Architecture: linux-any kfreebsd-any
+Architecture: linux-any kfreebsd-any hurd-any
Depends:
libdrm-common (>= ${source:Version}),
${shlibs:Depends},
@@ -100,7 +100,7 @@ Description: Testing tools from the libdrm project
Package: libdrm2-udeb
Package-Type: udeb
Section: debian-installer
-Architecture: linux-any kfreebsd-any
+Architecture: linux-any kfreebsd-any hurd-any
Depends:
${shlibs:Depends},
${misc:Depends},
@@ -108,7 +108,7 @@ Description: Userspace interface to kernel DRM services -- runtime
This is a udeb, or a microdeb, for the debian-installer.
Package: libdrm-intel1
-Architecture: amd64 i386 kfreebsd-amd64 kfreebsd-i386 x32
+Architecture: amd64 i386 kfreebsd-amd64 kfreebsd-i386 hurd-i386 x32
Depends:
${shlibs:Depends},
${misc:Depends},
@@ -135,7 +135,7 @@ Description: Userspace interface to nouveau-specific kernel DRM services -- runt
OpenGL drivers.
Package: libdrm-radeon1
-Architecture: linux-any kfreebsd-any
+Architecture: linux-any kfreebsd-any hurd-any
Depends:
${shlibs:Depends},
${misc:Depends},
@@ -205,7 +205,7 @@ Description: Userspace interface to tegra-specific kernel DRM services -- runtim
OpenGL drivers.
Package: libdrm-amdgpu1
-Architecture: linux-any kfreebsd-any
+Architecture: linux-any kfreebsd-any hurd-any
Depends:
${shlibs:Depends},
${misc:Depends},
diff --git a/debian/patches/hurd-port.diff b/debian/patches/hurd-port.diff
new file mode 100644
index 0000000..b5344dd
--- /dev/null
+++ b/debian/patches/hurd-port.diff
@@ -0,0 +1,177 @@
+--- a/include/drm/drm.h
++++ b/include/drm/drm.h
+@@ -42,6 +42,22 @@
+ #include <asm/ioctl.h>
+ typedef unsigned int drm_handle_t;
+
++#elif defined(__GNU__)
++
++#include <sys/types.h>
++#include <sys/ioctl.h>
++#include <mach/i386/ioccom.h>
++typedef __int8_t __s8;
++typedef __uint8_t __u8;
++typedef __int16_t __s16;
++typedef __uint16_t __u16;
++typedef __int32_t __s32;
++typedef __uint32_t __u32;
++typedef __int64_t __s64;
++typedef __uint64_t __u64;
++typedef size_t __kernel_size_t;
++typedef unsigned int drm_handle_t;
++
+ #else /* One of the BSDs */
+
+ #include <stdint.h>
+--- a/xf86drm.h
++++ b/xf86drm.h
+@@ -56,6 +56,16 @@ extern "C" {
+ #define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE
+ #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
+
++#elif defined(__GNU__)
++#include <mach/port.h>
++#include <hurd/ioctl.h>
++#define DRM_IOCTL_NR(n) ((n) & 0xff)
++#define DRM_IOC_VOID IOC_VOID
++#define DRM_IOC_READ IOC_OUT
++#define DRM_IOC_WRITE IOC_IN
++#define DRM_IOC_READWRITE IOC_INOUT
++#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
++
+ #else /* One of the *BSDs */
+
+ #include <sys/ioccom.h>
+--- a/xf86drm.c
++++ b/xf86drm.c
+@@ -2996,7 +2996,8 @@ static char *drmGetMinorNameForFD(int fd
+ return strdup(name);
+ #else
+ struct stat sbuf;
+- char buf[PATH_MAX + 1];
++ char *buf = NULL;
++ int len = 0;
+ const char *dev_name = drmGetDeviceName(type);
+ unsigned int maj, min;
+ int n;
+@@ -3013,11 +3014,18 @@ static char *drmGetMinorNameForFD(int fd
+ if (!dev_name)
+ return NULL;
+
+- n = snprintf(buf, sizeof(buf), dev_name, DRM_DIR_NAME, min);
+- if (n == -1 || n >= sizeof(buf))
++ len = snprintf(NULL, 0, dev_name, DRM_DIR_NAME, min);
++ if (len < 0)
+ return NULL;
++ len++;
++ buf = malloc(len);
++ n = snprintf(buf, len, dev_name, DRM_DIR_NAME, min);
++ if (n == -1 || n >= len) {
++ free(buf);
++ return NULL;
++ }
+
+- return strdup(buf);
++ return buf;
+ #endif
+ }
+
+@@ -3963,17 +3971,30 @@ process_device(drmDevicePtr *device, con
+ bool fetch_deviceinfo, uint32_t flags)
+ {
+ struct stat sbuf;
+- char node[PATH_MAX + 1];
++ char *node = NULL;
+ int node_type, subsystem_type;
++ int len = 0, n, ret = 0;
+ unsigned int maj, min;
+
+ node_type = drmGetNodeType(d_name);
+ if (node_type < 0)
+ return -1;
+
+- snprintf(node, PATH_MAX, "%s/%s", DRM_DIR_NAME, d_name);
+- if (stat(node, &sbuf))
++ len = snprintf(NULL, 0, "%s/%s", DRM_DIR_NAME, d_name);
++ if (len < 0)
++ return -1;
++ len++;
++ node = malloc(len);
++ n = snprintf(node, len, "%s/%s", DRM_DIR_NAME, d_name);
++ if (n == -1 || n >= len) {
++ free(node);
+ return -1;
++ }
++
++ if (stat(node, &sbuf)) {
++ free(node);
++ return -1;
++ }
+
+ maj = major(sbuf.st_rdev);
+ min = minor(sbuf.st_rdev);
+@@ -3988,18 +4009,27 @@ process_device(drmDevicePtr *device, con
+ switch (subsystem_type) {
+ case DRM_BUS_PCI:
+ case DRM_BUS_VIRTIO:
+- return drmProcessPciDevice(device, node, node_type, maj, min,
++ ret = drmProcessPciDevice(device, node, node_type, maj, min,
+ fetch_deviceinfo, flags);
++ free(node);
++ return ret;
+ case DRM_BUS_USB:
+- return drmProcessUsbDevice(device, node, node_type, maj, min,
++ ret = drmProcessUsbDevice(device, node, node_type, maj, min,
+ fetch_deviceinfo, flags);
++ free(node);
++ return ret;
+ case DRM_BUS_PLATFORM:
+- return drmProcessPlatformDevice(device, node, node_type, maj, min,
++ ret = drmProcessPlatformDevice(device, node, node_type, maj, min,
+ fetch_deviceinfo, flags);
++ free(node);
++ return ret;
+ case DRM_BUS_HOST1X:
+- return drmProcessHost1xDevice(device, node, node_type, maj, min,
++ ret = drmProcessHost1xDevice(device, node, node_type, maj, min,
+ fetch_deviceinfo, flags);
++ free(node);
++ return ret;
+ default:
++ free(node);
+ return -1;
+ }
+ }
+@@ -4322,10 +4352,10 @@ drm_public char *drmGetDeviceNameFromFd2
+ return drmGetDeviceNameFromFd(fd);
+ #else
+ struct stat sbuf;
+- char node[PATH_MAX + 1];
++ char *node = NULL;
+ const char *dev_name;
+ int node_type;
+- int maj, min, n;
++ int maj, min, n, len = 0;
+
+ if (fstat(fd, &sbuf))
+ return NULL;
+@@ -4344,11 +4374,16 @@ drm_public char *drmGetDeviceNameFromFd2
+ if (!dev_name)
+ return NULL;
+
+- n = snprintf(node, PATH_MAX, dev_name, DRM_DIR_NAME, min);
+- if (n == -1 || n >= PATH_MAX)
++ len = snprintf(NULL, 0, dev_name, DRM_DIR_NAME, min);
++ if (len < 0)
++ return NULL;
++ len++;
++ node = malloc(len);
++ n = snprintf(node, len, dev_name, DRM_DIR_NAME, min);
++ if (n == -1 || n >= len)
+ return NULL;
+
+- return strdup(node);
++ return node;
+ #endif
+ }
+
diff --git a/debian/patches/series b/debian/patches/series
index 8ca2297..a6cc732 100644
--- a/debian/patches/series
+++ b/debian/patches/series
@@ -1 +1,2 @@
01_default_perms.diff
+hurd-port.diff
diff --git a/debian/rules b/debian/rules
index a0f2097..4148fa5 100755
--- a/debian/rules
+++ b/debian/rules
@@ -31,7 +31,7 @@ endif
# Intel is only on x86:
ifneq (,$(filter amd64 i386,$(DEB_HOST_ARCH_CPU)))
-ifneq (,$(filter linux kfreebsd,$(DEB_HOST_ARCH_OS)))
+ifneq (,$(filter linux kfreebsd hurd,$(DEB_HOST_ARCH_OS)))
INTEL = yes
endif
endif
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index 4fe35d6..4e873dc 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -125,13 +125,19 @@ extern "C" {
/* Flag that BO sharing will be explicitly synchronized */
#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)
/* Flag that indicates allocating MQD gart on GFX9, where the mtype
- * for the second page onward should be set to NC.
+ * for the second page onward should be set to NC. It should never
+ * be used by user space applications.
*/
-#define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8)
+#define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8)
/* Flag that BO may contain sensitive data that must be wiped before
* releasing the memory
*/
#define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9)
+/* Flag that BO will be encrypted and that the TMZ bit should be
+ * set in the PTEs when mapping this buffer via GPUVM or
+ * accessing it with various hw blocks
+ */
+#define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10)
struct drm_amdgpu_gem_create_in {
/** the requested memory size */
@@ -345,6 +351,10 @@ struct drm_amdgpu_gem_userptr {
#define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF
#define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43
#define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1
+#define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44
+#define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1
+#define AMDGPU_TILING_SCANOUT_SHIFT 63
+#define AMDGPU_TILING_SCANOUT_MASK 0x1
/* Set/Get helpers for tiling flags. */
#define AMDGPU_TILING_SET(field, value) \
@@ -500,6 +510,8 @@ struct drm_amdgpu_gem_op {
#define AMDGPU_VM_MTYPE_CC (3 << 5)
/* Use UC MTYPE instead of default MTYPE */
#define AMDGPU_VM_MTYPE_UC (4 << 5)
+/* Use RW MTYPE instead of default MTYPE */
+#define AMDGPU_VM_MTYPE_RW (5 << 5)
struct drm_amdgpu_gem_va {
/** GEM object handle */
@@ -552,7 +564,7 @@ struct drm_amdgpu_cs_in {
/** Handle of resource list associated with CS */
__u32 bo_list_handle;
__u32 num_chunks;
- __u32 _pad;
+ __u32 flags;
/** this points to __u64 * which point to cs chunks */
__u64 chunks;
};
@@ -586,6 +598,14 @@ union drm_amdgpu_cs {
*/
#define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)
+/* Flag the IB as secure (TMZ)
+ */
+#define AMDGPU_IB_FLAGS_SECURE (1 << 5)
+
+/* Tell KMD to flush and invalidate caches
+ */
+#define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6)
+
struct drm_amdgpu_cs_chunk_ib {
__u32 _pad;
/** AMDGPU_IB_FLAG_* */
@@ -701,6 +721,9 @@ struct drm_amdgpu_cs_chunk_data {
/* Subquery id: Query DMCU firmware version */
#define AMDGPU_INFO_FW_DMCU 0x12
#define AMDGPU_INFO_FW_TA 0x13
+ /* Subquery id: Query DMCUB firmware version */
+ #define AMDGPU_INFO_FW_DMCUB 0x14
+
/* number of bytes moved for TTM migration */
#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
/* the used VRAM size */
diff --git a/intel/i915_pciids.h b/intel/i915_pciids.h
index 662d835..8e7ae30 100644
--- a/intel/i915_pciids.h
+++ b/intel/i915_pciids.h
@@ -258,9 +258,7 @@
INTEL_VGA_DEVICE(0x0f30, info), \
INTEL_VGA_DEVICE(0x0f31, info), \
INTEL_VGA_DEVICE(0x0f32, info), \
- INTEL_VGA_DEVICE(0x0f33, info), \
- INTEL_VGA_DEVICE(0x0157, info), \
- INTEL_VGA_DEVICE(0x0155, info)
+ INTEL_VGA_DEVICE(0x0f33, info)
#define INTEL_BDW_ULT_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
@@ -588,7 +586,11 @@
INTEL_VGA_DEVICE(0x4551, info), \
INTEL_VGA_DEVICE(0x4541, info), \
INTEL_VGA_DEVICE(0x4E71, info), \
+ INTEL_VGA_DEVICE(0x4557, info), \
+ INTEL_VGA_DEVICE(0x4555, info), \
INTEL_VGA_DEVICE(0x4E61, info), \
+ INTEL_VGA_DEVICE(0x4E57, info), \
+ INTEL_VGA_DEVICE(0x4E55, info), \
INTEL_VGA_DEVICE(0x4E51, info)
/* TGL */
@@ -605,4 +607,17 @@
INTEL_VGA_DEVICE(0x9AD9, info), \
INTEL_VGA_DEVICE(0x9AF8, info)
+/* RKL */
+#define INTEL_RKL_IDS(info) \
+ INTEL_VGA_DEVICE(0x4C80, info), \
+ INTEL_VGA_DEVICE(0x4C8A, info), \
+ INTEL_VGA_DEVICE(0x4C8B, info), \
+ INTEL_VGA_DEVICE(0x4C8C, info), \
+ INTEL_VGA_DEVICE(0x4C90, info), \
+ INTEL_VGA_DEVICE(0x4C9A, info)
+
+/* DG1 */
+#define INTEL_DG1_IDS(info) \
+ INTEL_VGA_DEVICE(0x4905, info)
+
#endif /* _I915_PCIIDS_H */
diff --git a/intel/intel_chipset.c b/intel/intel_chipset.c
index f6e37ee..439db3e 100644
--- a/intel/intel_chipset.c
+++ b/intel/intel_chipset.c
@@ -35,6 +35,8 @@ static const struct pci_device {
uint16_t gen;
} pciids[] = {
/* Keep ids sorted by gen; latest gen first */
+ INTEL_RKL_IDS(12),
+ INTEL_DG1_IDS(12),
INTEL_TGL_12_IDS(12),
INTEL_EHL_IDS(11),
INTEL_ICL_11_IDS(11),
diff --git a/man/drm-kms.xml b/man/drm-kms.xml
index eb04c26..888df66 100644
--- a/man/drm-kms.xml
+++ b/man/drm-kms.xml
@@ -309,8 +309,7 @@ static int modeset_find_crtc(int fd, drmModeRes *res, drmModeConnector *conn)
<refsect1>
<title>Reporting Bugs</title>
<para>Bugs in this manual should be reported to
- https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&amp;component=libdrm
- under the "DRI" product, component "libdrm"</para>
+ https://gitlab.freedesktop.org/mesa/drm/-/issues</para>
</refsect1>
<refsect1>
diff --git a/man/drm-memory.xml b/man/drm-memory.xml
index 3aa7cf2..33c05af 100644
--- a/man/drm-memory.xml
+++ b/man/drm-memory.xml
@@ -410,8 +410,7 @@ memset(map, 0, creq.size);
<refsect1>
<title>Reporting Bugs</title>
<para>Bugs in this manual should be reported to
- https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&amp;component=libdrm
- under the "DRI" product, component "libdrm"</para>
+ https://gitlab.freedesktop.org/mesa/drm/-/issues</para>
</refsect1>
<refsect1>
diff --git a/man/drm.xml b/man/drm.xml
index dbb67ad..e2e93ab 100644
--- a/man/drm.xml
+++ b/man/drm.xml
@@ -119,8 +119,7 @@
<refsect1>
<title>Reporting Bugs</title>
<para>Bugs in this manual should be reported to
- https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&amp;component=libdrm
- under the "DRI" product, component "libdrm"</para>
+ https://gitlab.freedesktop.org/mesa/drm/-/issues</para>
</refsect1>
<refsect1>
diff --git a/man/drmAvailable.xml b/man/drmAvailable.xml
index 1e5d787..2ea5b4d 100644
--- a/man/drmAvailable.xml
+++ b/man/drmAvailable.xml
@@ -61,8 +61,7 @@
<refsect1>
<title>Reporting Bugs</title>
<para>Bugs in this function should be reported to
- https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&amp;component=libdrm
- under the "DRI" product, component "libdrm"</para>
+ https://gitlab.freedesktop.org/mesa/drm/-/issues</para>
</refsect1>
<refsect1>
diff --git a/man/drmHandleEvent.xml b/man/drmHandleEvent.xml
index 8330442..0ca7494 100644
--- a/man/drmHandleEvent.xml
+++ b/man/drmHandleEvent.xml
@@ -86,8 +86,7 @@ typedef struct _drmEventContext {
<refsect1>
<title>Reporting Bugs</title>
<para>Bugs in this function should be reported to
- https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&amp;component=libdrm
- under the "DRI" product, component "libdrm"</para>
+ https://gitlab.freedesktop.org/mesa/drm/-/issues</para>
</refsect1>
<refsect1>
diff --git a/man/drmModeGetResources.xml b/man/drmModeGetResources.xml
index 0ab6a68..64a711f 100644
--- a/man/drmModeGetResources.xml
+++ b/man/drmModeGetResources.xml
@@ -116,8 +116,7 @@ typedef struct _drmModeRes {
<refsect1>
<title>Reporting Bugs</title>
<para>Bugs in this function should be reported to
- https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&amp;component=libdrm
- under the "DRI" product, component "libdrm"</para>
+ https://gitlab.freedesktop.org/mesa/drm/-/issues</para>
</refsect1>
<refsect1>
diff --git a/meson.build b/meson.build
index 831c883..5cf8e04 100644
--- a/meson.build
+++ b/meson.build
@@ -21,7 +21,7 @@
project(
'libdrm',
['c'],
- version : '2.4.102',
+ version : '2.4.103',
license : 'MIT',
meson_version : '>= 0.43',
default_options : ['buildtype=debugoptimized', 'c_std=gnu99'],
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index 47e1676..8c86767 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -58,6 +58,7 @@
#define VM_TESTS_STR "VM Tests"
#define RAS_TESTS_STR "RAS Tests"
#define SYNCOBJ_TIMELINE_TESTS_STR "SYNCOBJ TIMELINE Tests"
+#define SECURITY_TESTS_STR "Security Tests"
/**
* Open handles for amdgpu devices
@@ -130,6 +131,12 @@ static CU_SuiteInfo suites[] = {
.pCleanupFunc = suite_syncobj_timeline_tests_clean,
.pTests = syncobj_timeline_tests,
},
+ {
+ .pName = SECURITY_TESTS_STR,
+ .pInitFunc = suite_security_tests_init,
+ .pCleanupFunc = suite_security_tests_clean,
+ .pTests = security_tests,
+ },
CU_SUITE_INFO_NULL,
};
@@ -149,7 +156,7 @@ static CU_BOOL always_active()
static Suites_Active_Status suites_active_stat[] = {
{
.pName = BASIC_TESTS_STR,
- .pActive = always_active,
+ .pActive = suite_basic_tests_enable,
},
{
.pName = BO_TESTS_STR,
@@ -187,6 +194,10 @@ static Suites_Active_Status suites_active_stat[] = {
.pName = SYNCOBJ_TIMELINE_TESTS_STR,
.pActive = suite_syncobj_timeline_tests_enable,
},
+ {
+ .pName = SECURITY_TESTS_STR,
+ .pActive = suite_security_tests_enable,
+ },
};
diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
index f549225..98cec69 100644
--- a/tests/amdgpu/amdgpu_test.h
+++ b/tests/amdgpu/amdgpu_test.h
@@ -55,6 +55,11 @@ int suite_basic_tests_init();
int suite_basic_tests_clean();
/**
+ * Decide if the suite is enabled by default or not.
+ */
+CU_BOOL suite_basic_tests_enable(void);
+
+/**
* Tests in basic test suite
*/
extern CU_TestInfo basic_tests[];
@@ -243,6 +248,32 @@ void amdgpu_memcpy_draw_test(amdgpu_device_handle device_handle, uint32_t ring,
void amdgpu_memcpy_draw_hang_slow_test(amdgpu_device_handle device_handle, uint32_t ring);
/**
+ * Initialize security test suite
+ */
+int suite_security_tests_init();
+
+/**
+ * Deinitialize security test suite
+ */
+int suite_security_tests_clean();
+
+/**
+ * Decide if the suite is enabled by default or not.
+ */
+CU_BOOL suite_security_tests_enable(void);
+
+/**
+ * Tests in security test suite
+ */
+extern CU_TestInfo security_tests[];
+
+extern void
+amdgpu_command_submission_write_linear_helper_with_secure(amdgpu_device_handle
+ device,
+ unsigned ip_type,
+ bool secure);
+
+/**
* Helper functions
*/
static inline amdgpu_bo_handle gpu_mem_alloc(
@@ -418,4 +449,26 @@ static inline CU_ErrorCode amdgpu_set_test_active(const char *suite_name,
return r;
}
+static inline bool asic_is_arcturus(uint32_t asic_id)
+{
+ switch(asic_id) {
+ /* Arcturus asic DID */
+ case 0x738C:
+ case 0x7388:
+ case 0x738E:
+ return true;
+ default:
+ return false;
+ }
+}
+
+void amdgpu_test_exec_cs_helper_raw(amdgpu_device_handle device_handle,
+ amdgpu_context_handle context_handle,
+ unsigned ip_type, int instance, int pm4_dw,
+ uint32_t *pm4_src, int res_cnt,
+ amdgpu_bo_handle *resources,
+ struct amdgpu_cs_ib_info *ib_info,
+ struct amdgpu_cs_request *ibs_request,
+ bool secure);
+
#endif /* #ifdef _AMDGPU_TEST_H_ */
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index 57496c8..dc9ed94 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -39,6 +39,7 @@
#include "amdgpu_test.h"
#include "amdgpu_drm.h"
+#include "amdgpu_internal.h"
#include "util_math.h"
static amdgpu_device_handle device_handle;
@@ -69,7 +70,7 @@ static void amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle,
int res_cnt, amdgpu_bo_handle *resources,
struct amdgpu_cs_ib_info *ib_info,
struct amdgpu_cs_request *ibs_request);
-
+
CU_TestInfo basic_tests[] = {
{ "Query Info Test", amdgpu_query_info_test },
{ "Userptr Test", amdgpu_userptr_test },
@@ -106,6 +107,20 @@ CU_TestInfo basic_tests[] = {
#define SDMA_OPCODE_COPY 1
# define SDMA_COPY_SUB_OPCODE_LINEAR 0
+#define SDMA_OPCODE_ATOMIC 10
+# define SDMA_ATOMIC_LOOP(x) ((x) << 0)
+ /* 0 - single_pass_atomic.
+ * 1 - loop_until_compare_satisfied.
+ */
+# define SDMA_ATOMIC_TMZ(x) ((x) << 2)
+ /* 0 - non-TMZ.
+ * 1 - TMZ.
+ */
+# define SDMA_ATOMIC_OPCODE(x) ((x) << 9)
+ /* TC_OP_ATOMIC_CMPSWAP_RTN_32 0x00000008
+ * same as Packet 3
+ */
+
#define GFX_COMPUTE_NOP 0xffff1000
#define SDMA_NOP 0x0
@@ -157,6 +172,20 @@ CU_TestInfo basic_tests[] = {
* 2 - ce
*/
+#define PACKET3_ATOMIC_MEM 0x1E
+#define TC_OP_ATOMIC_CMPSWAP_RTN_32 0x00000008
+#define ATOMIC_MEM_COMMAND(x) ((x) << 8)
+ /* 0 - single_pass_atomic.
+ * 1 - loop_until_compare_satisfied.
+ */
+#define ATOMIC_MEM_CACHEPOLICAY(x) ((x) << 25)
+ /* 0 - lru.
+ * 1 - stream.
+ */
+#define ATOMIC_MEM_ENGINESEL(x) ((x) << 30)
+ /* 0 - micro_engine.
+ */
+
#define PACKET3_DMA_DATA 0x50
/* 1. header
* 2. CONTROL
@@ -586,6 +615,43 @@ int amdgpu_bo_alloc_and_map_raw(amdgpu_device_handle dev, unsigned size,
+CU_BOOL suite_basic_tests_enable(void)
+{
+ uint32_t asic_id;
+
+ if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
+ &minor_version, &device_handle))
+ return CU_FALSE;
+
+ asic_id = device_handle->info.asic_id;
+
+ if (amdgpu_device_deinitialize(device_handle))
+ return CU_FALSE;
+
+ /* disable gfx engine basic test cases for Arturus due to no CPG */
+ if (asic_is_arcturus(asic_id)) {
+ if (amdgpu_set_test_active("Basic Tests",
+ "Command submission Test (GFX)",
+ CU_FALSE))
+ fprintf(stderr, "test deactivation failed - %s\n",
+ CU_get_error_msg());
+
+ if (amdgpu_set_test_active("Basic Tests",
+ "Command submission Test (Multi-Fence)",
+ CU_FALSE))
+ fprintf(stderr, "test deactivation failed - %s\n",
+ CU_get_error_msg());
+
+ if (amdgpu_set_test_active("Basic Tests",
+ "Sync dependency Test",
+ CU_FALSE))
+ fprintf(stderr, "test deactivation failed - %s\n",
+ CU_get_error_msg());
+ }
+
+ return CU_TRUE;
+}
+
int suite_basic_tests_init(void)
{
struct amdgpu_gpu_info gpu_info = {0};
@@ -1232,12 +1298,15 @@ static void amdgpu_command_submission_compute(void)
* pm4_src, resources, ib_info, and ibs_request
* submit command stream described in ibs_request and wait for this IB accomplished
*/
-static void amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle,
- unsigned ip_type,
- int instance, int pm4_dw, uint32_t *pm4_src,
- int res_cnt, amdgpu_bo_handle *resources,
- struct amdgpu_cs_ib_info *ib_info,
- struct amdgpu_cs_request *ibs_request)
+void
+amdgpu_test_exec_cs_helper_raw(amdgpu_device_handle device_handle,
+ amdgpu_context_handle context_handle,
+ unsigned ip_type, int instance, int pm4_dw,
+ uint32_t *pm4_src, int res_cnt,
+ amdgpu_bo_handle *resources,
+ struct amdgpu_cs_ib_info *ib_info,
+ struct amdgpu_cs_request *ibs_request,
+ bool secure)
{
int r;
uint32_t expired;
@@ -1269,6 +1338,8 @@ static void amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle,
ib_info->ib_mc_address = ib_result_mc_address;
ib_info->size = pm4_dw;
+ if (secure)
+ ib_info->flags |= AMDGPU_IB_FLAGS_SECURE;
ibs_request->ip_type = ip_type;
ibs_request->ring = instance;
@@ -1310,7 +1381,24 @@ static void amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle,
CU_ASSERT_EQUAL(r, 0);
}
-static void amdgpu_command_submission_write_linear_helper(unsigned ip_type)
+static void
+amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle,
+ unsigned ip_type, int instance, int pm4_dw,
+ uint32_t *pm4_src, int res_cnt,
+ amdgpu_bo_handle *resources,
+ struct amdgpu_cs_ib_info *ib_info,
+ struct amdgpu_cs_request *ibs_request)
+{
+ amdgpu_test_exec_cs_helper_raw(device_handle, context_handle,
+ ip_type, instance, pm4_dw, pm4_src,
+ res_cnt, resources, ib_info,
+ ibs_request, false);
+}
+
+void
+amdgpu_command_submission_write_linear_helper_with_secure(amdgpu_device_handle
+ device, unsigned
+ ip_type, bool secure)
{
const int sdma_write_length = 128;
const int pm4_dw = 256;
@@ -1322,6 +1410,7 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type)
struct amdgpu_cs_request *ibs_request;
uint64_t bo_mc;
volatile uint32_t *bo_cpu;
+ uint32_t bo_cpu_origin;
int i, j, r, loop, ring_id;
uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC};
amdgpu_va_handle va_handle;
@@ -1336,10 +1425,14 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type)
ibs_request = calloc(1, sizeof(*ibs_request));
CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
- r = amdgpu_query_hw_ip_info(device_handle, ip_type, 0, &hw_ip_info);
+ r = amdgpu_query_hw_ip_info(device, ip_type, 0, &hw_ip_info);
CU_ASSERT_EQUAL(r, 0);
- r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+ for (i = 0; secure && (i < 2); i++)
+ gtt_flags[i] |= AMDGPU_GEM_CREATE_ENCRYPTED;
+
+ r = amdgpu_cs_ctx_create(device, &context_handle);
+
CU_ASSERT_EQUAL(r, 0);
/* prepare resource */
@@ -1350,7 +1443,7 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type)
loop = 0;
while(loop < 2) {
/* allocate UC bo for sDMA use */
- r = amdgpu_bo_alloc_and_map(device_handle,
+ r = amdgpu_bo_alloc_and_map(device,
sdma_write_length * sizeof(uint32_t),
4096, AMDGPU_GEM_DOMAIN_GTT,
gtt_flags[loop], &bo, (void**)&bo_cpu,
@@ -1370,8 +1463,9 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type)
sdma_write_length);
else
pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
- SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
- pm4[i++] = 0xffffffff & bo_mc;
+ SDMA_WRITE_SUB_OPCODE_LINEAR,
+ secure ? SDMA_ATOMIC_TMZ(1) : 0);
+ pm4[i++] = 0xfffffffc & bo_mc;
pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
if (family_id >= AMDGPU_FAMILY_AI)
pm4[i++] = sdma_write_length - 1;
@@ -1389,16 +1483,99 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type)
pm4[i++] = 0xdeadbeaf;
}
- amdgpu_test_exec_cs_helper(context_handle,
- ip_type, ring_id,
- i, pm4,
- 1, resources,
- ib_info, ibs_request);
+ amdgpu_test_exec_cs_helper_raw(device, context_handle,
+ ip_type, ring_id, i, pm4,
+ 1, resources, ib_info,
+ ibs_request, secure);
/* verify if SDMA test result meets with expected */
i = 0;
- while(i < sdma_write_length) {
- CU_ASSERT_EQUAL(bo_cpu[i++], 0xdeadbeaf);
+ if (!secure) {
+ while(i < sdma_write_length) {
+ CU_ASSERT_EQUAL(bo_cpu[i++], 0xdeadbeaf);
+ }
+ } else if (ip_type == AMDGPU_HW_IP_GFX) {
+ memset((void*)pm4, 0, pm4_dw * sizeof(uint32_t));
+ pm4[i++] = PACKET3(PACKET3_ATOMIC_MEM, 7);
+ /* atomic opcode for 32b w/ RTN and ATOMIC_SWAPCMP_RTN
+ * command, 1-loop_until_compare_satisfied.
+ * single_pass_atomic, 0-lru
+ * engine_sel, 0-micro_engine
+ */
+ pm4[i++] = (TC_OP_ATOMIC_CMPSWAP_RTN_32 |
+ ATOMIC_MEM_COMMAND(1) |
+ ATOMIC_MEM_CACHEPOLICAY(0) |
+ ATOMIC_MEM_ENGINESEL(0));
+ pm4[i++] = 0xfffffffc & bo_mc;
+ pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
+ pm4[i++] = 0x12345678;
+ pm4[i++] = 0x0;
+ pm4[i++] = 0xdeadbeaf;
+ pm4[i++] = 0x0;
+ pm4[i++] = 0x100;
+ amdgpu_test_exec_cs_helper_raw(device, context_handle,
+ ip_type, ring_id, i, pm4,
+ 1, resources, ib_info,
+ ibs_request, true);
+ } else if (ip_type == AMDGPU_HW_IP_DMA) {
+ /* restore the bo_cpu to compare */
+ bo_cpu_origin = bo_cpu[0];
+ memset((void*)pm4, 0, pm4_dw * sizeof(uint32_t));
+ /* atomic opcode for 32b w/ RTN and ATOMIC_SWAPCMP_RTN
+ * loop, 1-loop_until_compare_satisfied.
+ * single_pass_atomic, 0-lru
+ */
+ pm4[i++] = SDMA_PACKET(SDMA_OPCODE_ATOMIC,
+ 0,
+ SDMA_ATOMIC_LOOP(1) |
+ SDMA_ATOMIC_TMZ(1) |
+ SDMA_ATOMIC_OPCODE(TC_OP_ATOMIC_CMPSWAP_RTN_32));
+ pm4[i++] = 0xfffffffc & bo_mc;
+ pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
+ pm4[i++] = 0x12345678;
+ pm4[i++] = 0x0;
+ pm4[i++] = 0xdeadbeaf;
+ pm4[i++] = 0x0;
+ pm4[i++] = 0x100;
+ amdgpu_test_exec_cs_helper_raw(device, context_handle,
+ ip_type, ring_id, i, pm4,
+ 1, resources, ib_info,
+ ibs_request, true);
+ /* DMA's atomic behavir is unlike GFX
+ * If the comparing data is not equal to destination data,
+ * For GFX, loop again till gfx timeout(system hang).
+ * For DMA, loop again till timer expired and then send interrupt.
+ * So testcase can't use interrupt mechanism.
+ * We take another way to verify. When the comparing data is not
+ * equal to destination data, overwrite the source data to the destination
+ * buffer. Otherwise, original destination data unchanged.
+ * So if the bo_cpu data is overwritten, the result is passed.
+ */
+ CU_ASSERT_NOT_EQUAL(bo_cpu[0], bo_cpu_origin);
+
+ /* compare again for the case of dest_data != cmp_data */
+ i = 0;
+ /* restore again, here dest_data should be */
+ bo_cpu_origin = bo_cpu[0];
+ memset((void*)pm4, 0, pm4_dw * sizeof(uint32_t));
+ pm4[i++] = SDMA_PACKET(SDMA_OPCODE_ATOMIC,
+ 0,
+ SDMA_ATOMIC_LOOP(1) |
+ SDMA_ATOMIC_TMZ(1) |
+ SDMA_ATOMIC_OPCODE(TC_OP_ATOMIC_CMPSWAP_RTN_32));
+ pm4[i++] = 0xfffffffc & bo_mc;
+ pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
+ pm4[i++] = 0x87654321;
+ pm4[i++] = 0x0;
+ pm4[i++] = 0xdeadbeaf;
+ pm4[i++] = 0x0;
+ pm4[i++] = 0x100;
+ amdgpu_test_exec_cs_helper_raw(device, context_handle,
+ ip_type, ring_id, i, pm4,
+ 1, resources, ib_info,
+ ibs_request, true);
+ /* here bo_cpu[0] should be unchanged, still is 0x12345678, otherwise failed*/
+ CU_ASSERT_EQUAL(bo_cpu[0], bo_cpu_origin);
}
r = amdgpu_bo_unmap_and_free(bo, va_handle, bo_mc,
@@ -1418,6 +1595,13 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type)
CU_ASSERT_EQUAL(r, 0);
}
+static void amdgpu_command_submission_write_linear_helper(unsigned ip_type)
+{
+ amdgpu_command_submission_write_linear_helper_with_secure(device_handle,
+ ip_type,
+ false);
+}
+
static void amdgpu_command_submission_sdma_write_linear(void)
{
amdgpu_command_submission_write_linear_helper(AMDGPU_HW_IP_DMA);
diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c
index ae4f65f..10124c1 100644
--- a/tests/amdgpu/cs_tests.c
+++ b/tests/amdgpu/cs_tests.c
@@ -64,17 +64,21 @@ CU_TestInfo cs_tests[] = {
CU_BOOL suite_cs_tests_enable(void)
{
+ uint32_t asic_id;
+
if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
&minor_version, &device_handle))
return CU_FALSE;
family_id = device_handle->info.family_id;
+ asic_id = device_handle->info.asic_id;
if (amdgpu_device_deinitialize(device_handle))
return CU_FALSE;
- if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) {
+ if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI ||
+ asic_is_arcturus(asic_id)) {
printf("\n\nThe ASIC NOT support UVD, suite disabled\n");
return CU_FALSE;
}
diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c
index a18d578..248cc33 100644
--- a/tests/amdgpu/deadlock_tests.c
+++ b/tests/amdgpu/deadlock_tests.c
@@ -124,6 +124,7 @@ static void amdgpu_draw_hang_slow_gfx(void);
CU_BOOL suite_deadlock_tests_enable(void)
{
CU_BOOL enable = CU_TRUE;
+ uint32_t asic_id;
if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
&minor_version, &device_handle))
@@ -140,6 +141,15 @@ CU_BOOL suite_deadlock_tests_enable(void)
enable = CU_FALSE;
}
+ asic_id = device_handle->info.asic_id;
+ if (asic_is_arcturus(asic_id)) {
+ if (amdgpu_set_test_active("Deadlock Tests",
+ "gfx ring block test (set amdgpu.lockup_timeout=50)",
+ CU_FALSE))
+ fprintf(stderr, "test deactivation failed - %s\n",
+ CU_get_error_msg());
+ }
+
if (device_handle->info.family_id >= AMDGPU_FAMILY_AI)
use_uc_mtype = 1;
diff --git a/tests/amdgpu/decode_messages.h b/tests/amdgpu/decode_messages.h
index 52c1cbb..ee1deb4 100644
--- a/tests/amdgpu/decode_messages.h
+++ b/tests/amdgpu/decode_messages.h
@@ -361,7 +361,7 @@ static const uint8_t uvd_decode_msg[] = {
};
static const uint8_t avc_decode_msg[] = {
- 0x02,0x00,0x00,0x00,0x1e,0x00,0x00,0x00,0x05,0x00,0x00,0x00,0x88,0x00,0x00,0x00,
+ 0x02,0x00,0x00,0x00,0x1e,0x00,0x00,0x00,0x85,0x00,0x00,0x00,0x88,0x00,0x00,0x00,
0x01,0x00,0x00,0x01,0x00,0x03,0x02,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
@@ -826,7 +826,7 @@ static const uint8_t vcn_dec_decode_msg[] = {
0x28,0x00,0x00,0x00,0x90,0x06,0x00,0x00,0x02,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
0x03,0x00,0x44,0x40,0x01,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x38,0x00,0x00,0x00,
0xb4,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0xec,0x00,0x00,0x00,
- 0x5c,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+ 0x5c,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x60,0x03,0x00,0x00,0xe0,0x01,0x00,0x00,0x80,0x05,0x00,0x00,0x00,0x94,0x6b,0x00,
0x96,0x4e,0x0b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xaf,0x50,0x00,
0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 4dfa5c8..eb16a50 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -24,7 +24,7 @@ if dep_cunit.found()
files(
'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c',
'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c', 'deadlock_tests.c',
- 'vm_tests.c', 'ras_tests.c', 'syncobj_tests.c',
+ 'vm_tests.c', 'ras_tests.c', 'syncobj_tests.c', 'security_tests.c',
),
dependencies : [dep_cunit, dep_threads, dep_atomic_ops],
include_directories : [inc_root, inc_drm, include_directories('../../amdgpu')],
diff --git a/tests/amdgpu/security_tests.c b/tests/amdgpu/security_tests.c
new file mode 100644
index 0000000..9b39e16
--- /dev/null
+++ b/tests/amdgpu/security_tests.c
@@ -0,0 +1,481 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "CUnit/Basic.h"
+
+#include "amdgpu_test.h"
+#include "amdgpu_drm.h"
+#include "amdgpu_internal.h"
+
+#include <string.h>
+#include <unistd.h>
+#include <endian.h>
+#include <strings.h>
+#include <xf86drm.h>
+
+static amdgpu_device_handle device_handle;
+static uint32_t major_version;
+static uint32_t minor_version;
+
+static struct drm_amdgpu_info_hw_ip sdma_info;
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(_Arr) (sizeof(_Arr)/sizeof((_Arr)[0]))
+#endif
+
+
+/* --------------------- Secure bounce test ------------------------ *
+ *
+ * The secure bounce test tests that we can evict a TMZ buffer,
+ * and page it back in, via a bounce buffer, as it encryption/decryption
+ * depends on its physical address, and have the same data, i.e. data
+ * integrity is preserved.
+ *
+ * The steps are as follows (from Christian K.):
+ *
+ * Buffer A which is TMZ protected and filled by the CPU with a
+ * certain pattern. That the GPU is reading only random nonsense from
+ * that pattern is irrelevant for the test.
+ *
+ * This buffer A is then secure copied into buffer B which is also
+ * TMZ protected.
+ *
+ * Buffer B is moved around, from VRAM to GTT, GTT to SYSTEM,
+ * etc.
+ *
+ * Then, we use another secure copy of buffer B back to buffer A.
+ *
+ * And lastly we check with the CPU the pattern.
+ *
+ * Assuming that we don't have memory contention and buffer A stayed
+ * at the same place, we should still see the same pattern when read
+ * by the CPU.
+ *
+ * If we don't see the same pattern then something in the buffer
+ * migration code is not working as expected.
+ */
+
+#define SECURE_BOUNCE_TEST_STR "secure bounce"
+#define SECURE_BOUNCE_FAILED_STR SECURE_BOUNCE_TEST_STR " failed"
+
+#define PRINT_ERROR(_Res) fprintf(stderr, "%s:%d: %s (%d)\n", \
+ __func__, __LINE__, strerror(-(_Res)), _Res)
+
+#define PACKET_LCOPY_SIZE 7
+#define PACKET_NOP_SIZE 12
+
+struct sec_amdgpu_bo {
+ struct amdgpu_bo *bo;
+ struct amdgpu_va *va;
+};
+
+struct command_ctx {
+ struct amdgpu_device *dev;
+ struct amdgpu_cs_ib_info cs_ibinfo;
+ struct amdgpu_cs_request cs_req;
+ struct amdgpu_context *context;
+ int ring_id;
+};
+
+/**
+ * amdgpu_bo_alloc_map -- Allocate and map a buffer object (BO)
+ * @dev: The AMDGPU device this BO belongs to.
+ * @size: The size of the BO.
+ * @alignment: Alignment of the BO.
+ * @gem_domain: One of AMDGPU_GEM_DOMAIN_xyz.
+ * @alloc_flags: One of AMDGPU_GEM_CREATE_xyz.
+ * @sbo: the result
+ *
+ * Allocate a buffer object (BO) with the desired attributes
+ * as specified by the argument list and write out the result
+ * into @sbo.
+ *
+ * Return 0 on success and @sbo->bo and @sbo->va are set,
+ * or -errno on error.
+ */
+static int amdgpu_bo_alloc_map(struct amdgpu_device *dev,
+ unsigned size,
+ unsigned alignment,
+ unsigned gem_domain,
+ uint64_t alloc_flags,
+ struct sec_amdgpu_bo *sbo)
+{
+ void *cpu;
+ uint64_t mc_addr;
+
+ return amdgpu_bo_alloc_and_map_raw(dev,
+ size,
+ alignment,
+ gem_domain,
+ alloc_flags,
+ 0,
+ &sbo->bo,
+ &cpu, &mc_addr,
+ &sbo->va);
+}
+
+static void amdgpu_bo_unmap_free(struct sec_amdgpu_bo *sbo,
+ const uint64_t size)
+{
+ (void) amdgpu_bo_unmap_and_free(sbo->bo,
+ sbo->va,
+ sbo->va->address,
+ size);
+ sbo->bo = NULL;
+ sbo->va = NULL;
+}
+
+static void amdgpu_sdma_lcopy(uint32_t *packet,
+ const uint64_t dst,
+ const uint64_t src,
+ const uint32_t size,
+ const int secure)
+{
+ /* Set the packet to Linear copy with TMZ set.
+ */
+ packet[0] = htole32(secure << 18 | 1);
+ packet[1] = htole32(size-1);
+ packet[2] = htole32(0);
+ packet[3] = htole32((uint32_t)(src & 0xFFFFFFFFU));
+ packet[4] = htole32((uint32_t)(src >> 32));
+ packet[5] = htole32((uint32_t)(dst & 0xFFFFFFFFU));
+ packet[6] = htole32((uint32_t)(dst >> 32));
+}
+
+static void amdgpu_sdma_nop(uint32_t *packet, uint32_t nop_count)
+{
+ /* A packet of the desired number of NOPs.
+ */
+ packet[0] = htole32(nop_count << 16);
+ for ( ; nop_count > 0; nop_count--)
+ packet[nop_count-1] = 0;
+}
+
+/**
+ * amdgpu_bo_lcopy -- linear copy with TZM set, using sDMA
+ * @dev: AMDGPU device to which both buffer objects belong to
+ * @dst: destination buffer object
+ * @src: source buffer object
+ * @size: size of memory to move, in bytes.
+ * @secure: Set to 1 to perform secure copy, 0 for clear
+ *
+ * Issues and waits for completion of a Linear Copy with TMZ
+ * set, to the sDMA engine. @size should be a multiple of
+ * at least 16 bytes.
+ */
+static void amdgpu_bo_lcopy(struct command_ctx *ctx,
+ struct sec_amdgpu_bo *dst,
+ struct sec_amdgpu_bo *src,
+ const uint32_t size,
+ int secure)
+{
+ struct amdgpu_bo *bos[] = { dst->bo, src->bo };
+ uint32_t packet[PACKET_LCOPY_SIZE];
+
+ amdgpu_sdma_lcopy(packet,
+ dst->va->address,
+ src->va->address,
+ size, secure);
+ amdgpu_test_exec_cs_helper_raw(ctx->dev, ctx->context,
+ AMDGPU_HW_IP_DMA, ctx->ring_id,
+ ARRAY_SIZE(packet), packet,
+ ARRAY_SIZE(bos), bos,
+ &ctx->cs_ibinfo, &ctx->cs_req,
+ secure == 1);
+}
+
+/**
+ * amdgpu_bo_move -- Evoke a move of the buffer object (BO)
+ * @dev: device to which this buffer object belongs to
+ * @bo: the buffer object to be moved
+ * @whereto: one of AMDGPU_GEM_DOMAIN_xyz
+ * @secure: set to 1 to submit secure IBs
+ *
+ * Evokes a move of the buffer object @bo to the GEM domain
+ * descibed by @whereto.
+ *
+ * Returns 0 on sucess; -errno on error.
+ */
+static int amdgpu_bo_move(struct command_ctx *ctx,
+ struct amdgpu_bo *bo,
+ uint64_t whereto,
+ int secure)
+{
+ struct amdgpu_bo *bos[] = { bo };
+ struct drm_amdgpu_gem_op gop = {
+ .handle = bo->handle,
+ .op = AMDGPU_GEM_OP_SET_PLACEMENT,
+ .value = whereto,
+ };
+ uint32_t packet[PACKET_NOP_SIZE];
+ int res;
+
+ /* Change the buffer's placement.
+ */
+ res = drmIoctl(ctx->dev->fd, DRM_IOCTL_AMDGPU_GEM_OP, &gop);
+ if (res)
+ return -errno;
+
+ /* Now issue a NOP to actually evoke the MM to move
+ * it to the desired location.
+ */
+ amdgpu_sdma_nop(packet, PACKET_NOP_SIZE);
+ amdgpu_test_exec_cs_helper_raw(ctx->dev, ctx->context,
+ AMDGPU_HW_IP_DMA, ctx->ring_id,
+ ARRAY_SIZE(packet), packet,
+ ARRAY_SIZE(bos), bos,
+ &ctx->cs_ibinfo, &ctx->cs_req,
+ secure == 1);
+ return 0;
+}
+
+/* Safe, O Sec!
+ */
+static const uint8_t secure_pattern[] = { 0x5A, 0xFE, 0x05, 0xEC };
+
+#define SECURE_BUFFER_SIZE (4 * 1024 * sizeof(secure_pattern))
+
+static void amdgpu_secure_bounce(void)
+{
+ struct sec_amdgpu_bo alice, bob;
+ struct command_ctx sb_ctx;
+ long page_size;
+ uint8_t *pp;
+ int res;
+
+ page_size = sysconf(_SC_PAGESIZE);
+
+ memset(&sb_ctx, 0, sizeof(sb_ctx));
+ sb_ctx.dev = device_handle;
+ res = amdgpu_cs_ctx_create(sb_ctx.dev, &sb_ctx.context);
+ if (res) {
+ PRINT_ERROR(res);
+ CU_FAIL(SECURE_BOUNCE_FAILED_STR);
+ return;
+ }
+
+ /* Use the first present ring.
+ */
+ res = ffs(sdma_info.available_rings) - 1;
+ if (res == -1) {
+ PRINT_ERROR(-ENOENT);
+ CU_FAIL(SECURE_BOUNCE_FAILED_STR);
+ goto Out_free_ctx;
+ }
+ sb_ctx.ring_id = res;
+
+ /* Allocate a buffer named Alice in VRAM.
+ */
+ res = amdgpu_bo_alloc_map(device_handle,
+ SECURE_BUFFER_SIZE,
+ page_size,
+ AMDGPU_GEM_DOMAIN_VRAM,
+ AMDGPU_GEM_CREATE_ENCRYPTED,
+ &alice);
+ if (res) {
+ PRINT_ERROR(res);
+ CU_FAIL(SECURE_BOUNCE_FAILED_STR);
+ return;
+ }
+
+ /* Fill Alice with a pattern.
+ */
+ for (pp = alice.bo->cpu_ptr;
+ pp < (typeof(pp)) alice.bo->cpu_ptr + SECURE_BUFFER_SIZE;
+ pp += sizeof(secure_pattern))
+ memcpy(pp, secure_pattern, sizeof(secure_pattern));
+
+ /* Allocate a buffer named Bob in VRAM.
+ */
+ res = amdgpu_bo_alloc_map(device_handle,
+ SECURE_BUFFER_SIZE,
+ page_size,
+ AMDGPU_GEM_DOMAIN_VRAM,
+ 0 /* AMDGPU_GEM_CREATE_ENCRYPTED */,
+ &bob);
+ if (res) {
+ PRINT_ERROR(res);
+ CU_FAIL(SECURE_BOUNCE_FAILED_STR);
+ goto Out_free_Alice;
+ }
+
+ /* sDMA clear copy from Alice to Bob.
+ */
+ amdgpu_bo_lcopy(&sb_ctx, &bob, &alice, SECURE_BUFFER_SIZE, 0);
+
+ /* Move Bob to the GTT domain.
+ */
+ res = amdgpu_bo_move(&sb_ctx, bob.bo, AMDGPU_GEM_DOMAIN_GTT, 0);
+ if (res) {
+ PRINT_ERROR(res);
+ CU_FAIL(SECURE_BOUNCE_FAILED_STR);
+ goto Out_free_all;
+ }
+
+ /* sDMA clear copy from Bob to Alice.
+ */
+ amdgpu_bo_lcopy(&sb_ctx, &alice, &bob, SECURE_BUFFER_SIZE, 0);
+
+ /* Verify the contents of Alice.
+ */
+ for (pp = alice.bo->cpu_ptr;
+ pp < (typeof(pp)) alice.bo->cpu_ptr + SECURE_BUFFER_SIZE;
+ pp += sizeof(secure_pattern)) {
+ res = memcmp(pp, secure_pattern, sizeof(secure_pattern));
+ if (res) {
+ fprintf(stderr, SECURE_BOUNCE_FAILED_STR);
+ CU_FAIL(SECURE_BOUNCE_FAILED_STR);
+ break;
+ }
+ }
+
+Out_free_all:
+ amdgpu_bo_unmap_free(&bob, SECURE_BUFFER_SIZE);
+Out_free_Alice:
+ amdgpu_bo_unmap_free(&alice, SECURE_BUFFER_SIZE);
+Out_free_ctx:
+ res = amdgpu_cs_ctx_free(sb_ctx.context);
+ CU_ASSERT_EQUAL(res, 0);
+}
+
+/* ----------------------------------------------------------------- */
+
+static void amdgpu_security_alloc_buf_test(void)
+{
+ amdgpu_bo_handle bo;
+ amdgpu_va_handle va_handle;
+ uint64_t bo_mc;
+ int r;
+
+ /* Test secure buffer allocation in VRAM */
+ bo = gpu_mem_alloc(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_VRAM,
+ AMDGPU_GEM_CREATE_ENCRYPTED,
+ &bo_mc, &va_handle);
+
+ r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
+ CU_ASSERT_EQUAL(r, 0);
+
+ /* Test secure buffer allocation in system memory */
+ bo = gpu_mem_alloc(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT,
+ AMDGPU_GEM_CREATE_ENCRYPTED,
+ &bo_mc, &va_handle);
+
+ r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
+ CU_ASSERT_EQUAL(r, 0);
+
+ /* Test secure buffer allocation in invisible VRAM */
+ bo = gpu_mem_alloc(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT,
+ AMDGPU_GEM_CREATE_ENCRYPTED |
+ AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
+ &bo_mc, &va_handle);
+
+ r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
+ CU_ASSERT_EQUAL(r, 0);
+}
+
+static void amdgpu_security_gfx_submission_test(void)
+{
+ amdgpu_command_submission_write_linear_helper_with_secure(device_handle,
+ AMDGPU_HW_IP_GFX,
+ true);
+}
+
+static void amdgpu_security_sdma_submission_test(void)
+{
+ amdgpu_command_submission_write_linear_helper_with_secure(device_handle,
+ AMDGPU_HW_IP_DMA,
+ true);
+}
+
+/* ----------------------------------------------------------------- */
+
+CU_TestInfo security_tests[] = {
+ { "allocate secure buffer test", amdgpu_security_alloc_buf_test },
+ { "graphics secure command submission", amdgpu_security_gfx_submission_test },
+ { "sDMA secure command submission", amdgpu_security_sdma_submission_test },
+ { SECURE_BOUNCE_TEST_STR, amdgpu_secure_bounce },
+ CU_TEST_INFO_NULL,
+};
+
+CU_BOOL suite_security_tests_enable(void)
+{
+ CU_BOOL enable = CU_TRUE;
+
+ if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
+ &minor_version, &device_handle))
+ return CU_FALSE;
+
+ if (device_handle->info.family_id != AMDGPU_FAMILY_RV) {
+ printf("\n\nDon't support TMZ (trust memory zone), security suite disabled\n");
+ enable = CU_FALSE;
+ }
+
+ if ((major_version < 3) ||
+ ((major_version == 3) && (minor_version < 37))) {
+ printf("\n\nDon't support TMZ (trust memory zone), kernel DRM version (%d.%d)\n",
+ major_version, minor_version);
+ printf("is older, security suite disabled\n");
+ enable = CU_FALSE;
+ }
+
+ if (amdgpu_device_deinitialize(device_handle))
+ return CU_FALSE;
+
+ return enable;
+}
+
+int suite_security_tests_init(void)
+{
+ int res;
+
+ res = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
+ &minor_version, &device_handle);
+ if (res) {
+ PRINT_ERROR(res);
+ return CUE_SINIT_FAILED;
+ }
+
+ res = amdgpu_query_hw_ip_info(device_handle,
+ AMDGPU_HW_IP_DMA,
+ 0, &sdma_info);
+ if (res) {
+ PRINT_ERROR(res);
+ return CUE_SINIT_FAILED;
+ }
+
+ return CUE_SUCCESS;
+}
+
+int suite_security_tests_clean(void)
+{
+ int res;
+
+ res = amdgpu_device_deinitialize(device_handle);
+ if (res)
+ return CUE_SCLEAN_FAILED;
+
+ return CUE_SUCCESS;
+}
diff --git a/tests/amdgpu/vce_tests.c b/tests/amdgpu/vce_tests.c
index 0026826..5434e44 100644
--- a/tests/amdgpu/vce_tests.c
+++ b/tests/amdgpu/vce_tests.c
@@ -96,7 +96,7 @@ CU_TestInfo vce_tests[] = {
CU_BOOL suite_vce_tests_enable(void)
{
- uint32_t version, feature;
+ uint32_t version, feature, asic_id;
CU_BOOL ret_mv = CU_FALSE;
if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
@@ -107,6 +107,7 @@ CU_BOOL suite_vce_tests_enable(void)
chip_rev = device_handle->info.chip_rev;
chip_id = device_handle->info.chip_external_rev;
ids_flags = device_handle->info.ids_flags;
+ asic_id = device_handle->info.asic_id;
amdgpu_query_firmware_version(device_handle, AMDGPU_INFO_FW_VCE, 0,
0, &version, &feature);
@@ -114,7 +115,8 @@ CU_BOOL suite_vce_tests_enable(void)
if (amdgpu_device_deinitialize(device_handle))
return CU_FALSE;
- if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) {
+ if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI ||
+ asic_is_arcturus(asic_id)) {
printf("\n\nThe ASIC NOT support VCE, suite disabled\n");
return CU_FALSE;
}
diff --git a/tests/amdgpu/vcn_tests.c b/tests/amdgpu/vcn_tests.c
index 77ceeb1..e85174a 100644
--- a/tests/amdgpu/vcn_tests.c
+++ b/tests/amdgpu/vcn_tests.c
@@ -56,7 +56,11 @@ static amdgpu_device_handle device_handle;
static uint32_t major_version;
static uint32_t minor_version;
static uint32_t family_id;
+static uint32_t chip_rev;
+static uint32_t chip_id;
static uint32_t asic_id;
+static uint32_t chip_rev;
+static uint32_t chip_id;
static amdgpu_context_handle context_handle;
static amdgpu_bo_handle ib_handle;
@@ -90,23 +94,39 @@ CU_TestInfo vcn_tests[] = {
CU_BOOL suite_vcn_tests_enable(void)
{
+ struct drm_amdgpu_info_hw_ip info;
+ int r;
if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
&minor_version, &device_handle))
return CU_FALSE;
family_id = device_handle->info.family_id;
+ chip_rev = device_handle->info.chip_rev;
+ chip_id = device_handle->info.chip_external_rev;
asic_id = device_handle->info.asic_id;
+ chip_rev = device_handle->info.chip_rev;
+ chip_id = device_handle->info.chip_external_rev;
+
+ r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_VCN_DEC, 0, &info);
if (amdgpu_device_deinitialize(device_handle))
return CU_FALSE;
-
- if (family_id < AMDGPU_FAMILY_RV) {
+ if (r != 0 || !info.available_rings ||
+ (family_id < AMDGPU_FAMILY_RV &&
+ (family_id == AMDGPU_FAMILY_AI &&
+ chip_id != (chip_rev + 0x32)))) { /* Arcturus */
printf("\n\nThe ASIC NOT support VCN, suite disabled\n");
return CU_FALSE;
}
+ if (family_id == AMDGPU_FAMILY_AI) {
+ amdgpu_set_test_active("VCN Tests", "VCN ENC create", CU_FALSE);
+ amdgpu_set_test_active("VCN Tests", "VCN ENC decode", CU_FALSE);
+ amdgpu_set_test_active("VCN Tests", "VCN ENC destroy", CU_FALSE);
+ }
+
if (family_id == AMDGPU_FAMILY_RV) {
if (asic_id == 0x1636) {
reg.data0 = 0x504;
@@ -122,11 +142,26 @@ CU_BOOL suite_vcn_tests_enable(void)
reg.cntl = 0x81c6;
}
} else if (family_id == AMDGPU_FAMILY_NV) {
- reg.data0 = 0x504;
- reg.data1 = 0x505;
- reg.cmd = 0x503;
- reg.nop = 0x53f;
- reg.cntl = 0x506;
+ if (chip_id == (chip_rev + 0x28)) {
+ reg.data0 = 0x10;
+ reg.data1 = 0x11;
+ reg.cmd = 0xf;
+ reg.nop = 0x29;
+ reg.cntl = 0x26d;
+ }
+ else {
+ reg.data0 = 0x504;
+ reg.data1 = 0x505;
+ reg.cmd = 0x503;
+ reg.nop = 0x53f;
+ reg.cntl = 0x506;
+ }
+ } else if (family_id == AMDGPU_FAMILY_AI) {
+ reg.data0 = 0x10;
+ reg.data1 = 0x11;
+ reg.cmd = 0xf;
+ reg.nop = 0x29;
+ reg.cntl = 0x26d;
} else
return CU_FALSE;
diff --git a/tests/amdgpu/vm_tests.c b/tests/amdgpu/vm_tests.c
index 69bc468..95011ea 100644
--- a/tests/amdgpu/vm_tests.c
+++ b/tests/amdgpu/vm_tests.c
@@ -104,6 +104,14 @@ static void amdgpu_vmid_reserve_test(void)
amdgpu_bo_list_handle bo_list;
amdgpu_va_handle va_handle;
static uint32_t *ptr;
+ struct amdgpu_gpu_info gpu_info = {0};
+ unsigned gc_ip_type;
+
+ r = amdgpu_query_gpu_info(device_handle, &gpu_info);
+ CU_ASSERT_EQUAL(r, 0);
+
+ gc_ip_type = (asic_is_arcturus(gpu_info.asic_id)) ?
+ AMDGPU_HW_IP_COMPUTE : AMDGPU_HW_IP_GFX;
r = amdgpu_cs_ctx_create(device_handle, &context_handle);
CU_ASSERT_EQUAL(r, 0);
@@ -133,7 +141,7 @@ static void amdgpu_vmid_reserve_test(void)
ib_info.size = 16;
memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
- ibs_request.ip_type = AMDGPU_HW_IP_GFX;
+ ibs_request.ip_type = gc_ip_type;
ibs_request.ring = 0;
ibs_request.number_of_ibs = 1;
ibs_request.ibs = &ib_info;
@@ -146,7 +154,7 @@ static void amdgpu_vmid_reserve_test(void)
memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
fence_status.context = context_handle;
- fence_status.ip_type = AMDGPU_HW_IP_GFX;
+ fence_status.ip_type = gc_ip_type;
fence_status.ip_instance = 0;
fence_status.ring = 0;
fence_status.fence = ibs_request.seq_no;
diff --git a/tests/util/kms.c b/tests/util/kms.c
index dd1bbee..08b48fe 100644
--- a/tests/util/kms.c
+++ b/tests/util/kms.c
@@ -147,6 +147,8 @@ static const char * const modules[] = {
"stm",
"sun4i-drm",
"armada-drm",
+ "komeda",
+ "imx-dcss",
};
int util_open(const char *device, const char *module)
diff --git a/xf86drm.c b/xf86drm.c
index b49d42f..dbb7c14 100644
--- a/xf86drm.c
+++ b/xf86drm.c
@@ -124,6 +124,22 @@ static drmServerInfoPtr drm_server_info;
static bool drmNodeIsDRM(int maj, int min);
static char *drmGetMinorNameForFD(int fd, int type);
+static unsigned log2_int(unsigned x)
+{
+ unsigned l;
+
+ if (x < 2) {
+ return 0;
+ }
+ for (l = 2; ; l++) {
+ if ((unsigned)(1 << l) > x) {
+ return l - 1;
+ }
+ }
+ return 0;
+}
+
+
drm_public void drmSetServerInfo(drmServerInfoPtr info)
{
drm_server_info = info;
@@ -696,7 +712,7 @@ static int drmOpenByName(const char *name, int type)
int retcode;
sprintf(proc_name, "/proc/dri/%d/name", i);
- if ((fd = open(proc_name, 0, 0)) >= 0) {
+ if ((fd = open(proc_name, O_RDONLY, 0)) >= 0) {
retcode = read(fd, buf, sizeof(buf)-1);
close(fd);
if (retcode) {
@@ -2822,7 +2838,7 @@ static bool drmNodeIsDRM(int maj, int min)
snprintf(path, sizeof(path), "/sys/dev/char/%d:%d/device/drm",
maj, min);
return stat(path, &sbuf) == 0;
-#elif __FreeBSD__
+#elif defined(__FreeBSD__)
char name[SPECNAMELEN];
if (!devname_r(makedev(maj, min), S_IFCHR, name, sizeof(name)))
@@ -2935,7 +2951,7 @@ static char *drmGetMinorNameForFD(int fd, int type)
closedir(sysdir);
return NULL;
-#elif __FreeBSD__
+#elif defined(__FreeBSD__)
struct stat sbuf;
char dname[SPECNAMELEN];
const char *mname;
@@ -3255,7 +3271,7 @@ static int drmParsePciBusInfo(int maj, int min, drmPciBusInfoPtr info)
info->func = pinfo.func;
return 0;
-#elif __FreeBSD__
+#elif defined(__FreeBSD__)
return get_sysctl_pci_bus_info(maj, min, info);
#else
#warning "Missing implementation of drmParsePciBusInfo"
@@ -3424,7 +3440,7 @@ static int drmParsePciDeviceInfo(int maj, int min,
device->subdevice_id = pinfo.subdevice_id;
return 0;
-#elif __FreeBSD__
+#elif defined(__FreeBSD__)
drmPciBusInfo info;
struct pci_conf_io pc;
struct pci_match_conf patterns[1];
@@ -4001,7 +4017,7 @@ static void drmFoldDuplicatedDevices(drmDevicePtr local_devices[], int count)
for (j = i + 1; j < count; j++) {
if (drmDevicesEqual(local_devices[i], local_devices[j])) {
local_devices[i]->available_nodes |= local_devices[j]->available_nodes;
- node_type = log2(local_devices[j]->available_nodes);
+ node_type = log2_int(local_devices[j]->available_nodes);
memcpy(local_devices[i]->nodes[node_type],
local_devices[j]->nodes[node_type], drmGetMaxNodeName());
drmFreeDevice(&local_devices[j]);
@@ -4302,7 +4318,7 @@ drm_public char *drmGetDeviceNameFromFd2(int fd)
free(value);
return strdup(path);
-#elif __FreeBSD__
+#elif defined(__FreeBSD__)
return drmGetDeviceNameFromFd(fd);
#else
struct stat sbuf;