summaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
diff options
context:
space:
mode:
authorDaniel Baumann <daniel.baumann@progress-linux.org>2024-05-06 01:02:30 +0000
committerDaniel Baumann <daniel.baumann@progress-linux.org>2024-05-06 01:02:30 +0000
commit76cb841cb886eef6b3bee341a2266c76578724ad (patch)
treef5892e5ba6cc11949952a6ce4ecbe6d516d6ce58 /arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
parentInitial commit. (diff)
downloadlinux-76cb841cb886eef6b3bee341a2266c76578724ad.tar.xz
linux-76cb841cb886eef6b3bee341a2266c76578724ad.zip
Adding upstream version 4.19.249.upstream/4.19.249
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts')
-rw-r--r--arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts241
1 files changed, 241 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
new file mode 100644
index 000000000..d01f64b25
--- /dev/null
+++ b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2017 Moxa Inc. - https://www.moxa.com/
+ *
+ * Author: Harry YJ Jhou (周亞諄) <harryyj.jhou@moxa.com>
+ * Jimmy Chen (陳永達) <jimmy.chen@moxa.com>
+ * SZ Lin (林上智) <sz.lin@moxa.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "ls1021a.dtsi"
+
+/ {
+ model = "Moxa UC-8410A";
+
+ aliases {
+ enet0_rgmii_phy = &rgmii_phy0;
+ enet1_rgmii_phy = &rgmii_phy1;
+ enet2_rgmii_phy = &rgmii_phy2;
+ };
+
+ sys_mclk: clock-mclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ cel-pwr {
+ label = "UC8410A:CEL-PWR";
+ gpios = <&gpio3 27 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ cel-reset {
+ label = "UC8410A:CEL-RESET";
+ gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ str-led {
+ label = "UC8410A:RED:PROG";
+ gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ };
+
+ sw-ready {
+ label = "UC8410A:GREEN:SWRDY";
+ gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ beeper {
+ label = "UC8410A:BEEP";
+ gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ prog-led0 {
+ label = "UC8410A:GREEN:PROG2";
+ gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ prog-led1 {
+ label = "UC8410A:GREEN:PROG1";
+ gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ prog-led2 {
+ label = "UC8410A:GREEN:PROG0";
+ gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ wifi-signal0 {
+ label = "UC8410A:GREEN:CEL2";
+ gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ wifi-signal1 {
+ label = "UC8410A:GREEN:CEL1";
+ gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ wifi-signal2 {
+ label = "UC8410A:GREEN:CEL0";
+ gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ cpu-diag-red {
+ label = "UC8410A:RED:DIA";
+ gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ cpu-diag-green {
+ label = "UC8410A:GREEN:DIA";
+ gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ cpu-diag-yellow {
+ label = "UC8410A:YELLOW:DIA";
+ gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pushbtn-key {
+ label = "push button key";
+ gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_MISC>;
+ default-state = "on";
+ };
+ };
+};
+
+&enet0 {
+ phy-handle = <&rgmii_phy0>;
+ phy-connection-type = "rgmii-id";
+ status = "okay";
+};
+
+&enet1 {
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii-id";
+ status = "okay";
+};
+
+&enet2 {
+ phy-handle = <&rgmii_phy2>;
+ phy-connection-type = "rgmii-id";
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ tpm@20 {
+ compatible = "infineon,slb9635tt";
+ reg = <0x20>;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1374";
+ reg = <0x68>;
+ };
+};
+
+&lpuart0 {
+ status = "okay";
+};
+
+&mdio0 {
+ rgmii_phy0: ethernet-phy@0 {
+ compatible = "marvell,88e1118";
+ reg = <0x0>;
+ marvell,reg-init =
+ <3 0x11 0 0x4415>, /* Reg 3,17 */
+ <3 0x10 0 0x77>; /* Reg 3,16 */
+ };
+
+ rgmii_phy1: ethernet-phy@1 {
+ compatible = "marvell,88e1118";
+ reg = <0x1>;
+ marvell,reg-init =
+ <3 0x11 0 0x4415>, /* Reg 3,17 */
+ <3 0x10 0 0x77>; /* Reg 3,16 */
+ };
+
+ rgmii_phy2: ethernet-phy@2 {
+ compatible = "marvell,88e1118";
+ reg = <0x2>;
+ marvell,reg-init =
+ <3 0x11 0 0x4415>, /* Reg 3,17 */
+ <3 0x10 0 0x77>; /* Reg 3,16 */
+ };
+};
+
+&qspi {
+ bus-num = <0>;
+ fsl,spi-num-chipselects = <2>;
+ fsl,spi-flash-chipselects = <0>;
+ fsl,qspi-has-second-chip;
+ status = "okay";
+
+ flash: flash@0 {
+ compatible = "spansion,s25fl064l", "spansion,s25fl164k";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+
+ partitions@0 {
+ label = "U-Boot";
+ reg = <0x0 0x180000>;
+ };
+
+ partitions@180000 {
+ label = "U-Boot Env";
+ reg = <0x180000 0x680000>;
+ };
+ };
+};
+
+&sata {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};