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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-08 03:21:31 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-08 03:21:31 +0000 |
| commit | 5dca02f2ee931aef66bb21dd8067c8b1af1e0d3e (patch) | |
| tree | 6581b770eb1bd6cac1252a5451b89c092ea4c797 /arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi | |
| parent | Adding debian version 4.19.249-2. (diff) | |
| download | linux-5dca02f2ee931aef66bb21dd8067c8b1af1e0d3e.tar.xz linux-5dca02f2ee931aef66bb21dd8067c8b1af1e0d3e.zip | |
Merging upstream version 4.19.260.
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi index ff81dfda3..3ba927f30 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi @@ -232,6 +232,14 @@ &edp { status = "okay"; + /* + * eDP PHY/clk don't sync reliably at anything other than 24 MHz. Only + * set this here, because rk3399-gru.dtsi ensures we can generate this + * off GPLL=600MHz, whereas some other RK3399 boards may not. + */ + assigned-clocks = <&cru PCLK_EDP>; + assigned-clock-rates = <24000000>; + ports { edp_out: port@1 { reg = <1>; |