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author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-08 03:21:30 +0000 |
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committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-08 03:21:30 +0000 |
commit | a72bbcd13c515079b13dfcc3f57e933f28235f48 (patch) | |
tree | fd02a5f7642fbfb3141c285aa63a8f397fe41d76 /arch/arm64/boot/dts/rockchip | |
parent | Adding upstream version 4.19.249. (diff) | |
download | linux-a72bbcd13c515079b13dfcc3f57e933f28235f48.tar.xz linux-a72bbcd13c515079b13dfcc3f57e933f28235f48.zip |
Adding upstream version 4.19.260.upstream/4.19.260
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip')
-rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi | 8 | ||||
-rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi | 1 |
2 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi index ff81dfda3..3ba927f30 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi @@ -232,6 +232,14 @@ &edp { status = "okay"; + /* + * eDP PHY/clk don't sync reliably at anything other than 24 MHz. Only + * set this here, because rk3399-gru.dtsi ensures we can generate this + * off GPLL=600MHz, whereas some other RK3399 boards may not. + */ + assigned-clocks = <&cru PCLK_EDP>; + assigned-clock-rates = <24000000>; + ports { edp_out: port@1 { reg = <1>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi index ce1320e4c..6750b8100 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi @@ -102,7 +102,6 @@ vcc5v0_host: vcc5v0-host-regulator { compatible = "regulator-fixed"; gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>; - enable-active-low; pinctrl-names = "default"; pinctrl-0 = <&vcc5v0_host_en>; regulator-name = "vcc5v0_host"; |