diff options
Diffstat (limited to 'arch/arm/boot/dts/exynos5422-cpus.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/exynos5422-cpus.dtsi | 130 |
1 files changed, 130 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi new file mode 100644 index 000000000..e4a5857c1 --- /dev/null +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SAMSUNG EXYNOS5422 SoC cpu device tree source + * + * Copyright (c) 2015 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This file provides desired ordering for Exynos5422: CPU[0123] being the A7. + * + * The Exynos5420, 5422 and 5800 actually share the same CPU configuration + * but particular boards choose different booting order. + * + * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422 + * booting cluster (big or LITTLE) is chosen by IROM code by reading + * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting + * from the LITTLE: Cortex-A7. + */ + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + clocks = <&clock CLK_KFC_CLK>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; + operating-points-v2 = <&cluster_a7_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; + }; + + cpu1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + clocks = <&clock CLK_KFC_CLK>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; + operating-points-v2 = <&cluster_a7_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; + }; + + cpu2: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + clocks = <&clock CLK_KFC_CLK>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; + operating-points-v2 = <&cluster_a7_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; + }; + + cpu3: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x103>; + clocks = <&clock CLK_KFC_CLK>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; + operating-points-v2 = <&cluster_a7_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; + }; + + cpu4: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x0>; + clocks = <&clock CLK_ARM_CLK>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; + operating-points-v2 = <&cluster_a15_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; + }; + + cpu5: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x1>; + clocks = <&clock CLK_ARM_CLK>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; + operating-points-v2 = <&cluster_a15_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; + }; + + cpu6: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x2>; + clocks = <&clock CLK_ARM_CLK>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; + operating-points-v2 = <&cluster_a15_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; + }; + + cpu7: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x3>; + clocks = <&clock CLK_ARM_CLK>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; + operating-points-v2 = <&cluster_a15_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; + }; + }; +}; + +&arm_a7_pmu { + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + status = "okay"; +}; + +&arm_a15_pmu { + interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + status = "okay"; +}; |