From 76cb841cb886eef6b3bee341a2266c76578724ad Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Mon, 6 May 2024 03:02:30 +0200 Subject: Adding upstream version 4.19.249. Signed-off-by: Daniel Baumann --- arch/arm/boot/dts/sun8i-r40.dtsi | 821 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 821 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi (limited to 'arch/arm/boot/dts/sun8i-r40.dtsi') diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi new file mode 100644 index 000000000..5f547c161 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -0,0 +1,821 @@ +/* + * Copyright 2017 Chen-Yu Tsai + * Copyright 2017 Icenowy Zheng + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: osc24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <3>; + }; + }; + + de: display-engine { + compatible = "allwinner,sun8i-r40-display-engine"; + allwinner,pipelines = <&mixer0>, <&mixer1>; + status = "disabled"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display_clocks: clock@1000000 { + compatible = "allwinner,sun8i-r40-de2-clk", + "allwinner,sun8i-h3-de2-clk"; + reg = <0x01000000 0x100000>; + clocks = <&ccu CLK_DE>, + <&ccu CLK_BUS_DE>; + clock-names = "mod", + "bus"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mixer0: mixer@1100000 { + compatible = "allwinner,sun8i-r40-de2-mixer-0"; + reg = <0x01100000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER0>, + <&display_clocks CLK_MIXER0>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_MIXER0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer0_out: port@1 { + reg = <1>; + mixer0_out_tcon_top: endpoint { + remote-endpoint = <&tcon_top_mixer0_in_mixer0>; + }; + }; + }; + }; + + mixer1: mixer@1200000 { + compatible = "allwinner,sun8i-r40-de2-mixer-1"; + reg = <0x01200000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER1>, + <&display_clocks CLK_MIXER1>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_WB>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer1_out: port@1 { + reg = <1>; + mixer1_out_tcon_top: endpoint { + remote-endpoint = <&tcon_top_mixer1_in_mixer1>; + }; + }; + }; + }; + + nmi_intc: interrupt-controller@1c00030 { + compatible = "allwinner,sun7i-a20-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01c00030 0x0c>; + interrupts = ; + }; + + mmc0: mmc@1c0f000 { + compatible = "allwinner,sun8i-r40-mmc", + "allwinner,sun50i-a64-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + pinctrl-0 = <&mmc0_pins>; + pinctrl-names = "default"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@1c10000 { + compatible = "allwinner,sun8i-r40-mmc", + "allwinner,sun50i-a64-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@1c11000 { + compatible = "allwinner,sun8i-r40-emmc", + "allwinner,sun50i-a64-emmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC2>; + reset-names = "ahb"; + pinctrl-0 = <&mmc2_pins>; + pinctrl-names = "default"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc3: mmc@1c12000 { + compatible = "allwinner,sun8i-r40-mmc", + "allwinner,sun50i-a64-mmc"; + reg = <0x01c12000 0x1000>; + clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC3>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + usbphy: phy@1c13400 { + compatible = "allwinner,sun8i-r40-usb-phy"; + reg = <0x01c13400 0x14>, + <0x01c14800 0x4>, + <0x01c19800 0x4>, + <0x01c1c800 0x4>; + reg-names = "phy_ctrl", + "pmu0", + "pmu1", + "pmu2"; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>, + <&ccu CLK_USB_PHY2>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci1: usb@1c19000 { + compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; + reg = <0x01c19000 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_EHCI1>; + resets = <&ccu RST_BUS_EHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@1c19400 { + compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; + reg = <0x01c19400 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_BUS_OHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci2: usb@1c1c000 { + compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; + reg = <0x01c1c000 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_EHCI2>; + resets = <&ccu RST_BUS_EHCI2>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci2: usb@1c1c400 { + compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; + reg = <0x01c1c400 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_OHCI2>, + <&ccu CLK_USB_OHCI2>; + resets = <&ccu RST_BUS_OHCI2>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ccu: clock@1c20000 { + compatible = "allwinner,sun8i-r40-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pio: pinctrl@1c20800 { + compatible = "allwinner,sun8i-r40-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + gmac_rgmii_pins: gmac-rgmii-pins { + pins = "PA0", "PA1", "PA2", "PA3", + "PA4", "PA5", "PA6", "PA7", + "PA8", "PA10", "PA11", "PA12", + "PA13", "PA15", "PA16"; + function = "gmac"; + /* + * data lines in RGMII mode use DDR mode + * and need a higher signal drive strength + */ + drive-strength = <40>; + }; + + i2c0_pins: i2c0-pins { + pins = "PB0", "PB1"; + function = "i2c0"; + }; + + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", + "PF3", "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc1_pg_pins: mmc1-pg-pins { + pins = "PG0", "PG1", "PG2", + "PG3", "PG4", "PG5"; + function = "mmc1"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc2_pins: mmc2-pins { + pins = "PC5", "PC6", "PC7", "PC8", "PC9", + "PC10", "PC11", "PC12", "PC13", "PC14", + "PC15", "PC24"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + + uart0_pb_pins: uart0-pb-pins { + pins = "PB22", "PB23"; + function = "uart0"; + }; + }; + + wdt: watchdog@1c20c90 { + compatible = "allwinner,sun4i-a10-wdt"; + reg = <0x01c20c90 0x10>; + }; + + uart0: serial@1c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + status = "disabled"; + }; + + uart1: serial@1c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + + uart2: serial@1c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + status = "disabled"; + }; + + uart3: serial@1c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + status = "disabled"; + }; + + uart4: serial@1c29000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; + status = "disabled"; + }; + + uart5: serial@1c29400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29400 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART5>; + resets = <&ccu RST_BUS_UART5>; + status = "disabled"; + }; + + uart6: serial@1c29800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART6>; + resets = <&ccu RST_BUS_UART6>; + status = "disabled"; + }; + + uart7: serial@1c29c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29c00 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART7>; + resets = <&ccu RST_BUS_UART7>; + status = "disabled"; + }; + + i2c0: i2c@1c2ac00 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@1c2b000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@1c2b400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c3: i2c@1c2b800 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b800 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C3>; + resets = <&ccu RST_BUS_I2C3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c4: i2c@1c2c000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2c000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C4>; + resets = <&ccu RST_BUS_I2C4>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gmac: ethernet@1c50000 { + compatible = "allwinner,sun8i-r40-gmac"; + syscon = <&ccu>; + reg = <0x01c50000 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_GMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_GMAC>; + clock-names = "stmmaceth"; + status = "disabled"; + + gmac_mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + tcon_top: tcon-top@1c70000 { + compatible = "allwinner,sun8i-r40-tcon-top"; + reg = <0x01c70000 0x1000>; + clocks = <&ccu CLK_BUS_TCON_TOP>, + <&ccu CLK_TCON_TV0>, + <&ccu CLK_TVE0>, + <&ccu CLK_TCON_TV1>, + <&ccu CLK_TVE1>, + <&ccu CLK_DSI_DPHY>; + clock-names = "bus", + "tcon-tv0", + "tve0", + "tcon-tv1", + "tve1", + "dsi"; + clock-output-names = "tcon-top-tv0", + "tcon-top-tv1", + "tcon-top-dsi"; + resets = <&ccu RST_BUS_TCON_TOP>; + #clock-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon_top_mixer0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon_top_mixer0_in_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mixer0_out_tcon_top>; + }; + }; + + tcon_top_mixer0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { + reg = <0>; + }; + + tcon_top_mixer0_out_tcon_lcd1: endpoint@1 { + reg = <1>; + }; + + tcon_top_mixer0_out_tcon_tv0: endpoint@2 { + reg = <2>; + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; + }; + + tcon_top_mixer0_out_tcon_tv1: endpoint@3 { + reg = <3>; + remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>; + }; + }; + + tcon_top_mixer1_in: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + tcon_top_mixer1_in_mixer1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mixer1_out_tcon_top>; + }; + }; + + tcon_top_mixer1_out: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { + reg = <0>; + }; + + tcon_top_mixer1_out_tcon_lcd1: endpoint@1 { + reg = <1>; + }; + + tcon_top_mixer1_out_tcon_tv0: endpoint@2 { + reg = <2>; + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; + }; + + tcon_top_mixer1_out_tcon_tv1: endpoint@3 { + reg = <3>; + remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>; + }; + }; + + tcon_top_hdmi_in: port@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + tcon_top_hdmi_in_tcon_tv0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_tv0_out_tcon_top>; + }; + + tcon_top_hdmi_in_tcon_tv1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_tv1_out_tcon_top>; + }; + }; + + tcon_top_hdmi_out: port@5 { + reg = <5>; + + tcon_top_hdmi_out_hdmi: endpoint { + remote-endpoint = <&hdmi_in_tcon_top>; + }; + }; + }; + }; + + tcon_tv0: lcd-controller@1c73000 { + compatible = "allwinner,sun8i-r40-tcon-tv"; + reg = <0x01c73000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>; + clock-names = "ahb", "tcon-ch1"; + resets = <&ccu RST_BUS_TCON_TV0>; + reset-names = "lcd"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon_tv0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon_tv0_in_tcon_top_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; + }; + + tcon_tv0_in_tcon_top_mixer1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; + }; + }; + + tcon_tv0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon_tv0_out_tcon_top: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; + }; + }; + }; + }; + + tcon_tv1: lcd-controller@1c74000 { + compatible = "allwinner,sun8i-r40-tcon-tv"; + reg = <0x01c74000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top 1>; + clock-names = "ahb", "tcon-ch1"; + resets = <&ccu RST_BUS_TCON_TV1>; + reset-names = "lcd"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon_tv1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon_tv1_in_tcon_top_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>; + }; + + tcon_tv1_in_tcon_top_mixer1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>; + }; + }; + + tcon_tv1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon_tv1_out_tcon_top: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>; + }; + }; + }; + }; + + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x1000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + }; + + hdmi: hdmi@1ee0000 { + compatible = "allwinner,sun8i-r40-dw-hdmi", + "allwinner,sun8i-a83t-dw-hdmi"; + reg = <0x01ee0000 0x10000>; + reg-io-width = <1>; + interrupts = ; + clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>, + <&ccu CLK_HDMI>; + clock-names = "iahb", "isfr", "tmds"; + resets = <&ccu RST_BUS_HDMI1>; + reset-names = "ctrl"; + phys = <&hdmi_phy>; + phy-names = "hdmi-phy"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + + hdmi_in_tcon_top: endpoint { + remote-endpoint = <&tcon_top_hdmi_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + + hdmi_phy: hdmi-phy@1ef0000 { + compatible = "allwinner,sun8i-r40-hdmi-phy"; + reg = <0x01ef0000 0x10000>; + clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>, + <&ccu 7>, <&ccu 16>; + clock-names = "bus", "mod", "pll-0", "pll-1"; + resets = <&ccu RST_BUS_HDMI0>; + reset-names = "phy"; + #phy-cells = <0>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; +}; -- cgit v1.2.3