// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r8a77470 SoC * * Copyright (C) 2018 Renesas Electronics Corp. */ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/r8a77470-cpg-mssr.h> / { compatible = "renesas,r8a77470"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0>; clock-frequency = <1000000000>; clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>; power-domains = <&sysc 5>; next-level-cache = <&L2_CA7>; }; L2_CA7: cache-controller-0 { compatible = "cache"; cache-unified; cache-level = <2>; power-domains = <&sysc 21>; }; }; /* External root clock */ extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; }; /* External SCIF clock */ scif_clk: scif { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; }; soc { compatible = "simple-bus"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; ranges; cpg: clock-controller@e6150000 { compatible = "renesas,r8a77470-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; clocks = <&extal_clk>, <&usb_extal_clk>; clock-names = "extal", "usb_extal"; #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77470-rst"; reg = <0 0xe6160000 0 0x100>; }; sysc: system-controller@e6180000 { compatible = "renesas,r8a77470-sysc"; reg = <0 0xe6180000 0 0x200>; #power-domain-cells = <1>; }; irqc: interrupt-controller@e61c0000 { compatible = "renesas,irqc-r8a77470", "renesas,irqc"; #interrupt-cells = <2>; interrupt-controller; reg = <0 0xe61c0000 0 0x200>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 407>; power-domains = <&sysc 32>; resets = <&cpg 407>; }; icram0: sram@e63a0000 { compatible = "mmio-sram"; reg = <0 0xe63a0000 0 0x12000>; }; icram1: sram@e63c0000 { compatible = "mmio-sram"; reg = <0 0xe63c0000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0xe63c0000 0x1000>; smp-sram@0 { compatible = "renesas,smp-sram"; reg = <0 0x100>; }; }; icram2: sram@e6300000 { compatible = "mmio-sram"; reg = <0 0xe6300000 0 0x20000>; }; dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a77470", "renesas,rcar-dmac"; reg = <0 0xe6700000 0 0x20000>; interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; clocks = <&cpg CPG_MOD 219>; clock-names = "fck"; power-domains = <&sysc 32>; resets = <&cpg 219>; #dma-cells = <1>; dma-channels = <15>; }; dmac1: dma-controller@e6720000 { compatible = "renesas,dmac-r8a77470", "renesas,rcar-dmac"; reg = <0 0xe6720000 0 0x20000>; interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; power-domains = <&sysc 32>; resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <15>; }; avb: ethernet@e6800000 { compatible = "renesas,etheravb-r8a77470", "renesas,etheravb-rcar-gen2"; reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc 32>; resets = <&cpg 812>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; scif0: serial@e6e60000 { compatible = "renesas,scif-r8a77470", "renesas,rcar-gen2-scif", "renesas,scif"; reg = <0 0xe6e60000 0 0x40>; interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc 32>; resets = <&cpg 721>; status = "disabled"; }; scif1: serial@e6e68000 { compatible = "renesas,scif-r8a77470", "renesas,rcar-gen2-scif", "renesas,scif"; reg = <0 0xe6e68000 0 0x40>; interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, <&dmac1 0x2d>, <&dmac1 0x2e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc 32>; resets = <&cpg 720>; status = "disabled"; }; scif2: serial@e6e58000 { compatible = "renesas,scif-r8a77470", "renesas,rcar-gen2-scif", "renesas,scif"; reg = <0 0xe6e58000 0 0x40>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, <&dmac1 0x2b>, <&dmac1 0x2c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc 32>; resets = <&cpg 719>; status = "disabled"; }; scif3: serial@e6ea8000 { compatible = "renesas,scif-r8a77470", "renesas,rcar-gen2-scif", "renesas,scif"; reg = <0 0xe6ea8000 0 0x40>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2f>, <&dmac0 0x30>, <&dmac1 0x2f>, <&dmac1 0x30>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc 32>; resets = <&cpg 718>; status = "disabled"; }; scif4: serial@e6ee0000 { compatible = "renesas,scif-r8a77470", "renesas,rcar-gen2-scif", "renesas,scif"; reg = <0 0xe6ee0000 0 0x40>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, <&dmac1 0xfb>, <&dmac1 0xfc>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc 32>; resets = <&cpg 715>; status = "disabled"; }; scif5: serial@e6ee8000 { compatible = "renesas,scif-r8a77470", "renesas,rcar-gen2-scif", "renesas,scif"; reg = <0 0xe6ee8000 0 0x40>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, <&dmac1 0xfd>, <&dmac1 0xfe>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc 32>; resets = <&cpg 714>; status = "disabled"; }; gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc 32>; resets = <&cpg 408>; }; prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; }; }; timer { compatible = "arm,armv7-timer"; interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; }; /* External USB clock - can be overridden by the board */ usb_extal_clk: usb_extal { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; };