// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Freescale Layerscape-1046A family SoC. * * Copyright 2016 Freescale Semiconductor, Inc. * * Shaohui Xie <Shaohui.Xie@nxp.com> */ /dts-v1/; #include "fsl-ls1046a.dtsi" / { model = "LS1046A QDS Board"; compatible = "fsl,ls1046a-qds", "fsl,ls1046a"; aliases { gpio0 = &gpio0; gpio1 = &gpio1; gpio2 = &gpio2; gpio3 = &gpio3; serial0 = &duart0; serial1 = &duart1; serial2 = &duart2; serial3 = &duart3; }; chosen { stdout-path = "serial0:115200n8"; }; }; &dspi { bus-num = <0>; status = "okay"; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "n25q128a11", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <10000000>; }; flash@1 { #address-cells = <1>; #size-cells = <1>; compatible = "sst25wf040b", "jedec,spi-nor"; spi-cpol; spi-cpha; reg = <1>; spi-max-frequency = <10000000>; }; flash@2 { #address-cells = <1>; #size-cells = <1>; compatible = "en25s64", "jedec,spi-nor"; spi-cpol; spi-cpha; reg = <2>; spi-max-frequency = <10000000>; }; }; &duart0 { status = "okay"; }; &duart1 { status = "okay"; }; &i2c0 { status = "okay"; pca9547@77 { compatible = "nxp,pca9547"; reg = <0x77>; #address-cells = <1>; #size-cells = <0>; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <0x2>; ina220@40 { compatible = "ti,ina220"; reg = <0x40>; shunt-resistor = <1000>; }; ina220@41 { compatible = "ti,ina220"; reg = <0x41>; shunt-resistor = <1000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <0x3>; rtc@51 { compatible = "nxp,pcf2129"; reg = <0x51>; /* IRQ10_B */ interrupts = <0 150 0x4>; }; eeprom@56 { compatible = "atmel,24c512"; reg = <0x56>; }; eeprom@57 { compatible = "atmel,24c512"; reg = <0x57>; }; temp-sensor@4c { compatible = "adi,adt7461a"; reg = <0x4c>; }; }; }; }; &ifc { #address-cells = <2>; #size-cells = <1>; /* NOR, NAND Flashes and FPGA on board */ ranges = <0x0 0x0 0x0 0x60000000 0x08000000 0x1 0x0 0x0 0x7e800000 0x00010000 0x2 0x0 0x0 0x7fb00000 0x00000100>; status = "okay"; nor@0,0 { compatible = "cfi-flash"; reg = <0x0 0x0 0x8000000>; bank-width = <2>; device-width = <1>; }; nand@1,0 { compatible = "fsl,ifc-nand"; reg = <0x1 0x0 0x10000>; }; fpga: board-control@2,0 { compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis"; reg = <0x2 0x0 0x0000100>; }; }; &lpuart0 { status = "okay"; }; &qspi { num-cs = <2>; bus-num = <0>; status = "okay"; qflash0: s25fl128s@0 { compatible = "spansion,m25p80"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; reg = <0>; }; }; #include "fsl-ls1046-post.dtsi"