1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
|
/*
* Hisilicon Ltd. Hi3620 SoC
*
* Copyright (C) 2012-2013 Hisilicon Ltd.
* Copyright (C) 2012-2013 Linaro Ltd.
*
* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
#include <dt-bindings/clock/hi3620-clock.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
};
pclk: clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "apb_pclk";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "hisilicon,hi3620-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0x0>;
next-level-cache = <&L2>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
};
cpu@2 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <2>;
next-level-cache = <&L2>;
};
cpu@3 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <3>;
next-level-cache = <&L2>;
};
};
amba {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges = <0 0xfc000000 0x2000000>;
L2: l2-cache {
compatible = "arm,pl310-cache";
reg = <0x100000 0x100000>;
interrupts = <0 15 4>;
cache-unified;
cache-level = <2>;
};
gic: interrupt-controller@1000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
/* gic dist base, gic cpu base */
reg = <0x1000 0x1000>, <0x100 0x100>;
};
sysctrl: system-controller@802000 {
compatible = "hisilicon,sysctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x802000 0x1000>;
reg = <0x802000 0x1000>;
smp-offset = <0x31c>;
resume-offset = <0x308>;
reboot-offset = <0x4>;
clock: clock@0 {
compatible = "hisilicon,hi3620-clock";
reg = <0 0x10000>;
#clock-cells = <1>;
};
};
dual_timer0: dual_timer@800000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x800000 0x1000>;
/* timer00 & timer01 */
interrupts = <0 0 4>, <0 1 4>;
clocks = <&clock HI3620_TIMER0_MUX>, <&clock HI3620_TIMER1_MUX>;
clock-names = "apb_pclk";
status = "disabled";
};
dual_timer1: dual_timer@801000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x801000 0x1000>;
/* timer10 & timer11 */
interrupts = <0 2 4>, <0 3 4>;
clocks = <&clock HI3620_TIMER2_MUX>, <&clock HI3620_TIMER3_MUX>;
clock-names = "apb_pclk";
status = "disabled";
};
dual_timer2: dual_timer@a01000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0xa01000 0x1000>;
/* timer20 & timer21 */
interrupts = <0 4 4>, <0 5 4>;
clocks = <&clock HI3620_TIMER4_MUX>, <&clock HI3620_TIMER5_MUX>;
clock-names = "apb_pclk";
status = "disabled";
};
dual_timer3: dual_timer@a02000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0xa02000 0x1000>;
/* timer30 & timer31 */
interrupts = <0 6 4>, <0 7 4>;
clocks = <&clock HI3620_TIMER6_MUX>, <&clock HI3620_TIMER7_MUX>;
clock-names = "apb_pclk";
status = "disabled";
};
dual_timer4: dual_timer@a03000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0xa03000 0x1000>;
/* timer40 & timer41 */
interrupts = <0 96 4>, <0 97 4>;
clocks = <&clock HI3620_TIMER8_MUX>, <&clock HI3620_TIMER9_MUX>;
clock-names = "apb_pclk";
status = "disabled";
};
timer5: timer@600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x600 0x20>;
interrupts = <1 13 0xf01>;
};
uart0: uart@b00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb00000 0x1000>;
interrupts = <0 20 4>;
clocks = <&clock HI3620_UARTCLK0>;
clock-names = "apb_pclk";
status = "disabled";
};
uart1: uart@b01000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb01000 0x1000>;
interrupts = <0 21 4>;
clocks = <&clock HI3620_UARTCLK1>;
clock-names = "apb_pclk";
status = "disabled";
};
uart2: uart@b02000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb02000 0x1000>;
interrupts = <0 22 4>;
clocks = <&clock HI3620_UARTCLK2>;
clock-names = "apb_pclk";
status = "disabled";
};
uart3: uart@b03000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb03000 0x1000>;
interrupts = <0 23 4>;
clocks = <&clock HI3620_UARTCLK3>;
clock-names = "apb_pclk";
status = "disabled";
};
uart4: uart@b04000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb04000 0x1000>;
interrupts = <0 24 4>;
clocks = <&clock HI3620_UARTCLK4>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio0: gpio@806000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x806000 0x1000>;
interrupts = <0 64 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1
&pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK0>;
clock-names = "apb_pclk";
};
gpio1: gpio@807000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x807000 0x1000>;
interrupts = <0 65 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
&pmx0 3 3 1 &pmx0 4 3 1 &pmx0 5 4 1
&pmx0 6 5 1 &pmx0 7 6 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK1>;
clock-names = "apb_pclk";
};
gpio2: gpio@808000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x808000 0x1000>;
interrupts = <0 66 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1
&pmx0 3 10 1 &pmx0 4 3 1 &pmx0 5 3 1
&pmx0 6 3 1 &pmx0 7 3 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK2>;
clock-names = "apb_pclk";
};
gpio3: gpio@809000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x809000 0x1000>;
interrupts = <0 67 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
&pmx0 3 3 1 &pmx0 4 11 1 &pmx0 5 11 1
&pmx0 6 11 1 &pmx0 7 11 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK3>;
clock-names = "apb_pclk";
};
gpio4: gpio@80a000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x80a000 0x1000>;
interrupts = <0 68 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1
&pmx0 3 11 1 &pmx0 4 12 1 &pmx0 5 12 1
&pmx0 6 13 1 &pmx0 7 13 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK4>;
clock-names = "apb_pclk";
};
gpio5: gpio@80b000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x80b000 0x1000>;
interrupts = <0 69 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1
&pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1
&pmx0 6 16 1 &pmx0 7 16 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK5>;
clock-names = "apb_pclk";
};
gpio6: gpio@80c000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x80c000 0x1000>;
interrupts = <0 70 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1
&pmx0 3 17 1 &pmx0 4 18 1 &pmx0 5 18 1
&pmx0 6 18 1 &pmx0 7 19 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK6>;
clock-names = "apb_pclk";
};
gpio7: gpio@80d000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x80d000 0x1000>;
interrupts = <0 71 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1
&pmx0 3 22 1 &pmx0 4 23 1 &pmx0 5 24 1
&pmx0 6 25 1 &pmx0 7 26 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK7>;
clock-names = "apb_pclk";
};
gpio8: gpio@80e000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x80e000 0x1000>;
interrupts = <0 72 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1
&pmx0 3 30 1 &pmx0 4 31 1 &pmx0 5 32 1
&pmx0 6 33 1 &pmx0 7 34 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK8>;
clock-names = "apb_pclk";
};
gpio9: gpio@80f000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x80f000 0x1000>;
interrupts = <0 73 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1
&pmx0 3 38 1 &pmx0 4 39 1 &pmx0 5 40 1
&pmx0 6 41 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK9>;
clock-names = "apb_pclk";
};
gpio10: gpio@810000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x810000 0x1000>;
interrupts = <0 74 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1
&pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK10>;
clock-names = "apb_pclk";
};
gpio11: gpio@811000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x811000 0x1000>;
interrupts = <0 75 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1
&pmx0 3 47 1 &pmx0 4 47 1 &pmx0 5 48 1
&pmx0 6 49 1 &pmx0 7 49 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK11>;
clock-names = "apb_pclk";
};
gpio12: gpio@812000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x812000 0x1000>;
interrupts = <0 76 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1
&pmx0 3 49 1 &pmx0 4 51 1 &pmx0 5 51 1
&pmx0 6 51 1 &pmx0 7 52 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK12>;
clock-names = "apb_pclk";
};
gpio13: gpio@813000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x813000 0x1000>;
interrupts = <0 77 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1
&pmx0 3 53 1 &pmx0 4 53 1 &pmx0 5 54 1
&pmx0 6 55 1 &pmx0 7 56 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK13>;
clock-names = "apb_pclk";
};
gpio14: gpio@814000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x814000 0x1000>;
interrupts = <0 78 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1
&pmx0 3 58 1 &pmx0 4 59 1 &pmx0 5 60 1
&pmx0 6 60 1 &pmx0 7 61 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK14>;
clock-names = "apb_pclk";
};
gpio15: gpio@815000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x815000 0x1000>;
interrupts = <0 79 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1
&pmx0 3 63 1 &pmx0 4 63 1 &pmx0 5 64 1
&pmx0 6 64 1 &pmx0 7 65 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK15>;
clock-names = "apb_pclk";
};
gpio16: gpio@816000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x816000 0x1000>;
interrupts = <0 80 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1
&pmx0 3 69 1 &pmx0 4 70 1 &pmx0 5 71 1
&pmx0 6 72 1 &pmx0 7 73 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK16>;
clock-names = "apb_pclk";
};
gpio17: gpio@817000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x817000 0x1000>;
interrupts = <0 81 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1
&pmx0 3 77 1 &pmx0 4 78 1 &pmx0 5 79 1
&pmx0 6 80 1 &pmx0 7 81 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK17>;
clock-names = "apb_pclk";
};
gpio18: gpio@818000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x818000 0x1000>;
interrupts = <0 82 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1
&pmx0 3 84 1 &pmx0 4 84 1 &pmx0 5 85 1
&pmx0 6 86 1 &pmx0 7 87 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK18>;
clock-names = "apb_pclk";
};
gpio19: gpio@819000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x819000 0x1000>;
interrupts = <0 83 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1
&pmx0 3 88 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK19>;
clock-names = "apb_pclk";
};
gpio20: gpio@81a000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x81a000 0x1000>;
interrupts = <0 84 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1
&pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK20>;
clock-names = "apb_pclk";
};
gpio21: gpio@81b000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x81b000 0x1000>;
interrupts = <0 85 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 3 94 1 &pmx0 7 96 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK21>;
clock-names = "apb_pclk";
};
pmx0: pinmux@803000 {
compatible = "pinctrl-single";
reg = <0x803000 0x188>;
#address-cells = <1>;
#size-cells = <1>;
#pinctrl-cells = <1>;
#gpio-range-cells = <3>;
ranges;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <7>;
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
&range 12 1 0 &range 13 29 1
&range 43 1 0 &range 44 49 1
&range 94 1 1 &range 96 2 1>;
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
};
pmx1: pinmux@803800 {
compatible = "pinconf-single";
reg = <0x803800 0x2dc>;
#address-cells = <1>;
#size-cells = <1>;
#pinctrl-cells = <1>;
ranges;
pinctrl-single,register-width = <32>;
};
};
};
|
