summaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/imx6dl-gw53xx.dts
blob: 9bfc620d37bd0601d925b0dc7faa9e9d0aa3f032 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
/*
 * Copyright 2013 Gateworks Corporation
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-gw53xx.dtsi"

/ {
	model = "Gateworks Ventana i.MX6 DualLite/Solo GW53XX";
	compatible = "gw,imx6dl-gw53xx", "gw,ventana", "fsl,imx6dl";
};

&i2c3 {
	adv7180: camera@20 {
		compatible = "adi,adv7180";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_adv7180>;
		reg = <0x20>;
		powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
		interrupt-parent = <&gpio3>;
		interrupts = <30 IRQ_TYPE_LEVEL_LOW>;

		port {
			adv7180_to_ipu1_csi1_mux: endpoint {
				remote-endpoint = <&ipu1_csi1_mux_from_parallel_sensor>;
				bus-width = <8>;
			};
		};
	};
};

&ipu1_csi1_from_ipu1_csi1_mux {
	bus-width = <8>;
};

&ipu1_csi1_mux_from_parallel_sensor {
	remote-endpoint = <&adv7180_to_ipu1_csi1_mux>;
	bus-width = <8>;
};

&ipu1_csi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ipu1_csi1>;
};

&iomuxc {
	pinctrl_adv7180: adv7180grp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D30__GPIO3_IO30          0x0001b0b0
			MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x4001b0b0
		>;
	};

	pinctrl_ipu1_csi1: ipu1_csi1grp {
		fsl,pins = <
			MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19    0x1b0b0
			MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18    0x1b0b0
			MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17    0x1b0b0
			MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16    0x1b0b0
			MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15    0x1b0b0
			MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14    0x1b0b0
			MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13    0x1b0b0
			MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12    0x1b0b0
			MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC     0x1b0b0
			MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC     0x1b0b0
			MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK    0x1b0b0
		>;
	};
};