1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
|
/*
* IEEE754 floating point arithmetic
* single precision: MADDF.f (Fused Multiply Add)
* MADDF.fmt: FPR[fd] = FPR[fd] + (FPR[fs] x FPR[ft])
*
* MIPS floating point support
* Copyright (C) 2015 Imagination Technologies, Ltd.
* Author: Markos Chandras <markos.chandras@imgtec.com>
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; version 2 of the License.
*/
#include "ieee754sp.h"
static union ieee754sp _sp_maddf(union ieee754sp z, union ieee754sp x,
union ieee754sp y, enum maddf_flags flags)
{
int re;
int rs;
unsigned int rm;
u64 rm64;
u64 zm64;
int s;
COMPXSP;
COMPYSP;
COMPZSP;
EXPLODEXSP;
EXPLODEYSP;
EXPLODEZSP;
FLUSHXSP;
FLUSHYSP;
FLUSHZSP;
ieee754_clearcx();
/*
* Handle the cases when at least one of x, y or z is a NaN.
* Order of precedence is sNaN, qNaN and z, x, y.
*/
if (zc == IEEE754_CLASS_SNAN)
return ieee754sp_nanxcpt(z);
if (xc == IEEE754_CLASS_SNAN)
return ieee754sp_nanxcpt(x);
if (yc == IEEE754_CLASS_SNAN)
return ieee754sp_nanxcpt(y);
if (zc == IEEE754_CLASS_QNAN)
return z;
if (xc == IEEE754_CLASS_QNAN)
return x;
if (yc == IEEE754_CLASS_QNAN)
return y;
if (zc == IEEE754_CLASS_DNORM)
SPDNORMZ;
/* ZERO z cases are handled separately below */
switch (CLPAIR(xc, yc)) {
/*
* Infinity handling
*/
case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO):
case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF):
ieee754_setcx(IEEE754_INVALID_OPERATION);
return ieee754sp_indef();
case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF):
case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF):
case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM):
case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM):
case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF):
if ((zc == IEEE754_CLASS_INF) &&
((!(flags & MADDF_NEGATE_PRODUCT) && (zs != (xs ^ ys))) ||
((flags & MADDF_NEGATE_PRODUCT) && (zs == (xs ^ ys))))) {
/*
* Cases of addition of infinities with opposite signs
* or subtraction of infinities with same signs.
*/
ieee754_setcx(IEEE754_INVALID_OPERATION);
return ieee754sp_indef();
}
/*
* z is here either not an infinity, or an infinity having the
* same sign as product (x*y) (in case of MADDF.D instruction)
* or product -(x*y) (in MSUBF.D case). The result must be an
* infinity, and its sign is determined only by the value of
* (flags & MADDF_NEGATE_PRODUCT) and the signs of x and y.
*/
if (flags & MADDF_NEGATE_PRODUCT)
return ieee754sp_inf(1 ^ (xs ^ ys));
else
return ieee754sp_inf(xs ^ ys);
case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO):
case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM):
case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_DNORM):
case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO):
case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO):
if (zc == IEEE754_CLASS_INF)
return ieee754sp_inf(zs);
if (zc == IEEE754_CLASS_ZERO) {
/* Handle cases +0 + (-0) and similar ones. */
if ((!(flags & MADDF_NEGATE_PRODUCT)
&& (zs == (xs ^ ys))) ||
((flags & MADDF_NEGATE_PRODUCT)
&& (zs != (xs ^ ys))))
/*
* Cases of addition of zeros of equal signs
* or subtraction of zeroes of opposite signs.
* The sign of the resulting zero is in any
* such case determined only by the sign of z.
*/
return z;
return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD);
}
/* x*y is here 0, and z is not 0, so just return z */
return z;
case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM):
SPDNORMX;
/* fall through */
case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM):
if (zc == IEEE754_CLASS_INF)
return ieee754sp_inf(zs);
SPDNORMY;
break;
case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_NORM):
if (zc == IEEE754_CLASS_INF)
return ieee754sp_inf(zs);
SPDNORMX;
break;
case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM):
if (zc == IEEE754_CLASS_INF)
return ieee754sp_inf(zs);
/* continue to real computations */
}
/* Finally get to do some computation */
/*
* Do the multiplication bit first
*
* rm = xm * ym, re = xe + ye basically
*
* At this point xm and ym should have been normalized.
*/
/* rm = xm * ym, re = xe+ye basically */
assert(xm & SP_HIDDEN_BIT);
assert(ym & SP_HIDDEN_BIT);
re = xe + ye;
rs = xs ^ ys;
if (flags & MADDF_NEGATE_PRODUCT)
rs ^= 1;
/* Multiple 24 bit xm and ym to give 48 bit results */
rm64 = (uint64_t)xm * ym;
/* Shunt to top of word */
rm64 = rm64 << 16;
/* Put explicit bit at bit 62 if necessary */
if ((int64_t) rm64 < 0) {
rm64 = rm64 >> 1;
re++;
}
assert(rm64 & (1 << 62));
if (zc == IEEE754_CLASS_ZERO) {
/*
* Move explicit bit from bit 62 to bit 26 since the
* ieee754sp_format code expects the mantissa to be
* 27 bits wide (24 + 3 rounding bits).
*/
rm = XSPSRS64(rm64, (62 - 26));
return ieee754sp_format(rs, re, rm);
}
/* Move explicit bit from bit 23 to bit 62 */
zm64 = (uint64_t)zm << (62 - 23);
assert(zm64 & (1 << 62));
/* Make the exponents the same */
if (ze > re) {
/*
* Have to shift r fraction right to align.
*/
s = ze - re;
rm64 = XSPSRS64(rm64, s);
re += s;
} else if (re > ze) {
/*
* Have to shift z fraction right to align.
*/
s = re - ze;
zm64 = XSPSRS64(zm64, s);
ze += s;
}
assert(ze == re);
assert(ze <= SP_EMAX);
/* Do the addition */
if (zs == rs) {
/*
* Generate 64 bit result by adding two 63 bit numbers
* leaving result in zm64, zs and ze.
*/
zm64 = zm64 + rm64;
if ((int64_t)zm64 < 0) { /* carry out */
zm64 = XSPSRS1(zm64);
ze++;
}
} else {
if (zm64 >= rm64) {
zm64 = zm64 - rm64;
} else {
zm64 = rm64 - zm64;
zs = rs;
}
if (zm64 == 0)
return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD);
/*
* Put explicit bit at bit 62 if necessary.
*/
while ((zm64 >> 62) == 0) {
zm64 <<= 1;
ze--;
}
}
/*
* Move explicit bit from bit 62 to bit 26 since the
* ieee754sp_format code expects the mantissa to be
* 27 bits wide (24 + 3 rounding bits).
*/
zm = XSPSRS64(zm64, (62 - 26));
return ieee754sp_format(zs, ze, zm);
}
union ieee754sp ieee754sp_maddf(union ieee754sp z, union ieee754sp x,
union ieee754sp y)
{
return _sp_maddf(z, x, y, 0);
}
union ieee754sp ieee754sp_msubf(union ieee754sp z, union ieee754sp x,
union ieee754sp y)
{
return _sp_maddf(z, x, y, MADDF_NEGATE_PRODUCT);
}
|
