From 76cb841cb886eef6b3bee341a2266c76578724ad Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Mon, 6 May 2024 03:02:30 +0200 Subject: Adding upstream version 4.19.249. Signed-off-by: Daniel Baumann --- arch/m68k/ifpsp060/CHANGES | 120 + arch/m68k/ifpsp060/MISC | 201 + arch/m68k/ifpsp060/Makefile | 9 + arch/m68k/ifpsp060/README | 71 + arch/m68k/ifpsp060/TEST.DOC | 208 + arch/m68k/ifpsp060/fplsp.doc | 231 + arch/m68k/ifpsp060/fplsp.sa | 1946 +++ arch/m68k/ifpsp060/fpsp.doc | 295 + arch/m68k/ifpsp060/fpsp.sa | 3401 +++++ arch/m68k/ifpsp060/fskeleton.S | 342 + arch/m68k/ifpsp060/ftest.sa | 371 + arch/m68k/ifpsp060/ilsp.doc | 150 + arch/m68k/ifpsp060/ilsp.sa | 101 + arch/m68k/ifpsp060/iskeleton.S | 347 + arch/m68k/ifpsp060/isp.doc | 218 + arch/m68k/ifpsp060/isp.sa | 392 + arch/m68k/ifpsp060/itest.sa | 1281 ++ arch/m68k/ifpsp060/os.S | 396 + arch/m68k/ifpsp060/pfpsp.sa | 1730 +++ arch/m68k/ifpsp060/src/README-SRC | 12 + arch/m68k/ifpsp060/src/fplsp.S | 10980 ++++++++++++++++ arch/m68k/ifpsp060/src/fpsp.S | 24785 ++++++++++++++++++++++++++++++++++++ arch/m68k/ifpsp060/src/ftest.S | 1456 +++ arch/m68k/ifpsp060/src/ilsp.S | 932 ++ arch/m68k/ifpsp060/src/isp.S | 4299 +++++++ arch/m68k/ifpsp060/src/itest.S | 6386 ++++++++++ arch/m68k/ifpsp060/src/pfpsp.S | 14745 +++++++++++++++++++++ 27 files changed, 75405 insertions(+) create mode 100644 arch/m68k/ifpsp060/CHANGES create mode 100644 arch/m68k/ifpsp060/MISC create mode 100644 arch/m68k/ifpsp060/Makefile create mode 100644 arch/m68k/ifpsp060/README create mode 100644 arch/m68k/ifpsp060/TEST.DOC create mode 100644 arch/m68k/ifpsp060/fplsp.doc create mode 100644 arch/m68k/ifpsp060/fplsp.sa create mode 100644 arch/m68k/ifpsp060/fpsp.doc create mode 100644 arch/m68k/ifpsp060/fpsp.sa create mode 100644 arch/m68k/ifpsp060/fskeleton.S create mode 100644 arch/m68k/ifpsp060/ftest.sa create mode 100644 arch/m68k/ifpsp060/ilsp.doc create mode 100644 arch/m68k/ifpsp060/ilsp.sa create mode 100644 arch/m68k/ifpsp060/iskeleton.S create mode 100644 arch/m68k/ifpsp060/isp.doc create mode 100644 arch/m68k/ifpsp060/isp.sa create mode 100644 arch/m68k/ifpsp060/itest.sa create mode 100644 arch/m68k/ifpsp060/os.S create mode 100644 arch/m68k/ifpsp060/pfpsp.sa create mode 100644 arch/m68k/ifpsp060/src/README-SRC create mode 100644 arch/m68k/ifpsp060/src/fplsp.S create mode 100644 arch/m68k/ifpsp060/src/fpsp.S create mode 100644 arch/m68k/ifpsp060/src/ftest.S create mode 100644 arch/m68k/ifpsp060/src/ilsp.S create mode 100644 arch/m68k/ifpsp060/src/isp.S create mode 100644 arch/m68k/ifpsp060/src/itest.S create mode 100644 arch/m68k/ifpsp060/src/pfpsp.S (limited to 'arch/m68k/ifpsp060') diff --git a/arch/m68k/ifpsp060/CHANGES b/arch/m68k/ifpsp060/CHANGES new file mode 100644 index 000000000..ba9659691 --- /dev/null +++ b/arch/m68k/ifpsp060/CHANGES @@ -0,0 +1,120 @@ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP +M68000 Hi-Performance Microprocessor Division +M68060 Software Package +Production Release P1.00 -- October 10, 1994 + +M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. + +THE SOFTWARE is provided on an "AS IS" basis and without warranty. +To the maximum extent permitted by applicable law, +MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, +INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE +and any warranty against infringement with regard to the SOFTWARE +(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. + +To the maximum extent permitted by applicable law, +IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, +BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) +ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. +Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. + +You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE +so long as this entire notice is retained without alteration in any modified and/or +redistributed versions, and that such modified versions are clearly identified as such. +No licenses are granted by implication, estoppel or otherwise under any patents +or trademarks of Motorola, Inc. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +CHANGES SINCE LAST RELEASE: +--------------------------- + +1) "movep" emulation where data was being read from memory +was reading the intermediate bytes. Emulation now only +reads the required bytes. + +2) "flogn", "flog2", and "flog10" of "1" was setting the +Inexact FPSR bit. Emulation now does not set Inexact for +this case. + +3) For an opclass three FP instruction where the effective addressing +mode was pre-decrement or post-increment and the address register +was A0 or A1, the address register was not being updated as a result +of the operation. This has been corrected. + +4) Beta B.2 version had the following erratum: + + Scenario: + --------- + If {i,d}mem_{read,write}_{byte,word,long}() returns + a failing value to the 68060SP, the package ignores + this return value and continues with program execution + as if it never received a failing value. + + Effect: + ------- + For example, if a user executed "fsin.x ADDR,fp0" where + ADDR should cause a "segmentation violation", the memory read + requested by the package should return a failing value + to the package. Since the package currently ignores this + return value, the user program will continue to the + next instruction, and the result created in fp0 will be + undefined. + + Fix: + ---- + This has been fixed in the current release. + + Notes: + ------ + Upon receiving a non-zero (failing) return value from + a {i,d}mem_{read,write}_{byte,word,long}() "call-out", + the package creates a 16-byte access error stack frame + from the current exception stack frame and exits + through the "call-out" _real_access(). This is the process + as described in the MC68060 User's Manual. + + For instruction read access errors, the info stacked is: + SR = SR at time of exception + PC = PC of instruction being emulated + VOFF = $4008 (stack frame format type) + ADDRESS = PC of instruction being emulated + FSLW = FAULT STATUS LONGWORD + + The valid FSLW bits are: + bit 27 = 1 (misaligned bit) + bit 24 = 1 (read) + bit 23 = 0 (write) + bit 22:21 = 10 (SIZE = word) + bit 20:19 = 00 (TT) + bit 18:16 = x10 (TM; x = 1 for supervisor mode) + bit 15 = 1 (IO) + bit 0 = 1 (Software Emulation Error) + + all other bits are EQUAL TO ZERO and can be set by the _real_access() + "call-out" stub by the user as appropriate. The MC68060 User's Manual + stated that ONLY "bit 0" would be set. The 060SP attempts to set a few + other bits. + + For data read/write access errors, the info stacked is: + SR = SR at time of exception + PC = PC of instruction being emulated + VOFF = $4008 (stack frame format type) + ADDRESS = Address of source or destination operand + FSLW = FAULT STATUS LONGWORD + + The valid FSLW bits are: + bit 27 = 0 (misaligned bit) + bit 24 = x (read; 1 if read, 0 if write) + bit 23 = x (write; 1 if write, 0 if read) + bit 22:21 = xx (SIZE; see MC68060 User's Manual) + bit 20:19 = 00 (TT) + bit 18:16 = x01 (TM; x = 1 for supervisor mode) + bit 15 = 0 (IO) + bit 0 = 1 (Software Emulation Error) + + all other bits are EQUAL TO ZERO and can be set by the _real_access() + "call-out" stub by the user as appropriate. The MC68060 User's Manual + stated that ONLY "bit 0" would be set. The 060SP attempts to set a few + other bits. diff --git a/arch/m68k/ifpsp060/MISC b/arch/m68k/ifpsp060/MISC new file mode 100644 index 000000000..1a63913da --- /dev/null +++ b/arch/m68k/ifpsp060/MISC @@ -0,0 +1,201 @@ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP +M68000 Hi-Performance Microprocessor Division +M68060 Software Package +Production Release P1.00 -- October 10, 1994 + +M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. + +THE SOFTWARE is provided on an "AS IS" basis and without warranty. +To the maximum extent permitted by applicable law, +MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, +INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE +and any warranty against infringement with regard to the SOFTWARE +(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. + +To the maximum extent permitted by applicable law, +IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, +BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) +ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. +Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. + +You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE +so long as this entire notice is retained without alteration in any modified and/or +redistributed versions, and that such modified versions are clearly identified as such. +No licenses are granted by implication, estoppel or otherwise under any patents +or trademarks of Motorola, Inc. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +RELEASE FILE VERSIONS: +----------------------- + +fpsp.sa +---------- +freal.s : 2.4 +hdr.fpu : 2.4 +x_fovfl.s : 2.16 +x_funfl.s : 2.19 +x_funsupp.s : 2.27 +x_effadd.s : 2.21 +x_foperr.s : 2.9 +x_fsnan.s : 2.12 +x_finex.s : 2.14 +x_fdz.s : 2.5 +x_fline.s : 2.5 +x_funimp.s : 2.27 +fsin.s : 2.6 +ftan.s : 2.6 +fatan.s : 2.3 +fasin.s : 2.3 +facos.s : 2.5 +fetox.s : 2.4 +fgetem.s : 2.5 +fcosh.s : 2.4 +fsinh.s : 2.5 +ftanh.s : 2.3 +flogn.s : 2.6 +fatanh.s : 2.4 +flog2.s : 2.4 +ftwotox.s : 2.4 +fmovecr.s : 2.5 +fscale.s : 2.5 +frem_mod.s : 2.6 +fkern.s : 2.6 +fkern2.s : 2.5 +fgen_except.s: 2.7 +foptbl.s : 2.3 +fmul.s : 2.5 +fin.s : 2.4 +fdiv.s : 2.5 +fneg.s : 2.4 +ftst.s : 2.3 +fint.s : 2.3 +fintrz.s : 2.3 +fabs.s : 2.4 +fcmp.s : 2.4 +fsglmul.s : 2.5 +fsgldiv.s : 2.8 +fadd.s : 2.6 +fsub.s : 2.6 +fsqrt.s : 2.4 +fmisc.s : 2.3 +fdbcc.s : 2.8 +ftrapcc.s : 2.5 +fscc.s : 2.6 +fmovm.s : 2.15 +fctrl.s : 2.6 +fcalc_ea.s : 2.7 +fmem.s : 2.9 +fout.s : 2.9 +ireg.s : 2.6 +fdenorm.s : 2.3 +fround.s : 2.4 +fnorm.s : 2.3 +foptag_set.s: 2.4 +fresult.s : 2.3 +fpack.s : 2.6 +fdecbin.s : 2.4 +fbindec.s : 2.5 +fbinstr.s : 2.3 +faccess.s : 2.3 + +pfpsp.sa +---------- +freal.s : 2.4 +hdr.fpu : 2.4 +x_fovfl.s : 2.16 +x_funfl.s : 2.19 +x_funsupp.s : 2.27 +x_effadd.s : 2.21 +x_foperr.s : 2.9 +x_fsnan.s : 2.12 +x_finex.s : 2.14 +x_fdz.s : 2.5 +x_fline2.s : 2.3 +fcalc_ea.s : 2.7 +foptbl2.s : 2.4 +fmovm.s : 2.15 +fctrl.s : 2.6 +fmisc.s : 2.3 +fdenorm.s : 2.3 +fround.s : 2.4 +fnorm.s : 2.3 +foptag_set.s: 2.4 +fresult.s : 2.3 +fout.s : 2.9 +fmul.s : 2.5 +fin.s : 2.4 +fdiv.s : 2.5 +fneg.s : 2.4 +ftst.s : 2.3 +fint.s : 2.3 +fintrz.s : 2.3 +fabs.s : 2.4 +fcmp.s : 2.4 +fsglmul.s : 2.5 +fsgldiv.s : 2.8 +fadd.s : 2.6 +fsub.s : 2.6 +fsqrt.s : 2.4 +ireg.s : 2.6 +fpack.s : 2.6 +fdecbin.s : 2.4 +fbindec.s : 2.5 +fbinstr.s : 2.3 +faccess.s : 2.3 + +fplsp.sa +---------- +lfptop.s : 2.3 +hdr.fpu : 2.4 +fsin.s : 2.6 +ftan.s : 2.6 +fatan.s : 2.3 +fasin.s : 2.3 +facos.s : 2.5 +fetox.s : 2.4 +fgetem.s : 2.5 +fcosh.s : 2.4 +fsinh.s : 2.5 +ftanh.s : 2.3 +flogn.s : 2.6 +fatanh.s : 2.4 +flog2.s : 2.4 +ftwotox.s : 2.4 +fscale.s : 2.5 +frem_mod.s : 2.6 +l_support.s : 2.15 +fnorm.s : 2.3 + +isp.sa +---------- +ireal.s : 2.4 +hdr.int : 2.4 +x_uieh.s : 2.13 +icalc_ea.s : 2.11 +imovep.s : 2.8 +ichk2cmp2.s : 2.6 +idiv64.s : 2.10 +imul64.s : +icas2.s : 2.11 +icas.s : 2.12 +icas2_core.s: 2.6 +icas_core.s : 2.6 + +ilsp.sa +---------- +litop.s : 2.2 +l_idiv64.s : 2.8 +l_imul64.s : 2.6 +l_ichk2cmp2.s: 2.5 + +ex. files +---------- +wrk/fskeleton.s: 2.2 +wrk/iskeleton.s: 2.2 +wrk/os.s : 2.1 + +tests +---------- +itest.s : 2.2 +ftest.s : 2.1 diff --git a/arch/m68k/ifpsp060/Makefile b/arch/m68k/ifpsp060/Makefile new file mode 100644 index 000000000..43b435049 --- /dev/null +++ b/arch/m68k/ifpsp060/Makefile @@ -0,0 +1,9 @@ +# Makefile for 680x0 Linux 68060 integer/floating point support package +# +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "README.legal" in the main directory of this archive +# for more details. + +obj-y := fskeleton.o iskeleton.o os.o + +EXTRA_LDFLAGS := -x diff --git a/arch/m68k/ifpsp060/README b/arch/m68k/ifpsp060/README new file mode 100644 index 000000000..f6f8f5c59 --- /dev/null +++ b/arch/m68k/ifpsp060/README @@ -0,0 +1,71 @@ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP +M68000 Hi-Performance Microprocessor Division +M68060 Software Package +Production Release P1.00 -- October 10, 1994 + +M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. + +THE SOFTWARE is provided on an "AS IS" basis and without warranty. +To the maximum extent permitted by applicable law, +MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, +INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE +and any warranty against infringement with regard to the SOFTWARE +(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. + +To the maximum extent permitted by applicable law, +IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, +BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) +ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. +Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. + +You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE +so long as this entire notice is retained without alteration in any modified and/or +redistributed versions, and that such modified versions are clearly identified as such. +No licenses are granted by implication, estoppel or otherwise under any patents +or trademarks of Motorola, Inc. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Files in this directory: +------------------------- + +fpsp.sa Full FP Kernel Module - hex image +fpsp.s Full FP Kernel Module - source code +fpsp.doc Full FP Kernel Module - on-line documentation + +pfpsp.sa Partial FP Kernel Module - hex image +pfpsp.s Partial FP Kernel Module - source code + +fplsp.sa FP Library Module - hex image +fplsp.s FP Library Module - source code +fplsp.doc FP Library Module - on-line documentation + +isp.sa Integer Unimplemented Kernel Module - hex image +isp.s Integer Unimplemented Kernel Module - source code +isp.doc Integer Unimplemented Kernel Module - on-line doc + +ilsp.sa Integer Unimplemented Library Module - hex image +ilsp.s Integer Unimplemented Library Module - source code +ilsp.doc Integer Unimplemented Library Module - on-line doc + +fskeleton.s Sample Call-outs needed by fpsp.sa and pfpsp.sa + +iskeleton.s Sample Call-outs needed by isp.sa + +os.s Sample Call-outs needed by fpsp.sa, pfpsp.sa, and isp.sa + +ftest.sa Simple test program to test that {p}fpsp.sa + was connected properly; hex image +ftest.s above test; source code + +itest.sa Simple test program to test that isp.sa was + connected properly; hex image +itest.s above test; source code + +test.doc on-line documentation for {i,f}test.sa + +README This file + +ERRATA Known errata for this release + +MISC Release file version numbers diff --git a/arch/m68k/ifpsp060/TEST.DOC b/arch/m68k/ifpsp060/TEST.DOC new file mode 100644 index 000000000..1ba3aef15 --- /dev/null +++ b/arch/m68k/ifpsp060/TEST.DOC @@ -0,0 +1,208 @@ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP +M68000 Hi-Performance Microprocessor Division +M68060 Software Package +Production Release P1.00 -- October 10, 1994 + +M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. + +THE SOFTWARE is provided on an "AS IS" basis and without warranty. +To the maximum extent permitted by applicable law, +MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, +INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE +and any warranty against infringement with regard to the SOFTWARE +(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. + +To the maximum extent permitted by applicable law, +IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, +BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) +ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. +Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. + +You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE +so long as this entire notice is retained without alteration in any modified and/or +redistributed versions, and that such modified versions are clearly identified as such. +No licenses are granted by implication, estoppel or otherwise under any patents +or trademarks of Motorola, Inc. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +68060 SOFTWARE PACKAGE (Kernel version) SIMPLE TESTS +----------------------------------------------------- + +The files itest.sa and ftest.sa contain simple tests to check +the state of the 68060ISP and 68060FPSP once they have been installed. + +Release file format: +-------------------- +The release files itest.sa and ftest.sa are essentially +hexadecimal images of the actual tests. This format is the +ONLY format that will be supported. The hex images were created +by assembling the source code and then converting the resulting +binary output images into ASCII text files. The hexadecimal +numbers are listed using the Motorola Assembly syntax assembler +directive "dc.l" (define constant longword). The files can be +converted to other assembly syntaxes by using any word processor +with a global search and replace function. + +To assist in assembling and linking these modules with other modules, +the installer should add symbolic labels to the top of the files. +This will allow the calling routines to access the entry points +of these packages. + +The source code itest.s and ftest.s have been included but only +for documentation purposes. + +Release file structure: +----------------------- + +(top of module) + ----------------- + | | - 128 byte-sized section + (1) | Call-Out | - 4 bytes per entry (user fills these in) + | | + ----------------- + | | - 8 bytes per entry + (2) | Entry Point | - user does "bsr" or "jsr" to this address + | | + ----------------- + | | - code section + (3) ~ ~ + | | + ----------------- +(bottom of module) + +The first section of this module is the "Call-out" section. This section +is NOT INCLUDED in {i,f}test.sa (an example "Call-out" section is provided at +the end of this file). The purpose of this section is to allow the test +routines to reference external printing functions that must be provided +by the host operating system. This section MUST be exactly 128 bytes in +size. There are 32 fields, each 4 bytes in size. Each field corresponds +to a function required by the test packages (these functions and their +location are listed in "68060{ISP,FPSP}-TEST call-outs" below). Each field +entry should contain the address of the corresponding function RELATIVE to +the starting address of the "call-out" section. The "Call-out" section must +sit adjacent to the {i,f}test.sa image in memory. Since itest.sa and ftest.sa +are individual tests, they each require their own "Call-out" sections. + +The second section, the "Entry-point" section, is used by external routines +to access the test routines. Since the {i,f}test.sa hex files contain +no symbol names, this section contains function entry points that are fixed +with respect to the top of the package. The currently defined entry-points +are listed in section "68060{ISP,FPSP}-TEST entry points" below. A calling +routine would simply execute a "bsr" or "jsr" that jumped to the selected +function entry-point. + +For example, to run the 060ISP test, write a program that includes the +itest.sa data and execute something similar to: + + bsr _060ISP_TEST+128+0 + +(_060ISP_TEST is the starting address of the "Call-out" section; the "Call-out" +section is 128 bytes long; and the 68060ISP test entry point is located +0 bytes from the top of the "Entry-point" section.) + +The third section is the code section. After entering through an "Entry-point", +the entry code jumps to the appropriate test code within the code section. + +68060ISP-TEST Call-outs: +------------------------ +0x0: _print_string() +0x4: _print_number() + +68060FPSP-TEST Call-outs: +------------------------- +0x0: _print_string() +0x4: _print_number() + +The test packages call _print_string() and _print_number() +as subroutines and expect the main program to print a string +or a number to a file or to the screen. +In "C"-like fashion, the test program calls: + + print_string("Test passed"); + + or + + print_number(20); + +For _print_string(), the test programs pass a longword address +of the string on the stack. For _print_number(), the test programs pass +a longword number to be printed. + +For debugging purposes, after the main program performs a "print" +for a test package, it should flush the output so that it's not +buffered. In this way, if the test program crashes, at least the previous +statements printed will be seen. + +68060ISP-TEST Entry-points: +--------------------------- +0x0: integer test + +68060FPSP-TEST Entry-points: +---------------------------- +0x00: main fp test +0x08: FP unimplemented test +0x10: FP enabled snan/operr/ovfl/unfl/dz/inex + +The floating-point unit test has 3 entry points which will require +3 different calls to the package if each of the three following tests +is desired: + +main fp test: tests (1) unimp effective address exception + (2) unsupported data type exceptions + (3) non-maskable overflow/underflow exceptions + +FP unimplemented: tests FP unimplemented exception. this one is + separate from the previous tests for systems that don't + want FP unimplemented instructions. + +FP enabled: tests enabled snan/operr/ovfl/unfl/dz/inex. + basically, it enables each of these exceptions and forces + each using an implemented FP instruction. this process + exercises _fpsp_{snan,operr,ovfl,unfl,dz,inex}() and + _real_{snan,operr,ovfl,unfl,dz,inex}(). the test expects + _real_XXXX() to do nothing except clear the exception + and "rte". if a system's _real_XXXX() handler creates an + alternate result, the test will print "failed" but this + is acceptable. + +Miscellaneous: +-------------- +Again, itest.sa and ftest.sa are simple tests and do not thoroughly +test all 68060SP connections. For example, they do not test connections +to _real_access(), _real_trace(), _real_trap(), etc. because these +will be system-implemented several different ways and the test packages +must remain system independent. + +Example test package set-up: +---------------------------- +_print_str: + . # provided by system + rts + +_print_num: + . # provided by system + rts + + . + . + bsr _060FPSP_TEST+128+0 + . + . + rts + +# beginning of "Call-out" section; provided by integrator. +# MUST be 128 bytes long. +_060FPSP_TEST: + long _print_str - _060FPSP_TEST + long _print_num - _060FPSP_TEST + space 120 + +# ftest.sa starts here; start of "Entry-point" section. + long 0x60ff0000, 0x00002346 + long 0x60ff0000, 0x00018766 + long 0x60ff0000, 0x00023338 + long 0x24377299, 0xab2643ea + . + . + . diff --git a/arch/m68k/ifpsp060/fplsp.doc b/arch/m68k/ifpsp060/fplsp.doc new file mode 100644 index 000000000..89730a934 --- /dev/null +++ b/arch/m68k/ifpsp060/fplsp.doc @@ -0,0 +1,231 @@ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP +M68000 Hi-Performance Microprocessor Division +M68060 Software Package +Production Release P1.00 -- October 10, 1994 + +M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. + +THE SOFTWARE is provided on an "AS IS" basis and without warranty. +To the maximum extent permitted by applicable law, +MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, +INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE +and any warranty against infringement with regard to the SOFTWARE +(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. + +To the maximum extent permitted by applicable law, +IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, +BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) +ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. +Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. + +You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE +so long as this entire notice is retained without alteration in any modified and/or +redistributed versions, and that such modified versions are clearly identified as such. +No licenses are granted by implication, estoppel or otherwise under any patents +or trademarks of Motorola, Inc. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +68060 FLOATING-POINT SOFTWARE PACKAGE (Library version) +-------------------------------------------------------- + +The file fplsp.sa contains the "Library version" of the +68060SP Floating-Point Software Package. The routines +included in this module can be used to emulate the +FP instructions not implemented in 68060 hardware. These +instructions normally take exception vector #11 +"FP Unimplemented Instruction". + +By re-compiling a program that uses these instructions, and +making subroutine calls in place of the unimplemented +instructions, a program can avoid the overhead associated +with taking the exception. + +Release file format: +-------------------- +The file fplsp.sa is essentially a hexadecimal image of the +release package. This is the ONLY format which will be supported. +The hex image was created by assembling the source code and +then converting the resulting binary output image into an +ASCII text file. The hexadecimal numbers are listed +using the Motorola Assembly Syntax assembler directive "dc.l" +(define constant longword). The file can be converted to other +assembly syntaxes by using any word processor with a global +search and replace function. + +To assist in assembling and linking this module with other modules, +the installer should add a symbolic label to the top of the file. +This will allow calling routines to access the entry points +of this package. + +The source code fplsp.s has also been included but only for +documentation purposes. + +Release file structure: +----------------------- +The file fplsp.sa contains an "Entry-Point" section and a +code section. The FPLSP has no "Call-Out" section. The first section +is the "Entry-Point" section. In order to access a function in the +package, a program must "bsr" or "jsr" to the location listed +below in "68060FPLSP entry points" that corresponds to the desired +function. A branch instruction located at the selected entry point +within the package will then enter the correct emulation code routine. + +The entry point addresses at the beginning of the package will remain +fixed so that a program calling the routines will not have to be +re-compiled with every new 68060FPLSP release. + +There are 3 entry-points for each instruction type: single precision, +double precision, and extended precision. + +As an example, the "fsin" library instruction can be passed an +extended precision operand if program executes: + +# fsin.x fp0 + + fmovm.x &0x01,-(%sp) # pass operand on stack + bsr.l _060FPLSP_TOP+0x1a8 # branch to fsin routine + add.l &0xc,%sp # clear operand from stack + +Upon return, fp0 holds the correct result. The FPSR is +set correctly. The FPCR is unchanged. The FPIAR is undefined. + +Another example. This time, a dyadic operation: + +# frem.s %fp1,%fp0 + + fmov.s %fp1,-(%sp) # pass src operand + fmov.s %fp0,-(%sp) # pass dst operand + bsr.l _060FPLSP_TOP+0x168 # branch to frem routine + addq.l &0x8,%sp # clear operands from stack + +Again, the result is returned in fp0. Note that BOTH operands +are passed in single precision format. + +Exception reporting: +-------------------- +The package takes exceptions according to the FPCR value upon subroutine +entry. If an exception should be reported, then the package forces +this exception using implemented floating-point instructions. +For example, if the instruction being emulated should cause a +floating-point Operand Error exception, then the library routine +executes an FMUL of a zero and an infinity to force the OPERR +exception. Although the FPIAR will be undefined for the enabled +Operand Error exception handler, the user will at least be able +to record that the event occurred. + +Miscellaneous: +-------------- +The package does not attempt to correctly emulate instructions +with Signalling NAN inputs. Use of SNANs should be avoided with +this package. + +The fabs/fadd/fdiv/fint/fintrz/fmul/fneg/fsqrt/fsub entry points +are provided for the convenience of older compilers that make +subroutine calls for all fp instructions. The code does NOT emulate +the instruction but rather simply executes it. + +68060FPLSP entry points: +------------------------ +_060FPLSP_TOP: +0x000: _060LSP__facoss_ +0x008: _060LSP__facosd_ +0x010: _060LSP__facosx_ +0x018: _060LSP__fasins_ +0x020: _060LSP__fasind_ +0x028: _060LSP__fasinx_ +0x030: _060LSP__fatans_ +0x038: _060LSP__fatand_ +0x040: _060LSP__fatanx_ +0x048: _060LSP__fatanhs_ +0x050: _060LSP__fatanhd_ +0x058: _060LSP__fatanhx_ +0x060: _060LSP__fcoss_ +0x068: _060LSP__fcosd_ +0x070: _060LSP__fcosx_ +0x078: _060LSP__fcoshs_ +0x080: _060LSP__fcoshd_ +0x088: _060LSP__fcoshx_ +0x090: _060LSP__fetoxs_ +0x098: _060LSP__fetoxd_ +0x0a0: _060LSP__fetoxx_ +0x0a8: _060LSP__fetoxm1s_ +0x0b0: _060LSP__fetoxm1d_ +0x0b8: _060LSP__fetoxm1x_ +0x0c0: _060LSP__fgetexps_ +0x0c8: _060LSP__fgetexpd_ +0x0d0: _060LSP__fgetexpx_ +0x0d8: _060LSP__fgetmans_ +0x0e0: _060LSP__fgetmand_ +0x0e8: _060LSP__fgetmanx_ +0x0f0: _060LSP__flog10s_ +0x0f8: _060LSP__flog10d_ +0x100: _060LSP__flog10x_ +0x108: _060LSP__flog2s_ +0x110: _060LSP__flog2d_ +0x118: _060LSP__flog2x_ +0x120: _060LSP__flogns_ +0x128: _060LSP__flognd_ +0x130: _060LSP__flognx_ +0x138: _060LSP__flognp1s_ +0x140: _060LSP__flognp1d_ +0x148: _060LSP__flognp1x_ +0x150: _060LSP__fmods_ +0x158: _060LSP__fmodd_ +0x160: _060LSP__fmodx_ +0x168: _060LSP__frems_ +0x170: _060LSP__fremd_ +0x178: _060LSP__fremx_ +0x180: _060LSP__fscales_ +0x188: _060LSP__fscaled_ +0x190: _060LSP__fscalex_ +0x198: _060LSP__fsins_ +0x1a0: _060LSP__fsind_ +0x1a8: _060LSP__fsinx_ +0x1b0: _060LSP__fsincoss_ +0x1b8: _060LSP__fsincosd_ +0x1c0: _060LSP__fsincosx_ +0x1c8: _060LSP__fsinhs_ +0x1d0: _060LSP__fsinhd_ +0x1d8: _060LSP__fsinhx_ +0x1e0: _060LSP__ftans_ +0x1e8: _060LSP__ftand_ +0x1f0: _060LSP__ftanx_ +0x1f8: _060LSP__ftanhs_ +0x200: _060LSP__ftanhd_ +0x208: _060LSP__ftanhx_ +0x210: _060LSP__ftentoxs_ +0x218: _060LSP__ftentoxd_ +0x220: _060LSP__ftentoxx_ +0x228: _060LSP__ftwotoxs_ +0x230: _060LSP__ftwotoxd_ +0x238: _060LSP__ftwotoxx_ + +0x240: _060LSP__fabss_ +0x248: _060LSP__fabsd_ +0x250: _060LSP__fabsx_ +0x258: _060LSP__fadds_ +0x260: _060LSP__faddd_ +0x268: _060LSP__faddx_ +0x270: _060LSP__fdivs_ +0x278: _060LSP__fdivd_ +0x280: _060LSP__fdivx_ +0x288: _060LSP__fints_ +0x290: _060LSP__fintd_ +0x298: _060LSP__fintx_ +0x2a0: _060LSP__fintrzs_ +0x2a8: _060LSP__fintrzd_ +0x2b0: _060LSP__fintrzx_ +0x2b8: _060LSP__fmuls_ +0x2c0: _060LSP__fmuld_ +0x2c8: _060LSP__fmulx_ +0x2d0: _060LSP__fnegs_ +0x2d8: _060LSP__fnegd_ +0x2e0: _060LSP__fnegx_ +0x2e8: _060LSP__fsqrts_ +0x2f0: _060LSP__fsqrtd_ +0x2f8: _060LSP__fsqrtx_ +0x300: _060LSP__fsubs_ +0x308: _060LSP__fsubd_ +0x310: _060LSP__fsubx_ diff --git a/arch/m68k/ifpsp060/fplsp.sa b/arch/m68k/ifpsp060/fplsp.sa new file mode 100644 index 000000000..8826df032 --- /dev/null +++ b/arch/m68k/ifpsp060/fplsp.sa @@ -0,0 +1,1946 @@ + dc.l $60ff0000,$238e0000,$60ff0000,$24200000 + dc.l $60ff0000,$24b60000,$60ff0000,$11060000 + dc.l $60ff0000,$11980000,$60ff0000,$122e0000 + dc.l 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$9000f229,$48000000,$4a290000,$6b024e75 + dc.l $1d7c0008,$ff644e75,$122eff4f,$67ffffff + dc.l $f6a40c01,$00016700,$ff8e0c01,$000267ff + dc.l $fffff9f4,$0c010004,$67ffffff,$f68860ff + dc.l $fffffc00,$122eff4f,$67ffffff,$f9da0c01 + dc.l $000167ff,$fffff9d0,$0c010002,$67ffffff + dc.l $f9c60c01,$000467ff,$fffff9bc,$60ffffff + dc.l $fbd2122e,$ff4f6700,$ff5a0c01,$00016700 + dc.l $ff360c01,$000267ff,$fffff99c,$0c010004 + dc.l $67ffffff,$ff4060ff,$fffffba8,$122eff4f + dc.l $67ffffff,$f5000c01,$000167ff,$fffffd92 + dc.l $0c010002,$67ffffff,$fdb60c01,$000467ff + dc.l $fffff4e2,$60ffffff,$fb7a122e,$ff4f67ff + dc.l $fffff4d2,$0c010001,$67ffffff,$fd640c01 + dc.l $000267ff,$fffffd88,$0c010004,$67ffffff + dc.l $f4b460ff,$fffffb4c,$122eff4f,$67ffffff + dc.l $f9260c01,$000367ff,$fffffb38,$60ffffff + dc.l $f916122e,$ff4f0c01,$000367ff,$fffffb24 + dc.l $60ffffff,$fb3a2f02,$2f032028,$00042228 + dc.l $0008edc0,$2000671a,$e5a8e9c1,$30228083 + dc.l $e5a92140,$00042141,$00082002,$261f241f + dc.l $4e75edc1,$2000e5a9,$06820000,$00202141 + dc.l $000442a8,$00082002,$261f241f,$4e75ede8 + dc.l $00000004,$660eede8,$00000008,$67000074 + dc.l $06400020,$42813228,$00000241,$7fffb041 + dc.l $6e1c9240,$30280000,$02408000,$82403141 + dc.l $000061ff,$ffffff82,$103c0000,$4e750c01 + dc.l $00206e20,$e9e80840,$00042140,$00042028 + dc.l $0008e3a8,$21400008,$02688000,$0000103c + dc.l $00044e75,$04410020,$20280008,$e3a82140 + dc.l $000442a8,$00080268,$80000000,$103c0004 + dc.l $4e750268,$80000000,$103c0001,$4e7551fc diff --git a/arch/m68k/ifpsp060/fpsp.doc b/arch/m68k/ifpsp060/fpsp.doc new file mode 100644 index 000000000..23d513f72 --- /dev/null +++ b/arch/m68k/ifpsp060/fpsp.doc @@ -0,0 +1,295 @@ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP +M68000 Hi-Performance Microprocessor Division +M68060 Software Package +Production Release P1.00 -- October 10, 1994 + +M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. + +THE SOFTWARE is provided on an "AS IS" basis and without warranty. +To the maximum extent permitted by applicable law, +MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, +INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE +and any warranty against infringement with regard to the SOFTWARE +(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. + +To the maximum extent permitted by applicable law, +IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, +BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) +ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. +Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. + +You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE +so long as this entire notice is retained without alteration in any modified and/or +redistributed versions, and that such modified versions are clearly identified as such. +No licenses are granted by implication, estoppel or otherwise under any patents +or trademarks of Motorola, Inc. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +68060 FLOATING-POINT SOFTWARE PACKAGE (Kernel version) +------------------------------------------------------- + +The file fpsp.sa contains the 68060 Floating-Point Software +Package. This package is essentially a set of exception handlers +that can be integrated into an operating system. +These exception handlers emulate Unimplemented FP instructions, +instructions using unimplemented data types, and instructions +using unimplemented addressing modes. In addition, this package +includes exception handlers to provide full IEEE-754 compliant +exception handling. + +Release file format: +-------------------- +The file fpsp.sa is essentially a hexadecimal image of the +release package. This is the ONLY format which will be supported. +The hex image was created by assembling the source code and +then converting the resulting binary output image into an +ASCII text file. The hexadecimal numbers are listed +using the Motorola Assembly Syntax assembler directive "dc.l" +(define constant longword). The file can be converted to other +assembly syntaxes by using any word processor with a global +search and replace function. + +To assist in assembling and linking this module with other modules, +the installer should add a symbolic label to the top of the file. +This will allow calling routines to access the entry points +of this package. + +The source code fpsp.s has also been included but only for +documentation purposes. + +Release file structure: +----------------------- + +(top of module) + ----------------- + | | - 128 byte-sized section + (1) | Call-Out | - 4 bytes per entry (user fills these in) + | | - example routines in fskeleton.s + ----------------- + | | - 8 bytes per entry + (2) | Entry Point | - user does "bra" or "jmp" to this address + | | + ----------------- + | | - code section + (3) ~ ~ + | | + ----------------- +(bottom of module) + +The first section of this module is the "Call-out" section. This section +is NOT INCLUDED in fpsp.sa (an example "Call-out" section is provided at +the end of the file fskeleton.s). The purpose of this section is to allow +the FPSP routines to reference external functions that must be provided +by the host operating system. This section MUST be exactly 128 bytes in +size. There are 32 fields, each 4 bytes in size. Each field corresponds +to a function required by the FPSP (these functions and their location are +listed in "68060FPSP call-outs" below). Each field entry should contain +the address of the corresponding function RELATIVE to the starting address +of the "call-out" section. The "Call-out" section must sit adjacent to the +fpsp.sa image in memory. + +The second section, the "Entry-point" section, is used by external routines +to access the functions within the FPSP. Since the fpsp.sa hex file contains +no symbol names, this section contains function entry points that are fixed +with respect to the top of the package. The currently defined entry-points +are listed in section "68060 FPSP entry points" below. A calling routine +would simply execute a "bra" or "jmp" that jumped to the selected function +entry-point. + +For example, if the 68060 hardware took a "Line-F Emulator" exception +(vector #11), the operating system should execute something similar to: + + bra _060FPSP_TOP+128+48 + +(_060FPSP_TOP is the starting address of the "Call-out" section; the "Call-out" +section is 128 bytes long; and the F-Line FPSP handler entry point is located +48 bytes from the top of the "Entry-point" section.) + +The third section is the code section. After entering through an "Entry-point", +the entry code jumps to the appropriate emulation code within the code section. + +68060FPSP call-outs: (details in fskeleton.s) +-------------------- +0x000: _060_real_bsun +0x004: _060_real_snan +0x008: _060_real_operr +0x00c: _060_real_ovfl +0x010: _060_real_unfl +0x014: _060_real_dz +0x018: _060_real_inex +0x01c: _060_real_fline +0x020: _060_real_fpu_disabled +0x024: _060_real_trap +0x028: _060_real_trace +0x02c: _060_real_access +0x030: _060_fpsp_done + +0x034: (Motorola reserved) +0x038: (Motorola reserved) +0x03c: (Motorola reserved) + +0x040: _060_imem_read +0x044: _060_dmem_read +0x048: _060_dmem_write +0x04c: _060_imem_read_word +0x050: _060_imem_read_long +0x054: _060_dmem_read_byte +0x058: _060_dmem_read_word +0x05c: _060_dmem_read_long +0x060: _060_dmem_write_byte +0x064: _060_dmem_write_word +0x068: _060_dmem_write_long + +0x06c: (Motorola reserved) +0x070: (Motorola reserved) +0x074: (Motorola reserved) +0x078: (Motorola reserved) +0x07c: (Motorola reserved) + +68060FPSP entry points: +----------------------- +0x000: _060_fpsp_snan +0x008: _060_fpsp_operr +0x010: _060_fpsp_ovfl +0x018: _060_fpsp_unfl +0x020: _060_fpsp_dz +0x028: _060_fpsp_inex +0x030: _060_fpsp_fline +0x038: _060_fpsp_unsupp +0x040: _060_fpsp_effadd + + + +Miscellaneous: +-------------- + +_060_fpsp_snan: +---------------- +- documented in 3.5 of 060SP spec. +- Basic flow: + exception taken ---> enter _060_fpsp_snan --| + | + always exits through _060_real_snan <---- + +_060_fpsp_operr: +---------------- +- documented in 3.5 of 060SP spec. +- Basic flow: + exception taken ---> enter _060_fpsp_operr --| + | + always exits through _060_real_operr <----- + +_060_fpsp_dz: +---------------- +- documented in 3.7 of 060SP spec. +- Basic flow: + exception taken ---> enter _060_fpsp_dz --| + | + always exits through _060_real_dz <---- + +_060_fpsp_inex: +---------------- +- documented in 3.6 of 060SP spec. +- Basic flow: + exception taken ---> enter _060_fpsp_inex --| + | + always exits through _060_real_inex <---- + + +_060_fpsp_ovfl: +---------------- +- documented in 3.4 of 060SP spec. +- Basic flow: + exception taken ---> enter _060_fpsp_ovfl --| + | + may exit through _060_real_inex <---| + or | + may exit through _060_real_ovfl <---| + or | + may exit through _060_fpsp_done <---| + +_060_fpsp_unfl: +---------------- +- documented in 3.4 of 060SP spec. +- Basic flow: + exception taken ---> enter _060_fpsp_unfl --| + | + may exit through _060_real_inex <---| + or | + may exit through _060_real_unfl <---| + or | + may exit through _060_fpsp_done <---| + + +_060_fpsp_fline: +----------------- +- not fully documented in 060SP spec. +- Basic flow: + exception taken ---> enter _060_fpsp_fline --| + | + ------------------------------------------- + | | | + v v v + (unimplemented (fpu disabled) (possible F-line illegal) + stack frame) | v + | v special case "fmovecr"? + | exit through | + | _060_real_fpu_disabled ------------- + | | | + | ^ v v + | | (yes) (no) + | | v v + | | fpu disabled? exit through + | | | _060_real_fline + v | ------------- + | | | | + | | v v + | |-----------(yes) (no) + | | + |----<------------------------------------| + | + | + |----> may exit through _060_real_trace + | + |----> may exit through _060_real_trap + | + |----> may exit through _060_real_bsun + | + |----> may exit through _060_fpsp_done + + +_060_fpsp_unsupp: +------------------ +- documented in 3.1 of 060SP spec. +- Basic flow: + exception taken ---> enter _060_fpsp_unsupp --| + | + | + may exit through _060_real_snan <----| + or | + may exit through _060_real_operr <----| + or | + may exit through _060_real_ovfl <----| + or | + may exit through _060_real_unfl <----| + or | + may exit through _060_real_inex <----| + or | + may exit through _060_real_trace <----| + or | + may exit through _060_fpsp_done <----| + + +_060_fpsp_effadd: +------------------ +- documented in 3.3 of 060 spec. +- Basic flow: + exception taken ---> enter _060_fpsp_effadd --| + | + | + may exit through _060_real_trace <----| + or | + may exit through _060_real_fpu_disabled <----| + or | + may exit through _060_fpsp_done <----| diff --git a/arch/m68k/ifpsp060/fpsp.sa b/arch/m68k/ifpsp060/fpsp.sa new file mode 100644 index 000000000..d69486a44 --- /dev/null +++ b/arch/m68k/ifpsp060/fpsp.sa @@ -0,0 +1,3401 @@ + .long 0x60ff0000,0x17400000,0x60ff0000,0x15f40000 + .long 0x60ff0000,0x02b60000,0x60ff0000,0x04700000 + .long 0x60ff0000,0x1b100000,0x60ff0000,0x19aa0000 + .long 0x60ff0000,0x1b5a0000,0x60ff0000,0x062e0000 + .long 0x60ff0000,0x102c0000,0x51fc51fc,0x51fc51fc + .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc + .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc + .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc + .long 0x2f00203a,0xff2c487b,0x0930ffff,0xfef8202f + .long 0x00044e74,0x00042f00,0x203afef2,0x487b0930 + .long 0xfffffee2,0x202f0004,0x4e740004,0x2f00203a + .long 0xfee0487b,0x0930ffff,0xfecc202f,0x00044e74 + .long 0x00042f00,0x203afed2,0x487b0930,0xfffffeb6 + .long 0x202f0004,0x4e740004,0x2f00203a,0xfea4487b + .long 0x0930ffff,0xfea0202f,0x00044e74,0x00042f00 + .long 0x203afe96,0x487b0930,0xfffffe8a,0x202f0004 + .long 0x4e740004,0x2f00203a,0xfe7c487b,0x0930ffff + .long 0xfe74202f,0x00044e74,0x00042f00,0x203afe76 + .long 0x487b0930,0xfffffe5e,0x202f0004,0x4e740004 + .long 0x2f00203a,0xfe68487b,0x0930ffff,0xfe48202f + .long 0x00044e74,0x00042f00,0x203afe56,0x487b0930 + .long 0xfffffe32,0x202f0004,0x4e740004,0x2f00203a + .long 0xfe44487b,0x0930ffff,0xfe1c202f,0x00044e74 + .long 0x00042f00,0x203afe32,0x487b0930,0xfffffe06 + .long 0x202f0004,0x4e740004,0x2f00203a,0xfe20487b + .long 0x0930ffff,0xfdf0202f,0x00044e74,0x00042f00 + .long 0x203afe1e,0x487b0930,0xfffffdda,0x202f0004 + .long 0x4e740004,0x2f00203a,0xfe0c487b,0x0930ffff + .long 0xfdc4202f,0x00044e74,0x00042f00,0x203afdfa + .long 0x487b0930,0xfffffdae,0x202f0004,0x4e740004 + .long 0x2f00203a,0xfde8487b,0x0930ffff,0xfd98202f + .long 0x00044e74,0x00042f00,0x203afdd6,0x487b0930 + .long 0xfffffd82,0x202f0004,0x4e740004,0x2f00203a + .long 0xfdc4487b,0x0930ffff,0xfd6c202f,0x00044e74 + .long 0x00042f00,0x203afdb2,0x487b0930,0xfffffd56 + .long 0x202f0004,0x4e740004,0x2f00203a,0xfda0487b + .long 0x0930ffff,0xfd40202f,0x00044e74,0x00042f00 + .long 0x203afd8e,0x487b0930,0xfffffd2a,0x202f0004 + .long 0x4e740004,0x2f00203a,0xfd7c487b,0x0930ffff + .long 0xfd14202f,0x00044e74,0x00042f00,0x203afd6a + .long 0x487b0930,0xfffffcfe,0x202f0004,0x4e740004 + .long 0x40c62d38,0xd3d64634,0x3d6f90ae,0xb1e75cc7 + .long 0x40000000,0xc90fdaa2,0x2168c235,0x00000000 + .long 0x3fff0000,0xc90fdaa2,0x2168c235,0x00000000 + .long 0x3fe45f30,0x6dc9c883,0x4e56ff40,0xf32eff6c + .long 0x48ee0303,0xff9cf22e,0xbc00ff60,0xf22ef0c0 + .long 0xffdc2d6e,0xff68ff44,0x206eff44,0x58aeff44 + .long 0x61ffffff,0xff042d40,0xff40082e,0x0005ff42 + .long 0x66000116,0x41eeff6c,0x61ff0000,0x051c41ee + .long 0xff6c61ff,0x0000c1dc,0x1d40ff4e,0x082e0005 + .long 0xff436726,0xe9ee0183,0xff4261ff,0x0000bd22 + .long 0x41eeff78,0x61ff0000,0xc1ba0c00,0x00066606 + .long 0x61ff0000,0xc11e1d40,0xff4f4280,0x102eff63 + .long 0x122eff43,0x0241007f,0x02ae00ff,0x01ffff64 + .long 0xf23c9000,0x00000000,0xf23c8800,0x00000000 + .long 0x41eeff6c,0x43eeff78,0x223b1530,0x00007112 + .long 0x4ebb1930,0x0000710a,0xe9ee0183,0xff4261ff + .long 0x0000bd4e,0x082e0004,0xff626622,0x082e0001 + .long 0xff626644,0xf22ed0c0,0xffdcf22e,0x9c00ff60 + .long 0x4cee0303,0xff9c4e5e,0x60ffffff,0xfcc6f22e + .long 0xf040ff6c,0x3d7ce005,0xff6ef22e,0xd0c0ffdc + .long 0xf22e9c00,0xff604cee,0x0303ff9c,0xf36eff6c + .long 0x4e5e60ff,0xfffffcb2,0xf22ef040,0xff6c1d7c + .long 0x00c4000b,0x3d7ce001,0xff6ef22e,0xd0c0ffdc + .long 0xf22e9c00,0xff604cee,0x0303ff9c,0xf36eff6c + .long 0x4e5e60ff,0xfffffcae,0x1d7c0000,0xff4e4280 + .long 0x102eff63,0x02aeffff,0x00ffff64,0xf23c9000 + .long 0x00000000,0xf23c8800,0x00000000,0x41eeff6c + .long 0x61ff0000,0xb2ce082e,0x0004ff62,0x6600ff70 + .long 0x082e0001,0xff626600,0xff90f22e,0xd0c0ffdc + .long 0xf22e9c00,0xff604cee,0x0303ff9c,0x4e5e0817 + .long 0x000767ff,0xfffffc0c,0xf22fa400,0x00083f7c + .long 0x20240006,0x60ffffff,0xfcec4e56,0xff40f32e + .long 0xff6c48ee,0x0303ff9c,0xf22ebc00,0xff60f22e + .long 0xf0c0ffdc,0x2d6eff68,0xff44206e,0xff4458ae + .long 0xff4461ff,0xfffffd42,0x2d40ff40,0x082e0005 + .long 0xff426600,0x013241ee,0xff6c61ff,0x0000035a + .long 0x41eeff6c,0x61ff0000,0xc01a1d40,0xff4e082e + .long 0x0005ff43,0x672e082e,0x0004ff43,0x6626e9ee + .long 0x0183ff42,0x61ff0000,0xbb5841ee,0xff7861ff + .long 0x0000bff0,0x0c000006,0x660661ff,0x0000bf54 + .long 0x1d40ff4f,0x4280102e,0xff63122e,0xff430241 + .long 0x007f02ae,0x00ff01ff,0xff64f23c,0x90000000 + .long 0x0000f23c,0x88000000,0x000041ee,0xff6c43ee + .long 0xff78223b,0x15300000,0x6f484ebb,0x19300000 + .long 0x6f40e9ee,0x0183ff42,0x61ff0000,0xbb84082e + .long 0x0003ff62,0x6622082e,0x0001ff62,0x664ef22e + .long 0xd0c0ffdc,0xf22e9c00,0xff604cee,0x0303ff9c + .long 0x4e5e60ff,0xfffffafc,0x082e0003,0xff666700 + .long 0xffd6f22e,0xf040ff6c,0x3d7ce003,0xff6ef22e + .long 0xd0c0ffdc,0xf22e9c00,0xff604cee,0x0303ff9c + .long 0xf36eff6c,0x4e5e60ff,0xfffffaf4,0x082e0001 + .long 0xff666700,0xffaaf22e,0xf040ff6c,0x1d7c00c4 + .long 0x000b3d7c,0xe001ff6e,0xf22ed0c0,0xffdcf22e + .long 0x9c00ff60,0x4cee0303,0xff9cf36e,0xff6c4e5e + .long 0x60ffffff,0xfad01d7c,0x0000ff4e,0x4280102e + .long 0xff6302ae,0xffff00ff,0xff64f23c,0x90000000 + .long 0x0000f23c,0x88000000,0x000041ee,0xff6c61ff + .long 0x0000b0f0,0x082e0003,0xff626600,0xff66082e + .long 0x0001ff62,0x6600ff90,0xf22ed0c0,0xffdcf22e + .long 0x9c00ff60,0x4cee0303,0xff9c4e5e,0x08170007 + .long 0x67ffffff,0xfa2ef22f,0xa4000008,0x3f7c2024 + .long 0x000660ff,0xfffffb0e,0x4e56ff40,0xf32eff6c + .long 0x48ee0303,0xff9cf22e,0xbc00ff60,0xf22ef0c0 + .long 0xffdc082e,0x00050004,0x66084e68,0x2d48ffd8 + .long 0x600841ee,0x00102d48,0xffd82d6e,0xff68ff44 + .long 0x206eff44,0x58aeff44,0x61ffffff,0xfb4c2d40 + .long 0xff40422e,0xff4a082e,0x0005ff42,0x66000208 + .long 0xe9ee0006,0xff420c00,0x00136700,0x049e02ae + .long 0x00ff00ff,0xff64f23c,0x90000000,0x0000f23c + .long 0x88000000,0x000041ee,0xff6c61ff,0x0000013a + .long 0x41eeff6c,0x61ff0000,0xbdfa0c00,0x00066606 + .long 0x61ff0000,0xbd5e1d40,0xff4ee9ee,0x0183ff42 + .long 0x082e0005,0xff436728,0x0c2e003a,0xff436720 + .long 0x61ff0000,0xb92c41ee,0xff7861ff,0x0000bdc4 + .long 0x0c000006,0x660661ff,0x0000bd28,0x1d40ff4f + .long 0x4280102e,0xff63e9ee,0x1047ff43,0x41eeff6c + .long 0x43eeff78,0x223b1d30,0x00006d36,0x4ebb1930 + .long 0x00006d2e,0x102eff62,0x6634102e,0xff430200 + .long 0x00380c00,0x0038670c,0xe9ee0183,0xff4261ff + .long 0x0000b95e,0xf22ed0c0,0xffdcf22e,0x9c00ff60 + .long 0x4cee0303,0xff9c4e5e,0x60ffffff,0xf8e6c02e + .long 0xff66edc0,0x06086614,0x082e0004,0xff6667ba + .long 0x082e0001,0xff6267b2,0x60000066,0x04800000 + .long 0x00180c00,0x00066614,0x082e0003,0xff666600 + .long 0x004a082e,0x0004ff66,0x66000046,0x2f0061ff + .long 0x000007e0,0x201f3d7b,0x0222ff6e,0xf22ed0c0 + .long 0xffdcf22e,0x9c00ff60,0x4cee0303,0xff9cf36e + .long 0xff6c4e5e,0x60ffffff,0xf87ae000,0xe006e004 + .long 0xe005e003,0xe002e001,0xe001303c,0x000460bc + .long 0x303c0003,0x60b6e9ee,0x0006ff42,0x0c000011 + .long 0x67080c00,0x00156750,0x4e753028,0x00000240 + .long 0x7fff0c40,0x3f806708,0x0c40407f,0x672c4e75 + .long 0x02a87fff,0xffff0004,0x671861ff,0x0000bbbc + .long 0x44400640,0x3f810268,0x80000000,0x81680000 + .long 0x4e750268,0x80000000,0x4e750228,0x007f0004 + .long 0x00687fff,0x00004e75,0x30280000,0x02407fff + .long 0x0c403c00,0x67080c40,0x43ff67de,0x4e7502a8 + .long 0x7fffffff,0x00046606,0x4aa80008,0x67c461ff + .long 0x0000bb68,0x44400640,0x3c010268,0x80000000 + .long 0x81680000,0x4e75e9ee,0x00c3ff42,0x0c000003 + .long 0x670004a2,0x0c000007,0x6700049a,0x02aeffff + .long 0x00ffff64,0xf23c9000,0x00000000,0xf23c8800 + .long 0x00000000,0x302eff6c,0x02407fff,0x671041ee + .long 0xff6c61ff,0x0000bb5c,0x1d40ff4e,0x60061d7c + .long 0x0004ff4e,0x4280102e,0xff6341ee,0xff6c2d56 + .long 0xffd461ff,0x0000adec,0x102eff62,0x66000086 + .long 0x2caeffd4,0x082e0005,0x00046626,0x206effd8 + .long 0x4e60f22e,0xd0c0ffdc,0xf22e9c00,0xff604cee + .long 0x0303ff9c,0x4e5e0817,0x0007667a,0x60ffffff + .long 0xf7220c2e,0x0008ff4a,0x66d8f22e,0xf080ff6c + .long 0xf22ed0c0,0xffdcf22e,0x9c00ff60,0x4cee0303 + .long 0xff9c2c56,0x2f6f00c4,0x00b82f6f,0x00c800bc + .long 0x2f6f002c,0x00c42f6f,0x003000c8,0x2f6f0034 + .long 0x00ccdffc,0x000000b8,0x08170007,0x662860ff + .long 0xfffff6d0,0xc02eff66,0xedc00608,0x662a082e + .long 0x0004ff66,0x6700ff6a,0x082e0001,0xff626700 + .long 0xff606000,0x01663f7c,0x20240006,0xf22fa400 + .long 0x000860ff,0xfffff78e,0x04800000,0x0018303b + .long 0x020a4efb,0x00064afc,0x00080000,0x0000003a + .long 0x00640094,0x00000140,0x0000f22e,0xd0c0ffdc + .long 0xf22e9c00,0xff604cee,0x0303ff9c,0x3d7c30d8 + .long 0x000a3d7c,0xe006ff6e,0xf36eff6c,0x4e5e60ff + .long 0xfffff6d4,0xf22ed0c0,0xffdcf22e,0x9c00ff60 + .long 0x4cee0303,0xff9c3d7c,0x30d0000a,0x3d7ce004 + .long 0xff6ef36e,0xff6c4e5e,0x60ffffff,0xf694f22e + .long 0xf040ff6c,0xf22ed0c0,0xffdcf22e,0x9c00ff60 + .long 0x4cee0303,0xff9c3d7c,0x30d4000a,0x3d7ce005 + .long 0xff6ef36e,0xff6c4e5e,0x60ffffff,0xf60c2cae + .long 0xffd4082e,0x00050004,0x66000038,0x206effd8 + .long 0x4e60f22e,0xf040ff6c,0xf22ed0c0,0xffdcf22e + .long 0x9c00ff60,0x4cee0303,0xff9c3d7c,0x30cc000a + .long 0x3d7ce003,0xff6ef36e,0xff6c4e5e,0x60ffffff + .long 0xf5de0c2e,0x0008ff4a,0x66c8f22e,0xf080ff6c + .long 0xf22ef040,0xff78f22e,0xd0c0ffdc,0xf22e9c00 + .long 0xff604cee,0x0303ff9c,0x3d7c30cc,0x000a3d7c + .long 0xe003ff7a,0xf36eff78,0x2c562f6f,0x00c400b8 + .long 0x2f6f00c8,0x00bc2f6f,0x00cc00c0,0x2f6f002c + .long 0x00c42f6f,0x003000c8,0x2f6f0034,0x00ccdffc + .long 0x000000b8,0x60ffffff,0xf576f22e,0xf040ff6c + .long 0xf22ed0c0,0xffdcf22e,0x9c00ff60,0x4cee0303 + .long 0xff9c3d7c,0x30c4000a,0x3d7ce001,0xff6ef36e + .long 0xff6c4e5e,0x60ffffff,0xf55c02ae,0x00ff00ff + .long 0xff64f23c,0x90000000,0x0000f23c,0x88000000 + .long 0x000061ff,0x0000bdba,0x41eeff6c,0x61ff0000 + .long 0xb9621d40,0xff4ee9ee,0x0183ff42,0x082e0005 + .long 0xff436728,0x0c2e003a,0xff436720,0x61ff0000 + .long 0xb4a041ee,0xff7861ff,0x0000b938,0x0c000006 + .long 0x660661ff,0x0000b89c,0x1d40ff4f,0x4280102e + .long 0xff63e9ee,0x1047ff43,0x41eeff6c,0x43eeff78 + .long 0x223b1d30,0x000068aa,0x4ebb1930,0x000068a2 + .long 0x102eff62,0x6600008a,0x102eff43,0x02000038 + .long 0x0c000038,0x670ce9ee,0x0183ff42,0x61ff0000 + .long 0xb4d0082e,0x00050004,0x6600002a,0x206effd8 + .long 0x4e60f22e,0xd0c0ffdc,0xf22e9c00,0xff604cee + .long 0x0303ff9c,0x4e5e0817,0x00076600,0x012660ff + .long 0xfffff440,0x082e0002,0xff4a67d6,0xf22ed0c0 + .long 0xffdcf22e,0x9c00ff60,0x4cee0303,0xff9c4e5e + .long 0x2f6f0004,0x00102f6f,0x0000000c,0xdffc0000 + .long 0x000c0817,0x00076600,0x00ea60ff,0xfffff404 + .long 0xc02eff66,0xedc00608,0x6618082e,0x0004ff66 + .long 0x6700ff66,0x082e0001,0xff626700,0xff5c6000 + .long 0x006e0480,0x00000018,0x0c000006,0x6d14082e + .long 0x0003ff66,0x66000060,0x082e0004,0xff666600 + .long 0x004e082e,0x00050004,0x66000054,0x206effd8 + .long 0x4e603d7b,0x022aff6e,0xf22ed0c0,0xffdcf22e + .long 0x9c00ff60,0x4cee0303,0xff9cf36e,0xff6c4e5e + .long 0x08170007,0x6600006c,0x60ffffff,0xf386e000 + .long 0xe006e004,0xe005e003,0xe002e001,0xe001303c + .long 0x00036000,0xffae303c,0x00046000,0xffa6082e + .long 0x0002ff4a,0x67ac3d7b,0x02d6ff6e,0xf22ed0c0 + .long 0xffdcf22e,0x9c00ff60,0x4cee0303,0xff9cf36e + .long 0xff6c4e5e,0x2f6f0004,0x00102f6f,0x0000000c + .long 0xdffc0000,0x000c0817,0x00076606,0x60ffffff + .long 0xf3223f7c,0x20240006,0xf22fa400,0x000860ff + .long 0xfffff402,0x02aeffff,0x00ffff64,0xf23c9000 + .long 0x00000000,0xf23c8800,0x00000000,0xe9ee0183 + .long 0xff4261ff,0x0000b22a,0x41eeff6c,0x61ff0000 + .long 0xb7520c00,0x00066606,0x61ff0000,0xb6b61d40 + .long 0xff4e4280,0x102eff63,0x41eeff6c,0x2d56ffd4 + .long 0x61ff0000,0xa94e102e,0xff626600,0x00842cae + .long 0xffd4082e,0x00050004,0x6628206e,0xffd84e60 + .long 0xf22ed0c0,0xffdcf22e,0x9c00ff60,0x4cee0303 + .long 0xff9c4e5e,0x08170007,0x6600ff68,0x60ffffff + .long 0xf282082e,0x0003ff4a,0x67d6f22e,0xd0c0ffdc + .long 0xf22e9c00,0xff604cee,0x0303ff9c,0x2c562f6f + .long 0x00c400b8,0x2f6f00c8,0x00bc2f6f,0x003800c4 + .long 0x2f6f003c,0x00c82f6f,0x004000cc,0xdffc0000 + .long 0x00b80817,0x00076600,0xff1a60ff,0xfffff234 + .long 0xc02eff66,0xedc00608,0x6700ff74,0x2caeffd4 + .long 0x0c00001a,0x6e0000e8,0x67000072,0x082e0005 + .long 0x0004660a,0x206effd8,0x4e606000,0xfb8e0c2e + .long 0x0008ff4a,0x6600fb84,0xf22ed0c0,0xffdcf22e + .long 0x9c00ff60,0x4cee0303,0xff9c3d7c,0x30d8000a + .long 0x3d7ce006,0xff6ef36e,0xff6c2c56,0x2f6f00c4 + .long 0x00b82f6f,0x00c800bc,0x2f6f00cc,0x00c02f6f + .long 0x003800c4,0x2f6f003c,0x00c82f6f,0x004000cc + .long 0xdffc0000,0x00b860ff,0xfffff22c,0x082e0005 + .long 0x00046600,0x000c206e,0xffd84e60,0x6000fb46 + .long 0x0c2e0008,0xff4a6600,0xfb3cf22e,0xd0c0ffdc + .long 0xf22e9c00,0xff604cee,0x0303ff9c,0x3d7c30d0 + .long 0x000a3d7c,0xe004ff6e,0xf36eff6c,0x2c562f6f + .long 0x00c400b8,0x2f6f00c8,0x00bc2f6f,0x00cc00c0 + .long 0x2f6f0038,0x00c42f6f,0x003c00c8,0x2f6f0040 + .long 0x00ccdffc,0x000000b8,0x60ffffff,0xf1a4082e + .long 0x00050004,0x6600000c,0x206effd8,0x4e606000 + .long 0xfbda0c2e,0x0008ff4a,0x6600fbd0,0xf22ed0c0 + .long 0xffdcf22e,0x9c00ff60,0x4cee0303,0xff9c3d7c + .long 0x30c4000a,0x3d7ce001,0xff6ef36e,0xff6c2c56 + .long 0x2f6f00c4,0x00b82f6f,0x00c800bc,0x2f6f00cc + .long 0x00c02f6f,0x003800c4,0x2f6f003c,0x00c82f6f + .long 0x004000cc,0xdffc0000,0x00b860ff,0xfffff106 + .long 0xe9ee00c3,0xff420c00,0x00016708,0x0c000005 + .long 0x67344e75,0x302eff6c,0x02407fff,0x67260c40 + .long 0x3f806e20,0x44400640,0x3f81222e,0xff70e0a9 + .long 0x08c1001f,0x2d41ff70,0x026e8000,0xff6c006e + .long 0x3f80ff6c,0x4e75302e,0xff6c0240,0x7fff673a + .long 0x0c403c00,0x6e344a2e,0xff6c5bee,0xff6e3d40 + .long 0xff6c4280,0x41eeff6c,0x323c3c01,0x61ff0000 + .long 0xb156303c,0x3c004a2e,0xff6e6704,0x08c0000f + .long 0x08ee0007,0xff703d40,0xff6c4e75,0x082e0005 + .long 0x000467ff,0xfffff176,0x2d680000,0xff782d68 + .long 0x0004ff7c,0x2d680008,0xff804281,0x4e752f00 + .long 0x4e7a0808,0x08000001,0x66000460,0x201f4e56 + .long 0xff4048ee,0x0303ff9c,0xf22ebc00,0xff60f22e + .long 0xf0c0ffdc,0x2d6e0006,0xff44206e,0xff4458ae + .long 0xff4461ff,0xfffff152,0x2d40ff40,0x4a406b00 + .long 0x020e02ae,0x00ff00ff,0xff640800,0x000a6618 + .long 0x206eff44,0x43eeff6c,0x700c61ff,0xfffff0d2 + .long 0x4a816600,0x04926048,0x206eff44,0x43eeff6c + .long 0x700c61ff,0xfffff0ba,0x4a816600,0x047ae9ee + .long 0x004fff6c,0x0c407fff,0x6726102e,0xff6f0200 + .long 0x000f660c,0x4aaeff70,0x66064aae,0xff746710 + .long 0x41eeff6c,0x61ff0000,0xb88cf22e,0xf080ff6c + .long 0x06ae0000,0x000cff44,0x41eeff6c,0x61ff0000 + .long 0xb3c21d40,0xff4e0c00,0x0006660a,0x61ff0000 + .long 0xb3221d40,0xff4e422e,0xff53082e,0x0005ff43 + .long 0x6748082e,0x0004ff43,0x662ce9ee,0x0183ff42 + .long 0x61ff0000,0xaeec41ee,0xff7861ff,0x0000b384 + .long 0x1d40ff4f,0x0c000006,0x662061ff,0x0000b2e4 + .long 0x1d40ff4f,0x6014082e,0x0003ff43,0x670c50ee + .long 0xff53082e,0x0001ff43,0x67c04280,0x102eff63 + .long 0x122eff43,0x0241007f,0xf23c9000,0x00000000 + .long 0xf23c8800,0x00000000,0x41eeff6c,0x43eeff78 + .long 0x223b1530,0x000062ca,0x4ebb1930,0x000062c2 + .long 0x102eff62,0x66404a2e,0xff53660c,0xe9ee0183 + .long 0xff4261ff,0x0000aefa,0x2d6e0006,0xff682d6e + .long 0xff440006,0xf22ed0c0,0xffdcf22e,0x9c00ff60 + .long 0x4cee0303,0xff9c4e5e,0x08170007,0x66000096 + .long 0x60ffffff,0xee6ec02e,0xff66edc0,0x06086612 + .long 0x082e0004,0xff6667ae,0x082e0001,0xff6267ac + .long 0x60340480,0x00000018,0x0c000006,0x6610082e + .long 0x0004ff66,0x6620082e,0x0003ff66,0x66203d7b + .long 0x0206ff6e,0x601ee002,0xe006e004,0xe005e003 + .long 0xe002e001,0xe0013d7c,0xe005ff6e,0x60063d7c + .long 0xe003ff6e,0x2d6e0006,0xff682d6e,0xff440006 + .long 0xf22ed0c0,0xffdcf22e,0x9c00ff60,0x4cee0303 + .long 0xff9cf36e,0xff6c4e5e,0x08170007,0x660660ff + .long 0xffffede0,0x2f173f6f,0x00080004,0x3f7c2024 + .long 0x0006f22f,0xa4000008,0x60ffffff,0xeeb80800 + .long 0x000e6700,0x01c2082e,0x00050004,0x66164e68 + .long 0x2d48ffd8,0x61ff0000,0x9564206e,0xffd84e60 + .long 0x600001aa,0x422eff4a,0x41ee000c,0x2d48ffd8 + .long 0x61ff0000,0x95480c2e,0x0008ff4a,0x67000086 + .long 0x0c2e0004,0xff4a6600,0x0184082e,0x00070004 + .long 0x66363dae,0x00040804,0x2daeff44,0x08063dbc + .long 0x00f0080a,0x41f60804,0x2d480004,0xf22ed0c0 + .long 0xffdcf22e,0x9c00ff60,0x4cee0303,0xff9c4e5e + .long 0x2e5f60ff,0xffffed3c,0x3dae0004,0x08002dae + .long 0xff440802,0x3dbc2024,0x08062dae,0x00060808 + .long 0x41f60800,0x2d480004,0xf22ed0c0,0xffdcf22e + .long 0x9c00ff60,0x4cee0303,0xff9c4e5e,0x2e5f60ff + .long 0xffffedf2,0x1d41000a,0x1d40000b,0xf22ed0c0 + .long 0xffdcf22e,0x9c00ff60,0x4cee0303,0xff9c2f16 + .long 0x2f002f01,0x2f2eff44,0x4280102e,0x000b4480 + .long 0x082e0007,0x0004671c,0x3dae0004,0x08002dae + .long 0x00060808,0x2d9f0802,0x3dbc2024,0x08064876 + .long 0x08006014,0x3dae0004,0x08042d9f,0x08063dbc + .long 0x00f0080a,0x48760804,0x4281122e,0x000a4a01 + .long 0x6a0cf236,0xf080080c,0x06800000,0x000ce309 + .long 0x6a0cf236,0xf040080c,0x06800000,0x000ce309 + .long 0x6a0cf236,0xf020080c,0x06800000,0x000ce309 + .long 0x6a0cf236,0xf010080c,0x06800000,0x000ce309 + .long 0x6a0cf236,0xf008080c,0x06800000,0x000ce309 + .long 0x6a0cf236,0xf004080c,0x06800000,0x000ce309 + .long 0x6a0cf236,0xf002080c,0x06800000,0x000ce309 + .long 0x6a06f236,0xf001080c,0x222f0004,0x202f0008 + .long 0x2c6f000c,0x2e5f0817,0x000767ff,0xffffec04 + .long 0x60ffffff,0xecf061ff,0x00009bda,0xf22ed0c0 + .long 0xffdcf22e,0x9c00ff60,0x4cee0303,0xff9c082e + .long 0x00070004,0x660e2d6e,0xff440006,0x4e5e60ff + .long 0xffffebd0,0x2c563f6f,0x00c400c0,0x2f6f00c6 + .long 0x00c82f6f,0x000400c2,0x3f7c2024,0x00c6dffc + .long 0x000000c0,0x60ffffff,0xec9c201f,0x4e56ff40 + .long 0x48ee0303,0xff9c2d6e,0x0006ff44,0x206eff44 + .long 0x58aeff44,0x61ffffff,0xed002d40,0xff404a40 + .long 0x6b047010,0x60260800,0x000e6610,0xe9c014c3 + .long 0x700c0c01,0x00076614,0x58806010,0x428061ff + .long 0x0000967c,0x202eff44,0x90ae0006,0x3d40000a + .long 0x4cee0303,0xff9c4e5e,0x518f2f00,0x3f6f000c + .long 0x00042f6f,0x000e0006,0x4280302f,0x00122f6f + .long 0x00060010,0xd1af0006,0x3f7c402c,0x000a201f + .long 0x60ffffff,0xebe44e7a,0x08080800,0x0001660c + .long 0xf22e9c00,0xff60f22e,0xd0c0ffdc,0x4cee0303 + .long 0xff9c4e5e,0x514f2eaf,0x00083f6f,0x000c0004 + .long 0x3f7c4008,0x00062f6f,0x00020008,0x2f7c0942 + .long 0x8001000c,0x08170005,0x670608ef,0x0002000d + .long 0x60ffffff,0xebd64fee,0xff404e7a,0x18080801 + .long 0x0001660c,0xf22ed0c0,0xffdcf22f,0x9c000020 + .long 0x2c562f6f,0x00c400bc,0x3f6f00c8,0x00c03f7c + .long 0x400800c2,0x2f4800c4,0x3f4000c8,0x3f7c0001 + .long 0x00ca4cef,0x0303005c,0xdefc00bc,0x60a64e56 + .long 0xff40f32e,0xff6c48ee,0x0303ff9c,0xf22ebc00 + .long 0xff60f22e,0xf0c0ffdc,0x2d6eff68,0xff44206e + .long 0xff4458ae,0xff4461ff,0xffffebce,0x2d40ff40 + .long 0x0800000d,0x662841ee,0xff6c61ff,0xfffff1ea + .long 0xf22ed0c0,0xffdcf22e,0x9c00ff60,0x4cee0303 + .long 0xff9cf36e,0xff6c4e5e,0x60ffffff,0xea94322e + .long 0xff6c0241,0x7fff0c41,0x7fff661a,0x4aaeff74 + .long 0x660c222e,0xff700281,0x7fffffff,0x67082d6e + .long 0xff70ff54,0x6012223c,0x7fffffff,0x4a2eff6c + .long 0x6a025281,0x2d41ff54,0xe9c004c3,0x122eff41 + .long 0x307b0206,0x4efb8802,0x006c0000,0x0000ff98 + .long 0x003e0000,0x00100000,0x102eff54,0x0c010007 + .long 0x6f16206e,0x000c61ff,0xffffeb86,0x4a8166ff + .long 0x0000bca8,0x6000ff6a,0x02410007,0x61ff0000 + .long 0xa8046000,0xff5c302e,0xff540c01,0x00076f16 + .long 0x206e000c,0x61ffffff,0xeb6e4a81,0x66ff0000 + .long 0xbc886000,0xff3c0241,0x000761ff,0x0000a79a + .long 0x6000ff2e,0x202eff54,0x0c010007,0x6f16206e + .long 0x000c61ff,0xffffeb56,0x4a8166ff,0x0000bc68 + .long 0x6000ff0e,0x02410007,0x61ff0000,0xa7306000 + .long 0xff004e56,0xff40f32e,0xff6c48ee,0x0303ff9c + .long 0xf22ebc00,0xff60f22e,0xf0c0ffdc,0x2d6eff68 + .long 0xff44206e,0xff4458ae,0xff4461ff,0xffffea8a + .long 0x2d40ff40,0x0800000d,0x6600002a,0x41eeff6c + .long 0x61ffffff,0xf0a4f22e,0xd0c0ffdc,0xf22e9c00 + .long 0xff604cee,0x0303ff9c,0xf36eff6c,0x4e5e60ff + .long 0xffffe964,0xe9c004c3,0x122eff41,0x307b0206 + .long 0x4efb8802,0x007400a6,0x015a0000,0x00420104 + .long 0x00100000,0x102eff70,0x08c00006,0x0c010007 + .long 0x6f16206e,0x000c61ff,0xffffea76,0x4a8166ff + .long 0x0000bb98,0x6000ffa0,0x02410007,0x61ff0000 + .long 0xa6f46000,0xff92302e,0xff7008c0,0x000e0c01 + .long 0x00076f16,0x206e000c,0x61ffffff,0xea5a4a81 + .long 0x66ff0000,0xbb746000,0xff6e0241,0x000761ff + .long 0x0000a686,0x6000ff60,0x202eff70,0x08c0001e + .long 0x0c010007,0x6f16206e,0x000c61ff,0xffffea3e + .long 0x4a8166ff,0x0000bb50,0x6000ff3c,0x02410007 + .long 0x61ff0000,0xa6186000,0xff2e0c01,0x00076f2e + .long 0x202eff6c,0x02808000,0x00000080,0x7fc00000 + .long 0x222eff70,0xe0898081,0x206e000c,0x61ffffff + .long 0xe9fc4a81,0x66ff0000,0xbb0e6000,0xfefa202e + .long 0xff6c0280,0x80000000,0x00807fc0,0x00002f01 + .long 0x222eff70,0xe0898081,0x221f0241,0x000761ff + .long 0x0000a5ba,0x6000fed0,0x202eff6c,0x02808000 + .long 0x00000080,0x7ff80000,0x222eff70,0x2d40ff84 + .long 0x700be0a9,0x83aeff84,0x222eff70,0x02810000 + .long 0x07ffe0b9,0x2d41ff88,0x222eff74,0xe0a983ae + .long 0xff8841ee,0xff84226e,0x000c7008,0x61ffffff + .long 0xe8cc4a81,0x66ff0000,0xba9c6000,0xfe7a422e + .long 0xff4a3d6e,0xff6cff84,0x426eff86,0x202eff70 + .long 0x08c0001e,0x2d40ff88,0x2d6eff74,0xff8c082e + .long 0x00050004,0x66384e68,0x2d48ffd8,0x2d56ffd4 + .long 0x61ff0000,0x98922248,0x2d48000c,0x206effd8 + .long 0x4e602cae,0xffd441ee,0xff84700c,0x61ffffff + .long 0xe86c4a81,0x66ff0000,0xba4a6000,0xfe1a2d56 + .long 0xffd461ff,0x00009860,0x22482d48,0x000c2cae + .long 0xffd40c2e,0x0008ff4a,0x66ccf22e,0xd0c0ffdc + .long 0xf22e9c00,0xff604cee,0x0303ff9c,0xf36eff6c + .long 0x2c6effd4,0x2f6f00c4,0x00b82f6f,0x00c800bc + .long 0x2f6f00cc,0x00c02f6f,0x004400c4,0x2f6f0048 + .long 0x00c82f6f,0x004c00cc,0xdffc0000,0x00b860ff + .long 0xffffe734,0x4e56ff40,0xf32eff6c,0x48ee0303 + .long 0xff9cf22e,0xbc00ff60,0xf22ef0c0,0xffdc2d6e + .long 0xff68ff44,0x206eff44,0x58aeff44,0x61ffffff + .long 0xe7f82d40,0xff400800,0x000d6600,0x0106e9c0 + .long 0x04c36622,0x0c6e401e,0xff6c661a,0xf23c9000 + .long 0x00000000,0xf22e4000,0xff70f22e,0x6800ff6c + .long 0x3d7ce001,0xff6e41ee,0xff6c61ff,0xffffedea + .long 0x02ae00ff,0x01ffff64,0xf23c9000,0x00000000 + .long 0xf23c8800,0x00000000,0xe9ee1006,0xff420c01 + .long 0x00176700,0x009641ee,0xff6c61ff,0x0000aa84 + .long 0x1d40ff4e,0x082e0005,0xff43672e,0x082e0004 + .long 0xff436626,0xe9ee0183,0xff4261ff,0x0000a5c2 + .long 0x41eeff78,0x61ff0000,0xaa5a0c00,0x00066606 + .long 0x61ff0000,0xa9be1d40,0xff4f4280,0x102eff63 + .long 0x122eff43,0x0241007f,0x41eeff6c,0x43eeff78 + .long 0x223b1530,0x000059ca,0x4ebb1930,0x000059c2 + .long 0xe9ee0183,0xff4261ff,0x0000a606,0xf22ed0c0 + .long 0xffdcf22e,0x9c00ff60,0x4cee0303,0xff9cf36e + .long 0xff6c4e5e,0x60ffffff,0xe5cc4280,0x102eff63 + .long 0x122eff43,0x02810000,0x007f61ff,0x000043ce + .long 0x60be1d7c,0x0000ff4e,0x4280102e,0xff6302ae + .long 0xffff00ff,0xff6441ee,0xff6c61ff,0x00009be4 + .long 0x60aa4e56,0xff40f32e,0xff6c48ee,0x0303ff9c + .long 0xf22ebc00,0xff60f22e,0xf0c0ffdc,0x2d6eff68 + .long 0xff44206e,0xff4458ae,0xff4461ff,0xffffe69a + .long 0x2d40ff40,0x41eeff6c,0x61ffffff,0xecbcf22e + .long 0xd0c0ffdc,0xf22e9c00,0xff604cee,0x0303ff9c + .long 0xf36eff6c,0x4e5e60ff,0xffffe592,0x0c6f202c + .long 0x000667ff,0x000000aa,0x0c6f402c,0x000667ff + .long 0xffffe5a6,0x4e56ff40,0x48ee0303,0xff9c2d6e + .long 0x0006ff44,0x206eff44,0x58aeff44,0x61ffffff + .long 0xe638e9c0,0x100a0c41,0x03c86664,0xe9c01406 + .long 0x0c010017,0x665a4e7a,0x08080800,0x0001672a + .long 0x4cee0303,0xff9c4e5e,0x518f3eaf,0x00082f6f + .long 0x000a0002,0x3f7c402c,0x00062f6f,0x0002000c + .long 0x58af0002,0x60ffffff,0xe5404cee,0x0303ff9c + .long 0x4e5ef22f,0x84000002,0x58af0002,0x2f172f6f + .long 0x00080004,0x1f7c0020,0x000660ff,0x00000012 + .long 0x4cee0303,0xff9c4e5e,0x60ffffff,0xe4f64e56 + .long 0xff4048ee,0x0303ff9c,0xf22ebc00,0xff60f22e + .long 0xf0c0ffdc,0x082e0005,0x00046608,0x4e682d48 + .long 0xffd8600c,0x41ee0010,0x2d48ffd8,0x2d48ffd4 + .long 0x2d6eff68,0xff44206e,0xff4458ae,0xff4461ff + .long 0xffffe576,0x2d40ff40,0xf23c9000,0x00000000 + .long 0xf23c8800,0x00000000,0x422eff4a,0x08000016 + .long 0x66000182,0x422eff53,0x02ae00ff,0x00ffff64 + .long 0xe9c01406,0x0c010017,0x670000be,0x61ff0000 + .long 0x95fc4280,0x102eff63,0x122eff43,0x0241003f + .long 0xe749822e,0xff4e43ee,0xff7841ee,0xff6c323b + .long 0x132002b2,0x4ebb1120,0x02ac102e,0xff626600 + .long 0x00a2e9ee,0x0183ff42,0x61ff0000,0xa3e4f22e + .long 0xd0c0ffdc,0xf22e9c00,0xff604cee,0x0303ff9c + .long 0x0c2e0004,0xff4a672a,0x0c2e0008,0xff4a6722 + .long 0x4e5e0817,0x000767ff,0xffffe358,0xf327f22f + .long 0xa4000014,0xf35f3f7c,0x20240006,0x60ffffff + .long 0xe434082e,0x00050004,0x660c2f08,0x206effd8 + .long 0x4e60205f,0x60ca2f00,0x202effd8,0x90aeffd4 + .long 0x2dae0008,0x08082dae,0x00040804,0x3d400004 + .long 0x201f4e5e,0xded760aa,0x4280102e,0xff63122e + .long 0xff430281,0x0000007f,0x61ff0000,0x41506000 + .long 0xff5ac02e,0xff66edc0,0x06086616,0x082e0004 + .long 0xff666700,0xff4e082e,0x0001ff62,0x6700ff44 + .long 0x603e0480,0x00000018,0x0c000006,0x6610082e + .long 0x0004ff66,0x662a082e,0x0003ff66,0x66302f00 + .long 0x61ffffff,0xf1ee201f,0x3d7b0206,0xff6e602a + .long 0xe002e006,0xe004e005,0xe003e002,0xe001e001 + .long 0x61ffffff,0xf1ce3d7c,0xe005ff6e,0x600c61ff + .long 0xfffff1c0,0x3d7ce003,0xff6ef22e,0xd0c0ffdc + .long 0xf22e9c00,0xff604cee,0x0303ff9c,0xf36eff6c + .long 0x6000feee,0xe9c01283,0x0c010001,0x67000056 + .long 0x0c010007,0x66000078,0xe9c01343,0x0c010002 + .long 0x6d00006c,0x61ff0000,0x82780c2e,0x0002ff4a + .long 0x670000d2,0x0c2e0001,0xff4a6600,0x01002d6e + .long 0xff68000c,0x3d7c201c,0x000af22e,0xd0c0ffdc + .long 0xf22e9c00,0xff604cee,0x0303ff9c,0x4e5e60ff + .long 0xffffe2dc,0x206eff44,0x54aeff44,0x61ffffff + .long 0xe3524a81,0x6600047c,0x48c061ff,0x00007e60 + .long 0x0c2e0002,0xff4a6700,0x007c6000,0x00b061ff + .long 0x00008562,0x0c2e0002,0xff4a6700,0x0068082e + .long 0x00050004,0x660a206e,0xffd84e60,0x6000008e + .long 0x0c2e0008,0xff4a6600,0x0084f22e,0xd0c0ffdc + .long 0xf22e9c00,0xff604cee,0x0303ff9c,0x4e5e0817 + .long 0x00076612,0x558f2eaf,0x00022f6f,0x00060004 + .long 0x60ffffff,0xe17e558f,0x2eaf0002,0x3f6f0006 + .long 0x00043f7c,0x20240006,0xf22fa400,0x000860ff + .long 0xffffe252,0x3d7c00c0,0x000e2d6e,0xff68000a + .long 0x3d6e0004,0x00083d7c,0xe000ff6e,0xf22ed0c0 + .long 0xffdcf22e,0x9c00ff60,0x4cee0303,0xff9cf36e + .long 0xff6c4e5e,0x588f60ff,0xffffe180,0xf22ed0c0 + .long 0xffdcf22e,0x9c00ff60,0x4cee0303,0xff9c4e5e + .long 0x08170007,0x660660ff,0xffffe108,0xf22fa400 + .long 0x00081f7c,0x00240007,0x60ffffff,0xe1e84afc + .long 0x01c00000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x000028a4,0x4b1e4b4c,0x4f4c2982,0x4f3c0000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x000035c6,0x4b1e4b82,0x4f4c371a,0x4f3c0000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x000024b0,0x4b1e4b8c,0x4f4c2766,0x4f3c0000 + .long 0x00002988,0x4b1e4b94,0x4f4c2af0,0x4f3c0000 + .long 0x00001ab8,0x4b1e4bd0,0x4f4c1cf6,0x4f3c0000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00001cfc,0x4b1e4744,0x4f4c1daa,0x4f3c0000 + .long 0x00003720,0x4b1e4744,0x4f4c37a2,0x4f3c0000 + .long 0x00000468,0x4b1e4744,0x4f4c064c,0x4f3c0000 + .long 0x00000f2a,0x4b1e4744,0x4f4c108e,0x4f3c0000 + .long 0x000022e0,0x4b9a4b7a,0x4f4c248c,0x4f3c0000 + .long 0x00003d02,0x4b9a4b7a,0x4f4c3ddc,0x4f3c0000 + .long 0x00003dfa,0x4b9a4b7a,0x4f4c3f2a,0x4f3c0000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00003386,0x47324b82,0x4f4c3538,0x4f3c0000 + .long 0x000037c8,0x47324b82,0x4f4c37f8,0x4f3c0000 + .long 0x00003818,0x47324b82,0x4f4c3872,0x4f3c0000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x000027e6,0x4b9a4b52,0x4f4c288a,0x4f3c0000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00001db0,0x4bd64744,0x4f4c1e40,0x4f3c0000 + .long 0x00000472,0x4b9a4744,0x4f4c0652,0x4f3c0000 + .long 0x0000276c,0x4b1e4744,0x4f4c2788,0x4f3c0000 + .long 0x000027a0,0x4b1e4744,0x4f4c27ce,0x4f3c0000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00004ca4,0x4cda4d12,0x4ee24ca4,0x4ef40000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00004dac,0x4de24e1a,0x4ee24dac,0x4ef40000 + .long 0x00004e4e,0x4e864ebe,0x4ee24e4e,0x4ef40000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000660,0x4bf24c20,0x4c3008f6,0x4c400000 + .long 0x00000660,0x4bf24c20,0x4c3008f6,0x4c400000 + .long 0x00000660,0x4bf24c20,0x4c3008f6,0x4c400000 + .long 0x00000660,0x4bf24c20,0x4c3008f6,0x4c400000 + .long 0x00000660,0x4bf24c20,0x4c3008f6,0x4c400000 + .long 0x00000660,0x4bf24c20,0x4c3008f6,0x4c400000 + .long 0x00000660,0x4bf24c20,0x4c3008f6,0x4c400000 + .long 0x00000660,0x4bf24c20,0x4c3008f6,0x4c400000 + .long 0x00004cee,0x0303ff9c,0xf22e9c00,0xff60f22e + .long 0xd0c0ffdc,0x2d6eff68,0x00064e5e,0x2f173f6f + .long 0x00080004,0x3f7c4008,0x00062f6f,0x00020008 + .long 0x2f7c0942,0x8001000c,0x08170005,0x670608ef + .long 0x0002000d,0x60ffffff,0xde32bd6a,0xaa77ccc9 + .long 0x94f53de6,0x12097aae,0x8da1be5a,0xe6452a11 + .long 0x8ae43ec7,0x1de3a534,0x1531bf2a,0x01a01a01 + .long 0x8b590000,0x00000000,0x00003ff8,0x00008888 + .long 0x88888888,0x59af0000,0x0000bffc,0x0000aaaa + .long 0xaaaaaaaa,0xaa990000,0x00003d2a,0xc4d0d601 + .long 0x1ee3bda9,0x396f9f45,0xac193e21,0xeed90612 + .long 0xc972be92,0x7e4fb79d,0x9fcf3efa,0x01a01a01 + .long 0xd4230000,0x00000000,0x0000bff5,0x0000b60b + .long 0x60b60b61,0xd4380000,0x00003ffa,0x0000aaaa + .long 0xaaaaaaaa,0xab5ebf00,0x00002d7c,0x00000000 + .long 0xff5c6008,0x2d7c0000,0x0001ff5c,0xf2104800 + .long 0xf22e6800,0xff842210,0x32280004,0x02817fff + .long 0xffff0c81,0x3fd78000,0x6c046000,0x01780c81 + .long 0x4004bc7e,0x6d046000,0x0468f200,0x0080f23a + .long 0x54a3de7e,0x43fb0170,0x00000866,0xf22e6080 + .long 0xff58222e,0xff58e981,0xd3c1f219,0x4828f211 + .long 0x4428222e,0xff58d2ae,0xff5ce299,0x0c810000 + .long 0x00006d00,0x0088f227,0xe00cf22e,0x6800ff84 + .long 0xf2000023,0xf23a5580,0xfed2f23a,0x5500fed4 + .long 0xf2000080,0xf20004a3,0xe2990281,0x80000000 + .long 0xb3aeff84,0xf20005a3,0xf2000523,0xf23a55a2 + .long 0xfebaf23a,0x5522febc,0xf20005a3,0xf2000523 + .long 0xf23a55a2,0xfeb6f23a,0x4922fec0,0xf2000ca3 + .long 0xf2000123,0xf23a48a2,0xfec2f22e,0x4823ff84 + .long 0xf20008a2,0xf2000423,0xf21fd030,0xf2009000 + .long 0xf22e4822,0xff8460ff,0x00004364,0xf227e00c + .long 0xf2000023,0xf23a5500,0xfea2f23a,0x5580fea4 + .long 0xf2000080,0xf20004a3,0xf22e6800,0xff84e299 + .long 0x02818000,0x0000f200,0x0523b3ae,0xff840281 + .long 0x80000000,0xf20005a3,0x00813f80,0x00002d41 + .long 0xff54f23a,0x5522fe74,0xf23a55a2,0xfe76f200 + .long 0x0523f200,0x05a3f23a,0x5522fe70,0xf23a49a2 + .long 0xfe7af200,0x0523f200,0x0ca3f23a,0x4922fe7c + .long 0xf23a44a2,0xfe82f200,0x0823f200,0x0422f22e + .long 0x4823ff84,0xf21fd030,0xf2009000,0xf22e4422 + .long 0xff5460ff,0x000042c8,0x0c813fff,0x80006eff + .long 0x00000300,0x222eff5c,0x0c810000,0x00006e14 + .long 0xf2009000,0x123c0003,0xf22e4800,0xff8460ff + .long 0x0000428e,0xf23c4400,0x3f800000,0xf2009000 + .long 0xf23c4422,0x80800000,0x60ff0000,0x428a60ff + .long 0x00004110,0xf23c4400,0x3f800000,0x60ff0000 + .long 0x42762d7c,0x00000004,0xff5cf210,0x4800f22e + .long 0x6800ff84,0x22103228,0x00040281,0x7fffffff + .long 0x0c813fd7,0x80006c04,0x60000240,0x0c814004 + .long 0xbc7e6d04,0x6000027a,0xf2000080,0xf23a54a3 + .long 0xdc9043fb,0x01700000,0x0678f22e,0x6080ff58 + .long 0x222eff58,0xe981d3c1,0xf2194828,0xf2114428 + .long 0x222eff58,0xe2990c81,0x00000000,0x6c000106 + .long 0xf227e004,0xf22e6800,0xff84f200,0x0023f23a + .long 0x5480fce8,0xf23a5500,0xfd32f200,0x00a3f200 + .long 0x01232f02,0x2401e29a,0x02828000,0x0000b382 + .long 0x02828000,0x0000f23a,0x54a2fcc8,0xf23a5522 + .long 0xfd12f200,0x00a3b5ae,0xff84241f,0xf2000123 + .long 0xe2990281,0x80000000,0x2d7c3f80,0x0000ff54 + .long 0xb3aeff54,0xf23a54a2,0xfca2f23a,0x5522fcec + .long 0xf20000a3,0xf2000123,0xf22e6800,0xff90f23a + .long 0x54a2fc90,0xb3aeff90,0xf23a5522,0xfcd6f200 + .long 0x00a3f200,0x0123f23a,0x54a2fc80,0xf23a5522 + .long 0xfccaf200,0x00a3f200,0x0123f23a,0x48a2fc7c + .long 0xf23a4922,0xfcc6f200,0x00a3f200,0x0123f23a + .long 0x48a2fc78,0xf23a4922,0xfcc2f200,0x00a3f200 + .long 0x0823f22e,0x48a3ff84,0xf23a4422,0xfcbaf22e + .long 0x4823ff90,0xf21fd020,0xf2009000,0xf22e48a2 + .long 0xff8461ff,0x0000448e,0xf22e4422,0xff5460ff + .long 0x000040fc,0xf227e004,0xf22e6800,0xff84f200 + .long 0x0023f23a,0x5480fc34,0xf23a5500,0xfbdef200 + .long 0x00a3f22e,0x6800ff90,0xf2000123,0xe2990281 + .long 0x80000000,0xf23a54a2,0xfc1af23a,0x5522fbc4 + .long 0xb3aeff84,0xb3aeff90,0xf20000a3,0x00813f80 + .long 0x00002d41,0xff54f200,0x0123f23a,0x54a2fbfc + .long 0xf23a5522,0xfba6f200,0x00a3f200,0x0123f23a + .long 0x54a2fbf0,0xf23a5522,0xfb9af200,0x00a3f200 + .long 0x0123f23a,0x54a2fbe4,0xf23a5522,0xfb8ef200 + .long 0x00a3f200,0x0123f23a,0x48a2fbe0,0xf23a4922 + .long 0xfb8af200,0x00a3f200,0x0123f23a,0x48a2fbdc + .long 0xf23a4922,0xfb86f200,0x00a3f200,0x0823f23a + .long 0x44a2fbd4,0xf22e4823,0xff84f22e,0x48a3ff90 + .long 0xf21fd020,0xf2009000,0xf22e44a2,0xff5461ff + .long 0x000043a2,0xf22e4822,0xff8460ff,0x00004010 + .long 0x0c813fff,0x80006e00,0x0048f23c,0x44803f80 + .long 0x0000f200,0x9000f23c,0x44a80080,0x000061ff + .long 0x00004372,0xf200b000,0x123c0003,0xf22e4800 + .long 0xff8460ff,0x00003fca,0x2f00f23c,0x44803f80 + .long 0x000061ff,0x0000434e,0x201f60ff,0x00003e54 + .long 0xf227e03c,0x2f02f23c,0x44800000,0x00000c81 + .long 0x7ffeffff,0x66523d7c,0x7ffeff84,0x2d7cc90f + .long 0xdaa2ff88,0x42aeff8c,0x3d7c7fdc,0xff902d7c + .long 0x85a308d3,0xff9442ae,0xff98f200,0x003af294 + .long 0x000e002e,0x0080ff84,0x002e0080,0xff90f22e + .long 0x4822ff84,0xf2000080,0xf22e4822,0xff90f200 + .long 0x00a8f22e,0x48a2ff90,0xf22e6800,0xff84322e + .long 0xff842241,0x02810000,0x7fff0481,0x00003fff + .long 0x0c810000,0x001c6f0e,0x04810000,0x001b1d7c + .long 0x0000ff58,0x60084281,0x1d7c0001,0xff58243c + .long 0x00003ffe,0x94812d7c,0xa2f9836e,0xff882d7c + .long 0x4e44152a,0xff8c3d42,0xff84f200,0x0100f22e + .long 0x4923ff84,0x24094842,0x02828000,0x00000082 + .long 0x5f000000,0x2d42ff54,0xf22e4522,0xff54f22e + .long 0x4528ff54,0x24010682,0x00003fff,0x3d42ff84 + .long 0x2d7cc90f,0xdaa2ff88,0x42aeff8c,0x06810000 + .long 0x3fdd3d41,0xff902d7c,0x85a308d3,0xff9442ae + .long 0xff98122e,0xff58f200,0x0a00f22e,0x4a23ff84 + .long 0xf2000a80,0xf22e4aa3,0xff90f200,0x1180f200 + .long 0x15a2f200,0x0e28f200,0x0c28f200,0x1622f200 + .long 0x0180f200,0x10a8f200,0x04220c01,0x00006e00 + .long 0x000ef200,0x01a8f200,0x0ca26000,0xff0cf22e + .long 0x6100ff58,0x241ff21f,0xd03c222e,0xff5c0c81 + .long 0x00000004,0x6d00fa4c,0x6000fc36,0x3ea0b759 + .long 0xf50f8688,0xbef2baa5,0xa8924f04,0xbf346f59 + .long 0xb39ba65f,0x00000000,0x00000000,0x3ff60000 + .long 0xe073d3fc,0x199c4a00,0x00000000,0x3ff90000 + .long 0xd23cd684,0x15d95fa1,0x00000000,0xbffc0000 + .long 0x8895a6c5,0xfb423bca,0x00000000,0xbffd0000 + .long 0xeef57e0d,0xa84bc8ce,0x00000000,0x3ffc0000 + .long 0xa2f9836e,0x4e44152a,0x00000000,0x40010000 + .long 0xc90fdaa2,0x00000000,0x00000000,0x3fdf0000 + .long 0x85a308d4,0x00000000,0x00000000,0xc0040000 + .long 0xc90fdaa2,0x2168c235,0x21800000,0xc0040000 + .long 0xc2c75bcd,0x105d7c23,0xa0d00000,0xc0040000 + .long 0xbc7edcf7,0xff523611,0xa1e80000,0xc0040000 + .long 0xb6365e22,0xee46f000,0x21480000,0xc0040000 + .long 0xafeddf4d,0xdd3ba9ee,0xa1200000,0xc0040000 + .long 0xa9a56078,0xcc3063dd,0x21fc0000,0xc0040000 + .long 0xa35ce1a3,0xbb251dcb,0x21100000,0xc0040000 + .long 0x9d1462ce,0xaa19d7b9,0xa1580000,0xc0040000 + .long 0x96cbe3f9,0x990e91a8,0x21e00000,0xc0040000 + .long 0x90836524,0x88034b96,0x20b00000,0xc0040000 + .long 0x8a3ae64f,0x76f80584,0xa1880000,0xc0040000 + .long 0x83f2677a,0x65ecbf73,0x21c40000,0xc0030000 + .long 0xfb53d14a,0xa9c2f2c2,0x20000000,0xc0030000 + .long 0xeec2d3a0,0x87ac669f,0x21380000,0xc0030000 + .long 0xe231d5f6,0x6595da7b,0xa1300000,0xc0030000 + .long 0xd5a0d84c,0x437f4e58,0x9fc00000,0xc0030000 + .long 0xc90fdaa2,0x2168c235,0x21000000,0xc0030000 + .long 0xbc7edcf7,0xff523611,0xa1680000,0xc0030000 + .long 0xafeddf4d,0xdd3ba9ee,0xa0a00000,0xc0030000 + .long 0xa35ce1a3,0xbb251dcb,0x20900000,0xc0030000 + .long 0x96cbe3f9,0x990e91a8,0x21600000,0xc0030000 + .long 0x8a3ae64f,0x76f80584,0xa1080000,0xc0020000 + .long 0xfb53d14a,0xa9c2f2c2,0x1f800000,0xc0020000 + .long 0xe231d5f6,0x6595da7b,0xa0b00000,0xc0020000 + .long 0xc90fdaa2,0x2168c235,0x20800000,0xc0020000 + .long 0xafeddf4d,0xdd3ba9ee,0xa0200000,0xc0020000 + .long 0x96cbe3f9,0x990e91a8,0x20e00000,0xc0010000 + .long 0xfb53d14a,0xa9c2f2c2,0x1f000000,0xc0010000 + .long 0xc90fdaa2,0x2168c235,0x20000000,0xc0010000 + .long 0x96cbe3f9,0x990e91a8,0x20600000,0xc0000000 + .long 0xc90fdaa2,0x2168c235,0x1f800000,0xbfff0000 + .long 0xc90fdaa2,0x2168c235,0x1f000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x3fff0000 + .long 0xc90fdaa2,0x2168c235,0x9f000000,0x40000000 + .long 0xc90fdaa2,0x2168c235,0x9f800000,0x40010000 + .long 0x96cbe3f9,0x990e91a8,0xa0600000,0x40010000 + .long 0xc90fdaa2,0x2168c235,0xa0000000,0x40010000 + .long 0xfb53d14a,0xa9c2f2c2,0x9f000000,0x40020000 + .long 0x96cbe3f9,0x990e91a8,0xa0e00000,0x40020000 + .long 0xafeddf4d,0xdd3ba9ee,0x20200000,0x40020000 + .long 0xc90fdaa2,0x2168c235,0xa0800000,0x40020000 + .long 0xe231d5f6,0x6595da7b,0x20b00000,0x40020000 + .long 0xfb53d14a,0xa9c2f2c2,0x9f800000,0x40030000 + .long 0x8a3ae64f,0x76f80584,0x21080000,0x40030000 + .long 0x96cbe3f9,0x990e91a8,0xa1600000,0x40030000 + .long 0xa35ce1a3,0xbb251dcb,0xa0900000,0x40030000 + .long 0xafeddf4d,0xdd3ba9ee,0x20a00000,0x40030000 + .long 0xbc7edcf7,0xff523611,0x21680000,0x40030000 + .long 0xc90fdaa2,0x2168c235,0xa1000000,0x40030000 + .long 0xd5a0d84c,0x437f4e58,0x1fc00000,0x40030000 + .long 0xe231d5f6,0x6595da7b,0x21300000,0x40030000 + .long 0xeec2d3a0,0x87ac669f,0xa1380000,0x40030000 + .long 0xfb53d14a,0xa9c2f2c2,0xa0000000,0x40040000 + .long 0x83f2677a,0x65ecbf73,0xa1c40000,0x40040000 + .long 0x8a3ae64f,0x76f80584,0x21880000,0x40040000 + .long 0x90836524,0x88034b96,0xa0b00000,0x40040000 + .long 0x96cbe3f9,0x990e91a8,0xa1e00000,0x40040000 + .long 0x9d1462ce,0xaa19d7b9,0x21580000,0x40040000 + .long 0xa35ce1a3,0xbb251dcb,0xa1100000,0x40040000 + .long 0xa9a56078,0xcc3063dd,0xa1fc0000,0x40040000 + .long 0xafeddf4d,0xdd3ba9ee,0x21200000,0x40040000 + .long 0xb6365e22,0xee46f000,0xa1480000,0x40040000 + .long 0xbc7edcf7,0xff523611,0x21e80000,0x40040000 + .long 0xc2c75bcd,0x105d7c23,0x20d00000,0x40040000 + .long 0xc90fdaa2,0x2168c235,0xa1800000,0xf2104800 + .long 0x22103228,0x00040281,0x7fffffff,0x0c813fd7 + .long 0x80006c04,0x60000134,0x0c814004,0xbc7e6d04 + .long 0x60000144,0xf2000080,0xf23a54a3,0xd3d443fa + .long 0xfdbcf201,0x6080e981,0xd3c1f219,0x4828f211 + .long 0x4428ea99,0x02818000,0x0000f227,0xe00c0c81 + .long 0x00000000,0x6d000072,0xf2000080,0xf20004a3 + .long 0xf23a5580,0xfaf8f23a,0x5500fafa,0xf20005a3 + .long 0xf2000523,0xf23a55a2,0xfaf4f23a,0x4922fafe + .long 0xf20005a3,0xf2000523,0xf23a49a2,0xfb00f23a + .long 0x4922fb0a,0xf20005a3,0xf2000523,0xf23a49a2 + .long 0xfb0cf200,0x0123f200,0x0ca3f200,0x0822f23c + .long 0x44a23f80,0x0000f21f,0xd030f200,0x9000f200 + .long 0x042060ff,0x000038d8,0xf2000080,0xf2000023 + .long 0xf23a5580,0xfa88f23a,0x5500fa8a,0xf20001a3 + .long 0xf2000123,0xf23a55a2,0xfa84f23a,0x4922fa8e + .long 0xf20001a3,0xf2000123,0xf23a49a2,0xfa90f23a + .long 0x4922fa9a,0xf20001a3,0xf2000123,0xf23a49a2 + .long 0xfa9cf200,0x0523f200,0x0c23f200,0x08a2f23c + .long 0x44223f80,0x0000f21f,0xd030f227,0x68800a97 + .long 0x80000000,0xf2009000,0xf21f4820,0x60ff0000 + .long 0x385e0c81,0x3fff8000,0x6e1cf227,0x6800f200 + .long 0x9000123c,0x0003f21f,0x480060ff,0x00003832 + .long 0x60ff0000,0x36cef227,0xe03c2f02,0xf23c4480 + .long 0x00000000,0x0c817ffe,0xffff6652,0x3d7c7ffe + .long 0xff842d7c,0xc90fdaa2,0xff8842ae,0xff8c3d7c + .long 0x7fdcff90,0x2d7c85a3,0x08d3ff94,0x42aeff98 + .long 0xf200003a,0xf294000e,0x002e0080,0xff84002e + .long 0x0080ff90,0xf22e4822,0xff84f200,0x0080f22e + .long 0x4822ff90,0xf20000a8,0xf22e48a2,0xff90f22e + .long 0x6800ff84,0x322eff84,0x22410281,0x00007fff + .long 0x04810000,0x3fff0c81,0x0000001c,0x6f0e0481 + .long 0x0000001b,0x1d7c0000,0xff586008,0x42811d7c + .long 0x0001ff58,0x243c0000,0x3ffe9481,0x2d7ca2f9 + .long 0x836eff88,0x2d7c4e44,0x152aff8c,0x3d42ff84 + .long 0xf2000100,0xf22e4923,0xff842409,0x48420282 + .long 0x80000000,0x00825f00,0x00002d42,0xff54f22e + .long 0x4522ff54,0xf22e4528,0xff542401,0x06820000 + .long 0x3fff3d42,0xff842d7c,0xc90fdaa2,0xff8842ae + .long 0xff8c0681,0x00003fdd,0x3d41ff90,0x2d7c85a3 + .long 0x08d3ff94,0x42aeff98,0x122eff58,0xf2000a00 + .long 0xf22e4a23,0xff84f200,0x0a80f22e,0x4aa3ff90 + .long 0xf2001180,0xf20015a2,0xf2000e28,0xf2000c28 + .long 0xf2001622,0xf2000180,0xf20010a8,0xf2000422 + .long 0x0c010000,0x6e00000e,0xf20001a8,0xf2000ca2 + .long 0x6000ff0c,0xf22e6100,0xff54241f,0xf21fd03c + .long 0x222eff54,0xe2996000,0xfd72bff6,0x687e3149 + .long 0x87d84002,0xac6934a2,0x6db3bfc2,0x476f4e1d + .long 0xa28e3fb3,0x44447f87,0x6989bfb7,0x44ee7faf + .long 0x45db3fbc,0x71c64694,0x0220bfc2,0x49249218 + .long 0x72f93fc9,0x99999999,0x8fa9bfd5,0x55555555 + .long 0x5555bfb7,0x0bf39853,0x9e6a3fbc,0x7187962d + .long 0x1d7dbfc2,0x49248271,0x07b83fc9,0x99999996 + .long 0x263ebfd5,0x55555555,0x55363fff,0x0000c90f + .long 0xdaa22168,0xc2350000,0x0000bfff,0x0000c90f + .long 0xdaa22168,0xc2350000,0x00000001,0x00008000 + .long 0x00000000,0x00000000,0x00008001,0x00008000 + .long 0x00000000,0x00000000,0x00003ffb,0x000083d1 + .long 0x52c5060b,0x7a510000,0x00003ffb,0x00008bc8 + .long 0x54456549,0x8b8b0000,0x00003ffb,0x000093be + .long 0x40601762,0x6b0d0000,0x00003ffb,0x00009bb3 + .long 0x078d35ae,0xc2020000,0x00003ffb,0x0000a3a6 + .long 0x9a525ddc,0xe7de0000,0x00003ffb,0x0000ab98 + .long 0xe9436276,0x56190000,0x00003ffb,0x0000b389 + .long 0xe502f9c5,0x98620000,0x00003ffb,0x0000bb79 + .long 0x7e436b09,0xe6fb0000,0x00003ffb,0x0000c367 + .long 0xa5c739e5,0xf4460000,0x00003ffb,0x0000cb54 + .long 0x4c61cff7,0xd5c60000,0x00003ffb,0x0000d33f + .long 0x62f82488,0x533e0000,0x00003ffb,0x0000db28 + .long 0xda816240,0x4c770000,0x00003ffb,0x0000e310 + .long 0xa4078ad3,0x4f180000,0x00003ffb,0x0000eaf6 + .long 0xb0a8188e,0xe1eb0000,0x00003ffb,0x0000f2da + .long 0xf1949dbe,0x79d50000,0x00003ffb,0x0000fabd + .long 0x581361d4,0x7e3e0000,0x00003ffc,0x00008346 + .long 0xac210959,0xecc40000,0x00003ffc,0x00008b23 + .long 0x2a083042,0x82d80000,0x00003ffc,0x000092fb + .long 0x70b8d29a,0xe2f90000,0x00003ffc,0x00009acf + .long 0x476f5ccd,0x1cb40000,0x00003ffc,0x0000a29e + .long 0x76304954,0xf23f0000,0x00003ffc,0x0000aa68 + .long 0xc5d08ab8,0x52300000,0x00003ffc,0x0000b22d + .long 0xfffd9d53,0x9f830000,0x00003ffc,0x0000b9ed + .long 0xef453e90,0x0ea50000,0x00003ffc,0x0000c1a8 + .long 0x5f1cc75e,0x3ea50000,0x00003ffc,0x0000c95d + .long 0x1be82813,0x8de60000,0x00003ffc,0x0000d10b + .long 0xf300840d,0x2de40000,0x00003ffc,0x0000d8b4 + .long 0xb2ba6bc0,0x5e7a0000,0x00003ffc,0x0000e057 + .long 0x2a6bb423,0x35f60000,0x00003ffc,0x0000e7f3 + .long 0x2a70ea9c,0xaa8f0000,0x00003ffc,0x0000ef88 + .long 0x843264ec,0xefaa0000,0x00003ffc,0x0000f717 + .long 0x0a28ecc0,0x66660000,0x00003ffd,0x0000812f + .long 0xd288332d,0xad320000,0x00003ffd,0x000088a8 + .long 0xd1b1218e,0x4d640000,0x00003ffd,0x00009012 + .long 0xab3f23e4,0xaee80000,0x00003ffd,0x0000976c + .long 0xc3d411e7,0xf1b90000,0x00003ffd,0x00009eb6 + .long 0x89493889,0xa2270000,0x00003ffd,0x0000a5ef + .long 0x72c34487,0x361b0000,0x00003ffd,0x0000ad17 + .long 0x00baf07a,0x72270000,0x00003ffd,0x0000b42c + .long 0xbcfafd37,0xefb70000,0x00003ffd,0x0000bb30 + .long 0x3a940ba8,0x0f890000,0x00003ffd,0x0000c221 + .long 0x15c6fcae,0xbbaf0000,0x00003ffd,0x0000c8fe + .long 0xf3e68633,0x12210000,0x00003ffd,0x0000cfc9 + .long 0x8330b400,0x0c700000,0x00003ffd,0x0000d680 + .long 0x7aa1102c,0x5bf90000,0x00003ffd,0x0000dd23 + .long 0x99bc3125,0x2aa30000,0x00003ffd,0x0000e3b2 + .long 0xa8556b8f,0xc5170000,0x00003ffd,0x0000ea2d + .long 0x764f6431,0x59890000,0x00003ffd,0x0000f3bf + .long 0x5bf8bad1,0xa21d0000,0x00003ffe,0x0000801c + .long 0xe39e0d20,0x5c9a0000,0x00003ffe,0x00008630 + .long 0xa2dada1e,0xd0660000,0x00003ffe,0x00008c1a + .long 0xd445f3e0,0x9b8c0000,0x00003ffe,0x000091db + .long 0x8f1664f3,0x50e20000,0x00003ffe,0x00009773 + .long 0x1420365e,0x538c0000,0x00003ffe,0x00009ce1 + .long 0xc8e6a0b8,0xcdba0000,0x00003ffe,0x0000a228 + .long 0x32dbcada,0xae090000,0x00003ffe,0x0000a746 + .long 0xf2ddb760,0x22940000,0x00003ffe,0x0000ac3e + .long 0xc0fb997d,0xd6a20000,0x00003ffe,0x0000b110 + .long 0x688aebdc,0x6f6a0000,0x00003ffe,0x0000b5bc + .long 0xc49059ec,0xc4b00000,0x00003ffe,0x0000ba44 + .long 0xbc7dd470,0x782f0000,0x00003ffe,0x0000bea9 + .long 0x4144fd04,0x9aac0000,0x00003ffe,0x0000c2eb + .long 0x4abb6616,0x28b60000,0x00003ffe,0x0000c70b + .long 0xd54ce602,0xee140000,0x00003ffe,0x0000cd00 + .long 0x0549adec,0x71590000,0x00003ffe,0x0000d484 + .long 0x57d2d8ea,0x4ea30000,0x00003ffe,0x0000db94 + .long 0x8da712de,0xce3b0000,0x00003ffe,0x0000e238 + .long 0x55f969e8,0x096a0000,0x00003ffe,0x0000e877 + .long 0x1129c435,0x32590000,0x00003ffe,0x0000ee57 + .long 0xc16e0d37,0x9c0d0000,0x00003ffe,0x0000f3e1 + .long 0x0211a87c,0x37790000,0x00003ffe,0x0000f919 + .long 0x039d758b,0x8d410000,0x00003ffe,0x0000fe05 + .long 0x8b8f6493,0x5fb30000,0x00003fff,0x00008155 + .long 0xfb497b68,0x5d040000,0x00003fff,0x00008388 + .long 0x9e3549d1,0x08e10000,0x00003fff,0x0000859c + .long 0xfa76511d,0x724b0000,0x00003fff,0x00008795 + .long 0x2ecfff81,0x31e70000,0x00003fff,0x00008973 + .long 0x2fd19557,0x641b0000,0x00003fff,0x00008b38 + .long 0xcad10193,0x2a350000,0x00003fff,0x00008ce7 + .long 0xa8d8301e,0xe6b50000,0x00003fff,0x00008f46 + .long 0xa39e2eae,0x52810000,0x00003fff,0x0000922d + .long 0xa7d79188,0x84870000,0x00003fff,0x000094d1 + .long 0x9fcbdedf,0x52410000,0x00003fff,0x0000973a + .long 0xb94419d2,0xa08b0000,0x00003fff,0x0000996f + .long 0xf00e08e1,0x0b960000,0x00003fff,0x00009b77 + .long 0x3f951232,0x1da70000,0x00003fff,0x00009d55 + .long 0xcc320f93,0x56240000,0x00003fff,0x00009f10 + .long 0x0575006c,0xc5710000,0x00003fff,0x0000a0a9 + .long 0xc290d97c,0xc06c0000,0x00003fff,0x0000a226 + .long 0x59ebebc0,0x630a0000,0x00003fff,0x0000a388 + .long 0xb4aff6ef,0x0ec90000,0x00003fff,0x0000a4d3 + .long 0x5f1061d2,0x92c40000,0x00003fff,0x0000a608 + .long 0x95dcfbe3,0x187e0000,0x00003fff,0x0000a72a + .long 0x51dc7367,0xbeac0000,0x00003fff,0x0000a83a + .long 0x51530956,0x168f0000,0x00003fff,0x0000a93a + .long 0x20077539,0x546e0000,0x00003fff,0x0000aa9e + .long 0x7245023b,0x26050000,0x00003fff,0x0000ac4c + .long 0x84ba6fe4,0xd58f0000,0x00003fff,0x0000adce + .long 0x4a4a606b,0x97120000,0x00003fff,0x0000af2a + .long 0x2dcd8d26,0x3c9c0000,0x00003fff,0x0000b065 + .long 0x6f81f222,0x65c70000,0x00003fff,0x0000b184 + .long 0x65150f71,0x496a0000,0x00003fff,0x0000b28a + .long 0xaa156f9a,0xda350000,0x00003fff,0x0000b37b + .long 0x44ff3766,0xb8950000,0x00003fff,0x0000b458 + .long 0xc3dce963,0x04330000,0x00003fff,0x0000b525 + .long 0x529d5622,0x46bd0000,0x00003fff,0x0000b5e2 + .long 0xcca95f9d,0x88cc0000,0x00003fff,0x0000b692 + .long 0xcada7aca,0x1ada0000,0x00003fff,0x0000b736 + .long 0xaea7a692,0x58380000,0x00003fff,0x0000b7cf + .long 0xab287e9f,0x7b360000,0x00003fff,0x0000b85e + .long 0xcc66cb21,0x98350000,0x00003fff,0x0000b8e4 + .long 0xfd5a20a5,0x93da0000,0x00003fff,0x0000b99f + .long 0x41f64aff,0x9bb50000,0x00003fff,0x0000ba7f + .long 0x1e17842b,0xbe7b0000,0x00003fff,0x0000bb47 + .long 0x12857637,0xe17d0000,0x00003fff,0x0000bbfa + .long 0xbe8a4788,0xdf6f0000,0x00003fff,0x0000bc9d + .long 0x0fad2b68,0x9d790000,0x00003fff,0x0000bd30 + .long 0x6a39471e,0xcd860000,0x00003fff,0x0000bdb6 + .long 0xc731856a,0xf18a0000,0x00003fff,0x0000be31 + .long 0xcac502e8,0x0d700000,0x00003fff,0x0000bea2 + .long 0xd55ce331,0x94e20000,0x00003fff,0x0000bf0b + .long 0x10b7c031,0x28f00000,0x00003fff,0x0000bf6b + .long 0x7a18dacb,0x778d0000,0x00003fff,0x0000bfc4 + .long 0xea4663fa,0x18f60000,0x00003fff,0x0000c018 + .long 0x1bde8b89,0xa4540000,0x00003fff,0x0000c065 + .long 0xb066cfbf,0x64390000,0x00003fff,0x0000c0ae + .long 0x345f5634,0x0ae60000,0x00003fff,0x0000c0f2 + .long 0x22919cb9,0xe6a70000,0x0000f210,0x48002210 + .long 0x32280004,0xf22e6800,0xff840281,0x7fffffff + .long 0x0c813ffb,0x80006c04,0x600000d0,0x0c814002 + .long 0xffff6f04,0x6000014c,0x02aef800,0x0000ff88 + .long 0x00ae0400,0x0000ff88,0x2d7c0000,0x0000ff8c + .long 0xf2000080,0xf22e48a3,0xff84f22e,0x4828ff84 + .long 0xf23c44a2,0x3f800000,0xf2000420,0x2f022401 + .long 0x02810000,0x78000282,0x7fff0000,0x04823ffb + .long 0x0000e282,0xd282ee81,0x43faf780,0xd3c12d59 + .long 0xff902d59,0xff942d59,0xff98222e,0xff840281 + .long 0x80000000,0x83aeff90,0x241ff227,0xe004f200 + .long 0x0080f200,0x04a3f23a,0x5500f6a0,0xf2000522 + .long 0xf2000523,0xf20000a3,0xf23a5522,0xf696f23a + .long 0x54a3f698,0xf20008a3,0xf2000422,0xf21fd020 + .long 0xf2009000,0xf22e4822,0xff9060ff,0x00002d30 + .long 0x0c813fff,0x80006e00,0x008a0c81,0x3fd78000 + .long 0x6d00006c,0xf227e00c,0xf2000023,0xf2000080 + .long 0xf20004a3,0xf23a5500,0xf65af23a,0x5580f65c + .long 0xf2000523,0xf20005a3,0xf23a5522,0xf656f23a + .long 0x55a2f658,0xf2000523,0xf2000ca3,0xf23a5522 + .long 0xf652f23a,0x54a2f654,0xf2000123,0xf22e4823 + .long 0xff84f200,0x08a2f200,0x0423f21f,0xd030f200 + .long 0x9000f22e,0x4822ff84,0x60ff0000,0x2cb2f200 + .long 0x9000123c,0x0003f22e,0x4800ff84,0x60ff0000 + .long 0x2c900c81,0x40638000,0x6e00008e,0xf227e00c + .long 0xf23c4480,0xbf800000,0xf20000a0,0xf2000400 + .long 0xf2000023,0xf22e6880,0xff84f200,0x0080f200 + .long 0x04a3f23a,0x5580f5ec,0xf23a5500,0xf5eef200 + .long 0x05a3f200,0x0523f23a,0x55a2f5e8,0xf23a5522 + .long 0xf5eaf200,0x0ca3f200,0x0123f23a,0x54a2f5e4 + .long 0xf22e4823,0xff84f200,0x08a2f200,0x0423f22e + .long 0x4822ff84,0xf21fd030,0xf2009000,0x4a106a0c + .long 0xf23a4822,0xf5d660ff,0x00002c24,0xf23a4822 + .long 0xf5ba60ff,0x00002c10,0x4a106a16,0xf23a4800 + .long 0xf5baf200,0x9000f23a,0x4822f5c0,0x60ff0000 + .long 0x2bfef23a,0x4800f594,0xf2009000,0xf23a4822 + .long 0xf5ba60ff,0x00002be0,0x60ff0000,0x2a66f210 + .long 0x48002210,0x32280004,0x02817fff,0xffff0c81 + .long 0x3fff8000,0x6c4e0c81,0x3fd78000,0x6d00007c + .long 0xf23c4480,0x3f800000,0xf20000a8,0xf227e004 + .long 0xf23c4500,0x3f800000,0xf2000122,0xf20008a3 + .long 0xf21fd020,0xf2000484,0xf2000420,0xf227e001 + .long 0x41d761ff,0xfffffd66,0xdffc0000,0x000c60ff + .long 0x00002b6c,0xf2000018,0xf23c4438,0x3f800000 + .long 0xf2d20000,0x29d4f23a,0x4800c5a6,0x22100281 + .long 0x80000000,0x00813f80,0x00002f01,0xf2009000 + .long 0xf21f4423,0x60ff0000,0x2b36f200,0x9000123c + .long 0x0003f210,0x480060ff,0x00002b16,0x60ff0000 + .long 0x29b2f210,0x48002210,0x32280004,0x02817fff + .long 0xffff0c81,0x3fff8000,0x6c44f23c,0x44803f80 + .long 0x0000f200,0x00a2f200,0x001af23c,0x44223f80 + .long 0x0000f200,0x0420f200,0x00042f00,0x4280f227 + .long 0xe00141d7,0x61ffffff,0xfcc4dffc,0x0000000c + .long 0xf21f9000,0xf2000022,0x60ff0000,0x2acaf200 + .long 0x0018f23c,0x44383f80,0x0000f2d2,0x0000292a + .long 0x4a106a18,0xf23a4800,0xc4e8f200,0x9000f23c + .long 0x44220080,0x000060ff,0x00002a9c,0x60ff0000 + .long 0x2ce8f200,0x9000f23a,0x4800c4d6,0x60ff0000 + .long 0x2a863fdc,0x000082e3,0x08654361,0xc4c60000 + .long 0x00003fa5,0x55555555,0x4cc13fc5,0x55555555 + .long 0x4a543f81,0x11111117,0x43853fa5,0x55555555 + .long 0x4f5a3fc5,0x55555555,0x55550000,0x00000000 + .long 0x00003ec7,0x1de3a577,0x46823efa,0x01a019d7 + .long 0xcb683f2a,0x01a01a01,0x9df33f56,0xc16c16c1 + .long 0x70e23f81,0x11111111,0x11113fa5,0x55555555 + .long 0x55553ffc,0x0000aaaa,0xaaaaaaaa,0xaaab0000 + .long 0x000048b0,0x00000000,0x00003730,0x00000000 + .long 0x00003fff,0x00008000,0x00000000,0x00000000 + .long 0x00003fff,0x00008164,0xd1f3bc03,0x07749f84 + .long 0x1a9b3fff,0x000082cd,0x8698ac2b,0xa1d89fc1 + .long 0xd5b93fff,0x0000843a,0x28c3acde,0x4048a072 + .long 0x83693fff,0x000085aa,0xc367cc48,0x7b141fc5 + .long 0xc95c3fff,0x0000871f,0x61969e8d,0x10101ee8 + .long 0x5c9f3fff,0x00008898,0x0e8092da,0x85289fa2 + .long 0x07293fff,0x00008a14,0xd575496e,0xfd9ca07b + .long 0xf9af3fff,0x00008b95,0xc1e3ea8b,0xd6e8a002 + .long 0x0dcf3fff,0x00008d1a,0xdf5b7e5b,0xa9e4205a + .long 0x63da3fff,0x00008ea4,0x398b45cd,0x53c01eb7 + .long 0x00513fff,0x00009031,0xdc431466,0xb1dc1f6e + .long 0xb0293fff,0x000091c3,0xd373ab11,0xc338a078 + .long 0x14943fff,0x0000935a,0x2b2f13e6,0xe92c9eb3 + .long 0x19b03fff,0x000094f4,0xefa8fef7,0x09602017 + .long 0x457d3fff,0x00009694,0x2d372018,0x5a001f11 + .long 0xd5373fff,0x00009837,0xf0518db8,0xa9709fb9 + .long 0x52dd3fff,0x000099e0,0x459320b7,0xfa641fe4 + .long 0x30873fff,0x00009b8d,0x39b9d54e,0x55381fa2 + .long 0xa8183fff,0x00009d3e,0xd9a72cff,0xb7501fde + .long 0x494d3fff,0x00009ef5,0x326091a1,0x11ac2050 + .long 0x48903fff,0x0000a0b0,0x510fb971,0x4fc4a073 + .long 0x691c3fff,0x0000a270,0x43030c49,0x68181f9b + .long 0x7a053fff,0x0000a435,0x15ae09e6,0x80a0a079 + .long 0x71263fff,0x0000a5fe,0xd6a9b151,0x38eca071 + .long 0xa1403fff,0x0000a7cd,0x93b4e965,0x3568204f + .long 0x62da3fff,0x0000a9a1,0x5ab4ea7c,0x0ef81f28 + .long 0x3c4a3fff,0x0000ab7a,0x39b5a93e,0xd3389f9a + .long 0x7fdc3fff,0x0000ad58,0x3eea42a1,0x4ac8a05b + .long 0x3fac3fff,0x0000af3b,0x78ad690a,0x43741fdf + .long 0x26103fff,0x0000b123,0xf581d2ac,0x25909f70 + .long 0x5f903fff,0x0000b311,0xc412a911,0x2488201f + .long 0x678a3fff,0x0000b504,0xf333f9de,0x64841f32 + .long 0xfb133fff,0x0000b6fd,0x91e328d1,0x77902003 + .long 0x8b303fff,0x0000b8fb,0xaf4762fb,0x9ee8200d + .long 0xc3cc3fff,0x0000baff,0x5ab2133e,0x45fc9f8b + .long 0x2ae63fff,0x0000bd08,0xa39f580c,0x36c0a02b + .long 0xbf703fff,0x0000bf17,0x99b67a73,0x1084a00b + .long 0xf5183fff,0x0000c12c,0x4cca6670,0x9458a041 + .long 0xdd413fff,0x0000c346,0xccda2497,0x64089fdf + .long 0x137b3fff,0x0000c567,0x2a115506,0xdadc201f + .long 0x15683fff,0x0000c78d,0x74c8abb9,0xb15c1fc1 + .long 0x3a2e3fff,0x0000c9b9,0xbd866e2f,0x27a4a03f + .long 0x8f033fff,0x0000cbec,0x14fef272,0x7c5c1ff4 + .long 0x907d3fff,0x0000ce24,0x8c151f84,0x80e49e6e + .long 0x53e43fff,0x0000d063,0x33daef2b,0x25941fd6 + .long 0xd45c3fff,0x0000d2a8,0x1d91f12a,0xe45ca076 + .long 0xedb93fff,0x0000d4f3,0x5aabcfed,0xfa209fa6 + .long 0xde213fff,0x0000d744,0xfccad69d,0x6af41ee6 + .long 0x9a2f3fff,0x0000d99d,0x15c278af,0xd7b4207f + .long 0x439f3fff,0x0000dbfb,0xb797daf2,0x3754201e + .long 0xc2073fff,0x0000de60,0xf4825e0e,0x91249e8b + .long 0xe1753fff,0x0000e0cc,0xdeec2a94,0xe1102003 + .long 0x2c4b3fff,0x0000e33f,0x8972be8a,0x5a502004 + .long 0xdff53fff,0x0000e5b9,0x06e77c83,0x48a81e72 + .long 0xf47a3fff,0x0000e839,0x6a503c4b,0xdc681f72 + .long 0x2f223fff,0x0000eac0,0xc6e7dd24,0x3930a017 + .long 0xe9453fff,0x0000ed4f,0x301ed994,0x2b841f40 + .long 0x1a5b3fff,0x0000efe4,0xb99bdcda,0xf5cc9fb9 + .long 0xa9e33fff,0x0000f281,0x773c59ff,0xb1382074 + .long 0x4c053fff,0x0000f525,0x7d152486,0xcc2c1f77 + .long 0x3a193fff,0x0000f7d0,0xdf730ad1,0x3bb81ffe + .long 0x90d53fff,0x0000fa83,0xb2db722a,0x033ca041 + .long 0xed223fff,0x0000fd3e,0x0c0cf486,0xc1741f85 + .long 0x3f3a2210,0x02817fff,0x00000c81,0x3fbe0000 + .long 0x6c0660ff,0x00000108,0x32280004,0x0c81400c + .long 0xb1676d06,0x60ff0000,0x010cf210,0x4800f200 + .long 0x0080f23c,0x442342b8,0xaa3bf227,0xe00c2d7c + .long 0x00000000,0xff58f201,0x600043fa,0xfbb6f201 + .long 0x40002d41,0xff540281,0x0000003f,0xe989d3c1 + .long 0x222eff54,0xec810641,0x3fff3d7a,0xfb06ff54 + .long 0xf2000100,0xf23c4423,0xbc317218,0xf23a4923 + .long 0xfaf2f200,0x0422f200,0x0822f200,0x0080f200 + .long 0x04a3f23c,0x45003ab6,0x0b70f200,0x0523f200 + .long 0x0580f23c,0x45a33c08,0x8895f23a,0x5522fad4 + .long 0xf23a55a2,0xfad6f200,0x05233d41,0xff842d7c + .long 0x80000000,0xff8842ae,0xff8cf200,0x05a3f23c + .long 0x45223f00,0x0000f200,0x01a3f200,0x0523f200 + .long 0x0c22f219,0x4880f200,0x0822f200,0x0423f21f + .long 0xd030f211,0x4422f200,0x0422222e,0xff584a81 + .long 0x6706f22e,0x4823ff90,0xf2009000,0x123c0000 + .long 0xf22e4823,0xff8460ff,0x000024c6,0xf210d080 + .long 0xf2009000,0xf23c4422,0x3f800000,0x60ff0000 + .long 0x24c60c81,0x400cb27c,0x6e66f210,0x4800f200 + .long 0x0080f23c,0x442342b8,0xaa3bf227,0xe00c2d7c + .long 0x00000001,0xff58f201,0x600043fa,0xfaa6f201 + .long 0x40002d41,0xff540281,0x0000003f,0xe989d3c1 + .long 0x222eff54,0xec812d41,0xff54e281,0x93aeff54 + .long 0x06413fff,0x3d41ff90,0x2d7c8000,0x0000ff94 + .long 0x42aeff98,0x222eff54,0x06413fff,0x6000fed2 + .long 0x4a106bff,0x00002370,0x60ff0000,0x24122f10 + .long 0x02978000,0x00000097,0x00800000,0xf23c4400 + .long 0x3f800000,0xf2009000,0xf21f4422,0x60ff0000 + .long 0x24262210,0x02817fff,0x00000c81,0x3ffd0000 + .long 0x6c0660ff,0x0000015e,0x32280004,0x0c814004 + .long 0xc2156f06,0x60ff0000,0x026cf210,0x4800f200 + .long 0x0080f23c,0x442342b8,0xaa3bf227,0xe00cf201 + .long 0x600043fa,0xf9eef201,0x40002d41,0xff540281 + .long 0x0000003f,0xe989d3c1,0x222eff54,0xec812d41 + .long 0xff54f200,0x0100f23c,0x4423bc31,0x7218f23a + .long 0x4923f930,0xf2000422,0xf2000822,0x06413fff + .long 0xf2000080,0xf20004a3,0xf23c4500,0x3950097b + .long 0xf2000523,0xf2000580,0xf23c45a3,0x3ab60b6a + .long 0xf23a5522,0xf91ef23a,0x55a2f920,0x3d41ff84 + .long 0x2d7c8000,0x0000ff88,0x42aeff8c,0xf2000523 + .long 0x222eff54,0x4441f200,0x05a30641,0x3ffff23a + .long 0x5522f900,0xf23c45a2,0x3f000000,0xf2000523 + .long 0x00418000,0x3d41ff90,0x2d7c8000,0x0000ff94 + .long 0x42aeff98,0xf2000ca3,0xf2000123,0xf2000422 + .long 0xf2000822,0xf21fd030,0xf2114823,0x222eff54 + .long 0x0c810000,0x003f6f1a,0xf2294480,0x000cf22e + .long 0x48a2ff90,0xf2000422,0xf2114822,0x60ff0000 + .long 0x00340c81,0xfffffffd,0x6c16f229,0x4422000c + .long 0xf2114822,0xf22e4822,0xff9060ff,0x00000016 + .long 0xf2194880,0xf2114422,0xf22e48a2,0xff90f200 + .long 0x0422f200,0x9000f22e,0x4823ff84,0x60ff0000 + .long 0x22ae0c81,0x3fbe0000,0x6c6c0c81,0x00330000 + .long 0x6d2c2d7c,0x80010000,0xff842d7c,0x80000000 + .long 0xff8842ae,0xff8cf210,0x4800f200,0x9000123c + .long 0x0002f22e,0x4822ff84,0x60ff0000,0x2264f210 + .long 0x4800f23a,0x5423f86c,0x2d7c8001,0x0000ff84 + .long 0x2d7c8000,0x0000ff88,0x42aeff8c,0xf22e4822 + .long 0xff84f200,0x9000123c,0x0000f23a,0x5423f84c + .long 0x60ff0000,0x222cf210,0x4800f200,0x0023f227 + .long 0xe00cf23c,0x44802f30,0xcaa8f200,0x00a3f23c + .long 0x4500310f,0x8290f23c,0x44a232d7,0x3220f200 + .long 0x0123f200,0x00a3f23c,0x45223493,0xf281f23a + .long 0x54a2f7c0,0xf2000123,0xf20000a3,0xf23a5522 + .long 0xf7baf23a,0x54a2f7bc,0xf2000123,0xf20000a3 + .long 0xf23a5522,0xf7b6f23a,0x54a2f7b8,0xf2000123 + .long 0xf20000a3,0xf23a5522,0xf7b2f23a,0x48a2f7b4 + .long 0xf2000123,0xf20000a3,0xf2000123,0xf21048a3 + .long 0xf23c4423,0x3f000000,0xf20008a2,0xf21fd030 + .long 0xf2000422,0xf2009000,0xf2104822,0x60ff0000 + .long 0x218e2210,0x0c810000,0x00006e00,0xfbacf23c + .long 0x4400bf80,0x0000f200,0x9000f23c,0x44220080 + .long 0x000060ff,0x00002178,0x60ff0000,0x1ff63028 + .long 0x00000880,0x000f0440,0x3ffff200,0x50006d02 + .long 0x4e751d7c,0x0008ff64,0x4e7561ff,0x00007cfc + .long 0x44400440,0x3ffff200,0x50001d7c,0x0008ff64 + .long 0x4e753028,0x00000040,0x7fff0880,0x000e2d68 + .long 0x0004ff88,0x2d680008,0xff8c3d40,0xff84f22e + .long 0x4800ff84,0x6b024e75,0x1d7c0008,0xff644e75 + .long 0x61ff0000,0x7cb660ca,0x7ffb0000,0x80000000 + .long 0x00000000,0x00000000,0xf2104800,0x22103228 + .long 0x00040281,0x7fffffff,0x0c81400c,0xb1676e42 + .long 0xf2000018,0x2f004280,0xf227e001,0x41d761ff + .long 0xfffffad2,0xdffc0000,0x000cf23c,0x44233f00 + .long 0x0000201f,0xf23c4480,0x3e800000,0xf20000a0 + .long 0xf2009000,0x123c0002,0xf2000422,0x60ff0000 + .long 0x20800c81,0x400cb2b3,0x6e3cf200,0x0018f23a + .long 0x5428baae,0xf23a5428,0xbab02f00,0x4280f227 + .long 0xe00141d7,0x61ffffff,0xfa7cdffc,0x0000000c + .long 0x201ff200,0x9000123c,0x0000f23a,0x4823ff5a + .long 0x60ff0000,0x203c60ff,0x00002014,0xf23c4400 + .long 0x3f800000,0xf2009000,0xf23c4422,0x00800000 + .long 0x60ff0000,0x2032f210,0x48002210,0x32280004 + .long 0x22410281,0x7fffffff,0x0c81400c,0xb1676e62 + .long 0xf2000018,0x48e78040,0xf227e001,0x41d74280 + .long 0x61ffffff,0xfbe0dffc,0x0000000c,0xf23c9000 + .long 0x00000000,0x4cdf0201,0xf2000080,0xf23c44a2 + .long 0x3f800000,0xf2276800,0xf2000420,0x22090281 + .long 0x80000000,0x00813f00,0x0000f21f,0x48222f01 + .long 0xf2009000,0x123c0000,0xf21f4423,0x60ff0000 + .long 0x1fa00c81,0x400cb2b3,0x6eff0000,0x1f4cf200 + .long 0x0018f23a,0x5428b9ca,0x2f3c0000,0x00002f3c + .long 0x80000000,0x22090281,0x80000000,0x00817ffb + .long 0x00002f01,0xf23a5428,0xb9b02f00,0x4280f227 + .long 0xe00141d7,0x61ffffff,0xf97cdffc,0x0000000c + .long 0x201ff200,0x9000123c,0x0000f21f,0x482360ff + .long 0x00001f3e,0x60ff0000,0x1ddaf210,0x4800f22e + .long 0x6800ff84,0x22103228,0x00042d41,0xff840281 + .long 0x7fffffff,0x0c813fd7,0x80006d00,0x00740c81 + .long 0x3fffddce,0x6e00006a,0x222eff84,0x2d41ff5c + .long 0x02817fff,0x00000681,0x00010000,0x2d41ff84 + .long 0x02ae8000,0x0000ff5c,0xf22e4800,0xff842f00 + .long 0x4280f227,0xe00141d7,0x61ffffff,0xfac8dffc + .long 0x0000000c,0x201ff200,0x0080f23c,0x44a24000 + .long 0x0000222e,0xff5cf22e,0x6880ff84,0xb3aeff84 + .long 0xf2009000,0xf22e4820,0xff8460ff,0x00001eb0 + .long 0x0c813fff,0x80006d00,0x00880c81,0x40048aa1 + .long 0x6e000092,0x222eff84,0x2d41ff5c,0x02817fff + .long 0x00000681,0x00010000,0x2d41ff84,0x02ae8000 + .long 0x0000ff5c,0x222eff5c,0xf22e4800,0xff842f00 + .long 0x4280f227,0xe00141d7,0x61ffffff,0xf878dffc + .long 0x0000000c,0x201f222e,0xff5cf23c,0x44223f80 + .long 0x00000a81,0xc0000000,0xf2014480,0xf20000a0 + .long 0x222eff5c,0x00813f80,0x0000f201,0x4400f200 + .long 0x9000123c,0x0002f200,0x042260ff,0x00001e20 + .long 0xf2009000,0x123c0003,0xf22e4800,0xff8460ff + .long 0x00001dfe,0x222eff84,0x02818000,0x00000081 + .long 0x3f800000,0xf2014400,0x02818000,0x00000a81 + .long 0x80800000,0xf2009000,0xf2014422,0x60ff0000 + .long 0x1dde60ff,0x00001c6c,0x3ffe0000,0xb17217f7 + .long 0xd1cf79ac,0x00000000,0x3f800000,0x00000000 + .long 0x7f800000,0xbf800000,0x3fc2499a,0xb5e4040b + .long 0xbfc555b5,0x848cb7db,0x3fc99999,0x987d8730 + .long 0xbfcfffff,0xff6f7e97,0x3fd55555,0x555555a4 + .long 0xbfe00000,0x00000008,0x3f175496,0xadd7dad6 + .long 0x3f3c71c2,0xfe80c7e0,0x3f624924,0x928bccff + .long 0x3f899999,0x999995ec,0x3fb55555,0x55555555 + .long 0x40000000,0x00000000,0x3f990000,0x80000000 + .long 0x00000000,0x00000000,0x3ffe0000,0xfe03f80f + .long 0xe03f80fe,0x00000000,0x3ff70000,0xff015358 + .long 0x833c47e2,0x00000000,0x3ffe0000,0xfa232cf2 + .long 0x52138ac0,0x00000000,0x3ff90000,0xbdc8d83e + .long 0xad88d549,0x00000000,0x3ffe0000,0xf6603d98 + .long 0x0f6603da,0x00000000,0x3ffa0000,0x9cf43dcf + .long 0xf5eafd48,0x00000000,0x3ffe0000,0xf2b9d648 + .long 0x0f2b9d65,0x00000000,0x3ffa0000,0xda16eb88 + .long 0xcb8df614,0x00000000,0x3ffe0000,0xef2eb71f + .long 0xc4345238,0x00000000,0x3ffb0000,0x8b29b775 + .long 0x1bd70743,0x00000000,0x3ffe0000,0xebbdb2a5 + .long 0xc1619c8c,0x00000000,0x3ffb0000,0xa8d839f8 + .long 0x30c1fb49,0x00000000,0x3ffe0000,0xe865ac7b + .long 0x7603a197,0x00000000,0x3ffb0000,0xc61a2eb1 + .long 0x8cd907ad,0x00000000,0x3ffe0000,0xe525982a + .long 0xf70c880e,0x00000000,0x3ffb0000,0xe2f2a47a + .long 0xde3a18af,0x00000000,0x3ffe0000,0xe1fc780e + .long 0x1fc780e2,0x00000000,0x3ffb0000,0xff64898e + .long 0xdf55d551,0x00000000,0x3ffe0000,0xdee95c4c + .long 0xa037ba57,0x00000000,0x3ffc0000,0x8db956a9 + .long 0x7b3d0148,0x00000000,0x3ffe0000,0xdbeb61ee + .long 0xd19c5958,0x00000000,0x3ffc0000,0x9b8fe100 + .long 0xf47ba1de,0x00000000,0x3ffe0000,0xd901b203 + .long 0x6406c80e,0x00000000,0x3ffc0000,0xa9372f1d + .long 0x0da1bd17,0x00000000,0x3ffe0000,0xd62b80d6 + .long 0x2b80d62c,0x00000000,0x3ffc0000,0xb6b07f38 + .long 0xce90e46b,0x00000000,0x3ffe0000,0xd3680d36 + .long 0x80d3680d,0x00000000,0x3ffc0000,0xc3fd0329 + .long 0x06488481,0x00000000,0x3ffe0000,0xd0b69fcb + .long 0xd2580d0b,0x00000000,0x3ffc0000,0xd11de0ff + .long 0x15ab18ca,0x00000000,0x3ffe0000,0xce168a77 + .long 0x25080ce1,0x00000000,0x3ffc0000,0xde1433a1 + .long 0x6c66b150,0x00000000,0x3ffe0000,0xcb8727c0 + .long 0x65c393e0,0x00000000,0x3ffc0000,0xeae10b5a + .long 0x7ddc8add,0x00000000,0x3ffe0000,0xc907da4e + .long 0x871146ad,0x00000000,0x3ffc0000,0xf7856e5e + .long 0xe2c9b291,0x00000000,0x3ffe0000,0xc6980c69 + .long 0x80c6980c,0x00000000,0x3ffd0000,0x82012ca5 + .long 0xa68206d7,0x00000000,0x3ffe0000,0xc4372f85 + .long 0x5d824ca6,0x00000000,0x3ffd0000,0x882c5fcd + .long 0x7256a8c5,0x00000000,0x3ffe0000,0xc1e4bbd5 + .long 0x95f6e947,0x00000000,0x3ffd0000,0x8e44c60b + .long 0x4ccfd7de,0x00000000,0x3ffe0000,0xbfa02fe8 + .long 0x0bfa02ff,0x00000000,0x3ffd0000,0x944ad09e + .long 0xf4351af6,0x00000000,0x3ffe0000,0xbd691047 + .long 0x07661aa3,0x00000000,0x3ffd0000,0x9a3eecd4 + .long 0xc3eaa6b2,0x00000000,0x3ffe0000,0xbb3ee721 + .long 0xa54d880c,0x00000000,0x3ffd0000,0xa0218434 + .long 0x353f1de8,0x00000000,0x3ffe0000,0xb92143fa + .long 0x36f5e02e,0x00000000,0x3ffd0000,0xa5f2fcab + .long 0xbbc506da,0x00000000,0x3ffe0000,0xb70fbb5a + .long 0x19be3659,0x00000000,0x3ffd0000,0xabb3b8ba + .long 0x2ad362a5,0x00000000,0x3ffe0000,0xb509e68a + .long 0x9b94821f,0x00000000,0x3ffd0000,0xb1641795 + .long 0xce3ca97b,0x00000000,0x3ffe0000,0xb30f6352 + .long 0x8917c80b,0x00000000,0x3ffd0000,0xb7047551 + .long 0x5d0f1c61,0x00000000,0x3ffe0000,0xb11fd3b8 + .long 0x0b11fd3c,0x00000000,0x3ffd0000,0xbc952afe + .long 0xea3d13e1,0x00000000,0x3ffe0000,0xaf3addc6 + .long 0x80af3ade,0x00000000,0x3ffd0000,0xc2168ed0 + .long 0xf458ba4a,0x00000000,0x3ffe0000,0xad602b58 + .long 0x0ad602b6,0x00000000,0x3ffd0000,0xc788f439 + .long 0xb3163bf1,0x00000000,0x3ffe0000,0xab8f69e2 + .long 0x8359cd11,0x00000000,0x3ffd0000,0xccecac08 + .long 0xbf04565d,0x00000000,0x3ffe0000,0xa9c84a47 + .long 0xa07f5638,0x00000000,0x3ffd0000,0xd2420487 + .long 0x2dd85160,0x00000000,0x3ffe0000,0xa80a80a8 + .long 0x0a80a80b,0x00000000,0x3ffd0000,0xd7894992 + .long 0x3bc3588a,0x00000000,0x3ffe0000,0xa655c439 + .long 0x2d7b73a8,0x00000000,0x3ffd0000,0xdcc2c4b4 + .long 0x9887dacc,0x00000000,0x3ffe0000,0xa4a9cf1d + .long 0x96833751,0x00000000,0x3ffd0000,0xe1eebd3e + .long 0x6d6a6b9e,0x00000000,0x3ffe0000,0xa3065e3f + .long 0xae7cd0e0,0x00000000,0x3ffd0000,0xe70d785c + .long 0x2f9f5bdc,0x00000000,0x3ffe0000,0xa16b312e + .long 0xa8fc377d,0x00000000,0x3ffd0000,0xec1f392c + .long 0x5179f283,0x00000000,0x3ffe0000,0x9fd809fd + .long 0x809fd80a,0x00000000,0x3ffd0000,0xf12440d3 + .long 0xe36130e6,0x00000000,0x3ffe0000,0x9e4cad23 + .long 0xdd5f3a20,0x00000000,0x3ffd0000,0xf61cce92 + .long 0x346600bb,0x00000000,0x3ffe0000,0x9cc8e160 + .long 0xc3fb19b9,0x00000000,0x3ffd0000,0xfb091fd3 + .long 0x8145630a,0x00000000,0x3ffe0000,0x9b4c6f9e + .long 0xf03a3caa,0x00000000,0x3ffd0000,0xffe97042 + .long 0xbfa4c2ad,0x00000000,0x3ffe0000,0x99d722da + .long 0xbde58f06,0x00000000,0x3ffe0000,0x825efced + .long 0x49369330,0x00000000,0x3ffe0000,0x9868c809 + .long 0x868c8098,0x00000000,0x3ffe0000,0x84c37a7a + .long 0xb9a905c9,0x00000000,0x3ffe0000,0x97012e02 + .long 0x5c04b809,0x00000000,0x3ffe0000,0x87224c2e + .long 0x8e645fb7,0x00000000,0x3ffe0000,0x95a02568 + .long 0x095a0257,0x00000000,0x3ffe0000,0x897b8cac + .long 0x9f7de298,0x00000000,0x3ffe0000,0x94458094 + .long 0x45809446,0x00000000,0x3ffe0000,0x8bcf55de + .long 0xc4cd05fe,0x00000000,0x3ffe0000,0x92f11384 + .long 0x0497889c,0x00000000,0x3ffe0000,0x8e1dc0fb + .long 0x89e125e5,0x00000000,0x3ffe0000,0x91a2b3c4 + .long 0xd5e6f809,0x00000000,0x3ffe0000,0x9066e68c + .long 0x955b6c9b,0x00000000,0x3ffe0000,0x905a3863 + .long 0x3e06c43b,0x00000000,0x3ffe0000,0x92aade74 + .long 0xc7be59e0,0x00000000,0x3ffe0000,0x8f1779d9 + .long 0xfdc3a219,0x00000000,0x3ffe0000,0x94e9bff6 + .long 0x15845643,0x00000000,0x3ffe0000,0x8dda5202 + .long 0x37694809,0x00000000,0x3ffe0000,0x9723a1b7 + .long 0x20134203,0x00000000,0x3ffe0000,0x8ca29c04 + .long 0x6514e023,0x00000000,0x3ffe0000,0x995899c8 + .long 0x90eb8990,0x00000000,0x3ffe0000,0x8b70344a + .long 0x139bc75a,0x00000000,0x3ffe0000,0x9b88bdaa + .long 0x3a3dae2f,0x00000000,0x3ffe0000,0x8a42f870 + .long 0x5669db46,0x00000000,0x3ffe0000,0x9db4224f + .long 0xffe1157c,0x00000000,0x3ffe0000,0x891ac73a + .long 0xe9819b50,0x00000000,0x3ffe0000,0x9fdadc26 + .long 0x8b7a12da,0x00000000,0x3ffe0000,0x87f78087 + .long 0xf78087f8,0x00000000,0x3ffe0000,0xa1fcff17 + .long 0xce733bd4,0x00000000,0x3ffe0000,0x86d90544 + .long 0x7a34acc6,0x00000000,0x3ffe0000,0xa41a9e8f + .long 0x5446fb9f,0x00000000,0x3ffe0000,0x85bf3761 + .long 0x2cee3c9b,0x00000000,0x3ffe0000,0xa633cd7e + .long 0x6771cd8b,0x00000000,0x3ffe0000,0x84a9f9c8 + .long 0x084a9f9d,0x00000000,0x3ffe0000,0xa8489e60 + .long 0x0b435a5e,0x00000000,0x3ffe0000,0x83993052 + .long 0x3fbe3368,0x00000000,0x3ffe0000,0xaa59233c + .long 0xcca4bd49,0x00000000,0x3ffe0000,0x828cbfbe + .long 0xb9a020a3,0x00000000,0x3ffe0000,0xac656dae + .long 0x6bcc4985,0x00000000,0x3ffe0000,0x81848da8 + .long 0xfaf0d277,0x00000000,0x3ffe0000,0xae6d8ee3 + .long 0x60bb2468,0x00000000,0x3ffe0000,0x80808080 + .long 0x80808081,0x00000000,0x3ffe0000,0xb07197a2 + .long 0x3c46c654,0x00000000,0xf2104800,0x2d7c0000 + .long 0x0000ff54,0x22103228,0x00042d50,0xff842d68 + .long 0x0004ff88,0x2d680008,0xff8c0c81,0x00000000 + .long 0x6d000182,0x0c813ffe,0xf07d6d0a,0x0c813fff + .long 0x88416f00,0x00e2e081,0xe0810481,0x00003fff + .long 0xd2aeff54,0x41faf7b2,0xf2014080,0x2d7c3fff + .long 0x0000ff84,0x2d6eff88,0xff9402ae,0xfe000000 + .long 0xff9400ae,0x01000000,0xff94222e,0xff940281 + .long 0x7e000000,0xe081e081,0xe881d1c1,0xf22e4800 + .long 0xff842d7c,0x3fff0000,0xff9042ae,0xff98f22e + .long 0x4828ff90,0xf227e00c,0xf2104823,0xf23a48a3 + .long 0xf6c8f200,0x0100f200,0x0923f22e,0x6880ff84 + .long 0xf2000980,0xf2000880,0xf23a54a3,0xf6ccf23a + .long 0x5523f6ce,0xf23a54a2,0xf6d0f23a,0x5522f6d2 + .long 0xf2000ca3,0xf2000d23,0xf23a54a2,0xf6ccf23a + .long 0x5522f6ce,0xf2000ca3,0xd1fc0000,0x0010f200 + .long 0x0d23f200,0x00a3f200,0x0822f210,0x48a2f21f + .long 0xd030f200,0x0422f200,0x9000f22e,0x4822ff84 + .long 0x60ff0000,0x142af23c,0x58380001,0xf2c10000 + .long 0x1678f200,0x0080f23a,0x44a8f64e,0xf23a4422 + .long 0xf648f200,0x04a2f200,0x00a0f227,0xe00cf200 + .long 0x0400f200,0x0023f22e,0x6880ff84,0xf2000080 + .long 0xf20004a3,0xf23a5580,0xf660f23a,0x5500f662 + .long 0xf20005a3,0xf2000523,0xf23a55a2,0xf65cf23a + .long 0x5522f65e,0xf2000ca3,0xf2000123,0xf23a54a2 + .long 0xf658f22e,0x4823ff84,0xf20008a2,0xf21fd030 + .long 0xf2000423,0xf2009000,0xf22e4822,0xff8460ff + .long 0x0000139c,0x60ff0000,0x12102d7c,0xffffff9c + .long 0xff5448e7,0x3f002610,0x28280004,0x2a280008 + .long 0x42824a84,0x66342805,0x42857420,0x4286edc4 + .long 0x6000edac,0xd4862d43,0xff842d44,0xff882d45 + .long 0xff8c4482,0x2d42ff54,0xf22e4800,0xff844cdf + .long 0x00fc41ee,0xff846000,0xfe0c4286,0xedc46000 + .long 0x2406edac,0x2e05edad,0x44860686,0x00000020 + .long 0xecaf8887,0x2d43ff84,0x2d44ff88,0x2d45ff8c + .long 0x44822d42,0xff54f22e,0x4800ff84,0x4cdf00fc + .long 0x41eeff84,0x6000fdce,0xf2104800,0xf2000018 + .long 0xf23a4838,0xf5a4f292,0x0014f200,0x9000123c + .long 0x0003f210,0x480060ff,0x000012d6,0xf2104800 + .long 0x2d7c0000,0x0000ff54,0xf2000080,0xf23a4422 + .long 0xf508f22e,0x6800ff84,0x3d6eff88,0xff86222e + .long 0xff840c81,0x00000000,0x6f0000da,0x0c813ffe + .long 0x80006d00,0xfda20c81,0x3fffc000,0x6e00fd98 + .long 0x0c813ffe,0xf07d6d00,0x001a0c81,0x3fff8841 + .long 0x6e000010,0xf20004a2,0xf23a4422,0xf4bc6000 + .long 0xfe762d6e,0xff88ff94,0x02aefe00,0x0000ff94 + .long 0x00ae0100,0x0000ff94,0x0c813fff,0x80006c44 + .long 0xf23a4400,0xf4fc2d7c,0x3fff0000,0xff9042ae + .long 0xff98f22e,0x4828ff90,0x222eff94,0x02817e00 + .long 0x0000e081,0xe081e881,0xf20004a2,0xf227e00c + .long 0xf2000422,0x41faf4e2,0xd1c1f23a,0x4480f466 + .long 0x6000fd76,0xf23a4400,0xf4502d7c,0x3fff0000 + .long 0xff9042ae,0xff98f22e,0x4828ff90,0x222eff94 + .long 0x02817e00,0x0000e081,0xe081e881,0xf2000422 + .long 0xf227e00c,0x41faf4a2,0xd1c1f23a,0x4480f41e + .long 0x6000fd36,0x0c810000,0x00006d10,0xf23a4400 + .long 0xf414f200,0x900060ff,0x00001014,0xf23a4400 + .long 0xf3fcf200,0x900060ff,0x0000102e,0x60ff0000 + .long 0x10422210,0x32280004,0x02817fff,0xffff0c81 + .long 0x3fff8000,0x6c56f210,0x4818f200,0x0080f200 + .long 0x049af200,0x0022f23c,0x44a23f80,0x0000f200 + .long 0x04202210,0x02818000,0x00000081,0x3f000000 + .long 0x2f012f00,0x4280f227,0xe00141d7,0x61ffffff + .long 0xfe5adffc,0x0000000c,0x201ff200,0x9000123c + .long 0x0000f21f,0x442360ff,0x00001136,0xf2104818 + .long 0xf23c4438,0x3f800000,0xf2d20000,0x0fac60ff + .long 0x00000f7c,0x60ff0000,0x0fba3ffd,0x0000de5b + .long 0xd8a93728,0x71950000,0x00003fff,0x0000b8aa + .long 0x3b295c17,0xf0bc0000,0x0000f23c,0x58000001 + .long 0xf2104838,0xf2c10000,0x13502210,0x6d000090 + .long 0x2f004280,0x61ffffff,0xfba2f21f,0x9000f23a + .long 0x4823ffb8,0x60ff0000,0x10d62210,0x6d000070 + .long 0x2f004280,0x61ffffff,0xfd34f21f,0x9000f23a + .long 0x4823ff98,0x60ff0000,0x10c62210,0x6d000050 + .long 0x22280008,0x662e2228,0x00040281,0x7fffffff + .long 0x66223210,0x02810000,0x7fff0481,0x00003fff + .long 0x67ff0000,0x12e4f200,0x9000f201,0x400060ff + .long 0x0000107c,0x2f004280,0x61ffffff,0xfb2ef21f + .long 0x9000f23a,0x4823ff54,0x60ff0000,0x106260ff + .long 0x00000ed6,0x22106d00,0xfff62f00,0x428061ff + .long 0xfffffcba,0xf21f9000,0xf23a4823,0xff2e60ff + .long 0x0000104c,0x406a934f,0x0979a371,0x3f734413 + .long 0x509f8000,0xbfcd0000,0xc0219dc1,0xda994fd2 + .long 0x00000000,0x40000000,0x935d8ddd,0xaaa8ac17 + .long 0x00000000,0x3ffe0000,0xb17217f7,0xd1cf79ac + .long 0x00000000,0x3f56c16d,0x6f7bd0b2,0x3f811112 + .long 0x302c712c,0x3fa55555,0x55554cc1,0x3fc55555 + .long 0x55554a54,0x3fe00000,0x00000000,0x00000000 + .long 0x00000000,0x3fff0000,0x80000000,0x00000000 + .long 0x3f738000,0x3fff0000,0x8164d1f3,0xbc030773 + .long 0x3fbef7ca,0x3fff0000,0x82cd8698,0xac2ba1d7 + .long 0x3fbdf8a9,0x3fff0000,0x843a28c3,0xacde4046 + .long 0x3fbcd7c9,0x3fff0000,0x85aac367,0xcc487b15 + .long 0xbfbde8da,0x3fff0000,0x871f6196,0x9e8d1010 + .long 0x3fbde85c,0x3fff0000,0x88980e80,0x92da8527 + .long 0x3fbebbf1,0x3fff0000,0x8a14d575,0x496efd9a + .long 0x3fbb80ca,0x3fff0000,0x8b95c1e3,0xea8bd6e7 + .long 0xbfba8373,0x3fff0000,0x8d1adf5b,0x7e5ba9e6 + .long 0xbfbe9670,0x3fff0000,0x8ea4398b,0x45cd53c0 + .long 0x3fbdb700,0x3fff0000,0x9031dc43,0x1466b1dc + .long 0x3fbeeeb0,0x3fff0000,0x91c3d373,0xab11c336 + .long 0x3fbbfd6d,0x3fff0000,0x935a2b2f,0x13e6e92c + .long 0xbfbdb319,0x3fff0000,0x94f4efa8,0xfef70961 + .long 0x3fbdba2b,0x3fff0000,0x96942d37,0x20185a00 + .long 0x3fbe91d5,0x3fff0000,0x9837f051,0x8db8a96f + .long 0x3fbe8d5a,0x3fff0000,0x99e04593,0x20b7fa65 + .long 0xbfbcde7b,0x3fff0000,0x9b8d39b9,0xd54e5539 + .long 0xbfbebaaf,0x3fff0000,0x9d3ed9a7,0x2cffb751 + .long 0xbfbd86da,0x3fff0000,0x9ef53260,0x91a111ae + .long 0xbfbebedd,0x3fff0000,0xa0b0510f,0xb9714fc2 + .long 0x3fbcc96e,0x3fff0000,0xa2704303,0x0c496819 + .long 0xbfbec90b,0x3fff0000,0xa43515ae,0x09e6809e + .long 0x3fbbd1db,0x3fff0000,0xa5fed6a9,0xb15138ea + .long 0x3fbce5eb,0x3fff0000,0xa7cd93b4,0xe965356a + .long 0xbfbec274,0x3fff0000,0xa9a15ab4,0xea7c0ef8 + .long 0x3fbea83c,0x3fff0000,0xab7a39b5,0xa93ed337 + .long 0x3fbecb00,0x3fff0000,0xad583eea,0x42a14ac6 + .long 0x3fbe9301,0x3fff0000,0xaf3b78ad,0x690a4375 + .long 0xbfbd8367,0x3fff0000,0xb123f581,0xd2ac2590 + .long 0xbfbef05f,0x3fff0000,0xb311c412,0xa9112489 + .long 0x3fbdfb3c,0x3fff0000,0xb504f333,0xf9de6484 + .long 0x3fbeb2fb,0x3fff0000,0xb6fd91e3,0x28d17791 + .long 0x3fbae2cb,0x3fff0000,0xb8fbaf47,0x62fb9ee9 + .long 0x3fbcdc3c,0x3fff0000,0xbaff5ab2,0x133e45fb + .long 0x3fbee9aa,0x3fff0000,0xbd08a39f,0x580c36bf + .long 0xbfbeaefd,0x3fff0000,0xbf1799b6,0x7a731083 + .long 0xbfbcbf51,0x3fff0000,0xc12c4cca,0x66709456 + .long 0x3fbef88a,0x3fff0000,0xc346ccda,0x24976407 + .long 0x3fbd83b2,0x3fff0000,0xc5672a11,0x5506dadd + .long 0x3fbdf8ab,0x3fff0000,0xc78d74c8,0xabb9b15d + .long 0xbfbdfb17,0x3fff0000,0xc9b9bd86,0x6e2f27a3 + .long 0xbfbefe3c,0x3fff0000,0xcbec14fe,0xf2727c5d + .long 0xbfbbb6f8,0x3fff0000,0xce248c15,0x1f8480e4 + .long 0xbfbcee53,0x3fff0000,0xd06333da,0xef2b2595 + .long 0xbfbda4ae,0x3fff0000,0xd2a81d91,0xf12ae45a + .long 0x3fbc9124,0x3fff0000,0xd4f35aab,0xcfedfa1f + .long 0x3fbeb243,0x3fff0000,0xd744fcca,0xd69d6af4 + .long 0x3fbde69a,0x3fff0000,0xd99d15c2,0x78afd7b6 + .long 0xbfb8bc61,0x3fff0000,0xdbfbb797,0xdaf23755 + .long 0x3fbdf610,0x3fff0000,0xde60f482,0x5e0e9124 + .long 0xbfbd8be1,0x3fff0000,0xe0ccdeec,0x2a94e111 + .long 0x3fbacb12,0x3fff0000,0xe33f8972,0xbe8a5a51 + .long 0x3fbb9bfe,0x3fff0000,0xe5b906e7,0x7c8348a8 + .long 0x3fbcf2f4,0x3fff0000,0xe8396a50,0x3c4bdc68 + .long 0x3fbef22f,0x3fff0000,0xeac0c6e7,0xdd24392f + .long 0xbfbdbf4a,0x3fff0000,0xed4f301e,0xd9942b84 + .long 0x3fbec01a,0x3fff0000,0xefe4b99b,0xdcdaf5cb + .long 0x3fbe8cac,0x3fff0000,0xf281773c,0x59ffb13a + .long 0xbfbcbb3f,0x3fff0000,0xf5257d15,0x2486cc2c + .long 0x3fbef73a,0x3fff0000,0xf7d0df73,0x0ad13bb9 + .long 0xbfb8b795,0x3fff0000,0xfa83b2db,0x722a033a + .long 0x3fbef84b,0x3fff0000,0xfd3e0c0c,0xf486c175 + .long 0xbfbef581,0xf210d080,0x22103228,0x0004f22e + .long 0x6800ff84,0x02817fff,0xffff0c81,0x3fb98000 + .long 0x6c046000,0x00880c81,0x400d80c0,0x6f046000 + .long 0x007cf200,0x0080f23c,0x44a34280,0x0000f22e + .long 0x6080ff54,0x2f0243fa,0xfbbcf22e,0x4080ff54 + .long 0x222eff54,0x24010281,0x0000003f,0xe981d3c1 + .long 0xec822202,0xe2819481,0x06820000,0x3ffff227 + .long 0xe00cf23c,0x44a33c80,0x00002d59,0xff842d59 + .long 0xff882d59,0xff8c3d59,0xff90f200,0x04283d59 + .long 0xff94426e,0xff9642ae,0xff98d36e,0xff84f23a + .long 0x4823fb22,0xd36eff90,0x60000100,0x0c813fff + .long 0x80006e12,0xf2009000,0xf23c4422,0x3f800000 + .long 0x60ff0000,0x0b12222e,0xff840c81,0x00000000 + .long 0x6d0660ff,0x00000ac8,0x60ff0000,0x0a1af200 + .long 0x9000f23c,0x44003f80,0x00002210,0x00810080 + .long 0x0001f201,0x442260ff,0x00000adc,0xf210d080 + .long 0x22103228,0x0004f22e,0x6800ff84,0x02817fff + .long 0xffff0c81,0x3fb98000,0x6c046000,0xff900c81 + .long 0x400b9b07,0x6f046000,0xff84f200,0x0080f23a + .long 0x54a3fa62,0xf22e6080,0xff542f02,0x43fafac6 + .long 0xf22e4080,0xff54222e,0xff542401,0x02810000 + .long 0x003fe981,0xd3c1ec82,0x2202e281,0x94810682 + .long 0x00003fff,0xf227e00c,0xf2000500,0xf23a54a3 + .long 0xfa2c2d59,0xff84f23a,0x4923fa2a,0x2d59ff88 + .long 0x2d59ff8c,0xf2000428,0x3d59ff90,0xf2000828 + .long 0x3d59ff94,0x426eff96,0x42aeff98,0xf23a4823 + .long 0xfa14d36e,0xff84d36e,0xff90f200,0x0080f200 + .long 0x04a3f23a,0x5500fa1e,0xf23a5580,0xfa20f200 + .long 0x0523f200,0x05a3f23a,0x5522fa1a,0xf23a55a2 + .long 0xfa1cf200,0x0523f200,0x05a3f23a,0x5522fa16 + .long 0xf20001a3,0xf2000523,0xf2000c22,0xf2000822 + .long 0xf21fd030,0xf22e4823,0xff84f22e,0x4822ff90 + .long 0xf22e4822,0xff84f200,0x90003d42,0xff84241f + .long 0x2d7c8000,0x0000ff88,0x42aeff8c,0x123c0000 + .long 0xf22e4823,0xff8460ff,0x00000996,0xf2009000 + .long 0xf23c4400,0x3f800000,0x22100081,0x00800001 + .long 0xf2014422,0x60ff0000,0x098e2f01,0xe8082200 + .long 0x02410003,0x0240000c,0x48403001,0x221f4a01 + .long 0x671e0c01,0x000a6f12,0x0c01000e,0x6f3c0c01 + .long 0x002f6f06,0x0c01003f,0x6f6260ff,0x00000baa + .long 0x4a00660c,0x41fb0170,0x000000d6,0x60000086 + .long 0x0c000003,0x670a41fb,0x01700000,0x00d06074 + .long 0x41fb0170,0x000000d2,0x606a0401,0x000b4a00 + .long 0x661041fb,0x01700000,0x00cc0c01,0x00026f54 + .long 0x605a0c00,0x0003670a,0x41fb0170,0x000000f2 + .long 0x60e841fb,0x01700000,0x012460de,0x04010030 + .long 0x4a006616,0x41fb0170,0x0000014e,0x0c010001 + .long 0x6f220c01,0x00076f24,0x601a0c00,0x0003670a + .long 0x41fb0170,0x000001f2,0x60e241fb,0x01700000 + .long 0x02a860d8,0x00ae0000,0x0208ff64,0xc2fc000c + .long 0x48404a00,0x6608f230,0xd0801000,0x4e754840 + .long 0x3d701000,0xff902d70,0x1004ff94,0x2d701008 + .long 0xff982200,0x428041ee,0xff904268,0x000261ff + .long 0x000062c6,0xf210d080,0x4e7551fc,0x40000000 + .long 0xc90fdaa2,0x2168c235,0x40000000,0xc90fdaa2 + .long 0x2168c234,0x40000000,0xc90fdaa2,0x2168c235 + .long 0x3ffd0000,0x9a209a84,0xfbcff798,0x40000000 + .long 0xadf85458,0xa2bb4a9a,0x3fff0000,0xb8aa3b29 + .long 0x5c17f0bc,0x3ffd0000,0xde5bd8a9,0x37287195 + .long 0x00000000,0x00000000,0x00000000,0x3ffd0000 + .long 0x9a209a84,0xfbcff798,0x40000000,0xadf85458 + .long 0xa2bb4a9a,0x3fff0000,0xb8aa3b29,0x5c17f0bb + .long 0x3ffd0000,0xde5bd8a9,0x37287195,0x00000000 + .long 0x00000000,0x00000000,0x3ffd0000,0x9a209a84 + .long 0xfbcff799,0x40000000,0xadf85458,0xa2bb4a9b + .long 0x3fff0000,0xb8aa3b29,0x5c17f0bc,0x3ffd0000 + .long 0xde5bd8a9,0x37287195,0x00000000,0x00000000 + .long 0x00000000,0x3ffe0000,0xb17217f7,0xd1cf79ac + .long 0x40000000,0x935d8ddd,0xaaa8ac17,0x3fff0000 + .long 0x80000000,0x00000000,0x40020000,0xa0000000 + .long 0x00000000,0x40050000,0xc8000000,0x00000000 + .long 0x400c0000,0x9c400000,0x00000000,0x40190000 + .long 0xbebc2000,0x00000000,0x40340000,0x8e1bc9bf + .long 0x04000000,0x40690000,0x9dc5ada8,0x2b70b59e + .long 0x40d30000,0xc2781f49,0xffcfa6d5,0x41a80000 + .long 0x93ba47c9,0x80e98ce0,0x43510000,0xaa7eebfb + .long 0x9df9de8e,0x46a30000,0xe319a0ae,0xa60e91c7 + .long 0x4d480000,0xc9767586,0x81750c17,0x5a920000 + .long 0x9e8b3b5d,0xc53d5de5,0x75250000,0xc4605202 + .long 0x8a20979b,0x3ffe0000,0xb17217f7,0xd1cf79ab + .long 0x40000000,0x935d8ddd,0xaaa8ac16,0x3fff0000 + .long 0x80000000,0x00000000,0x40020000,0xa0000000 + .long 0x00000000,0x40050000,0xc8000000,0x00000000 + .long 0x400c0000,0x9c400000,0x00000000,0x40190000 + .long 0xbebc2000,0x00000000,0x40340000,0x8e1bc9bf + .long 0x04000000,0x40690000,0x9dc5ada8,0x2b70b59d + .long 0x40d30000,0xc2781f49,0xffcfa6d5,0x41a80000 + .long 0x93ba47c9,0x80e98cdf,0x43510000,0xaa7eebfb + .long 0x9df9de8d,0x46a30000,0xe319a0ae,0xa60e91c6 + .long 0x4d480000,0xc9767586,0x81750c17,0x5a920000 + .long 0x9e8b3b5d,0xc53d5de4,0x75250000,0xc4605202 + .long 0x8a20979a,0x3ffe0000,0xb17217f7,0xd1cf79ac + .long 0x40000000,0x935d8ddd,0xaaa8ac17,0x3fff0000 + .long 0x80000000,0x00000000,0x40020000,0xa0000000 + .long 0x00000000,0x40050000,0xc8000000,0x00000000 + .long 0x400c0000,0x9c400000,0x00000000,0x40190000 + .long 0xbebc2000,0x00000000,0x40340000,0x8e1bc9bf + .long 0x04000000,0x40690000,0x9dc5ada8,0x2b70b59e + .long 0x40d30000,0xc2781f49,0xffcfa6d6,0x41a80000 + .long 0x93ba47c9,0x80e98ce0,0x43510000,0xaa7eebfb + .long 0x9df9de8e,0x46a30000,0xe319a0ae,0xa60e91c7 + .long 0x4d480000,0xc9767586,0x81750c18,0x5a920000 + .long 0x9e8b3b5d,0xc53d5de5,0x75250000,0xc4605202 + .long 0x8a20979b,0x2f003229,0x00005bee,0xff540281 + .long 0x00007fff,0x30280000,0x02407fff,0x0c403fff + .long 0x6d0000c0,0x0c40400c,0x6e0000a4,0xf2284803 + .long 0x0000f200,0x6000f23c,0x88000000,0x00004a29 + .long 0x00046b5e,0x2f003d69,0x0000ff84,0x2d690004 + .long 0xff882d69,0x0008ff8c,0x41eeff84,0x61ff0000 + .long 0x60ba4480,0xd09ff22e,0xd080ff84,0x0c40c001 + .long 0x6c36f21f,0x9000223c,0x80000000,0x0480ffff + .long 0xc0014480,0x0c000020,0x6c0ae0a9,0x42a72f01 + .long 0x42a76028,0x04000020,0xe0a92f01,0x42a742a7 + .long 0x601af229,0xd0800000,0xf21f9000,0x06403fff + .long 0x484042a7,0x2f3c8000,0x00002f00,0xf200b000 + .long 0x123c0000,0xf21f4823,0x60ff0000,0x04ce201f + .long 0xc1494a29,0x00006bff,0x0000038c,0x60ff0000 + .long 0x03c44a29,0x00046a16,0x201ff200,0x9000123c + .long 0x0003f229,0x48000000,0x60ff0000,0x049e201f + .long 0x204960ff,0x000002e2,0x00010000,0x80000000 + .long 0x00000000,0x00000000,0x422eff65,0x2f00422e + .long 0xff5c600c,0x422eff65,0x2f001d7c,0x0001ff5c + .long 0x48e73f00,0x36280000,0x3d43ff58,0x02830000 + .long 0x7fff2828,0x00042a28,0x00084a83,0x663c263c + .long 0x00003ffe,0x4a846616,0x28054285,0x04830000 + .long 0x00204286,0xedc46000,0xedac9686,0x60224286 + .long 0xedc46000,0x9686edac,0x2e05edad,0x44860686 + .long 0x00000020,0xecaf8887,0x60060683,0x00003ffe + .long 0x30290000,0x3d40ff5a,0x322eff58,0xb1810281 + .long 0x00008000,0x3d41ff5e,0x02800000,0x7fff2229 + .long 0x00042429,0x00084a80,0x663c203c,0x00003ffe + .long 0x4a816616,0x22024282,0x04800000,0x00204286 + .long 0xedc16000,0xeda99086,0x60224286,0xedc16000 + .long 0x9086eda9,0x2e02edaa,0x44860686,0x00000020 + .long 0xecaf8287,0x60060680,0x00003ffe,0x2d43ff54 + .long 0x2f009083,0x42864283,0x227c0000,0x00004a80 + .long 0x6c06201f,0x6000006a,0x588f4a86,0x6e0eb284 + .long 0x6608b485,0x66046000,0x01366508,0x94859384 + .long 0x42865283,0x4a80670e,0xd683d482,0xe39155c6 + .long 0x52895380,0x60d4202e,0xff544a81,0x66162202 + .long 0x42820480,0x00000020,0x4286edc1,0x6000eda9 + .long 0x9086601c,0x4286edc1,0x60006b14,0x9086eda9 + .long 0x2e02edaa,0x44860686,0x00000020,0xecaf8287 + .long 0x0c800000,0x41fe6c2a,0x3d40ff90,0x2d41ff94 + .long 0x2d42ff98,0x2c2eff54,0x3d46ff84,0x2d44ff88 + .long 0x2d45ff8c,0xf22e4800,0xff901d7c,0x0001ff5d + .long 0x60362d41,0xff942d42,0xff980480,0x00003ffe + .long 0x3d40ff90,0x2c2eff54,0x04860000,0x3ffe2d46 + .long 0xff54f22e,0x4800ff90,0x3d46ff84,0x2d44ff88 + .long 0x2d45ff8c,0x422eff5d,0x4a2eff5c,0x67222c2e + .long 0xff545386,0xb0866d18,0x6e0eb284,0x6608b485 + .long 0x66046000,0x007a6508,0xf22e4828,0xff845283 + .long 0x3c2eff5a,0x6c04f200,0x001a4286,0x3c2eff5e + .long 0x7e08eeae,0x02830000,0x007f8686,0x1d43ff65 + .long 0x4cdf00fc,0x201ff200,0x90004a2e,0xff5d6710 + .long 0x123c0000,0xf23a4823,0xfdc060ff,0x0000024c + .long 0x123c0003,0xf2000000,0x60ff0000,0x023e5283 + .long 0x0c800000,0x00086c04,0xe1ab6002,0x4283f23c + .long 0x44000000,0x0000422e,0xff5d6000,0xff942c03 + .long 0x02860000,0x00014a86,0x6700ff86,0x52833c2e + .long 0xff5a0a86,0x00008000,0x3d46ff5a,0x6000ff72 + .long 0x7fff0000,0xffffffff,0xffffffff,0x4a280000 + .long 0x6b12f23c,0x44007f80,0x000000ae,0x02000410 + .long 0xff644e75,0xf23c4400,0xff800000,0x00ae0a00 + .long 0x0410ff64,0x4e7500ae,0x01002080,0xff64f23a + .long 0xd080ffbe,0x4e7500ae,0x00000800,0xff646008 + .long 0x00ae0000,0x0a28ff64,0x22482200,0x020100c0 + .long 0x660e4a28,0x00006a18,0x08ee0003,0xff646010 + .long 0x2f094a28,0x00005bc1,0x61ff0000,0x0196225f + .long 0xf210d080,0x102eff62,0x0200000a,0x66024e75 + .long 0x3d690000,0xff842d69,0x0004ff88,0x2d690008 + .long 0xff8c41ee,0xff8461ff,0x00005cd0,0x06800000 + .long 0x6000026e,0x8000ff84,0x816eff84,0xf22ed040 + .long 0xff844e75,0x00ae0000,0x0a28ff64,0x4a105bc1 + .long 0x61ff0000,0x013ef210,0xd080f23c,0x44800000 + .long 0x00004e75,0x00ae0000,0x0a28ff64,0x51c161ff + .long 0x00000120,0xf210d080,0xf23c4480,0x00000000 + .long 0x4e7500ae,0x00001048,0xff641200,0x020100c0 + .long 0x675c4a28,0x00046b24,0x3d680000,0xff842d68 + .long 0x0004ff88,0x2d680008,0xff8c41ee,0xff8448e7 + .long 0xc08061ff,0x00005c44,0x4cdf0103,0x0c010040 + .long 0x660e4aa8,0x00086614,0x4a280007,0x660e601e + .long 0x22280008,0x02810000,0x07ff6712,0x00ae0000 + .long 0x0200ff64,0x600800ae,0x00001248,0xff644a28 + .long 0x00005bc1,0x61ff0000,0x5f261d40,0xff64f210 + .long 0xd080f23c,0x44800000,0x00004e75,0x00ae0000 + .long 0x1248ff64,0x51c161ff,0x00005f04,0x1d40ff64 + .long 0xf210d080,0xf23c4480,0x00000000,0x4e75f327 + .long 0x4a2f0002,0x6b2edffc,0x0000000c,0xf294000e + .long 0xf2810014,0x006e0208,0xff664e75,0x00ae0800 + .long 0x0208ff64,0x4e751d7c,0x0004ff64,0x006e0208 + .long 0xff664e75,0x006e0208,0xff6661ff,0x00000bae + .long 0xdffc0000,0x000c4e75,0xf3274a2f,0x00026bea + .long 0xdffc0000,0x000cf200,0xa80081ae,0xff644e75 + .long 0x00ae0000,0x0a28ff64,0x02410010,0xe8080200 + .long 0x000f8001,0x2200e309,0x1d7b000a,0xff6441fb + .long 0x16204e75,0x04040400,0x04040400,0x04040400 + .long 0x00000000,0x0c0c080c,0x0c0c080c,0x0c0c080c + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000001,0x00000000 + .long 0x3f810000,0x00000000,0x00000000,0x00000000 + .long 0x3f810000,0x00000000,0x00000000,0x00000000 + .long 0x3f810000,0x00000000,0x00000000,0x00000000 + .long 0x3f810000,0x00000100,0x00000000,0x00000000 + .long 0x3c010000,0x00000000,0x00000000,0x00000000 + .long 0x3c010000,0x00000000,0x00000000,0x00000000 + .long 0x3c010000,0x00000000,0x00000000,0x00000000 + .long 0x3c010000,0x00000000,0x00000800,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x80000000,0x00000000,0x00000000,0x00000000 + .long 0x80000000,0x00000000,0x00000000,0x00000000 + .long 0x80000000,0x00000000,0x00000001,0x00000000 + .long 0x80000000,0x00000000,0x00000000,0x00000000 + .long 0xbf810000,0x00000000,0x00000000,0x00000000 + .long 0xbf810000,0x00000000,0x00000000,0x00000000 + .long 0xbf810000,0x00000100,0x00000000,0x00000000 + .long 0xbf810000,0x00000000,0x00000000,0x00000000 + .long 0xbc010000,0x00000000,0x00000000,0x00000000 + .long 0xbc010000,0x00000000,0x00000000,0x00000000 + .long 0xbc010000,0x00000000,0x00000800,0x00000000 + .long 0xbc010000,0x00000000,0x00000000,0x00000000 + .long 0x4a280000,0x6b10f23c,0x44000000,0x00001d7c + .long 0x0004ff64,0x4e75f23c,0x44008000,0x00001d7c + .long 0x000cff64,0x4e754a29,0x00006bea,0x60d84a28 + .long 0x00006b10,0xf23c4400,0x7f800000,0x1d7c0002 + .long 0xff644e75,0xf23c4400,0xff800000,0x1d7c000a + .long 0xff644e75,0x4a290000,0x6bea60d8,0x4a280000 + .long 0x6ba460d0,0x4a280000,0x6b00fbbc,0x60c64a28 + .long 0x00006b16,0x60be4a28,0x00006b0e,0xf23c4400 + .long 0x3f800000,0x422eff64,0x4e75f23c,0x4400bf80 + .long 0x00001d7c,0x0008ff64,0x4e753fff,0x0000c90f + .long 0xdaa22168,0xc235bfff,0x0000c90f,0xdaa22168 + .long 0xc2354a28,0x00006b0e,0xf2009000,0xf23a4800 + .long 0xffda6000,0xfcf0f200,0x9000f23a,0x4800ffd8 + .long 0x6000fcea,0xf23c4480,0x3f800000,0x4a280000 + .long 0x6a10f23c,0x44008000,0x00001d7c,0x000cff64 + .long 0x6040f23c,0x44000000,0x00001d7c,0x0004ff64 + .long 0x6030f23a,0x4880faea,0x61ff0000,0x00286000 + .long 0xfb16f228,0x48800000,0x61ff0000,0x00186000 + .long 0x030ef228,0x48800000,0x61ff0000,0x00086000 + .long 0x02ee102e,0xff430240,0x0007303b,0x02064efb + .long 0x00020010,0x00180020,0x0026002c,0x00320038 + .long 0x003ef22e,0xf040ffdc,0x4e75f22e,0xf040ffe8 + .long 0x4e75f200,0x05004e75,0xf2000580,0x4e75f200 + .long 0x06004e75,0xf2000680,0x4e75f200,0x07004e75 + .long 0xf2000780,0x4e75122e,0xff4f67ff,0xfffff7dc + .long 0x0c010001,0x67000096,0x0c010002,0x67ffffff + .long 0xfa880c01,0x000467ff,0xfffff7c0,0x0c010005 + .long 0x67ff0000,0x024060ff,0x0000024a,0x122eff4f + .long 0x67ffffff,0xfa640c01,0x000167ff,0xfffffa5a + .long 0x0c010002,0x67ffffff,0xfa500c01,0x000467ff + .long 0xfffffa46,0x0c010003,0x67ff0000,0x021860ff + .long 0x00000202,0x122eff4f,0x67ff0000,0x004e0c01 + .long 0x000167ff,0x00000028,0x0c010002,0x67ffffff + .long 0xfa180c01,0x000467ff,0x00000030,0x0c010003 + .long 0x67ff0000,0x01e060ff,0x000001ca,0x12280000 + .long 0x10290000,0xb1010201,0x00801d41,0xff654a00 + .long 0x6a00fdc4,0x6000fdd0,0x422eff65,0x2f001228 + .long 0x00001029,0x0000b101,0x02010080,0x1d41ff65 + .long 0x0c2e0004,0xff4f660c,0x41e90000,0x201f60ff + .long 0xfffff9c6,0xf21f9000,0xf2294800,0x00004a29 + .long 0x00006b02,0x4e751d7c,0x0008ff64,0x4e75122e + .long 0xff4f67ff,0xfffff6e0,0x0c010001,0x6700ff8e + .long 0x0c010002,0x67ffffff,0xf9800c01,0x000467ff + .long 0xfffff6c4,0x0c010003,0x67ff0000,0x014860ff + .long 0x00000132,0x122eff4f,0x67ffffff,0xf95c0c01 + .long 0x000167ff,0xfffff952,0x0c010002,0x67ffffff + .long 0xf9480c01,0x000467ff,0xfffff93e,0x0c010003 + .long 0x67ff0000,0x011060ff,0x000000fa,0x122eff4f + .long 0x6700ff46,0x0c010001,0x6700ff22,0x0c010002 + .long 0x67ffffff,0xf9140c01,0x000467ff,0xffffff2c + .long 0x0c010003,0x67ff0000,0x00dc60ff,0x000000c6 + .long 0x122eff4f,0x67ffffff,0xf51e0c01,0x000167ff + .long 0xfffffce6,0x0c010002,0x67ffffff,0xfd0a0c01 + .long 0x000467ff,0xfffff500,0x0c010003,0x67ff0000 + .long 0x00a460ff,0x0000008e,0x122eff4f,0x67ffffff + .long 0xf4e60c01,0x000167ff,0xfffffcae,0x0c010002 + .long 0x67ffffff,0xfcd20c01,0x000467ff,0xfffff4c8 + .long 0x0c010003,0x67ff0000,0x006c60ff,0x00000056 + .long 0x122eff4f,0x67ffffff,0xf8800c01,0x000367ff + .long 0x00000052,0x0c010005,0x67ff0000,0x003860ff + .long 0xfffff866,0x122eff4f,0x0c010003,0x67340c01 + .long 0x0005671e,0x6058122e,0xff4f0c01,0x00036708 + .long 0x0c010005,0x670c6036,0x00ae0100,0x4080ff64 + .long 0x6010f229,0x48000000,0xf200a800,0x81aeff64 + .long 0x4e75f229,0x48000000,0x4a290000,0x6b081d7c + .long 0x0001ff64,0x4e751d7c,0x0009ff64,0x4e75f228 + .long 0x48000000,0xf200a800,0x81aeff64,0x4e75f228 + .long 0x48000000,0x4a280000,0x6bdc1d7c,0x0001ff64 + .long 0x4e751d7c,0x0009ff64,0x4e75122e,0xff4e67ff + .long 0xffffd936,0x0c010001,0x67ffffff,0xfba60c01 + .long 0x000267ff,0xfffffbca,0x0c010004,0x67ffffff + .long 0xd9f60c01,0x000367ff,0xffffffb6,0x60ffffff + .long 0xffa0122e,0xff4e67ff,0xffffe620,0x0c010001 + .long 0x67ffffff,0xfb6e0c01,0x000267ff,0xfffffbc8 + .long 0x0c010004,0x67ffffff,0xe7560c01,0x000367ff + .long 0xffffff7e,0x60ffffff,0xff68122e,0xff4e67ff + .long 0xffffd4d2,0x0c010001,0x67ffffff,0xfb360c01 + .long 0x000267ff,0xfffffb9a,0x0c010004,0x67ffffff + .long 0xd76a0c01,0x000367ff,0xffffff46,0x60ffffff + .long 0xff30122e,0xff4e67ff,0xffffd972,0x0c010001 + .long 0x67ffffff,0xfafe0c01,0x000267ff,0xfffffb6a + .long 0x0c010004,0x67ffffff,0xdabc0c01,0x000367ff + .long 0xffffff0e,0x60ffffff,0xfef8122e,0xff4e67ff + .long 0xffffca6a,0x0c010001,0x67ffffff,0xfac60c01 + .long 0x000267ff,0xfffffb6e,0x0c010004,0x67ffffff + .long 0xcc8a0c01,0x000367ff,0xfffffed6,0x60ffffff + .long 0xfec0122e,0xff4e67ff,0xffffcc76,0x0c010001 + .long 0x67ffffff,0xfa8e0c01,0x000267ff,0xfffff6aa + .long 0x0c010004,0x67ffffff,0xcd060c01,0x000367ff + .long 0xfffffe9e,0x60ffffff,0xfe88122e,0xff4e67ff + .long 0xffffe662,0x0c010001,0x67ffffff,0xfa560c01 + .long 0x000267ff,0xfffff672,0x0c010004,0x67ffffff + .long 0xe6c60c01,0x000367ff,0xfffffe66,0x60ffffff + .long 0xfe50122e,0xff4e67ff,0xffffb372,0x0c010001 + .long 0x67ffffff,0xfa1e0c01,0x000267ff,0xfffff63a + .long 0x0c010004,0x67ffffff,0xb5380c01,0x000367ff + .long 0xfffffe2e,0x60ffffff,0xfe18122e,0xff4e67ff + .long 0xffffbdfc,0x0c010001,0x67ffffff,0xf9e60c01 + .long 0x000267ff,0xfffff602,0x0c010004,0x67ffffff + .long 0xbf420c01,0x000367ff,0xfffffdf6,0x60ffffff + .long 0xfde0122e,0xff4e67ff,0xffffd17a,0x0c010001 + .long 0x67ffffff,0xfa2a0c01,0x000267ff,0xfffffa00 + .long 0x0c010004,0x67ffffff,0xd3080c01,0x000367ff + .long 0xfffffdbe,0x60ffffff,0xfda8122e,0xff4e67ff + .long 0xffffeb64,0x0c010001,0x67ffffff,0xf9f20c01 + .long 0x000267ff,0xfffff9c8,0x0c010004,0x67ffffff + .long 0xec200c01,0x000367ff,0xfffffd86,0x60ffffff + .long 0xfd70122e,0xff4e67ff,0xffffec24,0x0c010001 + .long 0x67ffffff,0xf9ba0c01,0x000267ff,0xfffff990 + .long 0x0c010004,0x67ffffff,0xed360c01,0x000367ff + .long 0xfffffd4e,0x60ffffff,0xfd38122e,0xff4e67ff + .long 0xffffe178,0x0c010001,0x67ffffff,0xf51a0c01 + .long 0x000267ff,0xfffff960,0x0c010004,0x67ffffff + .long 0xe30c0c01,0x000367ff,0xfffffd16,0x60ffffff + .long 0xfd00122e,0xff4e67ff,0xffffe582,0x0c010001 + .long 0x67ffffff,0xf4e20c01,0x000267ff,0xfffff928 + .long 0x0c010004,0x67ffffff,0xe5940c01,0x000367ff + .long 0xfffffcde,0x60ffffff,0xfcc8122e,0xff4e67ff + .long 0xffffe59a,0x0c010001,0x67ffffff,0xf4aa0c01 + .long 0x000267ff,0xfffff8f0,0x0c010004,0x67ffffff + .long 0xe5d60c01,0x000367ff,0xfffffca6,0x60ffffff + .long 0xfc90122e,0xff4e67ff,0xffffd530,0x0c010001 + .long 0x67ffffff,0xf8da0c01,0x000267ff,0xfffff888 + .long 0x0c010004,0x67ffffff,0xd5b60c01,0x000367ff + .long 0xfffffc6e,0x60ffffff,0xfc58122e,0xff4e67ff + .long 0xffffcac2,0x0c010001,0x67ffffff,0xf8de0c01 + .long 0x000267ff,0xfffff442,0x0c010004,0x67ffffff + .long 0xcb340c01,0x000367ff,0xfffffc36,0x60ffffff + .long 0xfc20122e,0xff4e67ff,0xffffb14c,0x0c010001 + .long 0x67ffffff,0xf86a0c01,0x000267ff,0xfffff40a + .long 0x0c010004,0x67ffffff,0xb30e0c01,0x000367ff + .long 0xfffffbfe,0x60ffffff,0xfbe8122e,0xff4e67ff + .long 0xffffd40e,0x0c010001,0x67ffffff,0xf7b60c01 + .long 0x000267ff,0xfffff3d2,0x0c010004,0x67ffffff + .long 0xd40c0c01,0x000367ff,0xfffffbc6,0x60ffffff + .long 0xfbb0122e,0xff4e67ff,0xffffd40a,0x0c010001 + .long 0x67ffffff,0xf77e0c01,0x000267ff,0xfffff39a + .long 0x0c010004,0x67ffffff,0xd41a0c01,0x000367ff + .long 0xfffffb8e,0x60ffffff,0xfb78122e,0xff4e67ff + .long 0xffffb292,0x0c010001,0x67ffffff,0xf81a0c01 + .long 0x000267ff,0xfffff83e,0x0c010004,0x67ffffff + .long 0xb50a0c01,0x000367ff,0xfffff83a,0x60ffffff + .long 0xf844122e,0xff4e67ff,0xfffff89e,0x0c010001 + .long 0x67ffffff,0xf8ca0c01,0x000267ff,0xfffff8f8 + .long 0x0c010004,0x67ffffff,0xf8800c01,0x000367ff + .long 0xfffffab4,0x60ffffff,0xfac0122e,0xff4e67ff + .long 0xfffff96e,0x0c010001,0x67ffffff,0xf99a0c01 + .long 0x000267ff,0xfffff9c8,0x0c010004,0x67ffffff + .long 0xf9500c01,0x000367ff,0xfffffa7c,0x60ffffff + .long 0xfa88122e,0xff4e67ff,0xfffff9d8,0x0c010001 + .long 0x67ffffff,0xfa060c01,0x000267ff,0xfffffa34 + .long 0x0c010004,0x67ffffff,0xf9ba0c01,0x000367ff + .long 0xfffffa44,0x60ffffff,0xfa500c2f,0x00070003 + .long 0x673e1d7c,0x0000ff4e,0x1d7c0000,0xff4ff22e + .long 0xf080ff78,0x41ef0004,0x43eeff78,0x0c010003 + .long 0x67160c01,0x00026708,0x61ff0000,0x02004e75 + .long 0x61ff0000,0x1b9e4e75,0x61ff0000,0x05e44e75 + .long 0x1d7c0004,0xff4e60c0,0x4afc006d,0x000005d2 + .long 0x00000fc8,0xfffffa6e,0x0000106c,0x00002314 + .long 0x00000000,0xfffffaa6,0x00000000,0xfffffade + .long 0xfffffb16,0xfffffb4e,0x00000000,0xfffffb86 + .long 0xfffffbbe,0xfffffbf6,0xfffffc2e,0xfffffc66 + .long 0xfffffc9e,0xfffffcd6,0x00000000,0xfffffd0e + .long 0xfffffd46,0xfffffd7e,0x00000000,0x00001112 + .long 0xfffffdb6,0x00000ca8,0x00000000,0xfffffdee + .long 0xfffffe26,0xfffffe5e,0xfffffe96,0x0000089e + .long 0xffffff06,0x00001b84,0x000001de,0x00001854 + .long 0xffffff3e,0xffffff76,0x00001512,0x00001f4c + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0xfffffece + .long 0xfffffece,0xfffffece,0xfffffece,0xfffffece + .long 0xfffffece,0xfffffece,0xfffffece,0x000013b0 + .long 0x00000000,0x00000f56,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x000005c0 + .long 0x00002302,0x00000000,0x00000000,0x000005ca + .long 0x0000230c,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00001100 + .long 0x00000000,0x00000c96,0x00000000,0x0000110a + .long 0x00000000,0x00000ca0,0x00000000,0x0000088c + .long 0x00000000,0x00001b72,0x000001cc,0x00000896 + .long 0x00000000,0x00001b7c,0x000001d6,0x00001f3a + .long 0x00000000,0x00000000,0x00000000,0x00001f44 + .long 0xffffc001,0xffffff81,0xfffffc01,0x00004000 + .long 0x0000007f,0x000003ff,0x02000030,0x00000040 + .long 0x60080200,0x00300000,0x00802d40,0xff5c4241 + .long 0x122eff4f,0xe709822e,0xff4e6600,0x02e43d69 + .long 0x0000ff90,0x2d690004,0xff942d69,0x0008ff98 + .long 0x3d680000,0xff842d68,0x0004ff88,0x2d680008 + .long 0xff8c61ff,0x000024ce,0x2f0061ff,0x00002572 + .long 0xd197322e,0xff5eec09,0x201fb0bb,0x14846700 + .long 0x011e6d00,0x0062b0bb,0x14846700,0x021a6e00 + .long 0x014af22e,0xd080ff90,0xf22e9000,0xff5cf23c + .long 0x88000000,0x0000f22e,0x4823ff84,0xf201a800 + .long 0xf23c9000,0x00000000,0x83aeff64,0xf22ef080 + .long 0xff842f02,0x322eff84,0x24010281,0x00007fff + .long 0x02428000,0x92808242,0x3d41ff84,0x241ff22e + .long 0xd080ff84,0x4e75f22e,0xd080ff90,0xf22e9000 + .long 0xff5cf23c,0x88000000,0x0000f22e,0x4823ff84 + .long 0xf201a800,0xf23c9000,0x00000000,0x83aeff64 + .long 0x00ae0000,0x1048ff64,0x122eff62,0x02010013 + .long 0x661c082e,0x0003ff64,0x56c1202e,0xff5c61ff + .long 0x00004fcc,0x812eff64,0xf210d080,0x4e75222e + .long 0xff5c0201,0x00c06634,0xf22ef080,0xff842f02 + .long 0x322eff84,0x34010281,0x00007fff,0x92800481 + .long 0x00006000,0x02417fff,0x02428000,0x82423d41 + .long 0xff84241f,0xf22ed040,0xff8460a6,0xf22ed080 + .long 0xff90222e,0xff5c0201,0x0030f201,0x9000f22e + .long 0x4823ff84,0xf23c9000,0x00000000,0x60aaf22e + .long 0xd080ff90,0xf22e9000,0xff5cf23c,0x88000000 + .long 0x0000f22e,0x4823ff84,0xf201a800,0xf23c9000 + .long 0x00000000,0x83aeff64,0xf2000098,0xf23c58b8 + .long 0x0002f293,0xff3c6000,0xfee408ee,0x0003ff66 + .long 0xf22ed080,0xff90f23c,0x90000000,0x0010f23c + .long 0x88000000,0x0000f22e,0x4823ff84,0xf201a800 + .long 0xf23c9000,0x00000000,0x83aeff64,0x122eff62 + .long 0x0201000b,0x6620f22e,0xf080ff84,0x41eeff84 + .long 0x222eff5c,0x61ff0000,0x4dd8812e,0xff64f22e + .long 0xd080ff84,0x4e75f22e,0xd040ff90,0x222eff5c + .long 0x020100c0,0x6652f22e,0x9000ff5c,0xf23c8800 + .long 0x00000000,0xf22e48a3,0xff84f23c,0x90000000 + .long 0x0000f22e,0xf040ff84,0x2f02322e,0xff842401 + .long 0x02810000,0x7fff0242,0x80009280,0x06810000 + .long 0x60000241,0x7fff8242,0x3d41ff84,0x241ff22e + .long 0xd040ff84,0x6000ff80,0x222eff5c,0x02010030 + .long 0xf2019000,0x60a6f22e,0xd080ff90,0xf22e9000 + .long 0xff5cf23c,0x88000000,0x0000f22e,0x4823ff84 + .long 0xf201a800,0xf23c9000,0x00000000,0x83aeff64 + .long 0xf2000098,0xf23c58b8,0x0002f292,0xfde0f294 + .long 0xfefaf22e,0xd040ff90,0x222eff5c,0x020100c0 + .long 0x00010010,0xf2019000,0xf23c8800,0x00000000 + .long 0xf22e48a3,0xff84f23c,0x90000000,0x0000f200 + .long 0x0498f23c,0x58b80002,0xf293fda2,0x6000febc + .long 0x323b120a,0x4efb1006,0x4afc0030,0xfd120072 + .long 0x00cc006c,0xfd120066,0x00000000,0x00720072 + .long 0x0060006c,0x00720066,0x00000000,0x009e0060 + .long 0x009e006c,0x009e0066,0x00000000,0x006c006c + .long 0x006c006c,0x006c0066,0x00000000,0xfd120072 + .long 0x00cc006c,0xfd120066,0x00000000,0x00660066 + .long 0x00660066,0x00660066,0x00000000,0x60ff0000 + .long 0x230e60ff,0x00002284,0x60ff0000,0x227e1028 + .long 0x00001229,0x0000b101,0x6a10f23c,0x44008000 + .long 0x00001d7c,0x000cff64,0x4e75f23c,0x44000000 + .long 0x00001d7c,0x0004ff64,0x4e75f229,0xd0800000 + .long 0x10280000,0x12290000,0xb1016a10,0xf2000018 + .long 0xf200001a,0x1d7c000a,0xff644e75,0xf2000018 + .long 0x1d7c0002,0xff644e75,0xf228d080,0x00001028 + .long 0x00001229,0x0000b101,0x6ae260d0,0x02000030 + .long 0x00000040,0x60080200,0x00300000,0x00802d40 + .long 0xff5c122e,0xff4e6600,0x02620200,0x00c06600 + .long 0x007c4a28,0x00006a06,0x08ee0003,0xff64f228 + .long 0xd0800000,0x4e750200,0x00c06600,0x006008ee + .long 0x0003ff66,0x4a280000,0x6a0608ee,0x0003ff64 + .long 0xf228d080,0x0000082e,0x0003ff62,0x66024e75 + .long 0x3d680000,0xff842d68,0x0004ff88,0x2d680008 + .long 0xff8c41ee,0xff8461ff,0x00004950,0x44400640 + .long 0x6000322e,0xff840241,0x80000240,0x7fff8041 + .long 0x3d40ff84,0xf22ed040,0xff844e75,0x0c000040 + .long 0x667e3d68,0x0000ff84,0x2d680004,0xff882d68 + .long 0x0008ff8c,0x61ff0000,0x206c0c80,0x0000007f + .long 0x6c000092,0x0c80ffff,0xff816700,0x01786d00 + .long 0x00f4f23c,0x88000000,0x0000f22e,0x9000ff5c + .long 0xf22e4800,0xff84f201,0xa800f23c,0x90000000 + .long 0x000083ae,0xff642f02,0xf22ef080,0xff84322e + .long 0xff843401,0x02810000,0x7fff9280,0x02428000 + .long 0x84413d42,0xff84241f,0xf22ed080,0xff844e75 + .long 0x3d680000,0xff842d68,0x0004ff88,0x2d680008 + .long 0xff8c61ff,0x00001fee,0x0c800000,0x03ff6c00 + .long 0x00140c80,0xfffffc01,0x670000fa,0x6d000076 + .long 0x6000ff80,0x08ee0003,0xff664a2e,0xff846a06 + .long 0x08ee0003,0xff64122e,0xff620201,0x000b661a + .long 0x41eeff84,0x222eff5c,0x61ff0000,0x4a74812e + .long 0xff64f22e,0xd080ff84,0x4e752d6e,0xff88ff94 + .long 0x2d6eff8c,0xff98322e,0xff842f02,0x34010281 + .long 0x00007fff,0x92800242,0x80000681,0x00006000 + .long 0x02417fff,0x84413d42,0xff90f22e,0xd040ff90 + .long 0x241f60ac,0xf23c8800,0x00000000,0xf22e9000 + .long 0xff5cf22e,0x4800ff84,0xf23c9000,0x00000000 + .long 0xf201a800,0x83aeff64,0x00ae0000,0x1048ff64 + .long 0x122eff62,0x02010013,0x661c082e,0x0003ff64 + .long 0x56c1202e,0xff5c61ff,0x00004ae4,0x812eff64 + .long 0xf210d080,0x4e752f02,0x322eff84,0x24010281 + .long 0x00007fff,0x02428000,0x92800481,0x00006000 + .long 0x02417fff,0x82423d41,0xff84241f,0xf22ed040 + .long 0xff8460b6,0xf23c8800,0x00000000,0xf22e9000 + .long 0xff5cf22e,0x4800ff84,0xf201a800,0xf23c9000 + .long 0x00000000,0x83aeff64,0xf2000098,0xf23c58b8 + .long 0x0002f293,0xff746000,0xfe7e0c01,0x00046700 + .long 0xfdb60c01,0x000567ff,0x00001f98,0x0c010003 + .long 0x67ff0000,0x1fa2f228,0x48000000,0xf200a800 + .long 0xe1981d40,0xff644e75,0x51fc51fc,0x51fc51fc + .long 0x00003fff,0x0000007e,0x000003fe,0xffffc001 + .long 0xffffff81,0xfffffc01,0x02000030,0x00000040 + .long 0x60080200,0x00300000,0x00802d40,0xff5c4241 + .long 0x122eff4f,0xe709822e,0xff4e6600,0x02d63d69 + .long 0x0000ff90,0x2d690004,0xff942d69,0x0008ff98 + .long 0x3d680000,0xff842d68,0x0004ff88,0x2d680008 + .long 0xff8c61ff,0x00001e0e,0x2f0061ff,0x00001eb2 + .long 0x4497d197,0x322eff5e,0xec09201f,0xb0bb148e + .long 0x6f000074,0xb0bb1520,0xff7a6700,0x020c6e00 + .long 0x013cf22e,0xd080ff90,0xf22e9000,0xff5cf23c + .long 0x88000000,0x0000f22e,0x4820ff84,0xf201a800 + .long 0xf23c9000,0x00000000,0x83aeff64,0xf22ef080 + .long 0xff842f02,0x322eff84,0x24010281,0x00007fff + .long 0x02428000,0x92808242,0x3d41ff84,0x241ff22e + .long 0xd080ff84,0x4e750000,0x7fff0000,0x407f0000 + .long 0x43ff201f,0x60c62f00,0xf22ed080,0xff90f22e + .long 0x9000ff5c,0xf23c8800,0x00000000,0xf22e4820 + .long 0xff84f200,0xa800f23c,0x90000000,0x000081ae + .long 0xff64f227,0xe0013017,0xdffc0000,0x000c0280 + .long 0x00007fff,0x9097b0bb,0x14ae6db6,0x201f00ae + .long 0x00001048,0xff64122e,0xff620201,0x0013661c + .long 0x082e0003,0xff6456c1,0x202eff5c,0x61ff0000 + .long 0x48de812e,0xff64f210,0xd0804e75,0x222eff5c + .long 0x020100c0,0x6634f22e,0xf080ff84,0x2f02322e + .long 0xff843401,0x02810000,0x7fff9280,0x04810000 + .long 0x60000241,0x7fff0242,0x80008242,0x3d41ff84 + .long 0x241ff22e,0xd040ff84,0x60a6f22e,0xd080ff90 + .long 0x222eff5c,0x02010030,0xf2019000,0xf22e4820 + .long 0xff84f23c,0x90000000,0x000060aa,0x08ee0003 + .long 0xff66f22e,0xd080ff90,0xf23c9000,0x00000010 + .long 0xf23c8800,0x00000000,0xf22e4820,0xff84f201 + .long 0xa800f23c,0x90000000,0x000083ae,0xff64122e + .long 0xff620201,0x000b6620,0xf22ef080,0xff8441ee + .long 0xff84222e,0xff5c61ff,0x00004726,0x812eff64 + .long 0xf22ed080,0xff844e75,0xf22ed040,0xff90222e + .long 0xff5c0201,0x00c06652,0xf22e9000,0xff5cf23c + .long 0x88000000,0x0000f22e,0x48a0ff84,0xf23c9000 + .long 0x00000000,0xf22ef040,0xff842f02,0x322eff84 + .long 0x24010281,0x00007fff,0x02428000,0x92800681 + .long 0x00006000,0x02417fff,0x82423d41,0xff84241f + .long 0xf22ed040,0xff846000,0xff80222e,0xff5c0201 + .long 0x0030f201,0x900060a6,0xf22ed080,0xff90f22e + .long 0x9000ff5c,0xf23c8800,0x00000000,0xf22e4820 + .long 0xff84f201,0xa800f23c,0x90000000,0x000083ae + .long 0xff64f200,0x0098f23c,0x58b80001,0xf292fdee + .long 0xf294fefa,0xf22ed040,0xff90222e,0xff5c0201 + .long 0x00c00001,0x0010f201,0x9000f23c,0x88000000 + .long 0x0000f22e,0x48a0ff84,0xf23c9000,0x00000000 + .long 0xf2000498,0xf23c58b8,0x0001f293,0xfdb06000 + .long 0xfebc323b,0x120a4efb,0x10064afc,0x0030fd20 + .long 0x009e0072,0x0060fd20,0x00660000,0x00000072 + .long 0x006c0072,0x00600072,0x00660000,0x000000d0 + .long 0x00d0006c,0x006000d0,0x00660000,0x00000060 + .long 0x00600060,0x00600060,0x00660000,0x0000fd20 + .long 0x009e0072,0x0060fd20,0x00660000,0x00000066 + .long 0x00660066,0x00660066,0x00660000,0x000060ff + .long 0x00001bd8,0x60ff0000,0x1bd260ff,0x00001c50 + .long 0x10280000,0x12290000,0xb1016a10,0xf23c4400 + .long 0x80000000,0x1d7c000c,0xff644e75,0xf23c4400 + .long 0x00000000,0x1d7c0004,0xff644e75,0x006e0410 + .long 0xff661028,0x00001229,0x0000b101,0x6a10f23c + .long 0x4400ff80,0x00001d7c,0x000aff64,0x4e75f23c + .long 0x44007f80,0x00001d7c,0x0002ff64,0x4e751029 + .long 0x00001228,0x0000b101,0x6a16f229,0xd0800000 + .long 0xf2000018,0xf200001a,0x1d7c000a,0xff644e75 + .long 0xf229d080,0x0000f200,0x00181d7c,0x0002ff64 + .long 0x4e750200,0x00300000,0x00406008,0x02000030 + .long 0x00000080,0x2d40ff5c,0x122eff4e,0x66000276 + .long 0x020000c0,0x66000090,0x2d680004,0xff882d68 + .long 0x0008ff8c,0x30280000,0x0a408000,0x6a061d7c + .long 0x0008ff64,0x3d40ff84,0xf22ed080,0xff844e75 + .long 0x020000c0,0x666008ee,0x0003ff66,0x2d680004 + .long 0xff882d68,0x0008ff8c,0x30280000,0x0a408000 + .long 0x6a061d7c,0x0008ff64,0x3d40ff84,0xf22ed080 + .long 0xff84082e,0x0003ff62,0x66024e75,0x41eeff84 + .long 0x61ff0000,0x42664440,0x06406000,0x322eff84 + .long 0x02418000,0x02407fff,0x80413d40,0xff84f22e + .long 0xd040ff84,0x4e750c00,0x0040667e,0x3d680000 + .long 0xff842d68,0x0004ff88,0x2d680008,0xff8c61ff + .long 0x00001982,0x0c800000,0x007f6c00,0x00900c80 + .long 0xffffff81,0x67000178,0x6d0000f4,0xf23c8800 + .long 0x00000000,0xf22e9000,0xff5cf22e,0x481aff84 + .long 0xf201a800,0xf23c9000,0x00000000,0x83aeff64 + .long 0x2f02f22e,0xf080ff84,0x322eff84,0x34010281 + .long 0x00007fff,0x92800242,0x80008441,0x3d42ff84 + .long 0x241ff22e,0xd080ff84,0x4e753d68,0x0000ff84 + .long 0x2d680004,0xff882d68,0x0008ff8c,0x61ff0000 + .long 0x19040c80,0x000003ff,0x6c120c80,0xfffffc01 + .long 0x670000fc,0x6d000078,0x6000ff82,0x08ee0003 + .long 0xff660a2e,0x0080ff84,0x6a0608ee,0x0003ff64 + .long 0x122eff62,0x0201000b,0x661a41ee,0xff84222e + .long 0xff5c61ff,0x0000438a,0x812eff64,0xf22ed080 + .long 0xff844e75,0x2d6eff88,0xff942d6e,0xff8cff98 + .long 0x322eff84,0x2f022401,0x02810000,0x7fff0242 + .long 0x80009280,0x06810000,0x60000241,0x7fff8242 + .long 0x3d41ff90,0xf22ed040,0xff90241f,0x60acf23c + .long 0x88000000,0x0000f22e,0x9000ff5c,0xf22e481a + .long 0xff84f23c,0x90000000,0x0000f201,0xa80083ae + .long 0xff6400ae,0x00001048,0xff64122e,0xff620201 + .long 0x0013661c,0x082e0003,0xff6456c1,0x202eff5c + .long 0x61ff0000,0x43fa812e,0xff64f210,0xd0804e75 + .long 0x2f02322e,0xff842401,0x02810000,0x7fff0242 + .long 0x80009280,0x04810000,0x60000241,0x7fff8242 + .long 0x3d41ff84,0xf22ed040,0xff84241f,0x60b6f23c + .long 0x88000000,0x0000f22e,0x9000ff5c,0xf22e481a + .long 0xff84f201,0xa800f23c,0x90000000,0x000083ae + .long 0xff64f200,0x0098f23c,0x58b80002,0xf293ff74 + .long 0x6000fe7e,0x0c010004,0x6700fdb6,0x0c010005 + .long 0x67ff0000,0x18ae0c01,0x000367ff,0x000018b8 + .long 0xf228481a,0x0000f200,0xa800e198,0x1d40ff64 + .long 0x4e75122e,0xff4e6610,0x4a280000,0x6b024e75 + .long 0x1d7c0008,0xff644e75,0x0c010001,0x67400c01 + .long 0x00026724,0x0c010005,0x67ff0000,0x18660c01 + .long 0x000367ff,0x00001870,0x4a280000,0x6b024e75 + .long 0x1d7c0008,0xff644e75,0x4a280000,0x6b081d7c + .long 0x0002ff64,0x4e751d7c,0x000aff64,0x4e754a28 + .long 0x00006b08,0x1d7c0004,0xff644e75,0x1d7c000c + .long 0xff644e75,0x122eff4e,0x66280200,0x0030f200 + .long 0x9000f23c,0x88000000,0x0000f228,0x48010000 + .long 0xf23c9000,0x00000000,0xf200a800,0x81aeff64 + .long 0x4e750c01,0x0001672e,0x0c010002,0x674e0c01 + .long 0x00046710,0x0c010005,0x67ff0000,0x17d660ff + .long 0x000017e4,0x3d680000,0xff841d7c,0x0080ff88 + .long 0x41eeff84,0x60a44a28,0x00006b10,0xf23c4400 + .long 0x00000000,0x1d7c0004,0xff644e75,0xf23c4400 + .long 0x80000000,0x1d7c000c,0xff644e75,0xf228d080 + .long 0x00004a28,0x00006b08,0x1d7c0002,0xff644e75 + .long 0x1d7c000a,0xff644e75,0x122eff4e,0x6618f23c + .long 0x88000000,0x0000f228,0x48030000,0xf200a800 + .long 0x81aeff64,0x4e750c01,0x0001672e,0x0c010002 + .long 0x674e0c01,0x00046710,0x0c010005,0x67ff0000 + .long 0x174260ff,0x00001750,0x3d680000,0xff841d7c + .long 0x0080ff88,0x41eeff84,0x60b44a28,0x00006b10 + .long 0xf23c4400,0x00000000,0x1d7c0004,0xff644e75 + .long 0xf23c4400,0x80000000,0x1d7c000c,0xff644e75 + .long 0xf228d080,0x00004a28,0x00006b08,0x1d7c0002 + .long 0xff644e75,0x1d7c000a,0xff644e75,0x02000030 + .long 0x00000040,0x60080200,0x00300000,0x00802d40 + .long 0xff5c122e,0xff4e6600,0x025c0200,0x00c0667e + .long 0x2d680004,0xff882d68,0x0008ff8c,0x32280000 + .long 0x0881000f,0x3d41ff84,0xf22ed080,0xff844e75 + .long 0x020000c0,0x665808ee,0x0003ff66,0x2d680004 + .long 0xff882d68,0x0008ff8c,0x30280000,0x0880000f + .long 0x3d40ff84,0xf22ed080,0xff84082e,0x0003ff62 + .long 0x66024e75,0x41eeff84,0x61ff0000,0x3e0e4440 + .long 0x06406000,0x322eff84,0x02418000,0x02407fff + .long 0x80413d40,0xff84f22e,0xd040ff84,0x4e750c00 + .long 0x0040667e,0x3d680000,0xff842d68,0x0004ff88 + .long 0x2d680008,0xff8c61ff,0x0000152a,0x0c800000 + .long 0x007f6c00,0x00900c80,0xffffff81,0x67000170 + .long 0x6d0000ec,0xf23c8800,0x00000000,0xf22e9000 + .long 0xff5cf22e,0x4818ff84,0xf201a800,0xf23c9000 + .long 0x00000000,0x83aeff64,0x2f02f22e,0xf080ff84 + .long 0x322eff84,0x24010281,0x00007fff,0x92800242 + .long 0x80008441,0x3d42ff84,0x241ff22e,0xd080ff84 + .long 0x4e753d68,0x0000ff84,0x2d680004,0xff882d68 + .long 0x0008ff8c,0x61ff0000,0x14ac0c80,0x000003ff + .long 0x6c120c80,0xfffffc01,0x670000f4,0x6d000070 + .long 0x6000ff82,0x08ee0003,0xff6608ae,0x0007ff84 + .long 0x122eff62,0x0201000b,0x661a41ee,0xff84222e + .long 0xff5c61ff,0x00003f3a,0x812eff64,0xf22ed080 + .long 0xff844e75,0x2d6eff88,0xff942d6e,0xff8cff98 + .long 0x322eff84,0x2f022401,0x02810000,0x7fff0242 + .long 0x80009280,0x06810000,0x60000241,0x7fff8242 + .long 0x3d41ff90,0xf22ed040,0xff90241f,0x60acf23c + .long 0x88000000,0x0000f22e,0x9000ff5c,0xf22e4818 + .long 0xff84f23c,0x90000000,0x0000f201,0xa80083ae + .long 0xff6400ae,0x00001048,0xff64122e,0xff620201 + .long 0x0013661c,0x082e0003,0xff6456c1,0x202eff5c + .long 0x61ff0000,0x3faa812e,0xff64f210,0xd0804e75 + .long 0x2f02322e,0xff842401,0x02810000,0x7fff0242 + .long 0x80009280,0x04810000,0x60000241,0x7fff8242 + .long 0x3d41ff84,0xf22ed040,0xff84241f,0x60b6f23c + .long 0x88000000,0x0000f22e,0x9000ff5c,0xf22e4818 + .long 0xff84f201,0xa800f23c,0x90000000,0x000083ae + .long 0xff64f200,0x0098f23c,0x58b80002,0xf293ff74 + .long 0x6000fe86,0x0c010004,0x6700fdc6,0x0c010005 + .long 0x67ff0000,0x145e0c01,0x000367ff,0x00001468 + .long 0xf2284818,0x00000c01,0x00026708,0x1d7c0004 + .long 0xff644e75,0x1d7c0002,0xff644e75,0x4241122e + .long 0xff4fe709,0x822eff4e,0x6618f229,0xd0800000 + .long 0xf2284838,0x0000f200,0xa800e198,0x1d40ff64 + .long 0x4e75323b,0x120a4efb,0x10064afc,0x0030ffdc + .long 0xffdcffdc,0x006000f8,0x006e0000,0x0000ffdc + .long 0xffdcffdc,0x0060007c,0x006e0000,0x0000ffdc + .long 0xffdcffdc,0x0060007c,0x006e0000,0x00000060 + .long 0x00600060,0x00600060,0x006e0000,0x00000114 + .long 0x009c009c,0x006000bc,0x006e0000,0x0000006e + .long 0x006e006e,0x006e006e,0x006e0000,0x000061ff + .long 0x00001388,0x022e00f7,0xff644e75,0x61ff0000 + .long 0x137a022e,0x00f7ff64,0x4e753d68,0x0000ff84 + .long 0x20280004,0x08c0001f,0x2d40ff88,0x2d680008 + .long 0xff8c41ee,0xff846000,0xff422d69,0x0000ff84 + .long 0x20290004,0x08c0001f,0x2d40ff88,0x2d690008 + .long 0xff8c43ee,0xff846000,0xff223d69,0x0000ff90 + .long 0x3d680000,0xff842029,0x000408c0,0x001f2d40 + .long 0xff942028,0x000408c0,0x001f2d40,0xff882d69 + .long 0x0008ff98,0x2d680008,0xff8c43ee,0xff9041ee + .long 0xff846000,0xfee61028,0x00001229,0x0000b101 + .long 0x6b00ff78,0x4a006b02,0x4e751d7c,0x0008ff64 + .long 0x4e751028,0x00001229,0x0000b101,0x6b00ff7c + .long 0x4a006a02,0x4e751d7c,0x0008ff64,0x4e752d40 + .long 0xff5c4241,0x122eff4f,0xe709822e,0xff4e6600 + .long 0x02a03d69,0x0000ff90,0x2d690004,0xff942d69 + .long 0x0008ff98,0x3d680000,0xff842d68,0x0004ff88 + .long 0x2d680008,0xff8c61ff,0x0000119a,0x2f0061ff + .long 0x0000123e,0xd09f0c80,0xffffc001,0x670000f8 + .long 0x6d000064,0x0c800000,0x40006700,0x01da6e00 + .long 0x0122f22e,0xd080ff90,0xf22e9000,0xff5cf23c + .long 0x88000000,0x0000f22e,0x4827ff84,0xf201a800 + .long 0xf23c9000,0x00000000,0x83aeff64,0xf22ef080 + .long 0xff842f02,0x322eff84,0x24010281,0x00007fff + .long 0x02428000,0x92808242,0x3d41ff84,0x241ff22e + .long 0xd080ff84,0x4e75f22e,0xd080ff90,0xf22e9000 + .long 0xff5cf23c,0x88000000,0x0000f22e,0x4827ff84 + .long 0xf201a800,0xf23c9000,0x00000000,0x83aeff64 + .long 0x00ae0000,0x1048ff64,0x122eff62,0x02010013 + .long 0x6620082e,0x0003ff64,0x56c1202e,0xff5c0200 + .long 0x003061ff,0x00003c98,0x812eff64,0xf210d080 + .long 0x4e75f22e,0xf080ff84,0x2f02322e,0xff842401 + .long 0x02810000,0x7fff9280,0x04810000,0x60000241 + .long 0x7fff0242,0x80008242,0x3d41ff84,0x241ff22e + .long 0xd040ff84,0x60acf22e,0xd080ff90,0xf22e9000 + .long 0xff5cf23c,0x88000000,0x0000f22e,0x4827ff84 + .long 0xf201a800,0xf23c9000,0x00000000,0x83aeff64 + .long 0xf2000098,0xf23c58b8,0x0002f293,0xff646000 + .long 0xff0c08ee,0x0003ff66,0xf22ed080,0xff90f23c + .long 0x90000000,0x0010f23c,0x88000000,0x0000f22e + .long 0x4827ff84,0xf201a800,0xf23c9000,0x00000000 + .long 0x83aeff64,0x122eff62,0x0201000b,0x6620f22e + .long 0xf080ff84,0x41eeff84,0x222eff5c,0x61ff0000 + .long 0x3b56812e,0xff64f22e,0xd080ff84,0x4e75f22e + .long 0xd040ff90,0xf22e9000,0xff5cf23c,0x88000000 + .long 0x0000f22e,0x48a7ff84,0xf23c9000,0x00000000 + .long 0xf22ef040,0xff842f02,0x322eff84,0x24010281 + .long 0x00007fff,0x02428000,0x92800681,0x00006000 + .long 0x02417fff,0x82423d41,0xff84241f,0xf22ed040 + .long 0xff846000,0xff8af22e,0xd080ff90,0xf22e9000 + .long 0xff5cf23c,0x88000000,0x0000f22e,0x4827ff84 + .long 0xf201a800,0xf23c9000,0x00000000,0x83aeff64 + .long 0xf2000098,0xf23c58b8,0x0002f292,0xfe20f294 + .long 0xff12f22e,0xd040ff90,0x222eff5c,0x020100c0 + .long 0x00010010,0xf2019000,0xf23c8800,0x00000000 + .long 0xf22e48a7,0xff84f23c,0x90000000,0x0000f200 + .long 0x0498f23c,0x58b80002,0xf293fde2,0x6000fed4 + .long 0x323b120a,0x4efb1006,0x4afc0030,0xfd560072 + .long 0x0078006c,0xfd560066,0x00000000,0x00720072 + .long 0x0060006c,0x00720066,0x00000000,0x007e0060 + .long 0x007e006c,0x007e0066,0x00000000,0x006c006c + .long 0x006c006c,0x006c0066,0x00000000,0xfd560072 + .long 0x0078006c,0xfd560066,0x00000000,0x00660066 + .long 0x00660066,0x00660066,0x00000000,0x60ff0000 + .long 0x101e60ff,0x00000f94,0x60ff0000,0x0f8e60ff + .long 0xffffed0e,0x60ffffff,0xed6260ff,0xffffed2e + .long 0x2d40ff5c,0x4241122e,0xff4fe709,0x822eff4e + .long 0x6600027c,0x3d690000,0xff902d69,0x0004ff94 + .long 0x2d690008,0xff983d68,0x0000ff84,0x2d680004 + .long 0xff882d68,0x0008ff8c,0x61ff0000,0x0e582f00 + .long 0x61ff0000,0x0efc4497,0xd197322e,0xff5eec09 + .long 0x201f0c80,0xffffc001,0x6f000064,0x0c800000 + .long 0x3fff6700,0x01b66e00,0x0100f22e,0xd080ff90 + .long 0xf22e9000,0xff5cf23c,0x88000000,0x0000f22e + .long 0x4824ff84,0xf201a800,0xf23c9000,0x00000000 + .long 0x83aeff64,0xf22ef080,0xff842f02,0x322eff84 + .long 0x24010281,0x00007fff,0x02428000,0x92808242 + .long 0x3d41ff84,0x241ff22e,0xd080ff84,0x4e75f22e + .long 0xd080ff90,0xf22e9000,0xff5cf23c,0x88000000 + .long 0x0000f22e,0x4824ff84,0xf201a800,0xf23c9000 + .long 0x00000000,0x83aeff64,0xf227e001,0x3217dffc + .long 0x0000000c,0x02810000,0x7fff9280,0x0c810000 + .long 0x7fff6d90,0x006e1048,0xff66122e,0xff620201 + .long 0x00136620,0x082e0003,0xff6456c1,0x202eff5c + .long 0x02000030,0x61ff0000,0x3936812e,0xff64f210 + .long 0xd0804e75,0xf22ef080,0xff842f02,0x322eff84 + .long 0x24010281,0x00007fff,0x02428000,0x92800481 + .long 0x00006000,0x02417fff,0x82423d41,0xff84241f + .long 0xf22ed040,0xff8460ac,0x08ee0003,0xff66f22e + .long 0xd080ff90,0xf23c9000,0x00000010,0xf23c8800 + .long 0x00000000,0xf22e4824,0xff84f201,0xa800f23c + .long 0x90000000,0x000083ae,0xff64122e,0xff620201 + .long 0x000b6620,0xf22ef080,0xff8441ee,0xff84222e + .long 0xff5c61ff,0x00003830,0x812eff64,0xf22ed080 + .long 0xff844e75,0xf22ed040,0xff90f22e,0x9000ff5c + .long 0xf23c8800,0x00000000,0xf22e48a4,0xff84f23c + .long 0x90000000,0x0000f22e,0xf040ff84,0x2f02322e + .long 0xff842401,0x02810000,0x7fff0242,0x80009280 + .long 0x06810000,0x60000241,0x7fff8242,0x3d41ff84 + .long 0x241ff22e,0xd040ff84,0x608af22e,0xd080ff90 + .long 0xf22e9000,0xff5cf23c,0x88000000,0x0000f22e + .long 0x4824ff84,0xf201a800,0xf23c9000,0x00000000 + .long 0x83aeff64,0xf2000098,0xf23c58b8,0x0001f292 + .long 0xfe44f294,0xff14f22e,0xd040ff90,0x42810001 + .long 0x0010f201,0x9000f23c,0x88000000,0x0000f22e + .long 0x48a4ff84,0xf23c9000,0x00000000,0xf2000498 + .long 0xf23c58b8,0x0001f293,0xfe0c6000,0xfedc323b + .long 0x120a4efb,0x10064afc,0x0030fd7a,0x00720078 + .long 0x0060fd7a,0x00660000,0x00000078,0x006c0078 + .long 0x00600078,0x00660000,0x0000007e,0x007e006c + .long 0x0060007e,0x00660000,0x00000060,0x00600060 + .long 0x00600060,0x00660000,0x0000fd7a,0x00720078 + .long 0x0060fd7a,0x00660000,0x00000066,0x00660066 + .long 0x00660066,0x00660000,0x000060ff,0x00000c7c + .long 0x60ff0000,0x0c7660ff,0x00000cf4,0x60ffffff + .long 0xf0ce60ff,0xfffff09c,0x60ffffff,0xf0f40200 + .long 0x00300000,0x00406008,0x02000030,0x00000080 + .long 0x2d40ff5c,0x4241122e,0xff4fe709,0x822eff4e + .long 0x6600024c,0x61ff0000,0x0a5cf22e,0xd080ff90 + .long 0xf23c8800,0x00000000,0xf22e9000,0xff5cf22e + .long 0x4822ff84,0xf23c9000,0x00000000,0xf201a800 + .long 0x83aeff64,0xf281003c,0x2f02f227,0xe001322e + .long 0xff5eec09,0x34170282,0x00007fff,0x9480b4bb + .long 0x14246c38,0xb4bb142a,0x6d0000b8,0x67000184 + .long 0x32170241,0x80008242,0x3e81f21f,0xd080241f + .long 0x4e754e75,0x00007fff,0x0000407f,0x000043ff + .long 0x00000000,0x00003f81,0x00003c01,0x00ae0000 + .long 0x1048ff64,0x122eff62,0x02010013,0x6624dffc + .long 0x0000000c,0x082e0003,0xff6456c1,0x202eff5c + .long 0x61ff0000,0x366a812e,0xff64f210,0xd080241f + .long 0x4e75122e,0xff5c0201,0x00c0661a,0x32170241 + .long 0x80000482,0x00006000,0x02427fff,0x82423e81 + .long 0xf21fd040,0x60bef22e,0xd080ff90,0x222eff5c + .long 0x02010030,0xf2019000,0xf22e4822,0xff84f23c + .long 0x90000000,0x0000dffc,0x0000000c,0xf227e001 + .long 0x60ba08ee,0x0003ff66,0xdffc0000,0x000cf22e + .long 0xd080ff90,0xf23c9000,0x00000010,0xf23c8800 + .long 0x00000000,0xf22e4822,0xff84f23c,0x90000000 + .long 0x0000f201,0xa80083ae,0xff64122e,0xff620201 + .long 0x000b6622,0xf22ef080,0xff8441ee,0xff84222e + .long 0xff5c61ff,0x000034ba,0x812eff64,0xf22ed080 + .long 0xff84241f,0x4e75f22e,0xd040ff90,0x222eff5c + .long 0x020100c0,0x664ef22e,0x9000ff5c,0xf23c8800 + .long 0x00000000,0xf22e48a2,0xff84f23c,0x90000000 + .long 0x0000f22e,0xf040ff84,0x322eff84,0x24010281 + .long 0x00007fff,0x02428000,0x92800681,0x00006000 + .long 0x02417fff,0x82423d41,0xff84f22e,0xd040ff84 + .long 0x6000ff82,0x222eff5c,0x02010030,0xf2019000 + .long 0x60aa222e,0xff5c0201,0x00c06700,0xfe74222f + .long 0x00040c81,0x80000000,0x6600fe66,0x4aaf0008 + .long 0x6600fe5e,0x082e0001,0xff666700,0xfe54f22e + .long 0xd040ff90,0x222eff5c,0x020100c0,0x00010010 + .long 0xf2019000,0xf23c8800,0x00000000,0xf22e48a2 + .long 0xff84f23c,0x90000000,0x0000f200,0x0018f200 + .long 0x0498f200,0x0438f292,0xfeca6000,0xfe14323b + .long 0x120a4efb,0x10064afc,0x0030fdaa,0x00e4011c + .long 0x0060fdaa,0x00660000,0x000000bc,0x006c011c + .long 0x006000bc,0x00660000,0x00000130,0x0130010c + .long 0x00600130,0x00660000,0x00000060,0x00600060 + .long 0x00600060,0x00660000,0x0000fdaa,0x00e4011c + .long 0x0060fdaa,0x00660000,0x00000066,0x00660066 + .long 0x00660066,0x00660000,0x000060ff,0x0000097c + .long 0x60ff0000,0x09761028,0x00001229,0x0000b101 + .long 0x6b000016,0x4a006b2e,0xf23c4400,0x00000000 + .long 0x1d7c0004,0xff644e75,0x122eff5f,0x02010030 + .long 0x0c010020,0x6710f23c,0x44000000,0x00001d7c + .long 0x0004ff64,0x4e75f23c,0x44008000,0x00001d7c + .long 0x000cff64,0x4e753d68,0x0000ff84,0x2d680004 + .long 0xff882d68,0x0008ff8c,0x61ff0000,0x0828426e + .long 0xff9042ae,0xff9442ae,0xff986000,0xfcce3d69 + .long 0x0000ff90,0x2d690004,0xff942d69,0x0008ff98 + .long 0x61ff0000,0x08ac426e,0xff8442ae,0xff8842ae + .long 0xff8c6000,0xfca61028,0x00001229,0x0000b300 + .long 0x6bff0000,0x094af228,0xd0800000,0x4a280000 + .long 0x6a1c1d7c,0x000aff64,0x4e75f229,0xd0800000 + .long 0x4a290000,0x6a081d7c,0x000aff64,0x4e751d7c + .long 0x0002ff64,0x4e750200,0x00300000,0x00406008 + .long 0x02000030,0x00000080,0x2d40ff5c,0x4241122e + .long 0xff4fe709,0x822eff4e,0x6600024c,0x61ff0000 + .long 0x0694f22e,0xd080ff90,0xf23c8800,0x00000000 + .long 0xf22e9000,0xff5cf22e,0x4828ff84,0xf23c9000 + .long 0x00000000,0xf201a800,0x83aeff64,0xf281003c + .long 0x2f02f227,0xe001322e,0xff5eec09,0x34170282 + .long 0x00007fff,0x9480b4bb,0x14246c38,0xb4bb142a + .long 0x6d0000b8,0x67000184,0x32170241,0x80008242 + .long 0x3e81f21f,0xd080241f,0x4e754e75,0x00007fff + .long 0x0000407f,0x000043ff,0x00000000,0x00003f81 + .long 0x00003c01,0x00ae0000,0x1048ff64,0x122eff62 + .long 0x02010013,0x6624dffc,0x0000000c,0x082e0003 + .long 0xff6456c1,0x202eff5c,0x61ff0000,0x32a2812e + .long 0xff64f210,0xd080241f,0x4e75122e,0xff5c0201 + .long 0x00c0661a,0x32170241,0x80000482,0x00006000 + .long 0x02427fff,0x82423e81,0xf21fd040,0x60bef22e + .long 0xd080ff90,0x222eff5c,0x02010030,0xf2019000 + .long 0xf22e4828,0xff84f23c,0x90000000,0x0000dffc + .long 0x0000000c,0xf227e001,0x60ba08ee,0x0003ff66 + .long 0xdffc0000,0x000cf22e,0xd080ff90,0xf23c9000 + .long 0x00000010,0xf23c8800,0x00000000,0xf22e4828 + .long 0xff84f23c,0x90000000,0x0000f201,0xa80083ae + .long 0xff64122e,0xff620201,0x000b6622,0xf22ef080 + .long 0xff8441ee,0xff84222e,0xff5c61ff,0x000030f2 + .long 0x812eff64,0xf22ed080,0xff84241f,0x4e75f22e + .long 0xd040ff90,0x222eff5c,0x020100c0,0x664ef22e + .long 0x9000ff5c,0xf23c8800,0x00000000,0xf22e48a8 + .long 0xff84f23c,0x90000000,0x0000f22e,0xf040ff84 + .long 0x322eff84,0x24010281,0x00007fff,0x02428000 + .long 0x92800681,0x00006000,0x02417fff,0x82423d41 + .long 0xff84f22e,0xd040ff84,0x6000ff82,0x222eff5c + .long 0x02010030,0xf2019000,0x60aa222e,0xff5c0201 + .long 0x00c06700,0xfe74222f,0x00040c81,0x80000000 + .long 0x6600fe66,0x4aaf0008,0x6600fe5e,0x082e0001 + .long 0xff666700,0xfe54f22e,0xd040ff90,0x222eff5c + .long 0x020100c0,0x00010010,0xf2019000,0xf23c8800 + .long 0x00000000,0xf22e48a8,0xff84f23c,0x90000000 + .long 0x0000f200,0x0018f200,0x0498f200,0x0438f292 + .long 0xfeca6000,0xfe14323b,0x120a4efb,0x10064afc + .long 0x0030fdaa,0x00e2011a,0x0060fdaa,0x00660000 + .long 0x000000ba,0x006c011a,0x006000ba,0x00660000 + .long 0x00000130,0x0130010a,0x00600130,0x00660000 + .long 0x00000060,0x00600060,0x00600060,0x00660000 + .long 0x0000fdaa,0x00e2011a,0x0060fdaa,0x00660000 + .long 0x00000066,0x00660066,0x00660066,0x00660000 + .long 0x000060ff,0x000005b4,0x60ff0000,0x05ae1028 + .long 0x00001229,0x0000b300,0x6a144a00,0x6b2ef23c + .long 0x44000000,0x00001d7c,0x0004ff64,0x4e75122e + .long 0xff5f0201,0x00300c01,0x00206710,0xf23c4400 + .long 0x00000000,0x1d7c0004,0xff644e75,0xf23c4400 + .long 0x80000000,0x1d7c000c,0xff644e75,0x3d680000 + .long 0xff842d68,0x0004ff88,0x2d680008,0xff8c61ff + .long 0x00000462,0x426eff90,0x42aeff94,0x42aeff98 + .long 0x6000fcd0,0x3d690000,0xff902d69,0x0004ff94 + .long 0x2d690008,0xff9861ff,0x000004e6,0x426eff84 + .long 0x42aeff88,0x42aeff8c,0x6000fca8,0x10280000 + .long 0x12290000,0xb3006aff,0x00000584,0xf228d080 + .long 0x0000f200,0x001af293,0x001e1d7c,0x000aff64 + .long 0x4e75f229,0xd0800000,0x4a290000,0x6a081d7c + .long 0x000aff64,0x4e751d7c,0x0002ff64,0x4e750200 + .long 0x00300000,0x00406008,0x02000030,0x00000080 + .long 0x2d40ff5c,0x4241122e,0xff4e6600,0x02744a28 + .long 0x00006bff,0x00000528,0x020000c0,0x6648f22e + .long 0x9000ff5c,0xf23c8800,0x00000000,0xf2104804 + .long 0xf201a800,0x83aeff64,0x4e754a28,0x00006bff + .long 0x000004fc,0x020000c0,0x661c3d68,0x0000ff84 + .long 0x2d680004,0xff882d68,0x0008ff8c,0x61ff0000 + .long 0x03ae6000,0x003e0c00,0x00406600,0x00843d68 + .long 0x0000ff84,0x2d680004,0xff882d68,0x0008ff8c + .long 0x61ff0000,0x038a0c80,0x0000007e,0x67000098 + .long 0x6e00009e,0x0c80ffff,0xff806700,0x01a46d00 + .long 0x0120f23c,0x88000000,0x0000f22e,0x9000ff5c + .long 0xf22e4804,0xff84f201,0xa800f23c,0x90000000 + .long 0x000083ae,0xff642f02,0xf22ef080,0xff84322e + .long 0xff842401,0x02810000,0x7fff9280,0x02428000 + .long 0x84413d42,0xff84241f,0xf22ed080,0xff844e75 + .long 0x3d680000,0xff842d68,0x0004ff88,0x2d680008 + .long 0xff8c61ff,0x00000308,0x0c800000,0x03fe6700 + .long 0x00166e1c,0x0c80ffff,0xfc006700,0x01246d00 + .long 0x00a06000,0xff7e082e,0x0000ff85,0x6600ff74 + .long 0x08ee0003,0xff66f23c,0x90000000,0x0010f23c + .long 0x88000000,0x0000f22e,0x4804ff84,0xf201a800 + .long 0xf23c9000,0x00000000,0x83aeff64,0x122eff62 + .long 0x0201000b,0x6620f22e,0xf080ff84,0x41eeff84 + .long 0x222eff5c,0x61ff0000,0x2d28812e,0xff64f22e + .long 0xd080ff84,0x4e752d6e,0xff88ff94,0x2d6eff8c + .long 0xff98322e,0xff842f02,0x24010281,0x00007fff + .long 0x02428000,0x92800681,0x00006000,0x02417fff + .long 0x82423d41,0xff90f22e,0xd040ff90,0x241f60a6 + .long 0xf23c8800,0x00000000,0xf22e9000,0xff5cf22e + .long 0x4804ff84,0xf23c9000,0x00000000,0xf201a800 + .long 0x83aeff64,0x00ae0000,0x1048ff64,0x122eff62 + .long 0x02010013,0x661c082e,0x0003ff64,0x56c1202e + .long 0xff5c61ff,0x00002d98,0x812eff64,0xf210d080 + .long 0x4e752f02,0x322eff84,0x24010281,0x00007fff + .long 0x02428000,0x92800481,0x00006000,0x02417fff + .long 0x82423d41,0xff84f22e,0xd040ff84,0x241f60b6 + .long 0x082e0000,0xff856600,0xff78f23c,0x88000000 + .long 0x0000f22e,0x9000ff5c,0xf22e4804,0xff84f201 + .long 0xa800f23c,0x90000000,0x000083ae,0xff64f200 + .long 0x0080f23c,0x58b80001,0xf293ff6a,0x6000fe48 + .long 0x0c010004,0x6700fdb4,0x0c010001,0x67160c01 + .long 0x00026736,0x0c010005,0x67ff0000,0x023660ff + .long 0x00000244,0x4a280000,0x6b10f23c,0x44000000 + .long 0x00001d7c,0x0004ff64,0x4e75f23c,0x44008000 + .long 0x00001d7c,0x000cff64,0x4e754a28,0x00006bff + .long 0x0000026c,0xf228d080,0x00001d7c,0x0002ff64 + .long 0x4e752d68,0x0004ff88,0x2d690004,0xff942d68 + .long 0x0008ff8c,0x2d690008,0xff983028,0x00003229 + .long 0x00003d40,0xff843d41,0xff900240,0x7fff0241 + .long 0x7fff3d40,0xff543d41,0xff56b041,0x6cff0000 + .long 0x005c61ff,0x0000015a,0x2f000c2e,0x0004ff4e + .long 0x661041ee,0xff8461ff,0x00002940,0x44403d40 + .long 0xff54302e,0xff560440,0x0042b06e,0xff546c1a + .long 0x302eff54,0xd06f0002,0x322eff84,0x02418000 + .long 0x80413d40,0xff84201f,0x4e75026e,0x8000ff84 + .long 0x08ee0000,0xff85201f,0x4e7561ff,0x00000056 + .long 0x2f000c2e,0x0004ff4f,0x661041ee,0xff9061ff + .long 0x000028e8,0x44403d40,0xff56302e,0xff540440 + .long 0x0042b06e,0xff566c1a,0x302eff56,0xd06f0002 + .long 0x322eff90,0x02418000,0x80413d40,0xff90201f + .long 0x4e75026e,0x8000ff90,0x08ee0000,0xff91201f + .long 0x4e75322e,0xff843001,0x02810000,0x7fff0240 + .long 0x80000040,0x3fff3d40,0xff840c2e,0x0004ff4e + .long 0x670a203c,0x00003fff,0x90814e75,0x41eeff84 + .long 0x61ff0000,0x28764480,0x220060e6,0x0c2e0004 + .long 0xff4e673a,0x322eff84,0x02810000,0x7fff026e + .long 0x8000ff84,0x08010000,0x6712006e,0x3fffff84 + .long 0x203c0000,0x3fff9081,0xe2804e75,0x006e3ffe + .long 0xff84203c,0x00003ffe,0x9081e280,0x4e7541ee + .long 0xff8461ff,0x00002824,0x08000000,0x6710006e + .long 0x3fffff84,0x06800000,0x3fffe280,0x4e75006e + .long 0x3ffeff84,0x06800000,0x3ffee280,0x4e75322e + .long 0xff903001,0x02810000,0x7fff0240,0x80000040 + .long 0x3fff3d40,0xff900c2e,0x0004ff4f,0x670a203c + .long 0x00003fff,0x90814e75,0x41eeff90,0x61ff0000 + .long 0x27ca4480,0x220060e6,0x0c2e0005,0xff4f6732 + .long 0x0c2e0003,0xff4f673e,0x0c2e0003,0xff4e6714 + .long 0x08ee0006,0xff7000ae,0x01004080,0xff6441ee + .long 0xff6c6042,0x00ae0100,0x0000ff64,0x41eeff6c + .long 0x603400ae,0x01004080,0xff6408ee,0x0006ff7c + .long 0x41eeff78,0x602041ee,0xff780c2e,0x0005ff4e + .long 0x66ff0000,0x000c00ae,0x00004080,0xff6400ae + .long 0x01000000,0xff640828,0x00070000,0x670800ae + .long 0x08000000,0xff64f210,0xd0804e75,0x00ae0100 + .long 0x2080ff64,0xf23bd080,0x01700000,0x00084e75 + .long 0x7fff0000,0xffffffff,0xffffffff,0x2d40ff54 + .long 0x302eff42,0x4281122e,0xff64e099,0xf2018800 + .long 0x323b0206,0x4efb1002,0x02340040,0x02f8030c + .long 0x03200334,0x0348035c,0x03660352,0x033e032a + .long 0x03160302,0x004a0238,0x023a0276,0x0054009e + .long 0x0102014c,0x01b201fc,0x021801d8,0x018c0128 + .long 0x00de007a,0x02b6025a,0xf2810006,0x6000032a + .long 0x4e75f28e,0x00066000,0x03204e75,0xf2920022 + .long 0x082e0000,0xff646700,0x031000ae,0x00008080 + .long 0xff64082e,0x0007ff62,0x6600032c,0x600002fa + .long 0x4e75f29d,0x00066000,0x02f0082e,0x0000ff64 + .long 0x671200ae,0x00008080,0xff64082e,0x0007ff62 + .long 0x66000304,0x4e75f293,0x0022082e,0x0000ff64 + .long 0x670002c6,0x00ae0000,0x8080ff64,0x082e0007 + .long 0xff626600,0x02e26000,0x02b0082e,0x0000ff64 + .long 0x671200ae,0x00008080,0xff64082e,0x0007ff62 + .long 0x660002c4,0x4e75f29c,0x00066000,0x028c082e + .long 0x0000ff64,0x671200ae,0x00008080,0xff64082e + .long 0x0007ff62,0x660002a0,0x4e75f294,0x0022082e + .long 0x0000ff64,0x67000262,0x00ae0000,0x8080ff64 + .long 0x082e0007,0xff626600,0x027e6000,0x024c4e75 + .long 0xf29b0006,0x60000242,0x082e0000,0xff646712 + .long 0x00ae0000,0x8080ff64,0x082e0007,0xff626600 + .long 0x02564e75,0xf2950022,0x082e0000,0xff646700 + .long 0x021800ae,0x00008080,0xff64082e,0x0007ff62 + .long 0x66000234,0x60000202,0x082e0000,0xff646712 + .long 0x00ae0000,0x8080ff64,0x082e0007,0xff626600 + .long 0x02164e75,0xf29a0006,0x600001de,0x082e0000 + .long 0xff646700,0x001400ae,0x00008080,0xff64082e + .long 0x0007ff62,0x660001f0,0x4e75f296,0x0022082e + .long 0x0000ff64,0x670001b2,0x00ae0000,0x8080ff64 + .long 0x082e0007,0xff626600,0x01ce6000,0x019c4e75 + .long 0xf2990006,0x60000192,0x082e0000,0xff646712 + .long 0x00ae0000,0x8080ff64,0x082e0007,0xff626600 + .long 0x01a64e75,0xf2970018,0x00ae0000,0x8080ff64 + .long 0x082e0007,0xff626600,0x018e6000,0x015c4e75 + .long 0xf2980006,0x60000152,0x00ae0000,0x8080ff64 + .long 0x082e0007,0xff626600,0x016e4e75,0x6000013a + .long 0x4e75082e,0x0000ff64,0x6700012e,0x00ae0000 + .long 0x8080ff64,0x082e0007,0xff626600,0x014a6000 + .long 0x0118082e,0x0000ff64,0x671200ae,0x00008080 + .long 0xff64082e,0x0007ff62,0x6600012c,0x4e75f291 + .long 0x0022082e,0x0000ff64,0x670000ee,0x00ae0000 + .long 0x8080ff64,0x082e0007,0xff626600,0x010a6000 + .long 0x00d8082e,0x0000ff64,0x671200ae,0x00008080 + .long 0xff64082e,0x0007ff62,0x660000ec,0x4e75f29e + .long 0x0022082e,0x0000ff64,0x670000ae,0x00ae0000 + .long 0x8080ff64,0x082e0007,0xff626600,0x00ca6000 + .long 0x0098082e,0x0000ff64,0x67000014,0x00ae0000 + .long 0x8080ff64,0x082e0007,0xff626600,0x00aa4e75 + .long 0xf2820006,0x60000072,0x4e75f28d,0x00066000 + .long 0x00684e75,0xf2830006,0x6000005e,0x4e75f28c + .long 0x00066000,0x00544e75,0xf2840006,0x6000004a + .long 0x4e75f28b,0x00066000,0x00404e75,0xf2850006 + .long 0x60000036,0x4e75f28a,0x00066000,0x002c4e75 + .long 0xf2860006,0x60000022,0x4e75f289,0x00066000 + .long 0x00184e75,0xf2870006,0x6000000e,0x4e75f288 + .long 0x00066000,0x00044e75,0x122eff41,0x02410007 + .long 0x61ff0000,0x1d665340,0x61ff0000,0x1dd00c40 + .long 0xffff6602,0x4e75202e,0xff54d0ae,0xff685880 + .long 0x2d400006,0x4e751d7c,0x0002ff4a,0x4e75302e + .long 0xff424281,0x122eff64,0xe099f201,0x8800323b + .long 0x02064efb,0x1002021e,0x004002e4,0x02f002fc + .long 0x03080314,0x03200326,0x031a030e,0x030202f6 + .long 0x02ea0046,0x02200224,0x0260004c,0x009200f8 + .long 0x013e01a4,0x01ea0202,0x01c4017e,0x011800d2 + .long 0x006c02a2,0x0240f281,0x02ea4e75,0xf28e02e4 + .long 0x4e75f292,0x02de082e,0x0000ff64,0x671200ae + .long 0x00008080,0xff64082e,0x0007ff62,0x660002cc + .long 0x4e75f29d,0x00044e75,0x082e0000,0xff646700 + .long 0x02b200ae,0x00008080,0xff64082e,0x0007ff62 + .long 0x660002a8,0x6000029c,0xf293001e,0x082e0000 + .long 0xff646712,0x00ae0000,0x8080ff64,0x082e0007 + .long 0xff626600,0x02864e75,0x082e0000,0xff646700 + .long 0x027200ae,0x00008080,0xff64082e,0x0007ff62 + .long 0x66000268,0x6000025c,0xf29c0004,0x4e75082e + .long 0x0000ff64,0x6700024c,0x00ae0000,0x8080ff64 + .long 0x082e0007,0xff626600,0x02426000,0x0236f294 + .long 0x0232082e,0x0000ff64,0x671200ae,0x00008080 + .long 0xff64082e,0x0007ff62,0x66000220,0x4e75f29b + .long 0x00044e75,0x082e0000,0xff646700,0x020600ae + .long 0x00008080,0xff64082e,0x0007ff62,0x660001fc + .long 0x600001f0,0xf295001e,0x082e0000,0xff646712 + .long 0x00ae0000,0x8080ff64,0x082e0007,0xff626600 + .long 0x01da4e75,0x082e0000,0xff646700,0x01c600ae + .long 0x00008080,0xff64082e,0x0007ff62,0x660001bc + .long 0x600001b0,0xf29a0004,0x4e75082e,0x0000ff64 + .long 0x670001a0,0x00ae0000,0x8080ff64,0x082e0007 + .long 0xff626600,0x01966000,0x018af296,0x0186082e + .long 0x0000ff64,0x671200ae,0x00008080,0xff64082e + .long 0x0007ff62,0x66000174,0x4e75f299,0x00044e75 + .long 0x082e0000,0xff646700,0x015a00ae,0x00008080 + .long 0xff64082e,0x0007ff62,0x66000150,0x60000144 + .long 0xf2970140,0x00ae0000,0x8080ff64,0x082e0007 + .long 0xff626600,0x01364e75,0xf2980004,0x4e7500ae + .long 0x00008080,0xff64082e,0x0007ff62,0x6600011c + .long 0x60000110,0x4e756000,0x010a082e,0x0000ff64 + .long 0x671200ae,0x00008080,0xff64082e,0x0007ff62 + .long 0x660000f8,0x4e75082e,0x0000ff64,0x670000e4 + .long 0x00ae0000,0x8080ff64,0x082e0007,0xff626600 + .long 0x00da6000,0x00cef291,0x0020082e,0x0000ff64 + .long 0x67000014,0x00ae0000,0x8080ff64,0x082e0007 + .long 0xff626600,0x00b64e75,0x082e0000,0xff646700 + .long 0x00a200ae,0x00008080,0xff64082e,0x0007ff62 + .long 0x66000098,0x6000008c,0xf29e0020,0x082e0000 + .long 0xff646700,0x001400ae,0x00008080,0xff64082e + .long 0x0007ff62,0x66000074,0x4e75082e,0x0000ff64 + .long 0x67000060,0x00ae0000,0x8080ff64,0x082e0007 + .long 0xff626600,0x00566000,0x004af282,0x00464e75 + .long 0xf28d0040,0x4e75f283,0x003a4e75,0xf28c0034 + .long 0x4e75f284,0x002e4e75,0xf28b0028,0x4e75f285 + .long 0x00224e75,0xf28a001c,0x4e75f286,0x00164e75 + .long 0xf2890010,0x4e75f287,0x000a4e75,0xf2880004 + .long 0x4e751d7c,0x0001ff4a,0x4e751d7c,0x0002ff4a + .long 0x4e75302e,0xff424281,0x122eff64,0xe099f201 + .long 0x8800323b,0x02064efb,0x10020208,0x004002ac + .long 0x02cc02ec,0x030c032c,0x034c035c,0x033c031c + .long 0x02fc02dc,0x02bc0050,0x020e0214,0x02440060 + .long 0x00a400fa,0x013e0194,0x01d801f0,0x01b60172 + .long 0x011c00d8,0x00820278,0x022cf281,0x00084200 + .long 0x6000032e,0x50c06000,0x0328f28e,0x00084200 + .long 0x6000031e,0x50c06000,0x0318f292,0x001a4200 + .long 0x082e0000,0xff646700,0x030800ae,0x00008080 + .long 0xff646000,0x02f250c0,0x600002f6,0xf29d0008 + .long 0x42006000,0x02ec50c0,0x082e0000,0xff646700 + .long 0x02e000ae,0x00008080,0xff646000,0x02caf293 + .long 0x001a4200,0x082e0000,0xff646700,0x02c400ae + .long 0x00008080,0xff646000,0x02ae50c0,0x082e0000 + .long 0xff646700,0x02ac00ae,0x00008080,0xff646000 + .long 0x0296f29c,0x00084200,0x60000296,0x50c0082e + .long 0x0000ff64,0x6700028a,0x00ae0000,0x8080ff64 + .long 0x60000274,0xf294001a,0x4200082e,0x0000ff64 + .long 0x6700026e,0x00ae0000,0x8080ff64,0x60000258 + .long 0x50c06000,0x025cf29b,0x00084200,0x60000252 + .long 0x50c0082e,0x0000ff64,0x67000246,0x00ae0000 + .long 0x8080ff64,0x60000230,0xf295001a,0x4200082e + .long 0x0000ff64,0x6700022a,0x00ae0000,0x8080ff64 + .long 0x60000214,0x50c0082e,0x0000ff64,0x67000212 + .long 0x00ae0000,0x8080ff64,0x600001fc,0xf29a0008 + .long 0x42006000,0x01fc50c0,0x082e0000,0xff646700 + .long 0x01f000ae,0x00008080,0xff646000,0x01daf296 + .long 0x001a4200,0x082e0000,0xff646700,0x01d400ae + .long 0x00008080,0xff646000,0x01be50c0,0x600001c2 + .long 0xf2990008,0x42006000,0x01b850c0,0x082e0000 + .long 0xff646700,0x01ac00ae,0x00008080,0xff646000 + .long 0x0196f297,0x00104200,0x00ae0000,0x8080ff64 + .long 0x60000184,0x50c06000,0x0188f298,0x00084200 + .long 0x6000017e,0x50c000ae,0x00008080,0xff646000 + .long 0x01664200,0x6000016a,0x50c06000,0x01644200 + .long 0x082e0000,0xff646700,0x015800ae,0x00008080 + .long 0xff646000,0x014250c0,0x082e0000,0xff646700 + .long 0x014000ae,0x00008080,0xff646000,0x012af291 + .long 0x001a4200,0x082e0000,0xff646700,0x012400ae + .long 0x00008080,0xff646000,0x010e50c0,0x082e0000 + .long 0xff646700,0x010c00ae,0x00008080,0xff646000 + .long 0x00f6f29e,0x001a4200,0x082e0000,0xff646700 + .long 0x00f000ae,0x00008080,0xff646000,0x00da50c0 + .long 0x082e0000,0xff646700,0x00d800ae,0x00008080 + .long 0xff646000,0x00c2f282,0x00084200,0x600000c2 + .long 0x50c06000,0x00bcf28d,0x00084200,0x600000b2 + .long 0x50c06000,0x00acf283,0x00084200,0x600000a2 + .long 0x50c06000,0x009cf28c,0x00084200,0x60000092 + .long 0x50c06000,0x008cf284,0x00084200,0x60000082 + .long 0x50c06000,0x007cf28b,0x00084200,0x60000072 + .long 0x50c06000,0x006cf285,0x00084200,0x60000062 + .long 0x50c06000,0x005cf28a,0x00084200,0x60000052 + .long 0x50c06000,0x004cf286,0x00084200,0x60000042 + .long 0x50c06000,0x003cf289,0x00084200,0x60000032 + .long 0x50c06000,0x002cf287,0x00084200,0x60000022 + .long 0x50c06000,0x001cf288,0x00084200,0x60000012 + .long 0x50c06000,0x000c082e,0x0007ff62,0x66000088 + .long 0x2040122e,0xff412001,0x02010038,0x66102200 + .long 0x02410007,0x200861ff,0x0000172a,0x4e750c01 + .long 0x0018671a,0x0c010020,0x67382008,0x206e000c + .long 0x61ffffff,0x5a7c4a81,0x66000054,0x4e752008 + .long 0x206e000c,0x61ffffff,0x5a684a81,0x66000040 + .long 0x122eff41,0x02410007,0x700161ff,0x00001722 + .long 0x4e752008,0x206e000c,0x61ffffff,0x5a444a81 + .long 0x6600001c,0x122eff41,0x02410007,0x700161ff + .long 0x0000174e,0x4e751d7c,0x0002ff4a,0x4e753d7c + .long 0x00a1000a,0x60ff0000,0x2b86122e,0xff430241 + .long 0x0070e809,0x61ff0000,0x15b20280,0x000000ff + .long 0x2f00103b,0x09200148,0x2f0061ff,0x00000340 + .long 0x201f221f,0x67000134,0x082e0005,0xff426700 + .long 0x00b8082e,0x0004ff42,0x6600001a,0x123b1120 + .long 0x021e082e,0x00050004,0x670a0c2e,0x0008ff4a + .long 0x66024e75,0x22489fc0,0x41d74a01,0x6a0c20ee + .long 0xffdc20ee,0xffe020ee,0xffe4e309,0x6a0c20ee + .long 0xffe820ee,0xffec20ee,0xfff0e309,0x6a0af210 + .long 0xf020d1fc,0x0000000c,0xe3096a0a,0xf210f010 + .long 0xd1fc0000,0x000ce309,0x6a0af210,0xf008d1fc + .long 0x0000000c,0xe3096a0a,0xf210f004,0xd1fc0000 + .long 0x000ce309,0x6a0af210,0xf002d1fc,0x0000000c + .long 0xe3096a0a,0xf210f001,0xd1fc0000,0x000c2d49 + .long 0xff5441d7,0x2f0061ff,0xffff58b2,0x201fdfc0 + .long 0x4a816600,0x071e4e75,0x2d48ff54,0x9fc043d7 + .long 0x2f012f00,0x61ffffff,0x587e201f,0x4a816600 + .long 0x070e221f,0x41d74a01,0x6a0c2d58,0xffdc2d58 + .long 0xffe02d58,0xffe4e309,0x6a0c2d58,0xffe82d58 + .long 0xffec2d58,0xfff0e309,0x6a04f218,0xd020e309 + .long 0x6a04f218,0xd010e309,0x6a04f218,0xd008e309 + .long 0x6a04f218,0xd004e309,0x6a04f218,0xd002e309 + .long 0x6a04f218,0xd001dfc0,0x4e754e75,0x000c0c18 + .long 0x0c181824,0x0c181824,0x18242430,0x0c181824 + .long 0x18242430,0x18242430,0x2430303c,0x0c181824 + .long 0x18242430,0x18242430,0x2430303c,0x18242430 + .long 0x2430303c,0x2430303c,0x303c3c48,0x0c181824 + .long 0x18242430,0x18242430,0x2430303c,0x18242430 + .long 0x2430303c,0x2430303c,0x303c3c48,0x18242430 + .long 0x2430303c,0x2430303c,0x303c3c48,0x2430303c + .long 0x303c3c48,0x303c3c48,0x3c484854,0x0c181824 + .long 0x18242430,0x18242430,0x2430303c,0x18242430 + .long 0x2430303c,0x2430303c,0x303c3c48,0x18242430 + .long 0x2430303c,0x2430303c,0x303c3c48,0x2430303c + .long 0x303c3c48,0x303c3c48,0x3c484854,0x18242430 + .long 0x2430303c,0x2430303c,0x303c3c48,0x2430303c + .long 0x303c3c48,0x303c3c48,0x3c484854,0x2430303c + .long 0x303c3c48,0x303c3c48,0x3c484854,0x303c3c48 + .long 0x3c484854,0x3c484854,0x48545460,0x008040c0 + .long 0x20a060e0,0x109050d0,0x30b070f0,0x088848c8 + .long 0x28a868e8,0x189858d8,0x38b878f8,0x048444c4 + .long 0x24a464e4,0x149454d4,0x34b474f4,0x0c8c4ccc + .long 0x2cac6cec,0x1c9c5cdc,0x3cbc7cfc,0x028242c2 + .long 0x22a262e2,0x129252d2,0x32b272f2,0x0a8a4aca + .long 0x2aaa6aea,0x1a9a5ada,0x3aba7afa,0x068646c6 + .long 0x26a666e6,0x169656d6,0x36b676f6,0x0e8e4ece + .long 0x2eae6eee,0x1e9e5ede,0x3ebe7efe,0x018141c1 + .long 0x21a161e1,0x119151d1,0x31b171f1,0x098949c9 + .long 0x29a969e9,0x199959d9,0x39b979f9,0x058545c5 + .long 0x25a565e5,0x159555d5,0x35b575f5,0x0d8d4dcd + .long 0x2dad6ded,0x1d9d5ddd,0x3dbd7dfd,0x038343c3 + .long 0x23a363e3,0x139353d3,0x33b373f3,0x0b8b4bcb + .long 0x2bab6beb,0x1b9b5bdb,0x3bbb7bfb,0x078747c7 + .long 0x27a767e7,0x179757d7,0x37b777f7,0x0f8f4fcf + .long 0x2faf6fef,0x1f9f5fdf,0x3fbf7fff,0x2040302e + .long 0xff403200,0x0240003f,0x02810000,0x0007303b + .long 0x020a4efb,0x00064afc,0x00400000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000080,0x0086008c + .long 0x00900094,0x0098009c,0x00a000a6,0x00b600c6 + .long 0x00d200de,0x00ea00f6,0x01020118,0x01260134 + .long 0x013e0148,0x0152015c,0x0166017a,0x019801b6 + .long 0x01d201ee,0x020a0226,0x02420260,0x02600260 + .long 0x02600260,0x02600260,0x026002c0,0x02da02f4 + .long 0x03140000,0x00000000,0x0000206e,0xffa44e75 + .long 0x206effa8,0x4e75204a,0x4e75204b,0x4e75204c + .long 0x4e75204d,0x4e752056,0x4e75206e,0xffd84e75 + .long 0x202effa4,0x2200d288,0x2d41ffa4,0x20404e75 + .long 0x202effa8,0x2200d288,0x2d41ffa8,0x20404e75 + .long 0x200a2200,0xd2882441,0x20404e75,0x200b2200 + .long 0xd2882641,0x20404e75,0x200c2200,0xd2882841 + .long 0x20404e75,0x200d2200,0xd2882a41,0x20404e75 + .long 0x20162200,0xd2882c81,0x20404e75,0x1d7c0004 + .long 0xff4a202e,0xffd82200,0xd2882d41,0xffd82040 + .long 0x4e75202e,0xffa49088,0x2d40ffa4,0x20404e75 + .long 0x202effa8,0x90882d40,0xffa82040,0x4e75200a + .long 0x90882440,0x20404e75,0x200b9088,0x26402040 + .long 0x4e75200c,0x90882840,0x20404e75,0x200d9088 + .long 0x2a402040,0x4e752016,0x90882c80,0x20404e75 + .long 0x1d7c0008,0xff4a202e,0xffd89088,0x2d40ffd8 + .long 0x20404e75,0x206eff44,0x54aeff44,0x61ffffff + .long 0x54a24a81,0x66ffffff,0x68203040,0xd1eeffa4 + .long 0x4e75206e,0xff4454ae,0xff4461ff,0xffff5484 + .long 0x4a8166ff,0xffff6802,0x3040d1ee,0xffa84e75 + .long 0x206eff44,0x54aeff44,0x61ffffff,0x54664a81 + .long 0x66ffffff,0x67e43040,0xd1ca4e75,0x206eff44 + .long 0x54aeff44,0x61ffffff,0x544a4a81,0x66ffffff + .long 0x67c83040,0xd1cb4e75,0x206eff44,0x54aeff44 + .long 0x61ffffff,0x542e4a81,0x66ffffff,0x67ac3040 + .long 0xd1cc4e75,0x206eff44,0x54aeff44,0x61ffffff + .long 0x54124a81,0x66ffffff,0x67903040,0xd1cd4e75 + .long 0x206eff44,0x54aeff44,0x61ffffff,0x53f64a81 + .long 0x66ffffff,0x67743040,0xd1d64e75,0x206eff44 + .long 0x54aeff44,0x61ffffff,0x53da4a81,0x66ffffff + .long 0x67583040,0xd1eeffd8,0x4e755081,0x61ff0000 + .long 0x0fda2f00,0x206eff44,0x54aeff44,0x61ffffff + .long 0x53b24a81,0x66ffffff,0x6730205f,0x08000008 + .long 0x660000e6,0x2d40ff54,0x2200e959,0x0241000f + .long 0x61ff0000,0x0fa62f02,0x242eff54,0x0802000b + .long 0x660248c0,0x2202ef59,0x02810000,0x0003e3a8 + .long 0x49c2d082,0xd1c0241f,0x4e75206e,0xff4454ae + .long 0xff4461ff,0xffff535c,0x4a8166ff,0xffff66da + .long 0x30404e75,0x206eff44,0x58aeff44,0x61ffffff + .long 0x53584a81,0x66ffffff,0x66c02040,0x4e75206e + .long 0xff4454ae,0xff4461ff,0xffff5328,0x4a8166ff + .long 0xffff66a6,0x3040d1ee,0xff445588,0x4e75206e + .long 0xff4454ae,0xff4461ff,0xffff5308,0x4a8166ff + .long 0xffff6686,0x206eff44,0x55880800,0x00086600 + .long 0x00382d40,0xff542200,0xe9590241,0x000f61ff + .long 0x00000ef8,0x2f02242e,0xff540802,0x000b6602 + .long 0x48c02202,0xef590281,0x00000003,0xe3a849c2 + .long 0xd082d1c0,0x241f4e75,0x08000006,0x670c48e7 + .long 0x3c002a00,0x26084282,0x60282d40,0xff54e9c0 + .long 0x140461ff,0x00000eb4,0x48e73c00,0x24002a2e + .long 0xff542608,0x0805000b,0x660248c2,0xe9c50542 + .long 0xe1aa0805,0x00076702,0x4283e9c5,0x06820c00 + .long 0x00026d34,0x6718206e,0xff4458ae,0xff4461ff + .long 0xffff5276,0x4a8166ff,0x000000b0,0x6018206e + .long 0xff4454ae,0xff4461ff,0xffff5248,0x4a8166ff + .long 0x00000098,0x48c0d680,0xe9c50782,0x6700006e + .long 0x0c000002,0x6d346718,0x206eff44,0x58aeff44 + .long 0x61ffffff,0x52344a81,0x66ff0000,0x006e601c + .long 0x206eff44,0x54aeff44,0x61ffffff,0x52064a81 + .long 0x66ff0000,0x005648c0,0x60024280,0x28000805 + .long 0x00026714,0x204361ff,0xffff5240,0x4a816600 + .long 0x0028d082,0xd0846018,0xd6822043,0x61ffffff + .long 0x522a4a81,0x66000012,0xd0846004,0xd6822003 + .long 0x20404cdf,0x003c4e75,0x20434cdf,0x003c303c + .long 0x010160ff,0xffff6582,0x4cdf003c,0x60ffffff + .long 0x652861ff,0x000023c6,0x303c00e1,0x600a61ff + .long 0x000023ba,0x303c0161,0x206eff54,0x60ffffff + .long 0x6558102e,0xff420c00,0x009c6700,0x00b20c00 + .long 0x00986700,0x00740c00,0x00946736,0x206eff44 + .long 0x58aeff44,0x61ffffff,0x51704a81,0x66ffffff + .long 0x64d82d40,0xff64206e,0xff4458ae,0xff4461ff + .long 0xffff5156,0x4a8166ff,0xffff64be,0x2d40ff68 + .long 0x4e75206e,0xff4458ae,0xff4461ff,0xffff513a + .long 0x4a8166ff,0xffff64a2,0x2d40ff60,0x206eff44 + .long 0x58aeff44,0x61ffffff,0x51204a81,0x66ffffff + .long 0x64882d40,0xff684e75,0x206eff44,0x58aeff44 + .long 0x61ffffff,0x51044a81,0x66ffffff,0x646c2d40 + .long 0xff60206e,0xff4458ae,0xff4461ff,0xffff50ea + .long 0x4a8166ff,0xffff6452,0x2d40ff64,0x4e75206e + .long 0xff4458ae,0xff4461ff,0xffff50ce,0x4a8166ff + .long 0xffff6436,0x2d40ff60,0x206eff44,0x58aeff44 + .long 0x61ffffff,0x50b44a81,0x66ffffff,0x641c2d40 + .long 0xff64206e,0xff4458ae,0xff4461ff,0xffff509a + .long 0x4a8166ff,0xffff6402,0x2d40ff68,0x4e752040 + .long 0x102eff41,0x22000240,0x00380281,0x00000007 + .long 0x0c000018,0x67240c00,0x0020672c,0x80410c00 + .long 0x003c6706,0x206e000c,0x4e751d7c,0x0080ff4a + .long 0x41f60162,0xff680004,0x4e752008,0x61ff0000 + .long 0x0d70206e,0x000c4e75,0x200861ff,0x00000db2 + .long 0x206e000c,0x0c00000c,0x67024e75,0x51882d48 + .long 0x000c4e75,0x102eff41,0x22000240,0x00380281 + .long 0x00000007,0x0c000018,0x670e0c00,0x00206700 + .long 0x0076206e,0x000c4e75,0x323b120e,0x206e000c + .long 0x4efb1006,0x4afc0008,0x0010001a,0x0024002c + .long 0x0034003c,0x0044004e,0x06ae0000,0x000cffa4 + .long 0x4e7506ae,0x0000000c,0xffa84e75,0xd5fc0000 + .long 0x000c4e75,0xd7fc0000,0x000c4e75,0xd9fc0000 + .long 0x000c4e75,0xdbfc0000,0x000c4e75,0x06ae0000 + .long 0x000cffd4,0x4e751d7c,0x0004ff4a,0x06ae0000 + .long 0x000cffd8,0x4e75323b,0x1214206e,0x000c5188 + .long 0x51ae000c,0x4efb1006,0x4afc0008,0x00100016 + .long 0x001c0020,0x00240028,0x002c0032,0x2d48ffa4 + .long 0x4e752d48,0xffa84e75,0x24484e75,0x26484e75 + .long 0x28484e75,0x2a484e75,0x2d48ffd4,0x4e752d48 + .long 0xffd81d7c,0x0008ff4a,0x4e75082e,0x0006ff42 + .long 0x6664102e,0xff430800,0x0005672c,0x08000004 + .long 0x670a0240,0x007f0c40,0x0038661c,0xe9ee0183 + .long 0xff4261ff,0x00000d6a,0x61ff0000,0x12060c00 + .long 0x00066722,0x1d40ff4f,0xe9ee00c3,0xff4261ff + .long 0x00000cbe,0x61ff0000,0x11ea0c00,0x0006670e + .long 0x1d40ff4e,0x4e7561ff,0x00001148,0x60d661ff + .long 0x00001140,0x60ea302e,0xff420800,0x0005672c + .long 0x08000004,0x670a0240,0x007f0c40,0x0038661c + .long 0xe9ee0183,0xff4261ff,0x00000d06,0x61ff0000 + .long 0x11a20c00,0x00066726,0x1d40ff4f,0xe9ee00c3 + .long 0xff42e9ee,0x1283ff40,0x660000be,0x422eff4e + .long 0xe9ee1343,0xff40303b,0x02124efb,0x000e61ff + .long 0x000010e0,0x60d24afc,0x00080010,0x006a0000 + .long 0x0000002e,0x0000004c,0x000061ff,0x00000a5c + .long 0xf2004000,0xf22ef080,0xff6cf281,0x00044e75 + .long 0x1d7c0001,0xff4e4e75,0x61ff0000,0x0a3ef200 + .long 0x5000f22e,0xf080ff6c,0xf2810004,0x4e751d7c + .long 0x0001ff4e,0x4e7561ff,0x00000a20,0xf2005800 + .long 0xf22ef080,0xff6cf281,0x00044e75,0x1d7c0001 + .long 0xff4e4e75,0x61ff0000,0x0a022d40,0xff5441ee + .long 0xff5461ff,0x000011de,0x1d40ff4e,0x0c000005 + .long 0x670001a4,0x0c000004,0x6700015e,0xf2104400 + .long 0xf22ef080,0xff6c4e75,0x422eff4e,0x303b020a + .long 0x4efb0006,0x4afc0008,0x001000e2,0x027202b0 + .long 0x005601a0,0x009c0000,0x700461ff,0xfffffd22 + .long 0x0c2e0080,0xff4a6726,0x61ffffff,0x4dde4a81 + .long 0x66ff0000,0x1eecf200,0x4000f22e,0xf080ff6c + .long 0xf2810004,0x4e751d7c,0x0001ff4e,0x4e7561ff + .long 0xffff4d76,0x4a8166ff,0xffff6e8a,0x60d87002 + .long 0x61ffffff,0xfcdc0c2e,0x0080ff4a,0x672661ff + .long 0xffff4d82,0x4a8166ff,0x00001e98,0xf2005000 + .long 0xf22ef080,0xff6cf281,0x00044e75,0x1d7c0001 + .long 0xff4e4e75,0x61ffffff,0x4d1a4a81,0x66ffffff + .long 0x6e4460d8,0x700161ff,0xfffffc96,0x0c2e0080 + .long 0xff4a6726,0x61ffffff,0x4d264a81,0x66ff0000 + .long 0x1e42f200,0x5800f22e,0xf080ff6c,0xf2810004 + .long 0x4e751d7c,0x0001ff4e,0x4e7561ff,0xffff4cd4 + .long 0x4a8166ff,0xffff6dfe,0x60d87004,0x61ffffff + .long 0xfc500c2e,0x0080ff4a,0x673e61ff,0xffff4d0c + .long 0x2d40ff54,0x4a8166ff,0x00001e16,0x41eeff54 + .long 0x61ff0000,0x10a01d40,0xff4e0c00,0x00046700 + .long 0x00280c00,0x00056700,0x005ef22e,0x4400ff54 + .long 0xf22ef080,0xff6c4e75,0x61ffffff,0x4c8c4a81 + .long 0x66ffffff,0x6da060c4,0x426eff6c,0xe9d00257 + .long 0xe1882d40,0xff7042ae,0xff74426e,0xff6c0810 + .long 0x00076706,0x08ee0007,0xff6c41ee,0xff6c61ff + .long 0x00000e78,0x323c3f81,0x9240836e,0xff6c1d7c + .long 0x0000ff4e,0x4e753d7c,0x7fffff6c,0xe9d00257 + .long 0xe1882d40,0xff7042ae,0xff740810,0x00076706 + .long 0x08ee0007,0xff6c4e75,0x700861ff,0xfffffb92 + .long 0x0c2e0080,0xff4a6740,0x43eeff54,0x700861ff + .long 0xffff4bc4,0x4a8166ff,0x00001d64,0x41eeff54 + .long 0x61ff0000,0x0f701d40,0xff4e0c00,0x00046700 + .long 0x002e0c00,0x00056700,0x0068f22e,0x5400ff54 + .long 0xf22ef080,0xff6c4e75,0x43eeff54,0x700861ff + .long 0xffff4b6e,0x4a8166ff,0xffff6cda,0x60be426e + .long 0xff6ce9d0,0x031f2d40,0xff70e9e8,0x02d50004 + .long 0x720be3a8,0x2d40ff74,0x08100007,0x670608ee + .long 0x0007ff6c,0x41eeff6c,0x61ff0000,0x0dae323c + .long 0x3c019240,0x836eff6c,0x1d7c0000,0xff4e4e75 + .long 0x3d7c7fff,0xff6ce9d0,0x031f2d40,0xff70e9e8 + .long 0x02d50004,0x720be3a8,0x2d40ff74,0x08100007 + .long 0x670608ee,0x0007ff6c,0x4e75700c,0x61ffffff + .long 0xfac043ee,0xff6c700c,0x61ffffff,0x4afa4a81 + .long 0x66ff0000,0x1ca841ee,0xff6c61ff,0x00000e24 + .long 0x0c000006,0x67061d40,0xff4e4e75,0x61ff0000 + .long 0x0d821d40,0xff4e4e75,0x61ff0000,0x125441ee + .long 0xff6c61ff,0x00000dfc,0x0c000006,0x67061d40 + .long 0xff4e4e75,0x61ff0000,0x0d5a1d40,0xff4e4e75 + .long 0xe9ee10c3,0xff42327b,0x120a4efb,0x98064afc + .long 0x000800e0,0x01e00148,0x06200078,0x041a0010 + .long 0x06204a2e,0xff4e664c,0xf228d080,0x0000f200 + .long 0x9000f200,0x7800f23c,0x90000000,0x0000f201 + .long 0xa800836e,0xff66122e,0xff410201,0x00386714 + .long 0x206e000c,0x61ffffff,0x4ae84a81,0x66ff0000 + .long 0x1c0a4e75,0x122eff41,0x02410007,0x61ff0000 + .long 0x07644e75,0x22280000,0x02818000,0x00000081 + .long 0x00800000,0xf2014400,0x60a44a2e,0xff4e664c + .long 0xf228d080,0x0000f200,0x9000f200,0x7000f23c + .long 0x90000000,0x0000f201,0xa800836e,0xff66122e + .long 0xff410201,0x00386714,0x206e000c,0x61ffffff + .long 0x4a964a81,0x66ff0000,0x1bb04e75,0x122eff41 + .long 0x02410007,0x61ff0000,0x06c04e75,0x22280000 + .long 0x02818000,0x00000081,0x00800000,0xf2014400 + .long 0x60a44a2e,0xff4e664c,0xf228d080,0x0000f200 + .long 0x9000f200,0x6000f23c,0x90000000,0x0000f201 + .long 0xa800836e,0xff66122e,0xff410201,0x00386714 + .long 0x206e000c,0x61ffffff,0x4a444a81,0x66ff0000 + .long 0x1b564e75,0x122eff41,0x02410007,0x61ff0000 + .long 0x061c4e75,0x22280000,0x02818000,0x00000081 + .long 0x00800000,0xf2014400,0x60a43d68,0x0000ff84 + .long 0x426eff86,0x2d680004,0xff882d68,0x0008ff8c + .long 0xf228d080,0x000061ff,0xfffff94c,0x224841ee + .long 0xff84700c,0x0c2e0008,0xff4a6726,0x61ffffff + .long 0x492c4a81,0x66000052,0x4a2eff4e,0x66024e75 + .long 0x08ee0003,0xff66102e,0xff620200,0x000a6616 + .long 0x4e7561ff,0xffff5788,0x4a816600,0x002c4a2e + .long 0xff4e66dc,0x4e7541ee,0xff8461ff,0x00000b3c + .long 0x44400240,0x7fff026e,0x8000ff84,0x816eff84 + .long 0xf22ed040,0xff844e75,0x2caeffd4,0x60ff0000 + .long 0x1ab20200,0x00300000,0x00402d40,0xff5c3028 + .long 0x00000240,0x7fff0c40,0x407e6e00,0x00e66700 + .long 0x01520c40,0x3f816d00,0x0058f228,0xd0800000 + .long 0xf22e9000,0xff5cf23c,0x88000000,0x0000f200 + .long 0x6400f23c,0x90000000,0x0000f201,0xa800836e + .long 0xff66122e,0xff410201,0x00386714,0x206e000c + .long 0x61ffffff,0x49184a81,0x66ff0000,0x1a2a4e75 + .long 0x122eff41,0x02410007,0x61ff0000,0x04f04e75 + .long 0x08ee0003,0xff663d68,0x0000ff84,0x2d680004 + .long 0xff882d68,0x0008ff8c,0x2f084280,0x0c2e0004 + .long 0xff4e660a,0x41eeff84,0x61ff0000,0x0a6e41ee + .long 0xff84222e,0xff5c61ff,0x00000c86,0x41eeff84 + .long 0x61ff0000,0x034c122e,0xff410201,0x00386714 + .long 0x206e000c,0x61ffffff,0x48a44a81,0x66ff0000 + .long 0x19b6600e,0x122eff41,0x02410007,0x61ff0000 + .long 0x047c122e,0xff620201,0x000a6600,0x00b8588f + .long 0x4e754a28,0x0007660e,0x4aa80008,0x6608006e + .long 0x1048ff66,0x6006006e,0x1248ff66,0x2f084a28 + .long 0x00005bc1,0x202eff5c,0x61ff0000,0x0d12f210 + .long 0xd080f200,0x6400122e,0xff410201,0x00386714 + .long 0x206e000c,0x61ffffff,0x48344a81,0x66ff0000 + .long 0x1946600e,0x122eff41,0x02410007,0x61ff0000 + .long 0x040c122e,0xff620201,0x000a6600,0x007c588f + .long 0x4e753228,0x00000241,0x80000041,0x3fff3d41 + .long 0xff842d68,0x0004ff88,0x2d680008,0xff8cf22e + .long 0x9000ff5c,0xf22e4800,0xff84f23c,0x90000000 + .long 0x0000f200,0x0018f23c,0x58380002,0xf294fe7c + .long 0x6000ff50,0x205f3d68,0x0000ff84,0x2d680004 + .long 0xff882d68,0x0008ff8c,0x0c2e0004,0xff4e662c + .long 0x41eeff84,0x61ff0000,0x09424480,0x02407fff + .long 0xefee004f,0xff846014,0x205f3d68,0x0000ff84 + .long 0x2d680004,0xff882d68,0x0008ff8c,0x08ae0007 + .long 0xff8456ee,0xff8641ee,0xff84122e,0xff5fe809 + .long 0x0241000c,0x4841122e,0xff5fe809,0x02410003 + .long 0x428061ff,0x00000782,0x4a2eff86,0x670608ee + .long 0x0007ff84,0xf22ed040,0xff844e75,0x02000030 + .long 0x00000080,0x2d40ff5c,0x30280000,0x02407fff + .long 0x0c4043fe,0x6e0000c8,0x67000120,0x0c403c01 + .long 0x6d000046,0xf228d080,0x0000f22e,0x9000ff5c + .long 0xf23c8800,0x00000000,0xf22e7400,0xff54f23c + .long 0x90000000,0x0000f200,0xa800816e,0xff66226e + .long 0x000c41ee,0xff547008,0x61ffffff,0x46304a81 + .long 0x66ff0000,0x18004e75,0x08ee0003,0xff663d68 + .long 0x0000ff84,0x2d680004,0xff882d68,0x0008ff8c + .long 0x2f084280,0x0c2e0004,0xff4e660a,0x41eeff84 + .long 0x61ff0000,0x084641ee,0xff84222e,0xff5c61ff + .long 0x00000a5e,0x41eeff84,0x61ff0000,0x00d22d40 + .long 0xff542d41,0xff58226e,0x000c41ee,0xff547008 + .long 0x61ffffff,0x45c84a81,0x66ff0000,0x1798122e + .long 0xff620201,0x000a6600,0xfe9c588f,0x4e753028 + .long 0x000a0240,0x07ff6608,0x006e1048,0xff666006 + .long 0x006e1248,0xff662f08,0x4a280000,0x5bc1202e + .long 0xff5c61ff,0x00000af8,0xf210d080,0xf22e7400 + .long 0xff54226e,0x000c41ee,0xff547008,0x61ffffff + .long 0x456c4a81,0x66ff0000,0x173c122e,0xff620201 + .long 0x000a6600,0xfe74588f,0x4e753228,0x00000241 + .long 0x80000041,0x3fff3d41,0xff842d68,0x0004ff88 + .long 0x2d680008,0xff8cf22e,0x9000ff5c,0xf22e4800 + .long 0xff84f23c,0x90000000,0x0000f200,0x0018f23c + .long 0x58380002,0xf294feae,0x6000ff64,0x42803028 + .long 0x00000440,0x3fff0640,0x03ff4a28,0x00046b02 + .long 0x53404840,0xe9884a28,0x00006a04,0x08c0001f + .long 0x22280004,0xe9c11054,0x80812d40,0xff542228 + .long 0x00047015,0xe1a92d41,0xff582228,0x0008e9c1 + .long 0x0015222e,0xff588280,0x202eff54,0x4e754280 + .long 0x30280000,0x04403fff,0x0640007f,0x4a280004 + .long 0x6b025340,0x4840ef88,0x4a280000,0x6a0408c0 + .long 0x001f2228,0x00040281,0x7fffff00,0xe0898081 + .long 0x4e7561ff,0xfffff490,0x2f08102e,0xff4e6600 + .long 0x0082082e,0x0004ff42,0x6712122e,0xff43e809 + .long 0x02410007,0x61ff0000,0x00926004,0x102eff43 + .long 0xebc00647,0x2f0041ee,0xff6c61ff,0x00000ed0 + .long 0x02aecfff,0xf00fff84,0x201f4a2e,0xff876616 + .long 0x4aaeff88,0x66104aae,0xff8c660a,0x4a806606 + .long 0x026ef000,0xff8441ee,0xff84225f,0x700c0c2e + .long 0x0008ff4a,0x670e61ff,0xffff4412,0x4a816600 + .long 0xfb384e75,0x61ffffff,0x52864a81,0x6600fb2a + .long 0x4e750c00,0x00046700,0xff7a41ee,0xff6c426e + .long 0xff6e0c00,0x00056702,0x60c0006e,0x4080ff66 + .long 0x08ee0006,0xff7060b2,0x303b1206,0x4efb0002 + .long 0x00200026,0x002c0030,0x00340038,0x003c0040 + .long 0x0044004a,0x00500054,0x0058005c,0x00600064 + .long 0x202eff9c,0x4e75202e,0xffa04e75,0x20024e75 + .long 0x20034e75,0x20044e75,0x20054e75,0x20064e75 + .long 0x20074e75,0x202effa4,0x4e75202e,0xffa84e75 + .long 0x200a4e75,0x200b4e75,0x200c4e75,0x200d4e75 + .long 0x20164e75,0x202effd8,0x4e75323b,0x12064efb + .long 0x10020010,0x0016001c,0x00200024,0x0028002c + .long 0x00302d40,0xff9c4e75,0x2d40ffa0,0x4e752400 + .long 0x4e752600,0x4e752800,0x4e752a00,0x4e752c00 + .long 0x4e752e00,0x4e75323b,0x12064efb,0x10020010 + .long 0x0016001c,0x00200024,0x0028002c,0x00303d40 + .long 0xff9e4e75,0x3d40ffa2,0x4e753400,0x4e753600 + .long 0x4e753800,0x4e753a00,0x4e753c00,0x4e753e00 + .long 0x4e75323b,0x12064efb,0x10020010,0x0016001c + .long 0x00200024,0x0028002c,0x00301d40,0xff9f4e75 + .long 0x1d40ffa3,0x4e751400,0x4e751600,0x4e751800 + .long 0x4e751a00,0x4e751c00,0x4e751e00,0x4e75323b + .long 0x12064efb,0x10020010,0x0016001c,0x00200024 + .long 0x0028002c,0x0030d1ae,0xffa44e75,0xd1aeffa8 + .long 0x4e75d5c0,0x4e75d7c0,0x4e75d9c0,0x4e75dbc0 + .long 0x4e75d196,0x4e751d7c,0x0004ff4a,0x0c000001 + .long 0x6706d1ae,0xffd84e75,0x54aeffd8,0x4e75323b + .long 0x12064efb,0x10020010,0x0016001c,0x00200024 + .long 0x0028002c,0x003091ae,0xffa44e75,0x91aeffa8 + .long 0x4e7595c0,0x4e7597c0,0x4e7599c0,0x4e759bc0 + .long 0x4e759196,0x4e751d7c,0x0008ff4a,0x0c000001 + .long 0x670691ae,0xffd84e75,0x55aeffd8,0x4e75303b + .long 0x02064efb,0x00020010,0x00280040,0x004c0058 + .long 0x00640070,0x007c2d6e,0xffdcff6c,0x2d6effe0 + .long 0xff702d6e,0xffe4ff74,0x41eeff6c,0x4e752d6e + .long 0xffe8ff6c,0x2d6effec,0xff702d6e,0xfff0ff74 + .long 0x41eeff6c,0x4e75f22e,0xf020ff6c,0x41eeff6c + .long 0x4e75f22e,0xf010ff6c,0x41eeff6c,0x4e75f22e + .long 0xf008ff6c,0x41eeff6c,0x4e75f22e,0xf004ff6c + .long 0x41eeff6c,0x4e75f22e,0xf002ff6c,0x41eeff6c + .long 0x4e75f22e,0xf001ff6c,0x41eeff6c,0x4e75303b + .long 0x02064efb,0x00020010,0x00280040,0x004c0058 + .long 0x00640070,0x007c2d6e,0xffdcff78,0x2d6effe0 + .long 0xff7c2d6e,0xffe4ff80,0x41eeff78,0x4e752d6e + .long 0xffe8ff78,0x2d6effec,0xff7c2d6e,0xfff0ff80 + .long 0x41eeff78,0x4e75f22e,0xf020ff78,0x41eeff78 + .long 0x4e75f22e,0xf010ff78,0x41eeff78,0x4e75f22e + .long 0xf008ff78,0x41eeff78,0x4e75f22e,0xf004ff78 + .long 0x41eeff78,0x4e75f22e,0xf002ff78,0x41eeff78 + .long 0x4e75f22e,0xf001ff78,0x41eeff78,0x4e75303b + .long 0x02064efb,0x00020010,0x00180020,0x002a0034 + .long 0x003e0048,0x0052f22e,0xf080ffdc,0x4e75f22e + .long 0xf080ffe8,0x4e75f227,0xe001f21f,0xd0204e75 + .long 0xf227e001,0xf21fd010,0x4e75f227,0xe001f21f + .long 0xd0084e75,0xf227e001,0xf21fd004,0x4e75f227 + .long 0xe001f21f,0xd0024e75,0xf227e001,0xf21fd001 + .long 0x4e750000,0x3f813c01,0xe408323b,0x02f63001 + .long 0x90680000,0x0c400042,0x6a164280,0x082e0001 + .long 0xff666704,0x08c0001d,0x61ff0000,0x001a4e75 + .long 0x203c2000,0x00003141,0x000042a8,0x000442a8 + .long 0x00084e75,0x2d680008,0xff542d40,0xff582001 + .long 0x92680000,0x6f100c41,0x00206d10,0x0c410040 + .long 0x6d506000,0x009a202e,0xff584e75,0x2f023140 + .long 0x00007020,0x90410c41,0x001d6d08,0x142eff58 + .long 0x852eff57,0xe9e82020,0x0004e9e8,0x18000004 + .long 0xe9ee0800,0xff542142,0x00042141,0x0008e8c0 + .long 0x009e6704,0x08c0001d,0x0280e000,0x0000241f + .long 0x4e752f02,0x31400000,0x04410020,0x70209041 + .long 0x142eff58,0x852eff57,0xe9e82020,0x0004e9e8 + .long 0x18000004,0xe8c1009e,0x660ce8ee,0x081fff54 + .long 0x66042001,0x60062001,0x08c0001d,0x42a80004 + .long 0x21420008,0x0280e000,0x0000241f,0x4e753140 + .long 0x00000c41,0x00416d12,0x672442a8,0x000442a8 + .long 0x0008203c,0x20000000,0x4e752028,0x00042200 + .long 0x0280c000,0x00000281,0x3fffffff,0x60122028 + .long 0x00040280,0x80000000,0xe2880281,0x7fffffff + .long 0x66164aa8,0x00086610,0x4a2eff58,0x660a42a8 + .long 0x000442a8,0x00084e75,0x08c0001d,0x42a80004 + .long 0x42a80008,0x4e7561ff,0x00000110,0x4a806700 + .long 0x00fa006e,0x0208ff66,0x327b1206,0x4efb9802 + .long 0x004000ea,0x00240008,0x4a280002,0x6b0000dc + .long 0x70ff4841,0x0c010004,0x6700003e,0x6e000094 + .long 0x60000064,0x4a280002,0x6a0000c0,0x70ff4841 + .long 0x0c010004,0x67000022,0x6e000078,0x60000048 + .long 0xe3806400,0x00a64841,0x0c010004,0x6700000a + .long 0x6e000060,0x60000030,0x06a80000,0x01000004 + .long 0x640ce4e8,0x0004e4e8,0x00065268,0x00004a80 + .long 0x66060268,0xfe000006,0x02a8ffff,0xff000004 + .long 0x42a80008,0x4e7552a8,0x0008641a,0x52a80004 + .long 0x6414e4e8,0x0004e4e8,0x0006e4e8,0x0008e4e8 + .long 0x000a5268,0x00004a80,0x66060228,0x00fe000b + .long 0x4e7506a8,0x00000800,0x0008641a,0x52a80004 + .long 0x6414e4e8,0x0004e4e8,0x0006e4e8,0x0008e4e8 + .long 0x000a5268,0x00004a80,0x66060268,0xf000000a + .long 0x02a8ffff,0xf8000008,0x4e754841,0x0c010004 + .long 0x6700ff86,0x6eea4e75,0x48414a01,0x66044841 + .long 0x4e7548e7,0x30000c01,0x00046622,0xe9e83602 + .long 0x0004741e,0xe5ab2428,0x00040282,0x0000003f + .long 0x66284aa8,0x00086622,0x4a80661e,0x6020e9e8 + .long 0x35420008,0x741ee5ab,0x24280008,0x02820000 + .long 0x01ff6606,0x4a806602,0x600408c3,0x001d2003 + .long 0x4cdf000c,0x48414e75,0x2f022f03,0x20280004 + .long 0x22280008,0xedc02000,0x671ae5a8,0xe9c13022 + .long 0x8083e5a9,0x21400004,0x21410008,0x2002261f + .long 0x241f4e75,0xedc12000,0xe5a90682,0x00000020 + .long 0x21410004,0x42a80008,0x2002261f,0x241f4e75 + .long 0xede80000,0x0004660e,0xede80000,0x00086700 + .long 0x00740640,0x00204281,0x32280000,0x02417fff + .long 0xb0416e1c,0x92403028,0x00000240,0x80008240 + .long 0x31410000,0x61ffffff,0xff82103c,0x00004e75 + .long 0x0c010020,0x6e20e9e8,0x08400004,0x21400004 + .long 0x20280008,0xe3a82140,0x00080268,0x80000000 + .long 0x103c0004,0x4e750441,0x00202028,0x0008e3a8 + .long 0x21400004,0x42a80008,0x02688000,0x0000103c + .long 0x00044e75,0x02688000,0x0000103c,0x00014e75 + .long 0x30280000,0x02407fff,0x0c407fff,0x67480828 + .long 0x00070004,0x6706103c,0x00004e75,0x4a406618 + .long 0x4aa80004,0x660c4aa8,0x00086606,0x103c0001 + .long 0x4e75103c,0x00044e75,0x4aa80004,0x66124aa8 + .long 0x0008660c,0x02688000,0x0000103c,0x00014e75 + .long 0x103c0006,0x4e754aa8,0x00086612,0x20280004 + .long 0x02807fff,0xffff6606,0x103c0002,0x4e750828 + .long 0x00060004,0x6706103c,0x00034e75,0x103c0005 + .long 0x4e752028,0x00002200,0x02807ff0,0x0000670e + .long 0x0c807ff0,0x00006728,0x103c0000,0x4e750281 + .long 0x000fffff,0x66ff0000,0x00144aa8,0x000466ff + .long 0x0000000a,0x103c0001,0x4e75103c,0x00044e75 + .long 0x0281000f,0xffff66ff,0x00000014,0x4aa80004 + .long 0x66ff0000,0x000a103c,0x00024e75,0x08010013 + .long 0x66ff0000,0x000a103c,0x00054e75,0x103c0003 + .long 0x4e752028,0x00002200,0x02807f80,0x0000670e + .long 0x0c807f80,0x0000671e,0x103c0000,0x4e750281 + .long 0x007fffff,0x66ff0000,0x000a103c,0x00014e75 + .long 0x103c0004,0x4e750281,0x007fffff,0x66ff0000 + .long 0x000a103c,0x00024e75,0x08010016,0x66ff0000 + .long 0x000a103c,0x00054e75,0x103c0003,0x4e752f01 + .long 0x08280007,0x000056e8,0x00023228,0x00000241 + .long 0x7fff9240,0x31410000,0x2f08202f,0x00040240 + .long 0x00c0e848,0x61ffffff,0xfae22057,0x322f0006 + .long 0x024100c0,0xe8494841,0x322f0006,0x02410030 + .long 0xe84961ff,0xfffffc22,0x205f08a8,0x00070000 + .long 0x4a280002,0x670a08e8,0x00070000,0x42280002 + .long 0x42804aa8,0x0004660a,0x4aa80008,0x660408c0 + .long 0x0002082e,0x0001ff66,0x670608ee,0x0005ff67 + .long 0x588f4e75,0x2f010828,0x00070000,0x56e80002 + .long 0x32280000,0x02417fff,0x92403141,0x00002f08 + .long 0x428061ff,0xfffffa64,0x2057323c,0x00044841 + .long 0x322f0006,0x02410030,0xe84961ff,0xfffffbaa + .long 0x205f08a8,0x00070000,0x4a280002,0x670a08e8 + .long 0x00070000,0x42280002,0x42804aa8,0x0004660a + .long 0x4aa80008,0x660408c0,0x0002082e,0x0001ff66 + .long 0x670608ee,0x0005ff67,0x588f4e75,0x02410010 + .long 0xe8088200,0x3001e309,0x600e0241,0x00108200 + .long 0x48408200,0x3001e309,0x103b0008,0x41fb1620 + .long 0x4e750200,0x00020200,0x00020200,0x00020000 + .long 0x00000a08,0x0a080a08,0x0a080a08,0x0a087fff + .long 0x00000000,0x00000000,0x00000000,0x00007ffe + .long 0x0000ffff,0xffffffff,0xffff0000,0x00007ffe + .long 0x0000ffff,0xffffffff,0xffff0000,0x00007fff + .long 0x00000000,0x00000000,0x00000000,0x00007fff + .long 0x00000000,0x00000000,0x00000000,0x0000407e + .long 0x0000ffff,0xff000000,0x00000000,0x0000407e + .long 0x0000ffff,0xff000000,0x00000000,0x00007fff + .long 0x00000000,0x00000000,0x00000000,0x00007fff + .long 0x00000000,0x00000000,0x00000000,0x000043fe + .long 0x0000ffff,0xffffffff,0xf8000000,0x000043fe + .long 0x0000ffff,0xffffffff,0xf8000000,0x00007fff + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x0000ffff + .long 0x00000000,0x00000000,0x00000000,0x0000fffe + .long 0x0000ffff,0xffffffff,0xffff0000,0x0000ffff + .long 0x00000000,0x00000000,0x00000000,0x0000fffe + .long 0x0000ffff,0xffffffff,0xffff0000,0x0000ffff + .long 0x00000000,0x00000000,0x00000000,0x0000c07e + .long 0x0000ffff,0xff000000,0x00000000,0x0000ffff + .long 0x00000000,0x00000000,0x00000000,0x0000c07e + .long 0x0000ffff,0xff000000,0x00000000,0x0000ffff + .long 0x00000000,0x00000000,0x00000000,0x0000c3fe + .long 0x0000ffff,0xffffffff,0xf8000000,0x0000ffff + .long 0x00000000,0x00000000,0x00000000,0x0000c3fe + .long 0x0000ffff,0xffffffff,0xf8000000,0x0000700c + .long 0x61ffffff,0xe82c43ee,0xff6c700c,0x61ffffff + .long 0x38664a81,0x66ff0000,0x0a14e9ee,0x004fff6c + .long 0x0c407fff,0x66024e75,0x102eff6f,0x0200000f + .long 0x660e4aae,0xff706608,0x4aaeff74,0x66024e75 + .long 0x41eeff6c,0x61ff0000,0x001cf22e,0xf080ff6c + .long 0x4e750000,0x00000203,0x02030203,0x03020302 + .long 0x02032d68,0x0000ff84,0x2d680004,0xff882d68 + .long 0x0008ff8c,0x41eeff84,0x48e73c00,0xf227e001 + .long 0x74027604,0x28104281,0x4c3c1001,0x0000000a + .long 0xe9c408c4,0xd2805803,0x51caffee,0x0804001e + .long 0x67024481,0x04810000,0x00106c0e,0x44810084 + .long 0x40000000,0x00904000,0x00002f01,0x7201f23c + .long 0x44000000,0x0000e9d0,0x0704f200,0x58222830 + .long 0x1c007600,0x7407f23c,0x44234120,0x0000e9c4 + .long 0x08c4f200,0x58225803,0x51caffec,0x52810c81 + .long 0x00000002,0x6fd80810,0x001f6704,0xf200001a + .long 0x22170c81,0x0000001b,0x6f0000e4,0x0810001e + .long 0x66744281,0x2810e9c4,0x07046624,0x52817a01 + .long 0x28305c00,0x66085081,0x52852830,0x5c004283 + .long 0x7407e9c4,0x08c46608,0x58835281,0x51cafff4 + .long 0x20012217,0x92806c10,0x44812810,0x00844000 + .long 0x00000090,0x40000000,0x43fb0170,0x00000666 + .long 0x4283f23c,0x44803f80,0x00007403,0xe2806406 + .long 0xf23148a3,0x38000683,0x0000000c,0x4a8066ec + .long 0xf2000423,0x60684281,0x7a022830,0x5c006608 + .long 0x53855081,0x28305c00,0x761c7407,0xe9c408c4 + .long 0x66085983,0x528151ca,0xfff42001,0x22179280 + .long 0x6e104481,0x28100284,0xbfffffff,0x0290bfff + .long 0xffff43fb,0x01700000,0x05fc4283,0xf23c4480 + .long 0x3f800000,0x7403e280,0x6406f231,0x48a33800 + .long 0x06830000,0x000c4a80,0x66ecf200,0x0420262e + .long 0xff60e9c3,0x26822810,0xe582e9c4,0x0002d480 + .long 0x43fafe50,0x10312800,0x4283efc3,0x0682f203 + .long 0x9000e280,0x640a43fb,0x01700000,0x06446016 + .long 0xe280640a,0x43fb0170,0x000006d2,0x600843fb + .long 0x01700000,0x05902001,0x6a084480,0x00904000 + .long 0x00004283,0xf23c4480,0x3f800000,0xe2806406 + .long 0xf23148a3,0x38000683,0x0000000c,0x4a8066ec + .long 0x0810001e,0x6706f200,0x04206004,0xf2000423 + .long 0xf200a800,0x08800009,0x6706006e,0x0108ff66 + .long 0x588ff21f,0xd0404cdf,0x003cf23c,0x90000000 + .long 0x0000f23c,0x88000000,0x00004e75,0x3ffd0000 + .long 0x9a209a84,0xfbcff798,0x00000000,0x3ffd0000 + .long 0x9a209a84,0xfbcff799,0x00000000,0x3f800000 + .long 0x00000000,0x00000000,0x00000000,0x40000000 + .long 0x00000000,0x00000000,0x00000000,0x41200000 + .long 0x00000000,0x00000000,0x00000000,0x459a2800 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x03030202,0x03020203,0x02030302,0x48e73f20 + .long 0xf227e007,0xf23c9000,0x00000020,0x2d50ff58 + .long 0x2e00422e,0xff500c2e,0x0004ff4e,0x66000030 + .long 0x30100240,0x7fff2228,0x00042428,0x00085340 + .long 0xe38ae391,0x4a816cf6,0x4a406e04,0x50eeff50 + .long 0x02407fff,0x30802141,0x00042142,0x00082d50 + .long 0xff902d68,0x0004ff94,0x2d680008,0xff9802ae + .long 0x7fffffff,0xff904a2e,0xff506708,0x2c3cffff + .long 0xecbb6038,0x302eff90,0x3d7c3fff,0xff90f22e + .long 0x4800ff90,0x04403fff,0xf2005022,0xf23a4428 + .long 0xff1cf293,0x000ef23a,0x4823ff02,0xf2066000 + .long 0x600af23a,0x4823fee6,0xf2066000,0xf23c8800 + .long 0x00000000,0x42454a87,0x6f042807,0x60062806 + .long 0x98875284,0x4a846f18,0x0c840000,0x00116f12 + .long 0x78114a87,0x6f0c00ae,0x00002080,0xff646002 + .long 0x78014a87,0x6e06be86,0x6d022c07,0x20065280 + .long 0x90844845,0x42454242,0x4a806c14,0x52450c80 + .long 0xffffecd4,0x6e080680,0x00000018,0x74184480 + .long 0xf23a4480,0xfe98e9ee,0x1682ff60,0xe349d245 + .long 0xe3494aae,0xff586c02,0x528145fa,0xfec01632 + .long 0x1800e98b,0xf2039000,0xe88b4a03,0x660a43fb + .long 0x01700000,0x03706016,0xe20b640a,0x43fb0170 + .long 0x000003fe,0x600843fb,0x01700000,0x04904283 + .long 0xe2886406,0xf23148a3,0x38000683,0x0000000c + .long 0x4a8066ec,0xf23c8800,0x00000000,0xf23c9000 + .long 0x00000010,0xf2104800,0xf2000018,0x4a456608 + .long 0xf2000420,0x6000008e,0x4a2eff50,0x67000072 + .long 0xf227e002,0x36170243,0x7fff0050,0x8000d650 + .long 0x04433fff,0xd6690024,0x04433fff,0xd6690030 + .long 0x04433fff,0x6b000048,0x02578000,0x87570250 + .long 0x7fff2f28,0x00082f28,0x00042f3c,0x3fff0000 + .long 0xf21fd080,0xf21f4823,0x2f29002c,0x2f290028 + .long 0x2f3c3fff,0x00002f29,0x00382f29,0x00342f3c + .long 0x3fff0000,0xf21f4823,0xf21f4823,0x601660fe + .long 0x4a42670c,0xf2294823,0x0024f229,0x48230030 + .long 0xf2000423,0xf200a800,0xf22e6800,0xff9045ee + .long 0xff900800,0x0009670e,0x00aa0000,0x00010008 + .long 0xf22e4800,0xff902d6e,0xff60ff54,0x02ae0000 + .long 0x0030ff60,0x48e7c0c0,0x2f2eff54,0x2f2eff58 + .long 0x41eeff90,0xf2106800,0x4aaeff58,0x6c060090 + .long 0x80000000,0x2f2eff64,0xf22e9000,0xff60f23c + .long 0x88000000,0x0000f22e,0x4801ff90,0xf200a800 + .long 0x816eff66,0x1d57ff64,0x588f2d5f,0xff582d5f + .long 0xff544cdf,0x03032d6e,0xff58ff90,0x2d6eff54 + .long 0xff604845,0x4a4566ff,0x00000086,0xf23a4500 + .long 0xfcec2004,0x53804283,0xe2886406,0xf2314923 + .long 0x38000683,0x0000000c,0x4a8066ec,0x4a2eff50 + .long 0x670af200,0x001860ff,0x00000028,0xf2000018 + .long 0xf2000838,0xf293001a,0x53863a3c,0x0001f23c + .long 0x90000000,0x0020f23a,0x4523fcc2,0x6000fda8 + .long 0xf23a4523,0xfcb8f200,0x0838f294,0x005cf292 + .long 0x000cf23a,0x4420fca6,0x5286604c,0x52863a3c + .long 0x0001f23c,0x90000000,0x00206000,0xfd7af23a + .long 0x4500fc6a,0x20044283,0xe2886406,0xf2314923 + .long 0x38000683,0x0000000c,0x4a8066ec,0xf2000018 + .long 0xf2000838,0xf28e0012,0xf23a4420,0xfc605286 + .long 0x5284f23a,0x4523fc56,0xf23c9000,0x00000010 + .long 0xf2000820,0x41eeff84,0xf2106800,0x24280004 + .long 0x26280008,0x42a80004,0x42a80008,0x20104840 + .long 0x67140480,0x00003ffd,0x4a806e0a,0x4480e28a + .long 0xe29351c8,0xfffa4a82,0x66044a83,0x67104281 + .long 0x06830000,0x0080d581,0x0283ffff,0xff802004 + .long 0x568861ff,0x000002b0,0x4a2eff50,0x6728f200 + .long 0x003af281,0x000cf206,0x4000f200,0x0018602e + .long 0x4a876d08,0xf23a4400,0xfbe46022,0xf2064000 + .long 0xf2000018,0x6018f200,0x003af28e,0x000af23a + .long 0x4400fb9a,0x6008f206,0x4000f200,0x0018f229 + .long 0x48200018,0xf22e6800,0xff90242a,0x0004262a + .long 0x00083012,0x670e0440,0x3ffd4440,0xe28ae293 + .long 0x51c8fffa,0x42810683,0x00000080,0xd5810283 + .long 0xffffff80,0x700441ee,0xff5461ff,0x00000228 + .long 0x202eff54,0x720ce2a8,0xefee010c,0xff84e2a8 + .long 0xefee0404,0xff844a00,0x670800ae,0x00002080 + .long 0xff644280,0x022e000f,0xff844aae,0xff586c02 + .long 0x70024a86,0x6c025280,0xefee0002,0xff84f23c + .long 0x88000000,0x0000f21f,0xd0e04cdf,0x04fc4e75 + .long 0x40020000,0xa0000000,0x00000000,0x40050000 + .long 0xc8000000,0x00000000,0x400c0000,0x9c400000 + .long 0x00000000,0x40190000,0xbebc2000,0x00000000 + .long 0x40340000,0x8e1bc9bf,0x04000000,0x40690000 + .long 0x9dc5ada8,0x2b70b59e,0x40d30000,0xc2781f49 + .long 0xffcfa6d5,0x41a80000,0x93ba47c9,0x80e98ce0 + .long 0x43510000,0xaa7eebfb,0x9df9de8e,0x46a30000 + .long 0xe319a0ae,0xa60e91c7,0x4d480000,0xc9767586 + .long 0x81750c17,0x5a920000,0x9e8b3b5d,0xc53d5de5 + .long 0x75250000,0xc4605202,0x8a20979b,0x40020000 + .long 0xa0000000,0x00000000,0x40050000,0xc8000000 + .long 0x00000000,0x400c0000,0x9c400000,0x00000000 + .long 0x40190000,0xbebc2000,0x00000000,0x40340000 + .long 0x8e1bc9bf,0x04000000,0x40690000,0x9dc5ada8 + .long 0x2b70b59e,0x40d30000,0xc2781f49,0xffcfa6d6 + .long 0x41a80000,0x93ba47c9,0x80e98ce0,0x43510000 + .long 0xaa7eebfb,0x9df9de8e,0x46a30000,0xe319a0ae + .long 0xa60e91c7,0x4d480000,0xc9767586,0x81750c18 + .long 0x5a920000,0x9e8b3b5d,0xc53d5de5,0x75250000 + .long 0xc4605202,0x8a20979b,0x40020000,0xa0000000 + .long 0x00000000,0x40050000,0xc8000000,0x00000000 + .long 0x400c0000,0x9c400000,0x00000000,0x40190000 + .long 0xbebc2000,0x00000000,0x40340000,0x8e1bc9bf + .long 0x04000000,0x40690000,0x9dc5ada8,0x2b70b59d + .long 0x40d30000,0xc2781f49,0xffcfa6d5,0x41a80000 + .long 0x93ba47c9,0x80e98cdf,0x43510000,0xaa7eebfb + .long 0x9df9de8d,0x46a30000,0xe319a0ae,0xa60e91c6 + .long 0x4d480000,0xc9767586,0x81750c17,0x5a920000 + .long 0x9e8b3b5d,0xc53d5de4,0x75250000,0xc4605202 + .long 0x8a20979a,0x48e7ff00,0x7e015380,0x28022a03 + .long 0xe9c21003,0xe782e9c3,0x6003e783,0x8486e385 + .long 0xe3944846,0xd346d685,0x4e71d584,0x4e71d346 + .long 0x48464a47,0x67124847,0xe947de41,0x10c74847 + .long 0x424751c8,0xffc86012,0x48473e01,0x48475247 + .long 0x51c8ffba,0x4847e94f,0x10c74cdf,0x00ff4e75 + .long 0x70016100,0x00d63d7c,0x0121000a,0x6000007e + .long 0x70026100,0x00c63d7c,0x0141000a,0x606e7004 + .long 0x610000b8,0x3d7c0101,0x000a6060,0x70086100 + .long 0x00aa3d7c,0x0161000a,0x6052700c,0x6100009c + .long 0x3d7c0161,0x000a6044,0x70016100,0x008e3d7c + .long 0x00a1000a,0x60367002,0x61000080,0x3d7c00c1 + .long 0x000a6028,0x70046100,0x00723d7c,0x0081000a + .long 0x601a7008,0x61000064,0x3d7c00e1,0x000a600c + .long 0x700c6100,0x00563d7c,0x00e1000a,0x2d6eff68 + .long 0x0006f22e,0xd0c0ffdc,0xf22e9c00,0xff604cee + .long 0x0303ff9c,0x4e5e2f17,0x2f6f0008,0x00042f6f + .long 0x000c0008,0x2f7c0000,0x0001000c,0x3f6f0006 + .long 0x000c3f7c,0x40080006,0x08170005,0x670608ef + .long 0x0002000d,0x60ffffff,0x2d82122e,0xff410201 + .long 0x00380c01,0x00186700,0x000c0c01,0x00206700 + .long 0x00604e75,0x122eff41,0x02410007,0x323b1206 + .long 0x4efb1002,0x00100016,0x001c0020,0x00240028 + .long 0x002c0030,0x91aeffa4,0x4e7591ae,0xffa84e75 + .long 0x95c04e75,0x97c04e75,0x99c04e75,0x9bc04e75 + .long 0x91964e75,0x0c2e0030,0x000a6612,0x082e0005 + .long 0x0004660a,0x4e7a8800,0x91c04e7b,0x88004e75 + .long 0x448060a0,0x00000000,0x00000000,0x00000000 diff --git a/arch/m68k/ifpsp060/fskeleton.S b/arch/m68k/ifpsp060/fskeleton.S new file mode 100644 index 000000000..0a1ae4f44 --- /dev/null +++ b/arch/m68k/ifpsp060/fskeleton.S @@ -0,0 +1,342 @@ +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +|MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP +|M68000 Hi-Performance Microprocessor Division +|M68060 Software Package +|Production Release P1.00 -- October 10, 1994 +| +|M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. +| +|THE SOFTWARE is provided on an "AS IS" basis and without warranty. +|To the maximum extent permitted by applicable law, +|MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, +|INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE +|and any warranty against infringement with regard to the SOFTWARE +|(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. +| +|To the maximum extent permitted by applicable law, +|IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +|(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, +|BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) +|ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. +|Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. +| +|You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE +|so long as this entire notice is retained without alteration in any modified and/or +|redistributed versions, and that such modified versions are clearly identified as such. +|No licenses are granted by implication, estoppel or otherwise under any patents +|or trademarks of Motorola, Inc. +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| fskeleton.s +| +| This file contains: +| (1) example "Call-out"s +| (2) example package entry code +| (3) example "Call-out" table +| + +#include + +|################################ +| (1) EXAMPLE CALL-OUTS # +| # +| _060_fpsp_done() # +| _060_real_ovfl() # +| _060_real_unfl() # +| _060_real_operr() # +| _060_real_snan() # +| _060_real_dz() # +| _060_real_inex() # +| _060_real_bsun() # +| _060_real_fline() # +| _060_real_fpu_disabled() # +| _060_real_trap() # +|################################ + +| +| _060_fpsp_done(): +| +| This is the main exit point for the 68060 Floating-Point +| Software Package. For a normal exit, all 060FPSP routines call this +| routine. The operating system can do system dependent clean-up or +| simply execute an "rte" as with the sample code below. +| + .global _060_fpsp_done +_060_fpsp_done: + bral _060_isp_done | do the same as isp_done + +| +| _060_real_ovfl(): +| +| This is the exit point for the 060FPSP when an enabled overflow exception +| is present. The routine below should point to the operating system handler +| for enabled overflow conditions. The exception stack frame is an overflow +| stack frame. The FP state frame holds the EXCEPTIONAL OPERAND. +| +| The sample routine below simply clears the exception status bit and +| does an "rte". +| + .global _060_real_ovfl +_060_real_ovfl: + fsave -(%sp) + move.w #0x6000,0x2(%sp) + frestore (%sp)+ + bral trap | jump to trap handler + + +| +| _060_real_unfl(): +| +| This is the exit point for the 060FPSP when an enabled underflow exception +| is present. The routine below should point to the operating system handler +| for enabled underflow conditions. The exception stack frame is an underflow +| stack frame. The FP state frame holds the EXCEPTIONAL OPERAND. +| +| The sample routine below simply clears the exception status bit and +| does an "rte". +| + .global _060_real_unfl +_060_real_unfl: + fsave -(%sp) + move.w #0x6000,0x2(%sp) + frestore (%sp)+ + bral trap | jump to trap handler + +| +| _060_real_operr(): +| +| This is the exit point for the 060FPSP when an enabled operand error exception +| is present. The routine below should point to the operating system handler +| for enabled operand error exceptions. The exception stack frame is an operand error +| stack frame. The FP state frame holds the source operand of the faulting +| instruction. +| +| The sample routine below simply clears the exception status bit and +| does an "rte". +| + .global _060_real_operr +_060_real_operr: + fsave -(%sp) + move.w #0x6000,0x2(%sp) + frestore (%sp)+ + bral trap | jump to trap handler + +| +| _060_real_snan(): +| +| This is the exit point for the 060FPSP when an enabled signalling NaN exception +| is present. The routine below should point to the operating system handler +| for enabled signalling NaN exceptions. The exception stack frame is a signalling NaN +| stack frame. The FP state frame holds the source operand of the faulting +| instruction. +| +| The sample routine below simply clears the exception status bit and +| does an "rte". +| + .global _060_real_snan +_060_real_snan: + fsave -(%sp) + move.w #0x6000,0x2(%sp) + frestore (%sp)+ + bral trap | jump to trap handler + +| +| _060_real_dz(): +| +| This is the exit point for the 060FPSP when an enabled divide-by-zero exception +| is present. The routine below should point to the operating system handler +| for enabled divide-by-zero exceptions. The exception stack frame is a divide-by-zero +| stack frame. The FP state frame holds the source operand of the faulting +| instruction. +| +| The sample routine below simply clears the exception status bit and +| does an "rte". +| + .global _060_real_dz +_060_real_dz: + fsave -(%sp) + move.w #0x6000,0x2(%sp) + frestore (%sp)+ + bral trap | jump to trap handler + +| +| _060_real_inex(): +| +| This is the exit point for the 060FPSP when an enabled inexact exception +| is present. The routine below should point to the operating system handler +| for enabled inexact exceptions. The exception stack frame is an inexact +| stack frame. The FP state frame holds the source operand of the faulting +| instruction. +| +| The sample routine below simply clears the exception status bit and +| does an "rte". +| + .global _060_real_inex +_060_real_inex: + fsave -(%sp) + move.w #0x6000,0x2(%sp) + frestore (%sp)+ + bral trap | jump to trap handler + +| +| _060_real_bsun(): +| +| This is the exit point for the 060FPSP when an enabled bsun exception +| is present. The routine below should point to the operating system handler +| for enabled bsun exceptions. The exception stack frame is a bsun +| stack frame. +| +| The sample routine below clears the exception status bit, clears the NaN +| bit in the FPSR, and does an "rte". The instruction that caused the +| bsun will now be re-executed but with the NaN FPSR bit cleared. +| + .global _060_real_bsun +_060_real_bsun: +| fsave -(%sp) + + fmove.l %fpsr,-(%sp) + andi.b #0xfe,(%sp) + fmove.l (%sp)+,%fpsr + + bral trap | jump to trap handler + +| +| _060_real_fline(): +| +| This is the exit point for the 060FPSP when an F-Line Illegal exception is +| encountered. Three different types of exceptions can enter the F-Line exception +| vector number 11: FP Unimplemented Instructions, FP implemented instructions when +| the FPU is disabled, and F-Line Illegal instructions. The 060FPSP module +| _fpsp_fline() distinguishes between the three and acts appropriately. F-Line +| Illegals branch here. +| + .global _060_real_fline +_060_real_fline: + bral trap | jump to trap handler + +| +| _060_real_fpu_disabled(): +| +| This is the exit point for the 060FPSP when an FPU disabled exception is +| encountered. Three different types of exceptions can enter the F-Line exception +| vector number 11: FP Unimplemented Instructions, FP implemented instructions when +| the FPU is disabled, and F-Line Illegal instructions. The 060FPSP module +| _fpsp_fline() distinguishes between the three and acts appropriately. FPU disabled +| exceptions branch here. +| +| The sample code below enables the FPU, sets the PC field in the exception stack +| frame to the PC of the instruction causing the exception, and does an "rte". +| The execution of the instruction then proceeds with an enabled floating-point +| unit. +| + .global _060_real_fpu_disabled +_060_real_fpu_disabled: + move.l %d0,-(%sp) | enabled the fpu + .long 0x4E7A0808 |movec pcr,%d0 + bclr #0x1,%d0 + .long 0x4E7B0808 |movec %d0,pcr + move.l (%sp)+,%d0 + + move.l 0xc(%sp),0x2(%sp) | set "Current PC" + rte + +| +| _060_real_trap(): +| +| This is the exit point for the 060FPSP when an emulated "ftrapcc" instruction +| discovers that the trap condition is true and it should branch to the operating +| system handler for the trap exception vector number 7. +| +| The sample code below simply executes an "rte". +| + .global _060_real_trap +_060_real_trap: + bral trap | jump to trap handler + +|############################################################################ + +|################################# +| (2) EXAMPLE PACKAGE ENTRY CODE # +|################################# + + .global _060_fpsp_snan +_060_fpsp_snan: + bra.l _FP_CALL_TOP+0x80+0x00 + + .global _060_fpsp_operr +_060_fpsp_operr: + bra.l _FP_CALL_TOP+0x80+0x08 + + .global _060_fpsp_ovfl +_060_fpsp_ovfl: + bra.l _FP_CALL_TOP+0x80+0x10 + + .global _060_fpsp_unfl +_060_fpsp_unfl: + bra.l _FP_CALL_TOP+0x80+0x18 + + .global _060_fpsp_dz +_060_fpsp_dz: + bra.l _FP_CALL_TOP+0x80+0x20 + + .global _060_fpsp_inex +_060_fpsp_inex: + bra.l _FP_CALL_TOP+0x80+0x28 + + .global _060_fpsp_fline +_060_fpsp_fline: + bra.l _FP_CALL_TOP+0x80+0x30 + + .global _060_fpsp_unsupp +_060_fpsp_unsupp: + bra.l _FP_CALL_TOP+0x80+0x38 + + .global _060_fpsp_effadd +_060_fpsp_effadd: + bra.l _FP_CALL_TOP+0x80+0x40 + +|############################################################################ + +|############################### +| (3) EXAMPLE CALL-OUT SECTION # +|############################### + +| The size of this section MUST be 128 bytes!!! + +_FP_CALL_TOP: + .long _060_real_bsun - _FP_CALL_TOP + .long _060_real_snan - _FP_CALL_TOP + .long _060_real_operr - _FP_CALL_TOP + .long _060_real_ovfl - _FP_CALL_TOP + .long _060_real_unfl - _FP_CALL_TOP + .long _060_real_dz - _FP_CALL_TOP + .long _060_real_inex - _FP_CALL_TOP + .long _060_real_fline - _FP_CALL_TOP + .long _060_real_fpu_disabled - _FP_CALL_TOP + .long _060_real_trap - _FP_CALL_TOP + .long _060_real_trace - _FP_CALL_TOP + .long _060_real_access - _FP_CALL_TOP + .long _060_fpsp_done - _FP_CALL_TOP + + .long 0x00000000, 0x00000000, 0x00000000 + + .long _060_imem_read - _FP_CALL_TOP + .long _060_dmem_read - _FP_CALL_TOP + .long _060_dmem_write - _FP_CALL_TOP + .long _060_imem_read_word - _FP_CALL_TOP + .long _060_imem_read_long - _FP_CALL_TOP + .long _060_dmem_read_byte - _FP_CALL_TOP + .long _060_dmem_read_word - _FP_CALL_TOP + .long _060_dmem_read_long - _FP_CALL_TOP + .long _060_dmem_write_byte - _FP_CALL_TOP + .long _060_dmem_write_word - _FP_CALL_TOP + .long _060_dmem_write_long - _FP_CALL_TOP + + .long 0x00000000 + + .long 0x00000000, 0x00000000, 0x00000000, 0x00000000 + +|############################################################################ + +| 060 FPSP KERNEL PACKAGE NEEDS TO GO HERE!!! + +#include "fpsp.sa" diff --git a/arch/m68k/ifpsp060/ftest.sa b/arch/m68k/ifpsp060/ftest.sa new file mode 100644 index 000000000..b365bc2fd --- /dev/null +++ b/arch/m68k/ifpsp060/ftest.sa @@ -0,0 +1,371 @@ + dc.l $60ff0000,$00d40000,$60ff0000,$016c0000 + dc.l $60ff0000,$01a80000,$54657374,$696e6720 + dc.l $36383036,$30204650,$53502073,$74617274 + dc.l $65643a0a,$00546573,$74696e67,$20363830 + dc.l $36302046,$50535020,$756e696d,$706c656d + dc.l $656e7465,$6420696e,$73747275,$6374696f + dc.l $6e207374,$61727465,$643a0a00,$54657374 + dc.l $696e6720,$36383036,$30204650,$53502065 + dc.l $78636570,$74696f6e,$20656e61,$626c6564 + dc.l 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$2d7c3e66,$0000ff20,$2d7cd0ed,$23e8ff24 + dc.l $2d7cd140,$35bcff28,$2d7c0000,$0108feb8 + dc.l $41faffc2,$2d48febc,$61ff0000,$001e4a00 + dc.l $66ff0000,$004461ff,$00000046,$4a0066ff + dc.l $00000036,$42804e75,$41eeff80,$43eeffc0 + dc.l $700eb189,$66ff0000,$001c51c8,$fff6302e + dc.l $fea6322e,$fea4b041,$66ff0000,$00084280 + dc.l $4e757001,$4e75222e,$fea07001,$4e7541ee + dc.l $ff2043ee,$fec07017,$b18966ff,$0000002c + dc.l $51c8fff6,$41eefeb4,$43eefea8,$b18966ff + dc.l $00000018,$b18966ff,$00000010,$b18966ff + dc.l $00000008,$42804e75,$70014e75,$acacacac + dc.l $acacacac,$acacacac,$acacacac,$acacacac + dc.l $acacacac,$acacacac,$acacacac,$acacacac + dc.l $acacacac,$acacacac,$acacacac,$acacacac + dc.l $acacacac,$acacacac,$acacacac,$7fff0000 + dc.l $ffffffff,$ffffffff,$7fff0000,$ffffffff + dc.l $ffffffff,$7fff0000,$ffffffff,$ffffffff + dc.l $7fff0000,$ffffffff,$ffffffff,$7fff0000 + dc.l $ffffffff,$ffffffff,$7fff0000,$ffffffff + dc.l $ffffffff,$7fff0000,$ffffffff,$ffffffff + dc.l $7fff0000,$ffffffff,$ffffffff,$00000000 + dc.l $00000000,$00000000,$2f00203a,$e884487b + dc.l $0930ffff,$e880202f,$00044e74,$00042f00 + dc.l $203ae872,$487b0930,$ffffe86a,$202f0004 + dc.l $4e740004,$00000000,$00000000,$00000000 diff --git a/arch/m68k/ifpsp060/ilsp.doc b/arch/m68k/ifpsp060/ilsp.doc new file mode 100644 index 000000000..4e6292f09 --- /dev/null +++ b/arch/m68k/ifpsp060/ilsp.doc @@ -0,0 +1,150 @@ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP +M68000 Hi-Performance Microprocessor Division +M68060 Software Package +Production Release P1.00 -- October 10, 1994 + +M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. + +THE SOFTWARE is provided on an "AS IS" basis and without warranty. +To the maximum extent permitted by applicable law, +MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, +INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE +and any warranty against infringement with regard to the SOFTWARE +(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. + +To the maximum extent permitted by applicable law, +IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, +BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) +ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. +Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. + +You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE +so long as this entire notice is retained without alteration in any modified and/or +redistributed versions, and that such modified versions are clearly identified as such. +No licenses are granted by implication, estoppel or otherwise under any patents +or trademarks of Motorola, Inc. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +68060 INTEGER SOFTWARE PACKAGE (Library version) +------------------------------------------------- + +The file ilsp.s contains the "Library version" of the +68060 Integer Software Package. Routines included in this +module can be used to emulate 64-bit divide and multiply, +and the "cmp2" instruction. These instructions are not +implemented in hardware on the 68060 and normally take +exception vector #61 "Unimplemented Integer Instruction". + +By re-compiling a program that uses these instructions, and +making subroutine calls in place of the unimplemented +instructions, a program can avoid the overhead associated with +taking the exception. + +Release file format: +-------------------- +The file ilsp.sa is essentially a hexadecimal image of the +release package. This is the ONLY format which will be supported. +The hex image was created by assembling the source code and +then converting the resulting binary output image into an +ASCII text file. The hexadecimal numbers are listed +using the Motorola Assembly Syntax assembler directive "dc.l" +(define constant longword). The file can be converted to other +assembly syntaxes by using any word processor with a global +search and replace function. + +To assist in assembling and linking this module with other modules, +the installer should add a symbolic label to the top of the file. +This will allow calling routines to access the entry points +of this package. + +The source code ilsp.s has also been included but only for +documentation purposes. + +Release file structure: +----------------------- +The file ilsp.sa contains an "Entry-Point" section and a +code section. The ILSP has no "Call-Out" section. The first section +is the "Entry-Point" section. In order to access a function in the +package, a program must "bsr" or "jsr" to the location listed +below in "68060ILSP Entry Points" that corresponds to the desired +function. A branch instruction located at the selected entry point +within the package will then enter the correct emulation code routine. + +The entry point addresses at the beginning of the package will remain +fixed so that a program calling the routines will not have to be +re-compiled with every new 68060ILSP release. + +For example, to use a 64-bit multiply instruction, +do a "bsr" or "jsr" to the entry point defined by +the 060ILSP entry table. A compiler generated code sequence +for unsigned multiply could look like: + +# mulu.l ,Dh:Dl +# mulu.l _multiplier,%d1:%d0 + + subq.l &0x8,%sp # make room for result on stack + pea (%sp) # pass: result addr on stack + mov.l %d0,-(%sp) # pass: multiplicand on stack + mov.l _multiplier,-(%sp) # pass: multiplier on stack + bsr.l _060LISP_TOP+0x18 # branch to multiply routine + add.l &0xc,%sp # clear arguments from stack + mov.l (%sp)+,%d1 # load result[63:32] + mov.l (%sp)+,%d0 # load result[31:0] + +For a divide: + +# divu.l ,Dr:Dq +# divu.l _divisor,%d1:%d0 + + subq.l &0x8,%sp # make room for result on stack + pea (%sp) # pass: result addr on stack + mov.l %d0,-(%sp) # pass: dividend hi on stack + mov.l %d1,-(%sp) # pass: dividend hi on stack + mov.l _divisor,-(%sp) # pass: divisor on stack + bsr.l _060LISP_TOP+0x08 # branch to divide routine + add.l &0xc,%sp # clear arguments from stack + mov.l (%sp)+,%d1 # load remainder + mov.l (%sp)+,%d0 # load quotient + +The library routines also return the correct condition code +register value. If this is important, then the caller of the library +routine must make sure that the value isn't lost while popping +other items off of the stack. + +An example of using the "cmp2" instruction is as follows: + +# cmp2.l ,Rn +# cmp2.l _bounds,%d0 + + pea _bounds # pass ptr to bounds + mov.l %d0,-(%sp) # pass Rn + bsr.l _060LSP_TOP_+0x48 # branch to "cmp2" routine + mov.w %cc,_tmp # save off condition codes + addq.l &0x8,%sp # clear arguments from stack + +Exception reporting: +-------------------- +If the instruction being emulated is a divide and the source +operand is a zero, then the library routine, as its last +instruction, executes an implemented divide using a zero +source operand so that an "Integer Divide-by-Zero" exception +will be taken. Although the exception stack frame will not +point to the correct instruction, the user will at least be able +to record that such an event occurred if desired. + +68060ILSP entry points: +----------------------- +_060ILSP_TOP: +0x000: _060LSP__idivs64_ +0x008: _060LSP__idivu64_ + +0x010: _060LSP__imuls64_ +0x018: _060LSP__imulu64_ + +0x020: _060LSP__cmp2_Ab_ +0x028: _060LSP__cmp2_Aw_ +0x030: _060LSP__cmp2_Al_ +0x038: _060LSP__cmp2_Db_ +0x040: _060LSP__cmp2_Dw_ +0x048: _060LSP__cmp2_Dl_ diff --git a/arch/m68k/ifpsp060/ilsp.sa b/arch/m68k/ifpsp060/ilsp.sa new file mode 100644 index 000000000..2757d502b --- /dev/null +++ b/arch/m68k/ifpsp060/ilsp.sa @@ -0,0 +1,101 @@ + dc.l $60ff0000,$01fe0000,$60ff0000,$02080000 + dc.l $60ff0000,$04900000,$60ff0000,$04080000 + dc.l $60ff0000,$051e0000,$60ff0000,$053c0000 + dc.l $60ff0000,$055a0000,$60ff0000,$05740000 + dc.l $60ff0000,$05940000,$60ff0000,$05b40000 + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $4e56fff0,$48e73f00,$42eefff0,$50eeffff + dc.l $60104e56,$fff048e7,$3f0042ee,$fff051ee + dc.l $ffff2e2e,$00086700,$00ae2a2e,$000c2c2e + dc.l $00104a2e,$ffff671a,$4a875dee,$fffe6a02 + dc.l $44874a85,$5deefffd,$6a0844fc,$00004086 + dc.l $40854a85,$66164a86,$67000046,$be866306 + dc.l $cb466000,$00124c47,$6005600a,$be85634c + dc.l $61ff0000,$00864a2e,$ffff6724,$4a2efffd + dc.l $67024485,$102efffe,$b12efffd,$670c0c86 + dc.l $80000000,$62264486,$60060806,$001f661c + dc.l $026e0010,$fff044ee,$fff04a86,$48f60060 + dc.l $01610014,$4cdf00fc,$4e5e4e75,$2a2e000c + dc.l $2c2e0010,$026e001c,$fff0006e,$0002fff0 + dc.l $44eefff0,$60d62dae,$000c0161,$00142dae + dc.l $00100162,$00140004,$44eefff0,$4cdf00fc + dc.l $4e5e80fc,$00004e75,$0c870000,$ffff621e + dc.l $42814845,$48463a06,$8ac73205,$48463a06 + dc.l $8ac74841,$32054245,$48452c01,$4e7542ae + dc.l $fff8422e,$fffc4281,$0807001f,$660e52ae + dc.l $fff8e38f,$e38ee395,$6000ffee,$26072405 + dc.l $48424843,$b4436606,$323cffff,$600a2205 + dc.l $82c30281,$0000ffff,$2f064246,$48462607 + dc.l $2401c4c7,$4843c6c1,$28059883,$48443004 + dc.l $38064a40,$6600000a,$b4846304,$538160de + dc.l $2f052c01,$48462a07,$61ff0000,$006a2405 + dc.l $26062a1f,$2c1f9c83,$9b8264ff,$0000001a + dc.l $53814282,$26074843,$4243dc83,$db822607 + dc.l $42434843,$da834a2e,$fffc6616,$3d41fff4 + dc.l $42814845,$48463a06,$424650ee,$fffc6000 + dc.l $ff6c3d41,$fff63c05,$48464845,$2e2efff8 + dc.l $670a5387,$e28de296,$51cffffa,$2a062c2e + dc.l $fff44e75,$24062606,$28054843,$4844ccc5 + dc.l $cac3c4c4,$c6c44284,$4846dc45,$d744dc42 + dc.l $d7444846,$42454242,$48454842,$da82da83 + dc.l $4e754e56,$fffc48e7,$380042ee,$fffc202e + dc.l $00086700,$005a222e,$000c6700,$00522400 + dc.l $26002801,$48434844,$c0c1c2c3,$c4c4c6c4 + dc.l $42844840,$d041d784,$d042d784,$48404241 + dc.l $42424841,$4842d282,$d283382e,$fffc0204 + dc.l $00104a81,$6a040004,$000844c4,$c34048f6 + dc.l $00030161,$00104cdf,$001c4e5e,$4e754280 + dc.l $4281382e,$fffc0204,$00100004,$000444c4 + dc.l $60da4e56,$fffc48e7,$3c0042ee,$fffc202e + dc.l $000867da,$222e000c,$67d44205,$4a806c06 + dc.l $44800005,$00014a81,$6c064481,$0a050001 + dc.l $24002600,$28014843,$4844c0c1,$c2c3c4c4 + dc.l $c6c44284,$4840d041,$d784d042,$d7844840 + dc.l $42414242,$48414842,$d282d283,$4a056708 + dc.l $46804681,$5280d384,$382efffc,$02040010 + dc.l $4a816a04,$00040008,$44c4c340,$48f60003 + dc.l $01610010,$4cdf003c,$4e5e4e75,$42804281 + dc.l $382efffc,$02040010,$00040004,$44c460da + dc.l $4e56fffc,$48e73800,$42eefffc,$242e0008 + dc.l $10360161,$000c1236,$0162000c,$000149c0 + dc.l $49c16000,$00b84e56,$fffc48e7,$380042ee + dc.l $fffc242e,$00083036,$0161000c,$32360162 + dc.l $000c0002,$48c048c1,$60000092,$4e56fffc + dc.l $48e73800,$42eefffc,$242e0008,$20360161 + dc.l $000c2236,$0162000c,$00046000,$00704e56 + dc.l $fffc48e7,$380042ee,$fffc242e,$00081036 + dc.l $0161000c,$12360162,$000c0001,$49c049c1 + dc.l $49c26000,$00484e56,$fffc48e7,$380042ee + dc.l $fffc242e,$00083036,$0161000c,$32360162 + dc.l $000c0002,$48c048c1,$48c26000,$00204e56 + dc.l $fffc48e7,$380042ee,$fffc242e,$00082036 + dc.l $0161000c,$22360162,$000c0004,$948042c3 + dc.l $02030004,$9280b282,$42c48604,$02030005 + dc.l $382efffc,$0204001a,$880344c4,$4cdf001c + dc.l $4e5e4e75,$00000000,$00000000,$00000000 diff --git a/arch/m68k/ifpsp060/iskeleton.S b/arch/m68k/ifpsp060/iskeleton.S new file mode 100644 index 000000000..91a9c65fe --- /dev/null +++ b/arch/m68k/ifpsp060/iskeleton.S @@ -0,0 +1,347 @@ +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +|MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP +|M68000 Hi-Performance Microprocessor Division +|M68060 Software Package +|Production Release P1.00 -- October 10, 1994 +| +|M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. +| +|THE SOFTWARE is provided on an "AS IS" basis and without warranty. +|To the maximum extent permitted by applicable law, +|MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, +|INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE +|and any warranty against infringement with regard to the SOFTWARE +|(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. +| +|To the maximum extent permitted by applicable law, +|IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +|(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, +|BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) +|ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. +|Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. +| +|You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE +|so long as this entire notice is retained without alteration in any modified and/or +|redistributed versions, and that such modified versions are clearly identified as such. +|No licenses are granted by implication, estoppel or otherwise under any patents +|or trademarks of Motorola, Inc. +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| iskeleton.s +| +| This file contains: +| (1) example "Call-out"s +| (2) example package entry code +| (3) example "Call-out" table +| + +#include +#include +#include + + +|################################ +| (1) EXAMPLE CALL-OUTS # +| # +| _060_isp_done() # +| _060_real_chk() # +| _060_real_divbyzero() # +| # +| _060_real_cas() # +| _060_real_cas2() # +| _060_real_lock_page() # +| _060_real_unlock_page() # +|################################ + +| +| _060_isp_done(): +| +| This is and example main exit point for the Unimplemented Integer +| Instruction exception handler. For a normal exit, the +| _isp_unimp() branches to here so that the operating system +| can do any clean-up desired. The stack frame is the +| Unimplemented Integer Instruction stack frame with +| the PC pointing to the instruction following the instruction +| just emulated. +| To simply continue execution at the next instruction, just +| do an "rte". +| +| Linux/68k: If returning to user space, check for needed reselections. + + .global _060_isp_done +_060_isp_done: + btst #0x5,%sp@ | supervisor bit set in saved SR? + beq .Lnotkern + rte +.Lnotkern: + SAVE_ALL_INT + GET_CURRENT(%d0) + | deliver signals, reschedule etc.. + jra ret_from_exception + +| +| _060_real_chk(): +| +| This is an alternate exit point for the Unimplemented Integer +| Instruction exception handler. If the instruction was a "chk2" +| and the operand was out of bounds, then _isp_unimp() creates +| a CHK exception stack frame from the Unimplemented Integer Instrcution +| stack frame and branches to this routine. +| +| Linux/68k: commented out test for tracing + + .global _060_real_chk +_060_real_chk: +| tst.b (%sp) | is tracing enabled? +| bpls real_chk_end | no + +| +| CHK FRAME TRACE FRAME +| ***************** ***************** +| * Current PC * * Current PC * +| ***************** ***************** +| * 0x2 * 0x018 * * 0x2 * 0x024 * +| ***************** ***************** +| * Next * * Next * +| * PC * * PC * +| ***************** ***************** +| * SR * * SR * +| ***************** ***************** +| +| move.b #0x24,0x7(%sp) | set trace vecno +| bral _060_real_trace + +real_chk_end: + bral trap | jump to trap handler + +| +| _060_real_divbyzero: +| +| This is an alternate exit point for the Unimplemented Integer +| Instruction exception handler isp_unimp(). If the instruction is a 64-bit +| integer divide where the source operand is a zero, then the _isp_unimp() +| creates a Divide-by-zero exception stack frame from the Unimplemented +| Integer Instruction stack frame and branches to this routine. +| +| Remember that a trace exception may be pending. The code below performs +| no action associated with the "chk" exception. If tracing is enabled, +| then it create a Trace exception stack frame from the "chk" exception +| stack frame and branches to the _real_trace() entry point. +| +| Linux/68k: commented out test for tracing + + .global _060_real_divbyzero +_060_real_divbyzero: +| tst.b (%sp) | is tracing enabled? +| bpls real_divbyzero_end | no + +| +| DIVBYZERO FRAME TRACE FRAME +| ***************** ***************** +| * Current PC * * Current PC * +| ***************** ***************** +| * 0x2 * 0x014 * * 0x2 * 0x024 * +| ***************** ***************** +| * Next * * Next * +| * PC * * PC * +| ***************** ***************** +| * SR * * SR * +| ***************** ***************** +| +| move.b #0x24,0x7(%sp) | set trace vecno +| bral _060_real_trace + +real_divbyzero_end: + bral trap | jump to trap handler + +|########################## + +| +| _060_real_cas(): +| +| Entry point for the selected cas emulation code implementation. +| If the implementation provided by the 68060ISP is sufficient, +| then this routine simply re-enters the package through _isp_cas. +| + .global _060_real_cas +_060_real_cas: + bral _I_CALL_TOP+0x80+0x08 + +| +| _060_real_cas2(): +| +| Entry point for the selected cas2 emulation code implementation. +| If the implementation provided by the 68060ISP is sufficient, +| then this routine simply re-enters the package through _isp_cas2. +| + .global _060_real_cas2 +_060_real_cas2: + bral _I_CALL_TOP+0x80+0x10 + +| +| _060_lock_page(): +| +| Entry point for the operating system`s routine to "lock" a page +| from being paged out. This routine is needed by the cas/cas2 +| algorithms so that no page faults occur within the "core" code +| region. Note: the routine must lock two pages if the operand +| spans two pages. +| NOTE: THE ROUTINE SHOULD RETURN AN FSLW VALUE IN D0 ON FAILURE +| SO THAT THE 060SP CAN CREATE A PROPER ACCESS ERROR FRAME. +| Arguments: +| a0 = operand address +| d0 = `xxxxxxff -> supervisor; `xxxxxx00 -> user +| d1 = `xxxxxxff -> longword; `xxxxxx00 -> word +| Expected outputs: +| d0 = 0 -> success; non-zero -> failure +| +| Linux/m68k: Make sure the page is properly paged in, so we use +| plpaw and handle any exception here. The kernel must not be +| preempted until _060_unlock_page(), so that the page stays mapped. +| + .global _060_real_lock_page +_060_real_lock_page: + move.l %d2,-(%sp) + | load sfc/dfc + tst.b %d0 + jne 1f + moveq #1,%d0 + jra 2f +1: moveq #5,%d0 +2: movec.l %dfc,%d2 + movec.l %d0,%dfc + movec.l %d0,%sfc + + clr.l %d0 + | prefetch address + .chip 68060 + move.l %a0,%a1 +1: plpaw (%a1) + addq.w #1,%a0 + tst.b %d1 + jeq 2f + addq.w #2,%a0 +2: plpaw (%a0) +3: .chip 68k + + | restore sfc/dfc + movec.l %d2,%dfc + movec.l %d2,%sfc + move.l (%sp)+,%d2 + rts + +.section __ex_table,"a" + .align 4 + .long 1b,11f + .long 2b,21f +.previous +.section .fixup,"ax" + .even +11: move.l #0x020003c0,%d0 + or.l %d2,%d0 + swap %d0 + jra 3b +21: move.l #0x02000bc0,%d0 + or.l %d2,%d0 + swap %d0 + jra 3b +.previous + +| +| _060_unlock_page(): +| +| Entry point for the operating system`s routine to "unlock" a +| page that has been "locked" previously with _real_lock_page. +| Note: the routine must unlock two pages if the operand spans +| two pages. +| Arguments: +| a0 = operand address +| d0 = `xxxxxxff -> supervisor; `xxxxxx00 -> user +| d1 = `xxxxxxff -> longword; `xxxxxx00 -> word +| +| Linux/m68k: perhaps reenable preemption here... + + .global _060_real_unlock_page +_060_real_unlock_page: + clr.l %d0 + rts + +|########################################################################### + +|################################# +| (2) EXAMPLE PACKAGE ENTRY CODE # +|################################# + + .global _060_isp_unimp +_060_isp_unimp: + bral _I_CALL_TOP+0x80+0x00 + + .global _060_isp_cas +_060_isp_cas: + bral _I_CALL_TOP+0x80+0x08 + + .global _060_isp_cas2 +_060_isp_cas2: + bral _I_CALL_TOP+0x80+0x10 + + .global _060_isp_cas_finish +_060_isp_cas_finish: + bra.l _I_CALL_TOP+0x80+0x18 + + .global _060_isp_cas2_finish +_060_isp_cas2_finish: + bral _I_CALL_TOP+0x80+0x20 + + .global _060_isp_cas_inrange +_060_isp_cas_inrange: + bral _I_CALL_TOP+0x80+0x28 + + .global _060_isp_cas_terminate +_060_isp_cas_terminate: + bral _I_CALL_TOP+0x80+0x30 + + .global _060_isp_cas_restart +_060_isp_cas_restart: + bral _I_CALL_TOP+0x80+0x38 + +|########################################################################### + +|############################### +| (3) EXAMPLE CALL-OUT SECTION # +|############################### + +| The size of this section MUST be 128 bytes!!! + +_I_CALL_TOP: + .long _060_real_chk - _I_CALL_TOP + .long _060_real_divbyzero - _I_CALL_TOP + .long _060_real_trace - _I_CALL_TOP + .long _060_real_access - _I_CALL_TOP + .long _060_isp_done - _I_CALL_TOP + + .long _060_real_cas - _I_CALL_TOP + .long _060_real_cas2 - _I_CALL_TOP + .long _060_real_lock_page - _I_CALL_TOP + .long _060_real_unlock_page - _I_CALL_TOP + + .long 0x00000000, 0x00000000, 0x00000000, 0x00000000 + .long 0x00000000, 0x00000000, 0x00000000 + + .long _060_imem_read - _I_CALL_TOP + .long _060_dmem_read - _I_CALL_TOP + .long _060_dmem_write - _I_CALL_TOP + .long _060_imem_read_word - _I_CALL_TOP + .long _060_imem_read_long - _I_CALL_TOP + .long _060_dmem_read_byte - _I_CALL_TOP + .long _060_dmem_read_word - _I_CALL_TOP + .long _060_dmem_read_long - _I_CALL_TOP + .long _060_dmem_write_byte - _I_CALL_TOP + .long _060_dmem_write_word - _I_CALL_TOP + .long _060_dmem_write_long - _I_CALL_TOP + + .long 0x00000000 + .long 0x00000000, 0x00000000, 0x00000000, 0x00000000 + +|########################################################################### + +| 060 INTEGER KERNEL PACKAGE MUST GO HERE!!! +#include "isp.sa" diff --git a/arch/m68k/ifpsp060/isp.doc b/arch/m68k/ifpsp060/isp.doc new file mode 100644 index 000000000..9dadd727f --- /dev/null +++ b/arch/m68k/ifpsp060/isp.doc @@ -0,0 +1,218 @@ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP +M68000 Hi-Performance Microprocessor Division +M68060 Software Package +Production Release P1.00 -- October 10, 1994 + +M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. + +THE SOFTWARE is provided on an "AS IS" basis and without warranty. +To the maximum extent permitted by applicable law, +MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, +INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE +and any warranty against infringement with regard to the SOFTWARE +(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. + +To the maximum extent permitted by applicable law, +IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, +BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) +ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. +Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. + +You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE +so long as this entire notice is retained without alteration in any modified and/or +redistributed versions, and that such modified versions are clearly identified as such. +No licenses are granted by implication, estoppel or otherwise under any patents +or trademarks of Motorola, Inc. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +68060 INTEGER SOFTWARE PACKAGE (Kernel version) +------------------------------------------------ + +The file isp.sa contains the 68060 Integer Software Package. +This package is essentially an exception handler that can be +integrated into an operating system to handle the "Unimplemented +Integer Instruction" exception vector #61. +This exception is taken when any of the integer instructions +not hardware implemented on the 68060 are encountered. The +isp.sa provides full emulation support for these instructions. + +The unimplemented integer instructions are: + 64-bit divide + 64-bit multiply + movep + cmp2 + chk2 + cas (w/ a misaligned effective address) + cas2 + +Release file format: +-------------------- +The file isp.sa is essentially a hexadecimal image of the +release package. This is the ONLY format which will be supported. +The hex image was created by assembling the source code and +then converting the resulting binary output image into an +ASCII text file. The hexadecimal numbers are listed +using the Motorola Assembly Syntax assembler directive "dc.l" +(define constant longword). The file can be converted to other +assembly syntaxes by using any word processor with a global +search and replace function. + +To assist in assembling and linking this module with other modules, +the installer should add a symbolic label to the top of the file. +This will allow calling routines to access the entry points +of this package. + +The source code isp.s has also been included but only for +documentation purposes. + +Release file structure: +----------------------- + +(top of module) + ----------------- + | | - 128 byte-sized section + (1) | Call-Out | - 4 bytes per entry (user fills these in) + | | - example routines in iskeleton.s + ----------------- + | | - 8 bytes per entry + (2) | Entry Point | - user does a "bra" or "jmp" to this address + | | + ----------------- + | | - code section + (3) ~ ~ + | | + ----------------- +(bottom of module) + +The first section of this module is the "Call-out" section. This section +is NOT INCLUDED in isp.sa (an example "Call-out" section is provided at +the end of the file iskeleton.s). The purpose of this section is to allow +the ISP routines to reference external functions that must be provided +by the host operating system. This section MUST be exactly 128 bytes in +size. There are 32 fields, each 4 bytes in size. Each field corresponds +to a function required by the ISP (these functions and their location are +listed in "68060ISP call-outs" below). Each field entry should contain +the address of the corresponding function RELATIVE to the starting address +of the "call-out" section. The "Call-out" section must sit adjacent to the +isp.sa image in memory. + +The second section, the "Entry-point" section, is used by external routines +to access the functions within the ISP. Since the isp.sa hex file contains +no symbol names, this section contains function entry points that are fixed +with respect to the top of the package. The currently defined entry-points +are listed in section "68060 ISP entry points" below. A calling routine +would simply execute a "bra" or "jmp" that jumped to the selected function +entry-point. + +For example, if the 68060 hardware took a "Unimplemented Integer Instruction" +exception (vector #61), the operating system should execute something +similar to: + + bra _060ISP_TOP+128+0 + +(_060ISP_TOP is the starting address of the "Call-out" section; the "Call-out" +section is 128 bytes long; and the Unimplemented Integer ISP handler entry +point is located 0 bytes from the top of the "Entry-point" section.) + +The third section is the code section. After entering through an "Entry-point", +the entry code jumps to the appropriate emulation code within the code section. + +68060ISP call-outs: (details in iskeleton.s) +-------------------- +0x000: _060_real_chk +0x004: _060_real_divbyzero +0x008: _060_real_trace +0x00c: _060_real_access +0x010: _060_isp_done + +0x014: _060_real_cas +0x018: _060_real_cas2 +0x01c: _060_real_lock_page +0x020: _060_real_unlock_page + +0x024: (Motorola reserved) +0x028: (Motorola reserved) +0x02c: (Motorola reserved) +0x030: (Motorola reserved) +0x034: (Motorola reserved) +0x038: (Motorola reserved) +0x03c: (Motorola reserved) + +0x040: _060_imem_read +0x044: _060_dmem_read +0x048: _060_dmem_write +0x04c: _060_imem_read_word +0x050: _060_imem_read_long +0x054: _060_dmem_read_byte +0x058: _060_dmem_read_word +0x05c: _060_dmem_read_long +0x060: _060_dmem_write_byte +0x064: _060_dmem_write_word +0x068: _060_dmem_write_long + +0x06c: (Motorola reserved) +0x070: (Motorola reserved) +0x074: (Motorola reserved) +0x078: (Motorola reserved) +0x07c: (Motorola reserved) + +68060ISP entry points: +----------------------- +0x000: _060_isp_unimp + +0x008: _060_isp_cas +0x010: _060_isp_cas2 +0x018: _060_isp_cas_finish +0x020: _060_isp_cas2_finish +0x028: _060_isp_cas_inrange +0x030: _060_isp_cas_terminate +0x038: _060_isp_cas_restart + +Integrating cas/cas2: +--------------------- +The instructions "cas2" and "cas" (when used with a misaligned effective +address) take the Unimplemented Integer Instruction exception. When the +060ISP is installed properly, these instructions will enter through the +_060_isp_unimp() entry point of the ISP. + +After the 060ISP decodes the instruction type and fetches the appropriate +data registers, and BEFORE the actual emulated transfers occur, the +package calls either the "Call-out" _060_real_cas() or _060_real_cas2(). +If the emulation code provided by the 060ISP is sufficient for the +host system (see isp.s source code), then these "Call-out"s should be +made, by the system integrator, to point directly back into the package +through the "Entry-point"s _060_isp_cas() or _060_isp_cas2(). + +One other necessary action by the integrator is to supply the routines +_060_real_lock_page() and _060_real_unlock_page(). These functions are +defined further in iskeleton.s and the 68060 Software Package Specification. + +If the "core" emulation routines of either "cas" or "cas2" perform some +actions which are too system-specific, then the system integrator must +supply new emulation code. This new emulation code should reside within +the functions _060_real_cas() or _060_real_cas2(). When this new emulation +code has completed, then it should re-enter the 060ISP package through the +"Entry-point" _060_isp_cas_finish() or _060_isp_cas2_finish(). +To see what the register state is upon entering _060_real_cas() or +_060_real_cas2() and what it should be upon return to the package through +_060_isp_cas_finish() or _060_isp_cas2_finish(), please refer to the +source code in isp.s. + +Miscellaneous: +-------------- + +_060_isp_unimp: +---------------- +- documented in 2.2 in spec. +- Basic flow: + exception taken ---> enter _060_isp_unimp --| + | + | + may exit through _060_real_itrace <----| + or | + may exit through _060_real_chk <----| + or | + may exit through _060_real_divbyzero <----| + or | + may exit through _060_isp_done <----| diff --git a/arch/m68k/ifpsp060/isp.sa b/arch/m68k/ifpsp060/isp.sa new file mode 100644 index 000000000..2f88d2a7d --- /dev/null +++ b/arch/m68k/ifpsp060/isp.sa @@ -0,0 +1,392 @@ + .long 0x60ff0000,0x02360000,0x60ff0000,0x16260000 + .long 0x60ff0000,0x12dc0000,0x60ff0000,0x11ea0000 + .long 0x60ff0000,0x10de0000,0x60ff0000,0x12a40000 + .long 0x60ff0000,0x12560000,0x60ff0000,0x122a0000 + .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc + .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc + .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc + .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc + .long 0x2f00203a,0xfefc487b,0x0930ffff,0xfef8202f + .long 0x00044e74,0x00042f00,0x203afeea,0x487b0930 + .long 0xfffffee2,0x202f0004,0x4e740004,0x2f00203a + .long 0xfed8487b,0x0930ffff,0xfecc202f,0x00044e74 + .long 0x00042f00,0x203afec6,0x487b0930,0xfffffeb6 + .long 0x202f0004,0x4e740004,0x2f00203a,0xfeb4487b + .long 0x0930ffff,0xfea0202f,0x00044e74,0x00042f00 + .long 0x203afea2,0x487b0930,0xfffffe8a,0x202f0004 + .long 0x4e740004,0x2f00203a,0xfe90487b,0x0930ffff + .long 0xfe74202f,0x00044e74,0x00042f00,0x203afe7e + .long 0x487b0930,0xfffffe5e,0x202f0004,0x4e740004 + .long 0x2f00203a,0xfe6c487b,0x0930ffff,0xfe48202f + .long 0x00044e74,0x00042f00,0x203afe76,0x487b0930 + .long 0xfffffe32,0x202f0004,0x4e740004,0x2f00203a + .long 0xfe64487b,0x0930ffff,0xfe1c202f,0x00044e74 + .long 0x00042f00,0x203afe52,0x487b0930,0xfffffe06 + .long 0x202f0004,0x4e740004,0x2f00203a,0xfe40487b + .long 0x0930ffff,0xfdf0202f,0x00044e74,0x00042f00 + .long 0x203afe2e,0x487b0930,0xfffffdda,0x202f0004 + .long 0x4e740004,0x2f00203a,0xfe1c487b,0x0930ffff + .long 0xfdc4202f,0x00044e74,0x00042f00,0x203afe0a + .long 0x487b0930,0xfffffdae,0x202f0004,0x4e740004 + .long 0x2f00203a,0xfdf8487b,0x0930ffff,0xfd98202f + .long 0x00044e74,0x00042f00,0x203afde6,0x487b0930 + .long 0xfffffd82,0x202f0004,0x4e740004,0x2f00203a + .long 0xfdd4487b,0x0930ffff,0xfd6c202f,0x00044e74 + .long 0x00042f00,0x203afdc2,0x487b0930,0xfffffd56 + .long 0x202f0004,0x4e740004,0x4e56ffa0,0x48ee3fff + .long 0xffc02d56,0xfff8082e,0x00050004,0x66084e68 + .long 0x2d48fffc,0x600841ee,0x000c2d48,0xfffc422e + .long 0xffaa3d6e,0x0004ffa8,0x2d6e0006,0xffa4206e + .long 0xffa458ae,0xffa461ff,0xffffff26,0x2d40ffa0 + .long 0x0800001e,0x67680800,0x00166628,0x61ff0000 + .long 0x0cb0082e,0x00050004,0x670000ac,0x082e0002 + .long 0xffaa6700,0x00a2082e,0x00070004,0x66000186 + .long 0x600001b0,0x61ff0000,0x0a28082e,0x0002ffaa + .long 0x660e082e,0x0005ffaa,0x6600010a,0x60000078 + .long 0x082e0005,0x000467ea,0x082e0005,0xffaa6600 + .long 0x01264a2e,0x00046b00,0x014c6000,0x01760800 + .long 0x0018670a,0x61ff0000,0x07ae6000,0x004a0800 + .long 0x001b6730,0x48400c00,0x00fc670a,0x61ff0000 + .long 0x0e926000,0x0032206e,0xffa454ae,0xffa461ff + .long 0xfffffe68,0x4a816600,0x019861ff,0x00000d20 + .long 0x60000014,0x61ff0000,0x08c40c2e,0x0010ffaa + .long 0x66000004,0x605c1d6e,0xffa90005,0x082e0005 + .long 0x00046606,0x206efffc,0x4e604cee,0x3fffffc0 + .long 0x082e0007,0x00046612,0x2d6effa4,0x00062cae + .long 0xfff84e5e,0x60ffffff,0xfd622d6e,0xfff8fffc + .long 0x3d6e0004,0x00002d6e,0x00060008,0x2d6effa4 + .long 0x00023d7c,0x20240006,0x598e4e5e,0x60ffffff + .long 0xfd0e1d6e,0xffa90005,0x4cee3fff,0xffc03cae + .long 0x00042d6e,0x00060008,0x2d6effa4,0x00023d7c + .long 0x20180006,0x2c6efff8,0xdffc0000,0x006060ff + .long 0xfffffcb0,0x1d6effa9,0x00054cee,0x3fffffc0 + .long 0x3cae0004,0x2d6e0006,0x00082d6e,0xffa40002 + .long 0x3d7c2014,0x00062c6e,0xfff8dffc,0x00000060 + .long 0x60ffffff,0xfc941d6e,0xffa90005,0x4cee3fff + .long 0xffc02d6e,0x0006000c,0x3d7c2014,0x000a2d6e + .long 0xffa40006,0x2c6efff8,0xdffc0000,0x006460ff + .long 0xfffffc66,0x1d6effa9,0x00054cee,0x3fffffc0 + .long 0x2d6e0006,0x000c3d7c,0x2024000a,0x2d6effa4 + .long 0x00062c6e,0xfff8dffc,0x00000064,0x60ffffff + .long 0xfc4e1d6e,0xffa90005,0x4cee3fff,0xffc03d7c + .long 0x00f4000e,0x2d6effa4,0x000a3d6e,0x00040008 + .long 0x2c6efff8,0xdffc0000,0x006860ff,0xfffffc4c + .long 0x2c882d40,0xfffc4fee,0xffc04cdf,0x7fff2f2f + .long 0x000c2f6f,0x00040010,0x2f6f000c,0x00042f6f + .long 0x0008000c,0x2f5f0004,0x3f7c4008,0x00066028 + .long 0x4cee3fff,0xffc04e5e,0x514f2eaf,0x00083f6f + .long 0x000c0004,0x3f7c4008,0x00062f6f,0x00020008 + .long 0x2f7c0942,0x8001000c,0x08170005,0x670608ef + .long 0x0002000d,0x60ffffff,0xfbcc0c2e,0x0040ffaa + .long 0x660c4280,0x102effab,0x2daeffac,0x0ce04e75 + .long 0x2040302e,0xffa03200,0x0240003f,0x02810000 + .long 0x0007303b,0x020a4efb,0x00064afc,0x00400000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000080 + .long 0x0086008c,0x00920098,0x009e00a4,0x00aa00b0 + .long 0x00ce00ec,0x010a0128,0x01460164,0x01820196 + .long 0x01b401d2,0x01f0020e,0x022c024a,0x0268027c + .long 0x029a02b8,0x02d602f4,0x03120330,0x034e036c + .long 0x036c036c,0x036c036c,0x036c036c,0x036c03d6 + .long 0x03f0040a,0x042a03ca,0x00000000,0x0000206e + .long 0xffe04e75,0x206effe4,0x4e75206e,0xffe84e75 + .long 0x206effec,0x4e75206e,0xfff04e75,0x206efff4 + .long 0x4e75206e,0xfff84e75,0x206efffc,0x4e752008 + .long 0x206effe0,0xd0882d40,0xffe02d48,0xffac1d7c + .long 0x0000ffab,0x1d7c0040,0xffaa4e75,0x2008206e + .long 0xffe4d088,0x2d40ffe4,0x2d48ffac,0x1d7c0001 + .long 0xffab1d7c,0x0040ffaa,0x4e752008,0x206effe8 + .long 0xd0882d40,0xffe82d48,0xffac1d7c,0x0002ffab + .long 0x1d7c0040,0xffaa4e75,0x2008206e,0xffecd088 + .long 0x2d40ffec,0x2d48ffac,0x1d7c0003,0xffab1d7c + .long 0x0040ffaa,0x4e752008,0x206efff0,0xd0882d40 + .long 0xfff02d48,0xffac1d7c,0x0004ffab,0x1d7c0040 + .long 0xffaa4e75,0x2008206e,0xfff4d088,0x2d40fff4 + .long 0x2d48ffac,0x1d7c0005,0xffab1d7c,0x0040ffaa + .long 0x4e752008,0x206efff8,0xd0882d40,0xfff82d48 + .long 0xffac1d7c,0x0006ffab,0x1d7c0040,0xffaa4e75 + .long 0x1d7c0004,0xffaa2008,0x206efffc,0xd0882d40 + .long 0xfffc4e75,0x202effe0,0x2d40ffac,0x90882d40 + .long 0xffe02040,0x1d7c0000,0xffab1d7c,0x0040ffaa + .long 0x4e75202e,0xffe42d40,0xffac9088,0x2d40ffe4 + .long 0x20401d7c,0x0001ffab,0x1d7c0040,0xffaa4e75 + .long 0x202effe8,0x2d40ffac,0x90882d40,0xffe82040 + .long 0x1d7c0002,0xffab1d7c,0x0040ffaa,0x4e75202e + .long 0xffec2d40,0xffac9088,0x2d40ffec,0x20401d7c + .long 0x0003ffab,0x1d7c0040,0xffaa4e75,0x202efff0 + .long 0x2d40ffac,0x90882d40,0xfff02040,0x1d7c0004 + .long 0xffab1d7c,0x0040ffaa,0x4e75202e,0xfff42d40 + .long 0xffac9088,0x2d40fff4,0x20401d7c,0x0005ffab + .long 0x1d7c0040,0xffaa4e75,0x202efff8,0x2d40ffac + .long 0x90882d40,0xfff82040,0x1d7c0006,0xffab1d7c + .long 0x0040ffaa,0x4e751d7c,0x0008ffaa,0x202efffc + .long 0x90882d40,0xfffc2040,0x4e75206e,0xffa454ae + .long 0xffa461ff,0xfffff9d4,0x4a8166ff,0xfffffd04 + .long 0x3040d1ee,0xffe04e75,0x206effa4,0x54aeffa4 + .long 0x61ffffff,0xf9b64a81,0x66ffffff,0xfce63040 + .long 0xd1eeffe4,0x4e75206e,0xffa454ae,0xffa461ff + .long 0xfffff998,0x4a8166ff,0xfffffcc8,0x3040d1ee + .long 0xffe84e75,0x206effa4,0x54aeffa4,0x61ffffff + .long 0xf97a4a81,0x66ffffff,0xfcaa3040,0xd1eeffec + .long 0x4e75206e,0xffa454ae,0xffa461ff,0xfffff95c + .long 0x4a8166ff,0xfffffc8c,0x3040d1ee,0xfff04e75 + .long 0x206effa4,0x54aeffa4,0x61ffffff,0xf93e4a81 + .long 0x66ffffff,0xfc6e3040,0xd1eefff4,0x4e75206e + .long 0xffa454ae,0xffa461ff,0xfffff920,0x4a8166ff + .long 0xfffffc50,0x3040d1ee,0xfff84e75,0x206effa4 + .long 0x54aeffa4,0x61ffffff,0xf9024a81,0x66ffffff + .long 0xfc323040,0xd1eefffc,0x4e752f01,0x206effa4 + .long 0x54aeffa4,0x61ffffff,0xf8e24a81,0x66ffffff + .long 0xfc12221f,0x207614e0,0x08000008,0x670e48e7 + .long 0x3c002a00,0x260860ff,0x000000ec,0x2f022200 + .long 0xe9590241,0x000f2236,0x14c00800,0x000b6602 + .long 0x48c12400,0xef5a0282,0x00000003,0xe5a949c0 + .long 0xd081d1c0,0x241f4e75,0x1d7c0080,0xffaa206e + .long 0xffa44e75,0x206effa4,0x54aeffa4,0x61ffffff + .long 0xf87a4a81,0x66ffffff,0xfbaa3040,0x4e75206e + .long 0xffa458ae,0xffa461ff,0xfffff876,0x4a8166ff + .long 0xfffffb90,0x20404e75,0x206effa4,0x54aeffa4 + .long 0x61ffffff,0xf8464a81,0x66ffffff,0xfb763040 + .long 0xd1eeffa4,0x55884e75,0x206effa4,0x54aeffa4 + .long 0x61ffffff,0xf8264a81,0x66ffffff,0xfb56206e + .long 0xffa45588,0x08000008,0x670e48e7,0x3c002a00 + .long 0x260860ff,0x00000030,0x2f022200,0xe9590241 + .long 0x000f2236,0x14c00800,0x000b6602,0x48c12400 + .long 0xef5a0282,0x00000003,0xe5a949c0,0xd081d1c0 + .long 0x241f4e75,0x08050006,0x67044282,0x6016e9c5 + .long 0x24042436,0x24c00805,0x000b6602,0x48c2e9c5 + .long 0x0542e1aa,0x08050007,0x67024283,0xe9c50682 + .long 0x0c000002,0x6d346718,0x206effa4,0x58aeffa4 + .long 0x61ffffff,0xf7ac4a81,0x66ffffff,0xfac66018 + .long 0x206effa4,0x54aeffa4,0x61ffffff,0xf77e4a81 + .long 0x66ffffff,0xfaae48c0,0xd680e9c5,0x07826700 + .long 0x006a0c00,0x00026d34,0x6718206e,0xffa458ae + .long 0xffa461ff,0xfffff76a,0x4a8166ff,0xfffffa84 + .long 0x601c206e,0xffa454ae,0xffa461ff,0xfffff73c + .long 0x4a8166ff,0xfffffa6c,0x48c06002,0x42802800 + .long 0x08050002,0x67122043,0x61ffffff,0xf7764a81 + .long 0x6624d082,0xd0846016,0xd6822043,0x61ffffff + .long 0xf7624a81,0x6610d084,0x6004d682,0x20032040 + .long 0x4cdf003c,0x4e752043,0x203c0101,0x000160ff + .long 0xfffff9f0,0x322effa0,0x10010240,0x00072076 + .long 0x04e0d0ee,0xffa20801,0x00076700,0x008c3001 + .long 0xef580240,0x00072036,0x04c00801,0x00066752 + .long 0x24002448,0xe19a2002,0x61ffffff,0xf71c4a81 + .long 0x660000fc,0x544a204a,0xe19a2002,0x61ffffff + .long 0xf7084a81,0x660000e8,0x544a204a,0xe19a2002 + .long 0x61ffffff,0xf6f44a81,0x660000d4,0x544a204a + .long 0xe19a2002,0x61ffffff,0xf6e04a81,0x660000c0 + .long 0x4e752400,0x2448e048,0x61ffffff,0xf6cc4a81 + .long 0x660000ac,0x544a204a,0x200261ff,0xfffff6ba + .long 0x4a816600,0x009a4e75,0x08010006,0x675c2448 + .long 0x61ffffff,0xf6624a81,0x66000092,0x2400544a + .long 0x204a61ff,0xfffff650,0x4a816600,0x0080e14a + .long 0x1400544a,0x204a61ff,0xfffff63c,0x4a816600 + .long 0x006ce18a,0x1400544a,0x204a61ff,0xfffff628 + .long 0x4a816600,0x0058e18a,0x1400122e,0xffa0e209 + .long 0x02410007,0x2d8214c0,0x4e752448,0x61ffffff + .long 0xf6064a81,0x66000036,0x2400544a,0x204a61ff + .long 0xfffff5f4,0x4a816600,0x0024e14a,0x1400122e + .long 0xffa0e209,0x02410007,0x3d8214c2,0x4e75204a + .long 0x203c00a1,0x000160ff,0xfffff8a8,0x204a203c + .long 0x01210001,0x60ffffff,0xf89a61ff,0xfffff914 + .long 0x102effa2,0xe9180240,0x000f2436,0x04c00c2e + .long 0x0002ffa0,0x6d506728,0x244861ff,0xfffff5c4 + .long 0x4a816600,0x009e2600,0x588a204a,0x61ffffff + .long 0xf5b24a81,0x6600008c,0x22002003,0x60000048 + .long 0x244861ff,0xfffff59c,0x4a816600,0x00763200 + .long 0x484048c0,0x48c1082e,0x0007ffa2,0x66000028 + .long 0x48c26000,0x00222448,0x61ffffff,0xf5604a81 + .long 0x6600005e,0x1200e048,0x49c049c1,0x082e0007 + .long 0xffa26602,0x49c29480,0x42c30203,0x00049280 + .long 0xb28242c4,0x86040203,0x0005382e,0xffa80204 + .long 0x001a8803,0x3d44ffa8,0x082e0003,0xffa26602 + .long 0x4e750804,0x00006602,0x4e751d7c,0x0010ffaa + .long 0x4e75204a,0x203c0101,0x000160ff,0xfffff7c4 + .long 0x204a203c,0x01410001,0x60ffffff,0xf7b6102e + .long 0xffa10200,0x00386600,0x0208102e,0xffa10240 + .long 0x00072e36,0x04c06700,0x00c0102e,0xffa3122e + .long 0xffa20240,0x0007e809,0x02410007,0x3d40ffb2 + .long 0x3d41ffb4,0x2a3604c0,0x2c3614c0,0x082e0003 + .long 0xffa2671a,0x4a875dee,0xffb06a02,0x44874a85 + .long 0x5deeffb1,0x6a0844fc,0x00004086,0x40854a85 + .long 0x66164a86,0x67000048,0xbe866306,0xcb466000 + .long 0x00124c47,0x6005600a,0xbe85634e,0x61ff0000 + .long 0x0068082e,0x0003ffa2,0x67244a2e,0xffb16702 + .long 0x4485102e,0xffb0b12e,0xffb1670c,0x0c868000 + .long 0x00006226,0x44866006,0x0806001f,0x661c44ee + .long 0xffa84a86,0x42eeffa8,0x302effb2,0x322effb4 + .long 0x2d8504c0,0x2d8614c0,0x4e7508ee,0x0001ffa9 + .long 0x08ae0000,0xffa94e75,0x022e001e,0xffa9002e + .long 0x0020ffaa,0x4e750c87,0x0000ffff,0x621e4281 + .long 0x48454846,0x3a068ac7,0x32054846,0x3a068ac7 + .long 0x48413205,0x42454845,0x2c014e75,0x42aeffbc + .long 0x422effb6,0x42810807,0x001f660e,0x52aeffbc + .long 0xe38fe38e,0xe3956000,0xffee2607,0x24054842 + .long 0x4843b443,0x6606323c,0xffff600a,0x220582c3 + .long 0x02810000,0xffff2f06,0x42464846,0x26072401 + .long 0xc4c74843,0xc6c12805,0x98834844,0x30043806 + .long 0x4a406600,0x000ab484,0x63045381,0x60de2f05 + .long 0x2c014846,0x2a0761ff,0x0000006a,0x24052606 + .long 0x2a1f2c1f,0x9c839b82,0x64ff0000,0x001a5381 + .long 0x42822607,0x48434243,0xdc83db82,0x26074243 + .long 0x4843da83,0x4a2effb6,0x66163d41,0xffb84281 + .long 0x48454846,0x3a064246,0x50eeffb6,0x6000ff6c + .long 0x3d41ffba,0x3c054846,0x48452e2e,0xffbc670a + .long 0x5387e28d,0xe29651cf,0xfffa2a06,0x2c2effb8 + .long 0x4e752406,0x26062805,0x48434844,0xccc5cac3 + .long 0xc4c4c6c4,0x42844846,0xdc45d744,0xdc42d744 + .long 0x48464245,0x42424845,0x4842da82,0xda834e75 + .long 0x700461ff,0xfffff61c,0x0c2e0080,0xffaa6712 + .long 0x244861ff,0xfffff2dc,0x4a81661e,0x2e006000 + .long 0xfde658ae,0xffa461ff,0xfffff286,0x4a8166ff + .long 0xfffff5a0,0x2e006000,0xfdce61ff,0xfffff5ce + .long 0x204a203c,0x01010001,0x60ffffff,0xf556102e + .long 0xffa10c00,0x00076e00,0x00b40240,0x00072636 + .long 0x04c0342e,0xffa24241,0x1202e95a,0x02420007 + .long 0x283624c0,0x4a846700,0x00884a83,0x67000082 + .long 0x422effb0,0x082e0003,0xffa26718,0x4a836c08 + .long 0x4483002e,0x0001ffb0,0x4a846c08,0x44840a2e + .long 0x0001ffb0,0x2a032c03,0x2e044846,0x4847c6c4 + .long 0xc8c6cac7,0xccc74287,0x4843d644,0xdd87d645 + .long 0xdd874843,0x42444245,0x48444845,0xd885d886 + .long 0x4a2effb0,0x67084683,0x46845283,0xd9872d83 + .long 0x24c044fc,0x00002d84,0x14c042c7,0x02070008 + .long 0x1c2effa9,0x02060010,0x8c071d46,0xffa94e75 + .long 0x42b624c0,0x42b614c0,0x7e0460e4,0x700461ff + .long 0xfffff510,0x0c2e0080,0xffaa6714,0x244861ff + .long 0xfffff1d0,0x4a816600,0x00202600,0x6000ff34 + .long 0x58aeffa4,0x61ffffff,0xf1784a81,0x66ffffff + .long 0xf4922600,0x6000ff1c,0x61ffffff,0xf4c0204a + .long 0x203c0101,0x000160ff,0xfffff448,0x2d40ffb4 + .long 0x2200e958,0x0240000f,0x227604c0,0x2d49ffb0 + .long 0x2001ec49,0x02410007,0x2a3614c0,0x02400007 + .long 0x263604c0,0x3d40ffba,0x302effa2,0x2200e958 + .long 0x0240000f,0x207604c0,0x2d48ffbc,0x2001ec49 + .long 0x02410007,0x283614c0,0x02400007,0x243604c0 + .long 0x3d40ffb8,0x082e0001,0xffa056c7,0x082e0005 + .long 0x000456c6,0x24482649,0x22072006,0x61ffffff + .long 0xf05c204a,0x4a8066ff,0x000001c8,0x22072006 + .long 0x204b61ff,0xfffff046,0x204b4a80,0x660a204a + .long 0x224b60ff,0xfffff020,0x2f002207,0x2006204a + .long 0x61ffffff,0xf03e201f,0x204b60ff,0x00000194 + .long 0x082e0001,0xffa06648,0x44eeffa8,0xb0426602 + .long 0xb24342ee,0xffa84a04,0x6610362e,0xffba3d81 + .long 0x34c2342e,0xffb83d80,0x24c2082e,0x00050004 + .long 0x56c22002,0x51c1206e,0xffbc61ff,0xffffeff4 + .long 0x200251c1,0x206effb0,0x61ffffff,0xefe64e75 + .long 0x44eeffa8,0xb0826602,0xb28342ee,0xffa84a04 + .long 0x6610362e,0xffba2d81,0x34c0342e,0xffb82d80 + .long 0x24c0082e,0x00050004,0x56c22002,0x50c1206e + .long 0xffbc61ff,0xffffefac,0x200250c1,0x206effb0 + .long 0x61ffffff,0xef9e4e75,0x202effb4,0x6000feae + .long 0x082e0001,0xffa06610,0x700261ff,0xfffff364 + .long 0x2d48ffb4,0x51c7600e,0x700461ff,0xfffff354 + .long 0x2d48ffb4,0x50c7302e,0xffa22200,0xec480240 + .long 0x00072436,0x04c00241,0x00072836,0x14c03d41 + .long 0xffb8082e,0x00050004,0x56c62448,0x22072006 + .long 0x61ffffff,0xef284a80,0x66000096,0x204a60ff + .long 0xffffeeee,0x082e0001,0xffa0662c,0x44eeffa8 + .long 0xb04442ee,0xffa84a01,0x6608362e,0xffb83d80 + .long 0x34c2206e,0xffb451c1,0x082e0005,0x000456c0 + .long 0x61ffffff,0xeefe4e75,0x44eeffa8,0xb08442ee + .long 0xffa84a01,0x6608362e,0xffb82d80,0x34c0206e + .long 0xffb450c1,0x082e0005,0x000456c0,0x61ffffff + .long 0xeed24e75,0x4e7b6000,0x4e7b6001,0x0c2e00fc + .long 0xffa167ff,0xffffff24,0x206effb4,0x082e0001 + .long 0xffa056c7,0x6000ff40,0x4e7b6000,0x4e7b6001 + .long 0x24482f00,0x61ffffff,0xf264201f,0x588f518f + .long 0x518e721a,0x41ef0008,0x43ef0000,0x22d851c9 + .long 0xfffc3d7c,0x4008000a,0x2d4a000c,0x2d400010 + .long 0x4cee3fff,0xffc04e5e,0x60ffffff,0xedf84280 + .long 0x43fb0170,0x000005ae,0xb3c86d0e,0x43fb0170 + .long 0x00000010,0xb1c96d02,0x4e7570ff,0x4e754a06 + .long 0x66047001,0x60027005,0x4a076700,0x01e42448 + .long 0x26492848,0x2a49568c,0x568d220a,0x40c7007c + .long 0x07004e7a,0x60004e7b,0x00004e7b,0x0001f58a + .long 0xf58cf58b,0xf58df46a,0xf46cf46b,0xf46d2441 + .long 0x56812841,0xf5caf5cc,0x247c8000,0x0000267c + .long 0xa0000000,0x287c0000,0x00002008,0x02000003 + .long 0x671c0c00,0x00026700,0x00966000,0x010251fc + .long 0x4e7ba008,0x0e911000,0x0e900000,0x6002600e + .long 0xb082661c,0xb2836618,0x0e915800,0x6002600e + .long 0x4e7bb008,0x0e904800,0x4e7bc008,0x6034600e + .long 0x4e7bb008,0x0e900800,0x4e7bc008,0x6012600e + .long 0x4e714e71,0x4e714e71,0x4e714e71,0x4e7160b0 + .long 0x4e7b6000,0x4e7b6001,0x46c751c4,0x60ffffff + .long 0xfd424e7b,0x60004e7b,0x600146c7,0x50c460ff + .long 0xfffffd30,0x51fc51fc,0x51fc51fc,0x51fc51fc + .long 0x4e7ba008,0x0e911000,0x0e900000,0x6002600e + .long 0xb082662c,0xb2836628,0x0e915800,0x6002600e + .long 0x48440e58,0x48004e7b,0xb0084844,0x6002600e + .long 0x0e504800,0x4e7bc008,0x6000ffa8,0x4e71600e + .long 0x48400e58,0x08004e7b,0xb0084840,0x6002600e + .long 0x0e500800,0x4e7bc008,0x6000ff76,0x4e71600e + .long 0x4e714e71,0x4e714e71,0x4e714e71,0x4e716090 + .long 0x4e7ba008,0x0e911000,0x0e900000,0x6002600e + .long 0xb082663c,0xb2836638,0x0e915800,0x6002600e + .long 0xe19c0e18,0x48004844,0x0e584800,0x6002600e + .long 0xe19c4e7b,0xb0080e10,0x48006004,0x4e71600e + .long 0x4e7bc008,0x6000ff2c,0x4e714e71,0x4e71600e + .long 0xe1980e18,0x08004840,0x0e580800,0x6002600e + .long 0xe1984e7b,0xb0080e10,0x08006004,0x4e71600e + .long 0x4e7bc008,0x6000feea,0x4e714e71,0x4e71600c + .long 0x4e714e71,0x4e714e71,0x4e714e71,0x6000ff72 + .long 0x24482649,0x28482a49,0x528c528d,0x220a40c7 + .long 0x007c0700,0x4e7a6000,0x4e7b0000,0x4e7b0001 + .long 0xf58af58c,0xf58bf58d,0xf46af46c,0xf46bf46d + .long 0x24415681,0x2841f5ca,0xf5cc247c,0x80000000 + .long 0x267ca000,0x0000287c,0x00000000,0x20080800 + .long 0x00006600,0x009a6016,0x51fc51fc,0x51fc51fc + .long 0x4e7ba008,0x0e511000,0x0e500000,0x6002600e + .long 0xb042661c,0xb2436618,0x0e515800,0x6002600e + .long 0x4e7bb008,0x0e504800,0x4e7bc008,0x6034600e + .long 0x4e7bb008,0x0e500800,0x4e7bc008,0x6012600e + .long 0x4e714e71,0x4e714e71,0x4e714e71,0x4e7160b0 + .long 0x4e7b6000,0x4e7b6001,0x46c751c4,0x60ffffff + .long 0xfb624e7b,0x60004e7b,0x600146c7,0x50c460ff + .long 0xfffffb50,0x51fc51fc,0x51fc51fc,0x51fc51fc + .long 0x4e7ba008,0x0e511000,0x0e500000,0x6002600e + .long 0xb042662c,0xb2436628,0x0e515800,0x6002600e + .long 0xe09c0e18,0x48004e7b,0xb008e19c,0x6002600e + .long 0x0e104800,0x4e7bc008,0x6000ffa8,0x4e71600e + .long 0xe0980e18,0x08004e7b,0xb008e198,0x6002600e + .long 0x0e100800,0x4e7bc008,0x6000ff76,0x4e71600e + .long 0x4e714e71,0x4e714e71,0x4e714e71,0x4e716090 + .long 0x4a066604,0x70016002,0x70054a07,0x660000c6 + .long 0x22482448,0x528a2602,0xe04a40c7,0x007c0700 + .long 0x4e7a6000,0x4e7b0000,0x4e7b0001,0xf589f58a + .long 0xf469f46a,0x227c8000,0x0000247c,0xa0000000 + .long 0x267c0000,0x00006016,0x51fc51fc,0x51fc51fc + .long 0x4e7b9008,0x0e500000,0xb0446624,0x6002600e + .long 0x0e182800,0x4e7ba008,0x0e103800,0x6002600e + .long 0x4e7bb008,0x604c4e71,0x4e714e71,0x4e71600e + .long 0xe0980e18,0x08004e7b,0xa008e198,0x6002600e + .long 0x0e100800,0x4e7bb008,0x60164e71,0x4e71600e + .long 0x4e714e71,0x4e714e71,0x4e714e71,0x4e7160a0 + .long 0x4e7b6000,0x4e7b6001,0x46c751c1,0x60ffffff + .long 0xfb164e7b,0x60004e7b,0x600146c7,0x50c160ff + .long 0xfffffb04,0x22482448,0x568a2208,0x08010000 + .long 0x660000c2,0x26024842,0x40c7007c,0x07004e7a + .long 0x60004e7b,0x00004e7b,0x0001f589,0xf58af469 + .long 0xf46a227c,0x80000000,0x247ca000,0x0000267c + .long 0x00000000,0x601851fc,0x51fc51fc,0x51fc51fc + .long 0x4e7b9008,0x0e900000,0xb0846624,0x6002600e + .long 0x0e582800,0x4e7ba008,0x0e503800,0x6002600e + .long 0x4e7bb008,0x604c4e71,0x4e714e71,0x4e71600e + .long 0x48400e58,0x08004840,0x4e7ba008,0x6002600e + .long 0x0e500800,0x4e7bb008,0x60164e71,0x4e71600e + .long 0x4e714e71,0x4e714e71,0x4e714e71,0x4e7160a0 + .long 0x4e7b6000,0x4e7b6001,0x46c751c1,0x60ffffff + .long 0xfa464e7b,0x60004e7b,0x600146c7,0x50c160ff + .long 0xfffffa34,0x2a02e08a,0x26024842,0x40c7007c + .long 0x07004e7a,0x60004e7b,0x00004e7b,0x0001f589 + .long 0xf58af469,0xf46a227c,0x80000000,0x247ca000 + .long 0x0000267c,0x00000000,0x601451fc,0x51fc51fc + .long 0x4e7b9008,0x0e900000,0xb0846624,0x6002600e + .long 0x0e182800,0x0e583800,0x4e7ba008,0x6002600e + .long 0x0e105800,0x4e7bb008,0x6000ff88,0x4e71600e + .long 0xe1980e18,0x08004840,0x0e580800,0x6002600e + .long 0xe1984e7b,0xa0080e10,0x08006004,0x4e71600e + .long 0x4e7bb008,0x6000ff4a,0x4e714e71,0x4e71600e + .long 0x4e714e71,0x4e714e71,0x4e714e71,0x4e716090 diff --git a/arch/m68k/ifpsp060/itest.sa b/arch/m68k/ifpsp060/itest.sa new file mode 100644 index 000000000..7b15eaf63 --- /dev/null +++ b/arch/m68k/ifpsp060/itest.sa @@ -0,0 +1,1281 @@ + dc.l $60ff0000,$005c5465,$7374696e,$67203638 + dc.l $30363020,$49535020,$73746172,$7465643a + dc.l $0a007061,$73736564,$0a002066,$61696c65 + dc.l $640a0000,$4a80660e,$487affe8,$61ff0000 + dc.l $4f9a588f,$4e752f01,$61ff0000,$4fa4588f + dc.l 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$01700000,$03284282,$760247fa,$ff5449fa + dc.l $ff70288b,$99fc0000,$00107810,$3d7c0000 + dc.l $ff7c44fc,$000048ee,$ffffff80,$4c3b3402 + dc.l $4926ff70,$001042ee,$ff7e48ee,$ffffffc0 + dc.l $2d7c0000,$0004ff8c,$61ff0000,$02a84a00 + dc.l $66ff0000,$02ce52ae,$ff784cfb,$3fff0170 + dc.l $000002ca,$42827602,$47faff54,$49faff70 + dc.l $288b99fc,$00000010,$78083d7c,$0000ff7c + dc.l $44fc0000,$48eeffff,$ff804c3b,$34024326 + dc.l $ff700010,$42eeff7e,$48eeffff,$ffc02d7c + dc.l $00000004,$ff8c61ff,$0000024a,$4a0066ff + dc.l $00000270,$52aeff78,$4cfb3fff,$01700000 + dc.l $026c4282,$760247fa,$ff5449fa,$ff70288b + dc.l $99fc0000,$00107804,$3d7c0000,$ff7c44fc + dc.l $000048ee,$ffffff80,$4c3b3402,$4d26ff70 + dc.l $001042ee,$ff7e48ee,$ffffffc0,$2d7c0000 + dc.l $0004ff8c,$61ff0000,$01ec4a00,$66ff0000 + dc.l $021252ae,$ff784cfb,$3fff0170,$0000020e + dc.l $42827602,$47faff54,$49faff70,$288b99fc + dc.l $00000010,$78023d7c,$0000ff7c,$44fc0000 + dc.l $48eeffff,$ff804c3b,$34024f26,$ff700010 + dc.l $42eeff7e,$48eeffff,$ffc02d7c,$00000004 + dc.l $ff8c61ff,$0000018e,$4a0066ff,$000001b4 + dc.l $52aeff78,$4cfb3fff,$01700000,$01b04282 + dc.l $760247fa,$ff5449fa,$ff70288b,$99fc0000 + dc.l $00107802,$3d7c0000,$ff7c44fc,$000048ee + dc.l $ffffff80,$4c3b3402,$4f37ffff,$ff700000 + dc.l $001042ee,$ff7e48ee,$ffffffc0,$2d7c0000 + dc.l $0004ff8c,$61ff0000,$012c4a00,$66ff0000 + dc.l $015252ae,$ff784cfb,$3fff0170,$0000014e + dc.l $42827602,$47faff54,$49faff70,$288b7802 + dc.l $3d7c0000,$ff7c44fc,$000048ee,$ffffff80 + dc.l $4c3b3402,$0773ffff,$ff700000,$002042ee + dc.l $ff7e48ee,$ffffffc0,$2d7c0000,$0004ff8c + dc.l $61ff0000,$00d04a00,$66ff0000,$00f652ae + dc.l $ff784cfb,$3fff0170,$000000f2,$42827602 + dc.l $47faff54,$49faff70,$288b7804,$3d7c0000 + dc.l $ff7c44fc,$000048ee,$ffffff80,$4c303402 + dc.l $4fb5ffff,$ff7042ee,$ff7e48ee,$ffffffc0 + dc.l $2d7c0000,$0004ff8c,$61ff0000,$00784a00 + dc.l $66ff0000,$009e52ae,$ff784cfb,$3fff0170 + dc.l $0000009a,$204f4282,$760247fa,$ff744dfa + dc.l $ff702c8b,$ddfc0000,$00102e7c,$fffffffe + dc.l $3d7c0000,$ff7c44fc,$000048ee,$ffffff80 + dc.l $4c3b3402,$ff27ff70,$00000010,$42eeff7e + dc.l $48eeffff,$ffc02d7c,$00000004,$ff8c2e48 + dc.l $61ff0000,$00104a00,$66ff0000,$00364280 + dc.l $4e7541ee,$ff8043ee,$ffc0700e,$b18966ff + dc.l $0000001c,$51c8fff6,$302eff7c,$322eff7e + dc.l $b04166ff,$00000008,$42804e75,$70014e75 + dc.l $222eff78,$70014e75,$acacacac,$acacacac + dc.l $acacacac,$acacacac,$acacacac,$acacacac + dc.l $acacacac,$acacacac,$acacacac,$acacacac + dc.l $acacacac,$acacacac,$acacacac,$acacacac + dc.l $acacacac,$acacacac,$2f00203a,$afa4487b + dc.l $0930ffff,$afa0202f,$00044e74,$00042f00 + dc.l $203aaf92,$487b0930,$ffffaf8a,$202f0004 + dc.l $4e740004,$00000000,$00000000,$00000000 diff --git a/arch/m68k/ifpsp060/os.S b/arch/m68k/ifpsp060/os.S new file mode 100644 index 000000000..7a0d6e428 --- /dev/null +++ b/arch/m68k/ifpsp060/os.S @@ -0,0 +1,396 @@ +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +|MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP +|M68000 Hi-Performance Microprocessor Division +|M68060 Software Package +|Production Release P1.00 -- October 10, 1994 +| +|M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. +| +|THE SOFTWARE is provided on an "AS IS" basis and without warranty. +|To the maximum extent permitted by applicable law, +|MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, +|INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE +|and any warranty against infringement with regard to the SOFTWARE +|(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. +| +|To the maximum extent permitted by applicable law, +|IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +|(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, +|BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) +|ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. +|Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. +| +|You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE +|so long as this entire notice is retained without alteration in any modified and/or +|redistributed versions, and that such modified versions are clearly identified as such. +|No licenses are granted by implication, estoppel or otherwise under any patents +|or trademarks of Motorola, Inc. +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| os.s +| +| This file contains: +| - example "Call-Out"s required by both the ISP and FPSP. +| + +#include + +|################################ +| EXAMPLE CALL-OUTS # +| # +| _060_dmem_write() # +| _060_dmem_read() # +| _060_imem_read() # +| _060_dmem_read_byte() # +| _060_dmem_read_word() # +| _060_dmem_read_long() # +| _060_imem_read_word() # +| _060_imem_read_long() # +| _060_dmem_write_byte() # +| _060_dmem_write_word() # +| _060_dmem_write_long() # +| # +| _060_real_trace() # +| _060_real_access() # +|################################ + +| +| Each IO routine checks to see if the memory write/read is to/from user +| or supervisor application space. The examples below use simple "move" +| instructions for supervisor mode applications and call _copyin()/_copyout() +| for user mode applications. +| When installing the 060SP, the _copyin()/_copyout() equivalents for a +| given operating system should be substituted. +| +| The addresses within the 060SP are guaranteed to be on the stack. +| The result is that Unix processes are allowed to sleep as a consequence +| of a page fault during a _copyout. +| +| Linux/68k: The _060_[id]mem_{read,write}_{byte,word,long} functions +| (i.e. all the known length <= 4) are implemented by single moves +| statements instead of (more expensive) copy{in,out} calls, if +| working in user space + +| +| _060_dmem_write(): +| +| Writes to data memory while in supervisor mode. +| +| INPUTS: +| a0 - supervisor source address +| a1 - user destination address +| d0 - number of bytes to write +| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode +| OUTPUTS: +| d1 - 0 = success, !0 = failure +| + .global _060_dmem_write +_060_dmem_write: + subq.l #1,%d0 + btst #0x5,0x4(%a6) | check for supervisor state + beqs user_write +super_write: + move.b (%a0)+,(%a1)+ | copy 1 byte + dbra %d0,super_write | quit if --ctr < 0 + clr.l %d1 | return success + rts +user_write: + move.b (%a0)+,%d1 | copy 1 byte +copyoutae: + movs.b %d1,(%a1)+ + dbra %d0,user_write | quit if --ctr < 0 + clr.l %d1 | return success + rts + +| +| _060_imem_read(), _060_dmem_read(): +| +| Reads from data/instruction memory while in supervisor mode. +| +| INPUTS: +| a0 - user source address +| a1 - supervisor destination address +| d0 - number of bytes to read +| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode +| OUTPUTS: +| d1 - 0 = success, !0 = failure +| + .global _060_imem_read + .global _060_dmem_read +_060_imem_read: +_060_dmem_read: + subq.l #1,%d0 + btst #0x5,0x4(%a6) | check for supervisor state + beqs user_read +super_read: + move.b (%a0)+,(%a1)+ | copy 1 byte + dbra %d0,super_read | quit if --ctr < 0 + clr.l %d1 | return success + rts +user_read: +copyinae: + movs.b (%a0)+,%d1 + move.b %d1,(%a1)+ | copy 1 byte + dbra %d0,user_read | quit if --ctr < 0 + clr.l %d1 | return success + rts + +| +| _060_dmem_read_byte(): +| +| Read a data byte from user memory. +| +| INPUTS: +| a0 - user source address +| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode +| OUTPUTS: +| d0 - data byte in d0 +| d1 - 0 = success, !0 = failure +| + .global _060_dmem_read_byte +_060_dmem_read_byte: + clr.l %d0 | clear whole longword + clr.l %d1 | assume success + btst #0x5,0x4(%a6) | check for supervisor state + bnes dmrbs | supervisor +dmrbuae:movs.b (%a0),%d0 | fetch user byte + rts +dmrbs: move.b (%a0),%d0 | fetch super byte + rts + +| +| _060_dmem_read_word(): +| +| Read a data word from user memory. +| +| INPUTS: +| a0 - user source address +| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode +| OUTPUTS: +| d0 - data word in d0 +| d1 - 0 = success, !0 = failure +| +| _060_imem_read_word(): +| +| Read an instruction word from user memory. +| +| INPUTS: +| a0 - user source address +| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode +| OUTPUTS: +| d0 - instruction word in d0 +| d1 - 0 = success, !0 = failure +| + .global _060_dmem_read_word + .global _060_imem_read_word +_060_dmem_read_word: +_060_imem_read_word: + clr.l %d1 | assume success + clr.l %d0 | clear whole longword + btst #0x5,0x4(%a6) | check for supervisor state + bnes dmrws | supervisor +dmrwuae:movs.w (%a0), %d0 | fetch user word + rts +dmrws: move.w (%a0), %d0 | fetch super word + rts + +| +| _060_dmem_read_long(): +| + +| +| INPUTS: +| a0 - user source address +| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode +| OUTPUTS: +| d0 - data longword in d0 +| d1 - 0 = success, !0 = failure +| +| _060_imem_read_long(): +| +| Read an instruction longword from user memory. +| +| INPUTS: +| a0 - user source address +| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode +| OUTPUTS: +| d0 - instruction longword in d0 +| d1 - 0 = success, !0 = failure +| + .global _060_dmem_read_long + .global _060_imem_read_long +_060_dmem_read_long: +_060_imem_read_long: + clr.l %d1 | assume success + btst #0x5,0x4(%a6) | check for supervisor state + bnes dmrls | supervisor +dmrluae:movs.l (%a0),%d0 | fetch user longword + rts +dmrls: move.l (%a0),%d0 | fetch super longword + rts + +| +| _060_dmem_write_byte(): +| +| Write a data byte to user memory. +| +| INPUTS: +| a0 - user destination address +| d0 - data byte in d0 +| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode +| OUTPUTS: +| d1 - 0 = success, !0 = failure +| + .global _060_dmem_write_byte +_060_dmem_write_byte: + clr.l %d1 | assume success + btst #0x5,0x4(%a6) | check for supervisor state + bnes dmwbs | supervisor +dmwbuae:movs.b %d0,(%a0) | store user byte + rts +dmwbs: move.b %d0,(%a0) | store super byte + rts + +| +| _060_dmem_write_word(): +| +| Write a data word to user memory. +| +| INPUTS: +| a0 - user destination address +| d0 - data word in d0 +| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode +| OUTPUTS: +| d1 - 0 = success, !0 = failure +| + .global _060_dmem_write_word +_060_dmem_write_word: + clr.l %d1 | assume success + btst #0x5,0x4(%a6) | check for supervisor state + bnes dmwws | supervisor +dmwwu: +dmwwuae:movs.w %d0,(%a0) | store user word + bras dmwwr +dmwws: move.w %d0,(%a0) | store super word +dmwwr: clr.l %d1 | return success + rts + +| +| _060_dmem_write_long(): +| +| Write a data longword to user memory. +| +| INPUTS: +| a0 - user destination address +| d0 - data longword in d0 +| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode +| OUTPUTS: +| d1 - 0 = success, !0 = failure +| + .global _060_dmem_write_long +_060_dmem_write_long: + clr.l %d1 | assume success + btst #0x5,0x4(%a6) | check for supervisor state + bnes dmwls | supervisor +dmwluae:movs.l %d0,(%a0) | store user longword + rts +dmwls: move.l %d0,(%a0) | store super longword + rts + + +#if 0 +|############################################### + +| +| Use these routines if your kernel doesn't have _copyout/_copyin equivalents. +| Assumes that D0/D1/A0/A1 are scratch registers. The _copyin/_copyout +| below assume that the SFC/DFC have been set previously. +| +| Linux/68k: These are basically non-inlined versions of +| memcpy_{to,from}fs, but without long-transfer optimization +| Note: Assumed that SFC/DFC are pointing correctly to user data +| space... Should be right, or are there any exceptions? + +| +| int _copyout(supervisor_addr, user_addr, nbytes) +| + .global _copyout +_copyout: + move.l 4(%sp),%a0 | source + move.l 8(%sp),%a1 | destination + move.l 12(%sp),%d0 | count + subq.l #1,%d0 +moreout: + move.b (%a0)+,%d1 | fetch supervisor byte +copyoutae: + movs.b %d1,(%a1)+ | store user byte + dbra %d0,moreout | are we through yet? + moveq #0,%d0 | return success + rts + +| +| int _copyin(user_addr, supervisor_addr, nbytes) +| + .global _copyin +_copyin: + move.l 4(%sp),%a0 | source + move.l 8(%sp),%a1 | destination + move.l 12(%sp),%d0 | count + subq.l #1,%d0 +morein: +copyinae: + movs.b (%a0)+,%d1 | fetch user byte + move.b %d1,(%a1)+ | write supervisor byte + dbra %d0,morein | are we through yet? + moveq #0,%d0 | return success + rts +#endif + +|########################################################################### + +| +| _060_real_trace(): +| +| This is the exit point for the 060FPSP when an instruction is being traced +| and there are no other higher priority exceptions pending for this instruction +| or they have already been processed. +| +| The sample code below simply executes an "rte". +| + .global _060_real_trace +_060_real_trace: + bral trap + +| +| _060_real_access(): +| +| This is the exit point for the 060FPSP when an access error exception +| is encountered. The routine below should point to the operating system +| handler for access error exceptions. The exception stack frame is an +| 8-word access error frame. +| +| The sample routine below simply executes an "rte" instruction which +| is most likely the incorrect thing to do and could put the system +| into an infinite loop. +| + .global _060_real_access +_060_real_access: + bral buserr + + + +| Execption handling for movs access to illegal memory + .section .fixup,#alloc,#execinstr + .even +1: moveq #-1,%d1 + rts +.section __ex_table,#alloc + .align 4 + .long dmrbuae,1b + .long dmrwuae,1b + .long dmrluae,1b + .long dmwbuae,1b + .long dmwwuae,1b + .long dmwluae,1b + .long copyoutae,1b + .long copyinae,1b + .text diff --git a/arch/m68k/ifpsp060/pfpsp.sa b/arch/m68k/ifpsp060/pfpsp.sa new file mode 100644 index 000000000..d276b27f1 --- /dev/null +++ b/arch/m68k/ifpsp060/pfpsp.sa @@ -0,0 +1,1730 @@ + dc.l $60ff0000,$17400000,$60ff0000,$15f40000 + dc.l $60ff0000,$02b60000,$60ff0000,$04700000 + dc.l $60ff0000,$1b100000,$60ff0000,$19aa0000 + dc.l $60ff0000,$1b5a0000,$60ff0000,$062e0000 + dc.l $60ff0000,$102c0000,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $2f00203a,$ff2c487b,$0930ffff,$fef8202f + dc.l $00044e74,$00042f00,$203afef2,$487b0930 + dc.l $fffffee2,$202f0004,$4e740004,$2f00203a + dc.l $fee0487b,$0930ffff,$fecc202f,$00044e74 + dc.l $00042f00,$203afed2,$487b0930,$fffffeb6 + dc.l $202f0004,$4e740004,$2f00203a,$fea4487b + dc.l $0930ffff,$fea0202f,$00044e74,$00042f00 + dc.l $203afe96,$487b0930,$fffffe8a,$202f0004 + dc.l $4e740004,$2f00203a,$fe7c487b,$0930ffff + dc.l $fe74202f,$00044e74,$00042f00,$203afe76 + dc.l $487b0930,$fffffe5e,$202f0004,$4e740004 + dc.l $2f00203a,$fe68487b,$0930ffff,$fe48202f + dc.l $00044e74,$00042f00,$203afe56,$487b0930 + dc.l $fffffe32,$202f0004,$4e740004,$2f00203a + dc.l $fe44487b,$0930ffff,$fe1c202f,$00044e74 + dc.l $00042f00,$203afe32,$487b0930,$fffffe06 + dc.l $202f0004,$4e740004,$2f00203a,$fe20487b + dc.l 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$fb9a6008,$f2064000,$f2000018,$f2294820 + dc.l $0018f22e,$6800ff90,$242a0004,$262a0008 + dc.l $3012670e,$04403ffd,$4440e28a,$e29351c8 + dc.l $fffa4281,$06830000,$0080d581,$0283ffff + dc.l $ff807004,$41eeff54,$61ff0000,$0228202e + dc.l $ff54720c,$e2a8efee,$010cff84,$e2a8efee + dc.l $0404ff84,$4a006708,$00ae0000,$2080ff64 + dc.l $4280022e,$000fff84,$4aaeff58,$6c027002 + dc.l $4a866c02,$5280efee,$0002ff84,$f23c8800 + dc.l $00000000,$f21fd0e0,$4cdf04fc,$4e754002 + dc.l $0000a000,$00000000,$00004005,$0000c800 + dc.l $00000000,$0000400c,$00009c40,$00000000 + dc.l $00004019,$0000bebc,$20000000,$00004034 + dc.l $00008e1b,$c9bf0400,$00004069,$00009dc5 + dc.l $ada82b70,$b59e40d3,$0000c278,$1f49ffcf + dc.l $a6d541a8,$000093ba,$47c980e9,$8ce04351 + dc.l $0000aa7e,$ebfb9df9,$de8e46a3,$0000e319 + dc.l $a0aea60e,$91c74d48,$0000c976,$75868175 + dc.l $0c175a92,$00009e8b,$3b5dc53d,$5de57525 + dc.l $0000c460,$52028a20,$979b4002,$0000a000 + dc.l $00000000,$00004005,$0000c800,$00000000 + dc.l $0000400c,$00009c40,$00000000,$00004019 + dc.l $0000bebc,$20000000,$00004034,$00008e1b + dc.l $c9bf0400,$00004069,$00009dc5,$ada82b70 + dc.l $b59e40d3,$0000c278,$1f49ffcf,$a6d641a8 + dc.l $000093ba,$47c980e9,$8ce04351,$0000aa7e + dc.l $ebfb9df9,$de8e46a3,$0000e319,$a0aea60e + dc.l $91c74d48,$0000c976,$75868175,$0c185a92 + dc.l $00009e8b,$3b5dc53d,$5de57525,$0000c460 + dc.l $52028a20,$979b4002,$0000a000,$00000000 + dc.l $00004005,$0000c800,$00000000,$0000400c + dc.l $00009c40,$00000000,$00004019,$0000bebc + dc.l $20000000,$00004034,$00008e1b,$c9bf0400 + dc.l $00004069,$00009dc5,$ada82b70,$b59d40d3 + dc.l $0000c278,$1f49ffcf,$a6d541a8,$000093ba + dc.l $47c980e9,$8cdf4351,$0000aa7e,$ebfb9df9 + dc.l $de8d46a3,$0000e319,$a0aea60e,$91c64d48 + dc.l $0000c976,$75868175,$0c175a92,$00009e8b + dc.l $3b5dc53d,$5de47525,$0000c460,$52028a20 + dc.l $979a48e7,$ff007e01,$53802802,$2a03e9c2 + dc.l $1003e782,$e9c36003,$e7838486,$e385e394 + dc.l $4846d346,$d6854e71,$d5844e71,$d3464846 + dc.l $4a476712,$4847e947,$de4110c7,$48474247 + dc.l $51c8ffc8,$60124847,$3e014847,$524751c8 + dc.l $ffba4847,$e94f10c7,$4cdf00ff,$4e757001 + dc.l $610000d6,$3d7c0121,$000a6000,$007e7002 + dc.l $610000c6,$3d7c0141,$000a606e,$70046100 + dc.l $00b83d7c,$0101000a,$60607008,$610000aa + dc.l $3d7c0161,$000a6052,$700c6100,$009c3d7c + dc.l $0161000a,$60447001,$6100008e,$3d7c00a1 + dc.l $000a6036,$70026100,$00803d7c,$00c1000a + dc.l $60287004,$61000072,$3d7c0081,$000a601a + dc.l $70086100,$00643d7c,$00e1000a,$600c700c + dc.l $61000056,$3d7c00e1,$000a2d6e,$ff680006 + dc.l $f22ed0c0,$ffdcf22e,$9c00ff60,$4cee0303 + dc.l $ff9c4e5e,$2f172f6f,$00080004,$2f6f000c + dc.l $00082f7c,$00000001,$000c3f6f,$0006000c + dc.l $3f7c4008,$00060817,$00056706,$08ef0002 + dc.l $000d60ff,$ffff95f4,$122eff41,$02010038 + dc.l $0c010018,$6700000c,$0c010020,$67000060 + dc.l $4e75122e,$ff410241,$0007323b,$12064efb + dc.l $10020010,$0016001c,$00200024,$0028002c + dc.l $003091ae,$ffa44e75,$91aeffa8,$4e7595c0 + dc.l $4e7597c0,$4e7599c0,$4e759bc0,$4e759196 + dc.l $4e750c2e,$0030000a,$6612082e,$00050004 + dc.l $660a4e7a,$880091c0,$4e7b8800,$4e754480 + dc.l $60a051fc,$00000000,$00000000,$00000000 diff --git a/arch/m68k/ifpsp060/src/README-SRC b/arch/m68k/ifpsp060/src/README-SRC new file mode 100644 index 000000000..6be5cff2a --- /dev/null +++ b/arch/m68k/ifpsp060/src/README-SRC @@ -0,0 +1,12 @@ +This is the original source code from Motorola for the 68060 processor +support code, providing emulation for rarely used m68k instructions +not implemented in the 68060 silicon. + +The code provided here will not assemble out of the box using the GNU +assembler, however it is being included in order to comply with the +GNU General Public License. + +You don't need to actually assemble these files in order to compile a +workin m68k kernel, the precompiled .sa files in arch/m68k/ifpsp060 +are sufficient and were generated from these source files by +Motorola. diff --git a/arch/m68k/ifpsp060/src/fplsp.S b/arch/m68k/ifpsp060/src/fplsp.S new file mode 100644 index 000000000..3b7ea2dc9 --- /dev/null +++ b/arch/m68k/ifpsp060/src/fplsp.S @@ -0,0 +1,10980 @@ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP +M68000 Hi-Performance Microprocessor Division +M68060 Software Package +Production Release P1.00 -- October 10, 1994 + +M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. + +THE SOFTWARE is provided on an "AS IS" basis and without warranty. +To the maximum extent permitted by applicable law, +MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, +INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE +and any warranty against infringement with regard to the SOFTWARE +(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. + +To the maximum extent permitted by applicable law, +IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, +BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) +ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. +Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. + +You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE +so long as this entire notice is retained without alteration in any modified and/or +redistributed versions, and that such modified versions are clearly identified as such. +No licenses are granted by implication, estoppel or otherwise under any patents +or trademarks of Motorola, Inc. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +# +# lfptop.s: +# This file is appended to the top of the 060ILSP package +# and contains the entry points into the package. The user, in +# effect, branches to one of the branch table entries located here. +# + + bra.l _facoss_ + short 0x0000 + bra.l _facosd_ + short 0x0000 + bra.l _facosx_ + short 0x0000 + + bra.l _fasins_ + short 0x0000 + bra.l _fasind_ + short 0x0000 + bra.l _fasinx_ + short 0x0000 + + bra.l _fatans_ + short 0x0000 + bra.l _fatand_ + short 0x0000 + bra.l _fatanx_ + short 0x0000 + + bra.l _fatanhs_ + short 0x0000 + bra.l _fatanhd_ + short 0x0000 + bra.l _fatanhx_ + short 0x0000 + + bra.l _fcoss_ + short 0x0000 + bra.l _fcosd_ + short 0x0000 + bra.l _fcosx_ + short 0x0000 + + bra.l _fcoshs_ + short 0x0000 + bra.l _fcoshd_ + short 0x0000 + bra.l _fcoshx_ + short 0x0000 + + bra.l _fetoxs_ + short 0x0000 + bra.l _fetoxd_ + short 0x0000 + bra.l _fetoxx_ + short 0x0000 + + bra.l _fetoxm1s_ + short 0x0000 + bra.l _fetoxm1d_ + short 0x0000 + bra.l _fetoxm1x_ + short 0x0000 + + bra.l _fgetexps_ + short 0x0000 + bra.l _fgetexpd_ + short 0x0000 + bra.l _fgetexpx_ + short 0x0000 + + bra.l _fgetmans_ + short 0x0000 + bra.l _fgetmand_ + short 0x0000 + bra.l _fgetmanx_ + short 0x0000 + + bra.l _flog10s_ + short 0x0000 + bra.l _flog10d_ + short 0x0000 + bra.l _flog10x_ + short 0x0000 + + bra.l _flog2s_ + short 0x0000 + bra.l _flog2d_ + short 0x0000 + bra.l _flog2x_ + short 0x0000 + + bra.l _flogns_ + short 0x0000 + bra.l _flognd_ + short 0x0000 + bra.l _flognx_ + short 0x0000 + + bra.l _flognp1s_ + short 0x0000 + bra.l _flognp1d_ + short 0x0000 + bra.l _flognp1x_ + short 0x0000 + + bra.l _fmods_ + short 0x0000 + bra.l _fmodd_ + short 0x0000 + bra.l _fmodx_ + short 0x0000 + + bra.l _frems_ + short 0x0000 + bra.l _fremd_ + short 0x0000 + bra.l _fremx_ + short 0x0000 + + bra.l _fscales_ + short 0x0000 + bra.l _fscaled_ + short 0x0000 + bra.l _fscalex_ + short 0x0000 + + bra.l _fsins_ + short 0x0000 + bra.l _fsind_ + short 0x0000 + bra.l _fsinx_ + short 0x0000 + + bra.l _fsincoss_ + short 0x0000 + bra.l _fsincosd_ + short 0x0000 + bra.l _fsincosx_ + short 0x0000 + + bra.l _fsinhs_ + short 0x0000 + bra.l _fsinhd_ + short 0x0000 + bra.l _fsinhx_ + short 0x0000 + + bra.l _ftans_ + short 0x0000 + bra.l _ftand_ + short 0x0000 + bra.l _ftanx_ + short 0x0000 + + bra.l _ftanhs_ + short 0x0000 + bra.l _ftanhd_ + short 0x0000 + bra.l _ftanhx_ + short 0x0000 + + bra.l _ftentoxs_ + short 0x0000 + bra.l _ftentoxd_ + short 0x0000 + bra.l _ftentoxx_ + short 0x0000 + + bra.l _ftwotoxs_ + short 0x0000 + bra.l _ftwotoxd_ + short 0x0000 + bra.l _ftwotoxx_ + short 0x0000 + + bra.l _fabss_ + short 0x0000 + bra.l _fabsd_ + short 0x0000 + bra.l _fabsx_ + short 0x0000 + + bra.l _fadds_ + short 0x0000 + bra.l _faddd_ + short 0x0000 + bra.l _faddx_ + short 0x0000 + + bra.l _fdivs_ + short 0x0000 + bra.l _fdivd_ + short 0x0000 + bra.l _fdivx_ + short 0x0000 + + bra.l _fints_ + short 0x0000 + bra.l _fintd_ + short 0x0000 + bra.l _fintx_ + short 0x0000 + + bra.l _fintrzs_ + short 0x0000 + bra.l _fintrzd_ + short 0x0000 + bra.l _fintrzx_ + short 0x0000 + + bra.l _fmuls_ + short 0x0000 + bra.l _fmuld_ + short 0x0000 + bra.l _fmulx_ + short 0x0000 + + bra.l _fnegs_ + short 0x0000 + bra.l _fnegd_ + short 0x0000 + bra.l _fnegx_ + short 0x0000 + + bra.l _fsqrts_ + short 0x0000 + bra.l _fsqrtd_ + short 0x0000 + bra.l _fsqrtx_ + short 0x0000 + + bra.l _fsubs_ + short 0x0000 + bra.l _fsubd_ + short 0x0000 + bra.l _fsubx_ + short 0x0000 + +# leave room for future possible additions + align 0x400 + +# +# This file contains a set of define statements for constants +# in order to promote readability within the corecode itself. +# + +set LOCAL_SIZE, 192 # stack frame size(bytes) +set LV, -LOCAL_SIZE # stack offset + +set EXC_SR, 0x4 # stack status register +set EXC_PC, 0x6 # stack pc +set EXC_VOFF, 0xa # stacked vector offset +set EXC_EA, 0xc # stacked + +set EXC_FP, 0x0 # frame pointer + +set EXC_AREGS, -68 # offset of all address regs +set EXC_DREGS, -100 # offset of all data regs +set EXC_FPREGS, -36 # offset of all fp regs + +set EXC_A7, EXC_AREGS+(7*4) # offset of saved a7 +set OLD_A7, EXC_AREGS+(6*4) # extra copy of saved a7 +set EXC_A6, EXC_AREGS+(6*4) # offset of saved a6 +set EXC_A5, EXC_AREGS+(5*4) +set EXC_A4, EXC_AREGS+(4*4) +set EXC_A3, EXC_AREGS+(3*4) +set EXC_A2, EXC_AREGS+(2*4) +set EXC_A1, EXC_AREGS+(1*4) +set EXC_A0, EXC_AREGS+(0*4) +set EXC_D7, EXC_DREGS+(7*4) +set EXC_D6, EXC_DREGS+(6*4) +set EXC_D5, EXC_DREGS+(5*4) +set EXC_D4, EXC_DREGS+(4*4) +set EXC_D3, EXC_DREGS+(3*4) +set EXC_D2, EXC_DREGS+(2*4) +set EXC_D1, EXC_DREGS+(1*4) +set EXC_D0, EXC_DREGS+(0*4) + +set EXC_FP0, EXC_FPREGS+(0*12) # offset of saved fp0 +set EXC_FP1, EXC_FPREGS+(1*12) # offset of saved fp1 +set EXC_FP2, EXC_FPREGS+(2*12) # offset of saved fp2 (not used) + +set FP_SCR1, LV+80 # fp scratch 1 +set FP_SCR1_EX, FP_SCR1+0 +set FP_SCR1_SGN, FP_SCR1+2 +set FP_SCR1_HI, FP_SCR1+4 +set FP_SCR1_LO, FP_SCR1+8 + +set FP_SCR0, LV+68 # fp scratch 0 +set FP_SCR0_EX, FP_SCR0+0 +set FP_SCR0_SGN, FP_SCR0+2 +set FP_SCR0_HI, FP_SCR0+4 +set FP_SCR0_LO, FP_SCR0+8 + +set FP_DST, LV+56 # fp destination operand +set FP_DST_EX, FP_DST+0 +set FP_DST_SGN, FP_DST+2 +set FP_DST_HI, FP_DST+4 +set FP_DST_LO, FP_DST+8 + +set FP_SRC, LV+44 # fp source operand +set FP_SRC_EX, FP_SRC+0 +set FP_SRC_SGN, FP_SRC+2 +set FP_SRC_HI, FP_SRC+4 +set FP_SRC_LO, FP_SRC+8 + +set USER_FPIAR, LV+40 # FP instr address register + +set USER_FPSR, LV+36 # FP status register +set FPSR_CC, USER_FPSR+0 # FPSR condition codes +set FPSR_QBYTE, USER_FPSR+1 # FPSR qoutient byte +set FPSR_EXCEPT, USER_FPSR+2 # FPSR exception status byte +set FPSR_AEXCEPT, USER_FPSR+3 # FPSR accrued exception byte + +set USER_FPCR, LV+32 # FP control register +set FPCR_ENABLE, USER_FPCR+2 # FPCR exception enable +set FPCR_MODE, USER_FPCR+3 # FPCR rounding mode control + +set L_SCR3, LV+28 # integer scratch 3 +set L_SCR2, LV+24 # integer scratch 2 +set L_SCR1, LV+20 # integer scratch 1 + +set STORE_FLG, LV+19 # flag: operand store (ie. not fcmp/ftst) + +set EXC_TEMP2, LV+24 # temporary space +set EXC_TEMP, LV+16 # temporary space + +set DTAG, LV+15 # destination operand type +set STAG, LV+14 # source operand type + +set SPCOND_FLG, LV+10 # flag: special case (see below) + +set EXC_CC, LV+8 # saved condition codes +set EXC_EXTWPTR, LV+4 # saved current PC (active) +set EXC_EXTWORD, LV+2 # saved extension word +set EXC_CMDREG, LV+2 # saved extension word +set EXC_OPWORD, LV+0 # saved operation word + +################################ + +# Helpful macros + +set FTEMP, 0 # offsets within an +set FTEMP_EX, 0 # extended precision +set FTEMP_SGN, 2 # value saved in memory. +set FTEMP_HI, 4 +set FTEMP_LO, 8 +set FTEMP_GRS, 12 + +set LOCAL, 0 # offsets within an +set LOCAL_EX, 0 # extended precision +set LOCAL_SGN, 2 # value saved in memory. +set LOCAL_HI, 4 +set LOCAL_LO, 8 +set LOCAL_GRS, 12 + +set DST, 0 # offsets within an +set DST_EX, 0 # extended precision +set DST_HI, 4 # value saved in memory. +set DST_LO, 8 + +set SRC, 0 # offsets within an +set SRC_EX, 0 # extended precision +set SRC_HI, 4 # value saved in memory. +set SRC_LO, 8 + +set SGL_LO, 0x3f81 # min sgl prec exponent +set SGL_HI, 0x407e # max sgl prec exponent +set DBL_LO, 0x3c01 # min dbl prec exponent +set DBL_HI, 0x43fe # max dbl prec exponent +set EXT_LO, 0x0 # min ext prec exponent +set EXT_HI, 0x7ffe # max ext prec exponent + +set EXT_BIAS, 0x3fff # extended precision bias +set SGL_BIAS, 0x007f # single precision bias +set DBL_BIAS, 0x03ff # double precision bias + +set NORM, 0x00 # operand type for STAG/DTAG +set ZERO, 0x01 # operand type for STAG/DTAG +set INF, 0x02 # operand type for STAG/DTAG +set QNAN, 0x03 # operand type for STAG/DTAG +set DENORM, 0x04 # operand type for STAG/DTAG +set SNAN, 0x05 # operand type for STAG/DTAG +set UNNORM, 0x06 # operand type for STAG/DTAG + +################## +# FPSR/FPCR bits # +################## +set neg_bit, 0x3 # negative result +set z_bit, 0x2 # zero result +set inf_bit, 0x1 # infinite result +set nan_bit, 0x0 # NAN result + +set q_sn_bit, 0x7 # sign bit of quotient byte + +set bsun_bit, 7 # branch on unordered +set snan_bit, 6 # signalling NAN +set operr_bit, 5 # operand error +set ovfl_bit, 4 # overflow +set unfl_bit, 3 # underflow +set dz_bit, 2 # divide by zero +set inex2_bit, 1 # inexact result 2 +set inex1_bit, 0 # inexact result 1 + +set aiop_bit, 7 # accrued inexact operation bit +set aovfl_bit, 6 # accrued overflow bit +set aunfl_bit, 5 # accrued underflow bit +set adz_bit, 4 # accrued dz bit +set ainex_bit, 3 # accrued inexact bit + +############################# +# FPSR individual bit masks # +############################# +set neg_mask, 0x08000000 # negative bit mask (lw) +set inf_mask, 0x02000000 # infinity bit mask (lw) +set z_mask, 0x04000000 # zero bit mask (lw) +set nan_mask, 0x01000000 # nan bit mask (lw) + +set neg_bmask, 0x08 # negative bit mask (byte) +set inf_bmask, 0x02 # infinity bit mask (byte) +set z_bmask, 0x04 # zero bit mask (byte) +set nan_bmask, 0x01 # nan bit mask (byte) + +set bsun_mask, 0x00008000 # bsun exception mask +set snan_mask, 0x00004000 # snan exception mask +set operr_mask, 0x00002000 # operr exception mask +set ovfl_mask, 0x00001000 # overflow exception mask +set unfl_mask, 0x00000800 # underflow exception mask +set dz_mask, 0x00000400 # dz exception mask +set inex2_mask, 0x00000200 # inex2 exception mask +set inex1_mask, 0x00000100 # inex1 exception mask + +set aiop_mask, 0x00000080 # accrued illegal operation +set aovfl_mask, 0x00000040 # accrued overflow +set aunfl_mask, 0x00000020 # accrued underflow +set adz_mask, 0x00000010 # accrued divide by zero +set ainex_mask, 0x00000008 # accrued inexact + +###################################### +# FPSR combinations used in the FPSP # +###################################### +set dzinf_mask, inf_mask+dz_mask+adz_mask +set opnan_mask, nan_mask+operr_mask+aiop_mask +set nzi_mask, 0x01ffffff #clears N, Z, and I +set unfinx_mask, unfl_mask+inex2_mask+aunfl_mask+ainex_mask +set unf2inx_mask, unfl_mask+inex2_mask+ainex_mask +set ovfinx_mask, ovfl_mask+inex2_mask+aovfl_mask+ainex_mask +set inx1a_mask, inex1_mask+ainex_mask +set inx2a_mask, inex2_mask+ainex_mask +set snaniop_mask, nan_mask+snan_mask+aiop_mask +set snaniop2_mask, snan_mask+aiop_mask +set naniop_mask, nan_mask+aiop_mask +set neginf_mask, neg_mask+inf_mask +set infaiop_mask, inf_mask+aiop_mask +set negz_mask, neg_mask+z_mask +set opaop_mask, operr_mask+aiop_mask +set unfl_inx_mask, unfl_mask+aunfl_mask+ainex_mask +set ovfl_inx_mask, ovfl_mask+aovfl_mask+ainex_mask + +######### +# misc. # +######### +set rnd_stky_bit, 29 # stky bit pos in longword + +set sign_bit, 0x7 # sign bit +set signan_bit, 0x6 # signalling nan bit + +set sgl_thresh, 0x3f81 # minimum sgl exponent +set dbl_thresh, 0x3c01 # minimum dbl exponent + +set x_mode, 0x0 # extended precision +set s_mode, 0x4 # single precision +set d_mode, 0x8 # double precision + +set rn_mode, 0x0 # round-to-nearest +set rz_mode, 0x1 # round-to-zero +set rm_mode, 0x2 # round-tp-minus-infinity +set rp_mode, 0x3 # round-to-plus-infinity + +set mantissalen, 64 # length of mantissa in bits + +set BYTE, 1 # len(byte) == 1 byte +set WORD, 2 # len(word) == 2 bytes +set LONG, 4 # len(longword) == 2 bytes + +set BSUN_VEC, 0xc0 # bsun vector offset +set INEX_VEC, 0xc4 # inexact vector offset +set DZ_VEC, 0xc8 # dz vector offset +set UNFL_VEC, 0xcc # unfl vector offset +set OPERR_VEC, 0xd0 # operr vector offset +set OVFL_VEC, 0xd4 # ovfl vector offset +set SNAN_VEC, 0xd8 # snan vector offset + +########################### +# SPecial CONDition FLaGs # +########################### +set ftrapcc_flg, 0x01 # flag bit: ftrapcc exception +set fbsun_flg, 0x02 # flag bit: bsun exception +set mia7_flg, 0x04 # flag bit: (a7)+ +set mda7_flg, 0x08 # flag bit: -(a7) +set fmovm_flg, 0x40 # flag bit: fmovm instruction +set immed_flg, 0x80 # flag bit: & + +set ftrapcc_bit, 0x0 +set fbsun_bit, 0x1 +set mia7_bit, 0x2 +set mda7_bit, 0x3 +set immed_bit, 0x7 + +################################## +# TRANSCENDENTAL "LAST-OP" FLAGS # +################################## +set FMUL_OP, 0x0 # fmul instr performed last +set FDIV_OP, 0x1 # fdiv performed last +set FADD_OP, 0x2 # fadd performed last +set FMOV_OP, 0x3 # fmov performed last + +############# +# CONSTANTS # +############# +T1: long 0x40C62D38,0xD3D64634 # 16381 LOG2 LEAD +T2: long 0x3D6F90AE,0xB1E75CC7 # 16381 LOG2 TRAIL + +PI: long 0x40000000,0xC90FDAA2,0x2168C235,0x00000000 +PIBY2: long 0x3FFF0000,0xC90FDAA2,0x2168C235,0x00000000 + +TWOBYPI: + long 0x3FE45F30,0x6DC9C883 + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _fsins_ +_fsins_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L0_2s + bsr.l ssin # operand is a NORM + bra.b _L0_6s +_L0_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L0_3s # no + bsr.l src_zero # yes + bra.b _L0_6s +_L0_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L0_4s # no + bsr.l t_operr # yes + bra.b _L0_6s +_L0_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L0_5s # no + bsr.l src_qnan # yes + bra.b _L0_6s +_L0_5s: + bsr.l ssind # operand is a DENORM +_L0_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fsind_ +_fsind_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L0_2d + bsr.l ssin # operand is a NORM + bra.b _L0_6d +_L0_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L0_3d # no + bsr.l src_zero # yes + bra.b _L0_6d +_L0_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L0_4d # no + bsr.l t_operr # yes + bra.b _L0_6d +_L0_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L0_5d # no + bsr.l src_qnan # yes + bra.b _L0_6d +_L0_5d: + bsr.l ssind # operand is a DENORM +_L0_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fsinx_ +_fsinx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L0_2x + bsr.l ssin # operand is a NORM + bra.b _L0_6x +_L0_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L0_3x # no + bsr.l src_zero # yes + bra.b _L0_6x +_L0_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L0_4x # no + bsr.l t_operr # yes + bra.b _L0_6x +_L0_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L0_5x # no + bsr.l src_qnan # yes + bra.b _L0_6x +_L0_5x: + bsr.l ssind # operand is a DENORM +_L0_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _fcoss_ +_fcoss_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L1_2s + bsr.l scos # operand is a NORM + bra.b _L1_6s +_L1_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L1_3s # no + bsr.l ld_pone # yes + bra.b _L1_6s +_L1_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L1_4s # no + bsr.l t_operr # yes + bra.b _L1_6s +_L1_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L1_5s # no + bsr.l src_qnan # yes + bra.b _L1_6s +_L1_5s: + bsr.l scosd # operand is a DENORM +_L1_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fcosd_ +_fcosd_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L1_2d + bsr.l scos # operand is a NORM + bra.b _L1_6d +_L1_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L1_3d # no + bsr.l ld_pone # yes + bra.b _L1_6d +_L1_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L1_4d # no + bsr.l t_operr # yes + bra.b _L1_6d +_L1_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L1_5d # no + bsr.l src_qnan # yes + bra.b _L1_6d +_L1_5d: + bsr.l scosd # operand is a DENORM +_L1_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fcosx_ +_fcosx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L1_2x + bsr.l scos # operand is a NORM + bra.b _L1_6x +_L1_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L1_3x # no + bsr.l ld_pone # yes + bra.b _L1_6x +_L1_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L1_4x # no + bsr.l t_operr # yes + bra.b _L1_6x +_L1_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L1_5x # no + bsr.l src_qnan # yes + bra.b _L1_6x +_L1_5x: + bsr.l scosd # operand is a DENORM +_L1_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _fsinhs_ +_fsinhs_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L2_2s + bsr.l ssinh # operand is a NORM + bra.b _L2_6s +_L2_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L2_3s # no + bsr.l src_zero # yes + bra.b _L2_6s +_L2_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L2_4s # no + bsr.l src_inf # yes + bra.b _L2_6s +_L2_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L2_5s # no + bsr.l src_qnan # yes + bra.b _L2_6s +_L2_5s: + bsr.l ssinhd # operand is a DENORM +_L2_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fsinhd_ +_fsinhd_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L2_2d + bsr.l ssinh # operand is a NORM + bra.b _L2_6d +_L2_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L2_3d # no + bsr.l src_zero # yes + bra.b _L2_6d +_L2_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L2_4d # no + bsr.l src_inf # yes + bra.b _L2_6d +_L2_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L2_5d # no + bsr.l src_qnan # yes + bra.b _L2_6d +_L2_5d: + bsr.l ssinhd # operand is a DENORM +_L2_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fsinhx_ +_fsinhx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L2_2x + bsr.l ssinh # operand is a NORM + bra.b _L2_6x +_L2_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L2_3x # no + bsr.l src_zero # yes + bra.b _L2_6x +_L2_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L2_4x # no + bsr.l src_inf # yes + bra.b _L2_6x +_L2_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L2_5x # no + bsr.l src_qnan # yes + bra.b _L2_6x +_L2_5x: + bsr.l ssinhd # operand is a DENORM +_L2_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _flognp1s_ +_flognp1s_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L3_2s + bsr.l slognp1 # operand is a NORM + bra.b _L3_6s +_L3_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L3_3s # no + bsr.l src_zero # yes + bra.b _L3_6s +_L3_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L3_4s # no + bsr.l sopr_inf # yes + bra.b _L3_6s +_L3_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L3_5s # no + bsr.l src_qnan # yes + bra.b _L3_6s +_L3_5s: + bsr.l slognp1d # operand is a DENORM +_L3_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _flognp1d_ +_flognp1d_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L3_2d + bsr.l slognp1 # operand is a NORM + bra.b _L3_6d +_L3_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L3_3d # no + bsr.l src_zero # yes + bra.b _L3_6d +_L3_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L3_4d # no + bsr.l sopr_inf # yes + bra.b _L3_6d +_L3_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L3_5d # no + bsr.l src_qnan # yes + bra.b _L3_6d +_L3_5d: + bsr.l slognp1d # operand is a DENORM +_L3_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _flognp1x_ +_flognp1x_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L3_2x + bsr.l slognp1 # operand is a NORM + bra.b _L3_6x +_L3_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L3_3x # no + bsr.l src_zero # yes + bra.b _L3_6x +_L3_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L3_4x # no + bsr.l sopr_inf # yes + bra.b _L3_6x +_L3_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L3_5x # no + bsr.l src_qnan # yes + bra.b _L3_6x +_L3_5x: + bsr.l slognp1d # operand is a DENORM +_L3_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _fetoxm1s_ +_fetoxm1s_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L4_2s + bsr.l setoxm1 # operand is a NORM + bra.b _L4_6s +_L4_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L4_3s # no + bsr.l src_zero # yes + bra.b _L4_6s +_L4_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L4_4s # no + bsr.l setoxm1i # yes + bra.b _L4_6s +_L4_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L4_5s # no + bsr.l src_qnan # yes + bra.b _L4_6s +_L4_5s: + bsr.l setoxm1d # operand is a DENORM +_L4_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fetoxm1d_ +_fetoxm1d_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L4_2d + bsr.l setoxm1 # operand is a NORM + bra.b _L4_6d +_L4_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L4_3d # no + bsr.l src_zero # yes + bra.b _L4_6d +_L4_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L4_4d # no + bsr.l setoxm1i # yes + bra.b _L4_6d +_L4_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L4_5d # no + bsr.l src_qnan # yes + bra.b _L4_6d +_L4_5d: + bsr.l setoxm1d # operand is a DENORM +_L4_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fetoxm1x_ +_fetoxm1x_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L4_2x + bsr.l setoxm1 # operand is a NORM + bra.b _L4_6x +_L4_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L4_3x # no + bsr.l src_zero # yes + bra.b _L4_6x +_L4_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L4_4x # no + bsr.l setoxm1i # yes + bra.b _L4_6x +_L4_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L4_5x # no + bsr.l src_qnan # yes + bra.b _L4_6x +_L4_5x: + bsr.l setoxm1d # operand is a DENORM +_L4_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _ftanhs_ +_ftanhs_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L5_2s + bsr.l stanh # operand is a NORM + bra.b _L5_6s +_L5_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L5_3s # no + bsr.l src_zero # yes + bra.b _L5_6s +_L5_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L5_4s # no + bsr.l src_one # yes + bra.b _L5_6s +_L5_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L5_5s # no + bsr.l src_qnan # yes + bra.b _L5_6s +_L5_5s: + bsr.l stanhd # operand is a DENORM +_L5_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _ftanhd_ +_ftanhd_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L5_2d + bsr.l stanh # operand is a NORM + bra.b _L5_6d +_L5_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L5_3d # no + bsr.l src_zero # yes + bra.b _L5_6d +_L5_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L5_4d # no + bsr.l src_one # yes + bra.b _L5_6d +_L5_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L5_5d # no + bsr.l src_qnan # yes + bra.b _L5_6d +_L5_5d: + bsr.l stanhd # operand is a DENORM +_L5_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _ftanhx_ +_ftanhx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L5_2x + bsr.l stanh # operand is a NORM + bra.b _L5_6x +_L5_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L5_3x # no + bsr.l src_zero # yes + bra.b _L5_6x +_L5_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L5_4x # no + bsr.l src_one # yes + bra.b _L5_6x +_L5_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L5_5x # no + bsr.l src_qnan # yes + bra.b _L5_6x +_L5_5x: + bsr.l stanhd # operand is a DENORM +_L5_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _fatans_ +_fatans_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L6_2s + bsr.l satan # operand is a NORM + bra.b _L6_6s +_L6_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L6_3s # no + bsr.l src_zero # yes + bra.b _L6_6s +_L6_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L6_4s # no + bsr.l spi_2 # yes + bra.b _L6_6s +_L6_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L6_5s # no + bsr.l src_qnan # yes + bra.b _L6_6s +_L6_5s: + bsr.l satand # operand is a DENORM +_L6_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fatand_ +_fatand_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L6_2d + bsr.l satan # operand is a NORM + bra.b _L6_6d +_L6_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L6_3d # no + bsr.l src_zero # yes + bra.b _L6_6d +_L6_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L6_4d # no + bsr.l spi_2 # yes + bra.b _L6_6d +_L6_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L6_5d # no + bsr.l src_qnan # yes + bra.b _L6_6d +_L6_5d: + bsr.l satand # operand is a DENORM +_L6_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fatanx_ +_fatanx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L6_2x + bsr.l satan # operand is a NORM + bra.b _L6_6x +_L6_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L6_3x # no + bsr.l src_zero # yes + bra.b _L6_6x +_L6_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L6_4x # no + bsr.l spi_2 # yes + bra.b _L6_6x +_L6_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L6_5x # no + bsr.l src_qnan # yes + bra.b _L6_6x +_L6_5x: + bsr.l satand # operand is a DENORM +_L6_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _fasins_ +_fasins_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L7_2s + bsr.l sasin # operand is a NORM + bra.b _L7_6s +_L7_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L7_3s # no + bsr.l src_zero # yes + bra.b _L7_6s +_L7_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L7_4s # no + bsr.l t_operr # yes + bra.b _L7_6s +_L7_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L7_5s # no + bsr.l src_qnan # yes + bra.b _L7_6s +_L7_5s: + bsr.l sasind # operand is a DENORM +_L7_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fasind_ +_fasind_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L7_2d + bsr.l sasin # operand is a NORM + bra.b _L7_6d +_L7_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L7_3d # no + bsr.l src_zero # yes + bra.b _L7_6d +_L7_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L7_4d # no + bsr.l t_operr # yes + bra.b _L7_6d +_L7_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L7_5d # no + bsr.l src_qnan # yes + bra.b _L7_6d +_L7_5d: + bsr.l sasind # operand is a DENORM +_L7_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fasinx_ +_fasinx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L7_2x + bsr.l sasin # operand is a NORM + bra.b _L7_6x +_L7_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L7_3x # no + bsr.l src_zero # yes + bra.b _L7_6x +_L7_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L7_4x # no + bsr.l t_operr # yes + bra.b _L7_6x +_L7_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L7_5x # no + bsr.l src_qnan # yes + bra.b _L7_6x +_L7_5x: + bsr.l sasind # operand is a DENORM +_L7_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _fatanhs_ +_fatanhs_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L8_2s + bsr.l satanh # operand is a NORM + bra.b _L8_6s +_L8_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L8_3s # no + bsr.l src_zero # yes + bra.b _L8_6s +_L8_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L8_4s # no + bsr.l t_operr # yes + bra.b _L8_6s +_L8_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L8_5s # no + bsr.l src_qnan # yes + bra.b _L8_6s +_L8_5s: + bsr.l satanhd # operand is a DENORM +_L8_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fatanhd_ +_fatanhd_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L8_2d + bsr.l satanh # operand is a NORM + bra.b _L8_6d +_L8_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L8_3d # no + bsr.l src_zero # yes + bra.b _L8_6d +_L8_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L8_4d # no + bsr.l t_operr # yes + bra.b _L8_6d +_L8_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L8_5d # no + bsr.l src_qnan # yes + bra.b _L8_6d +_L8_5d: + bsr.l satanhd # operand is a DENORM +_L8_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fatanhx_ +_fatanhx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L8_2x + bsr.l satanh # operand is a NORM + bra.b _L8_6x +_L8_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L8_3x # no + bsr.l src_zero # yes + bra.b _L8_6x +_L8_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L8_4x # no + bsr.l t_operr # yes + bra.b _L8_6x +_L8_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L8_5x # no + bsr.l src_qnan # yes + bra.b _L8_6x +_L8_5x: + bsr.l satanhd # operand is a DENORM +_L8_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _ftans_ +_ftans_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L9_2s + bsr.l stan # operand is a NORM + bra.b _L9_6s +_L9_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L9_3s # no + bsr.l src_zero # yes + bra.b _L9_6s +_L9_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L9_4s # no + bsr.l t_operr # yes + bra.b _L9_6s +_L9_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L9_5s # no + bsr.l src_qnan # yes + bra.b _L9_6s +_L9_5s: + bsr.l stand # operand is a DENORM +_L9_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _ftand_ +_ftand_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L9_2d + bsr.l stan # operand is a NORM + bra.b _L9_6d +_L9_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L9_3d # no + bsr.l src_zero # yes + bra.b _L9_6d +_L9_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L9_4d # no + bsr.l t_operr # yes + bra.b _L9_6d +_L9_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L9_5d # no + bsr.l src_qnan # yes + bra.b _L9_6d +_L9_5d: + bsr.l stand # operand is a DENORM +_L9_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _ftanx_ +_ftanx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L9_2x + bsr.l stan # operand is a NORM + bra.b _L9_6x +_L9_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L9_3x # no + bsr.l src_zero # yes + bra.b _L9_6x +_L9_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L9_4x # no + bsr.l t_operr # yes + bra.b _L9_6x +_L9_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L9_5x # no + bsr.l src_qnan # yes + bra.b _L9_6x +_L9_5x: + bsr.l stand # operand is a DENORM +_L9_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _fetoxs_ +_fetoxs_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L10_2s + bsr.l setox # operand is a NORM + bra.b _L10_6s +_L10_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L10_3s # no + bsr.l ld_pone # yes + bra.b _L10_6s +_L10_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L10_4s # no + bsr.l szr_inf # yes + bra.b _L10_6s +_L10_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L10_5s # no + bsr.l src_qnan # yes + bra.b _L10_6s +_L10_5s: + bsr.l setoxd # operand is a DENORM +_L10_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fetoxd_ +_fetoxd_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L10_2d + bsr.l setox # operand is a NORM + bra.b _L10_6d +_L10_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L10_3d # no + bsr.l ld_pone # yes + bra.b _L10_6d +_L10_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L10_4d # no + bsr.l szr_inf # yes + bra.b _L10_6d +_L10_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L10_5d # no + bsr.l src_qnan # yes + bra.b _L10_6d +_L10_5d: + bsr.l setoxd # operand is a DENORM +_L10_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fetoxx_ +_fetoxx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L10_2x + bsr.l setox # operand is a NORM + bra.b _L10_6x +_L10_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L10_3x # no + bsr.l ld_pone # yes + bra.b _L10_6x +_L10_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L10_4x # no + bsr.l szr_inf # yes + bra.b _L10_6x +_L10_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L10_5x # no + bsr.l src_qnan # yes + bra.b _L10_6x +_L10_5x: + bsr.l setoxd # operand is a DENORM +_L10_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _ftwotoxs_ +_ftwotoxs_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L11_2s + bsr.l stwotox # operand is a NORM + bra.b _L11_6s +_L11_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L11_3s # no + bsr.l ld_pone # yes + bra.b _L11_6s +_L11_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L11_4s # no + bsr.l szr_inf # yes + bra.b _L11_6s +_L11_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L11_5s # no + bsr.l src_qnan # yes + bra.b _L11_6s +_L11_5s: + bsr.l stwotoxd # operand is a DENORM +_L11_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _ftwotoxd_ +_ftwotoxd_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L11_2d + bsr.l stwotox # operand is a NORM + bra.b _L11_6d +_L11_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L11_3d # no + bsr.l ld_pone # yes + bra.b _L11_6d +_L11_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L11_4d # no + bsr.l szr_inf # yes + bra.b _L11_6d +_L11_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L11_5d # no + bsr.l src_qnan # yes + bra.b _L11_6d +_L11_5d: + bsr.l stwotoxd # operand is a DENORM +_L11_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _ftwotoxx_ +_ftwotoxx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L11_2x + bsr.l stwotox # operand is a NORM + bra.b _L11_6x +_L11_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L11_3x # no + bsr.l ld_pone # yes + bra.b _L11_6x +_L11_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L11_4x # no + bsr.l szr_inf # yes + bra.b _L11_6x +_L11_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L11_5x # no + bsr.l src_qnan # yes + bra.b _L11_6x +_L11_5x: + bsr.l stwotoxd # operand is a DENORM +_L11_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _ftentoxs_ +_ftentoxs_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L12_2s + bsr.l stentox # operand is a NORM + bra.b _L12_6s +_L12_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L12_3s # no + bsr.l ld_pone # yes + bra.b _L12_6s +_L12_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L12_4s # no + bsr.l szr_inf # yes + bra.b _L12_6s +_L12_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L12_5s # no + bsr.l src_qnan # yes + bra.b _L12_6s +_L12_5s: + bsr.l stentoxd # operand is a DENORM +_L12_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _ftentoxd_ +_ftentoxd_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L12_2d + bsr.l stentox # operand is a NORM + bra.b _L12_6d +_L12_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L12_3d # no + bsr.l ld_pone # yes + bra.b _L12_6d +_L12_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L12_4d # no + bsr.l szr_inf # yes + bra.b _L12_6d +_L12_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L12_5d # no + bsr.l src_qnan # yes + bra.b _L12_6d +_L12_5d: + bsr.l stentoxd # operand is a DENORM +_L12_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _ftentoxx_ +_ftentoxx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L12_2x + bsr.l stentox # operand is a NORM + bra.b _L12_6x +_L12_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L12_3x # no + bsr.l ld_pone # yes + bra.b _L12_6x +_L12_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L12_4x # no + bsr.l szr_inf # yes + bra.b _L12_6x +_L12_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L12_5x # no + bsr.l src_qnan # yes + bra.b _L12_6x +_L12_5x: + bsr.l stentoxd # operand is a DENORM +_L12_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _flogns_ +_flogns_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L13_2s + bsr.l slogn # operand is a NORM + bra.b _L13_6s +_L13_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L13_3s # no + bsr.l t_dz2 # yes + bra.b _L13_6s +_L13_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L13_4s # no + bsr.l sopr_inf # yes + bra.b _L13_6s +_L13_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L13_5s # no + bsr.l src_qnan # yes + bra.b _L13_6s +_L13_5s: + bsr.l slognd # operand is a DENORM +_L13_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _flognd_ +_flognd_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L13_2d + bsr.l slogn # operand is a NORM + bra.b _L13_6d +_L13_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L13_3d # no + bsr.l t_dz2 # yes + bra.b _L13_6d +_L13_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L13_4d # no + bsr.l sopr_inf # yes + bra.b _L13_6d +_L13_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L13_5d # no + bsr.l src_qnan # yes + bra.b _L13_6d +_L13_5d: + bsr.l slognd # operand is a DENORM +_L13_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _flognx_ +_flognx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L13_2x + bsr.l slogn # operand is a NORM + bra.b _L13_6x +_L13_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L13_3x # no + bsr.l t_dz2 # yes + bra.b _L13_6x +_L13_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L13_4x # no + bsr.l sopr_inf # yes + bra.b _L13_6x +_L13_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L13_5x # no + bsr.l src_qnan # yes + bra.b _L13_6x +_L13_5x: + bsr.l slognd # operand is a DENORM +_L13_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _flog10s_ +_flog10s_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L14_2s + bsr.l slog10 # operand is a NORM + bra.b _L14_6s +_L14_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L14_3s # no + bsr.l t_dz2 # yes + bra.b _L14_6s +_L14_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L14_4s # no + bsr.l sopr_inf # yes + bra.b _L14_6s +_L14_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L14_5s # no + bsr.l src_qnan # yes + bra.b _L14_6s +_L14_5s: + bsr.l slog10d # operand is a DENORM +_L14_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _flog10d_ +_flog10d_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L14_2d + bsr.l slog10 # operand is a NORM + bra.b _L14_6d +_L14_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L14_3d # no + bsr.l t_dz2 # yes + bra.b _L14_6d +_L14_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L14_4d # no + bsr.l sopr_inf # yes + bra.b _L14_6d +_L14_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L14_5d # no + bsr.l src_qnan # yes + bra.b _L14_6d +_L14_5d: + bsr.l slog10d # operand is a DENORM +_L14_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _flog10x_ +_flog10x_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L14_2x + bsr.l slog10 # operand is a NORM + bra.b _L14_6x +_L14_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L14_3x # no + bsr.l t_dz2 # yes + bra.b _L14_6x +_L14_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L14_4x # no + bsr.l sopr_inf # yes + bra.b _L14_6x +_L14_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L14_5x # no + bsr.l src_qnan # yes + bra.b _L14_6x +_L14_5x: + bsr.l slog10d # operand is a DENORM +_L14_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _flog2s_ +_flog2s_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L15_2s + bsr.l slog2 # operand is a NORM + bra.b _L15_6s +_L15_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L15_3s # no + bsr.l t_dz2 # yes + bra.b _L15_6s +_L15_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L15_4s # no + bsr.l sopr_inf # yes + bra.b _L15_6s +_L15_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L15_5s # no + bsr.l src_qnan # yes + bra.b _L15_6s +_L15_5s: + bsr.l slog2d # operand is a DENORM +_L15_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _flog2d_ +_flog2d_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L15_2d + bsr.l slog2 # operand is a NORM + bra.b _L15_6d +_L15_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L15_3d # no + bsr.l t_dz2 # yes + bra.b _L15_6d +_L15_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L15_4d # no + bsr.l sopr_inf # yes + bra.b _L15_6d +_L15_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L15_5d # no + bsr.l src_qnan # yes + bra.b _L15_6d +_L15_5d: + bsr.l slog2d # operand is a DENORM +_L15_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _flog2x_ +_flog2x_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L15_2x + bsr.l slog2 # operand is a NORM + bra.b _L15_6x +_L15_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L15_3x # no + bsr.l t_dz2 # yes + bra.b _L15_6x +_L15_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L15_4x # no + bsr.l sopr_inf # yes + bra.b _L15_6x +_L15_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L15_5x # no + bsr.l src_qnan # yes + bra.b _L15_6x +_L15_5x: + bsr.l slog2d # operand is a DENORM +_L15_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _fcoshs_ +_fcoshs_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L16_2s + bsr.l scosh # operand is a NORM + bra.b _L16_6s +_L16_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L16_3s # no + bsr.l ld_pone # yes + bra.b _L16_6s +_L16_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L16_4s # no + bsr.l ld_pinf # yes + bra.b _L16_6s +_L16_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L16_5s # no + bsr.l src_qnan # yes + bra.b _L16_6s +_L16_5s: + bsr.l scoshd # operand is a DENORM +_L16_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fcoshd_ +_fcoshd_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L16_2d + bsr.l scosh # operand is a NORM + bra.b _L16_6d +_L16_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L16_3d # no + bsr.l ld_pone # yes + bra.b _L16_6d +_L16_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L16_4d # no + bsr.l ld_pinf # yes + bra.b _L16_6d +_L16_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L16_5d # no + bsr.l src_qnan # yes + bra.b _L16_6d +_L16_5d: + bsr.l scoshd # operand is a DENORM +_L16_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fcoshx_ +_fcoshx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L16_2x + bsr.l scosh # operand is a NORM + bra.b _L16_6x +_L16_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L16_3x # no + bsr.l ld_pone # yes + bra.b _L16_6x +_L16_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L16_4x # no + bsr.l ld_pinf # yes + bra.b _L16_6x +_L16_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L16_5x # no + bsr.l src_qnan # yes + bra.b _L16_6x +_L16_5x: + bsr.l scoshd # operand is a DENORM +_L16_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _facoss_ +_facoss_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L17_2s + bsr.l sacos # operand is a NORM + bra.b _L17_6s +_L17_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L17_3s # no + bsr.l ld_ppi2 # yes + bra.b _L17_6s +_L17_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L17_4s # no + bsr.l t_operr # yes + bra.b _L17_6s +_L17_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L17_5s # no + bsr.l src_qnan # yes + bra.b _L17_6s +_L17_5s: + bsr.l sacosd # operand is a DENORM +_L17_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _facosd_ +_facosd_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L17_2d + bsr.l sacos # operand is a NORM + bra.b _L17_6d +_L17_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L17_3d # no + bsr.l ld_ppi2 # yes + bra.b _L17_6d +_L17_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L17_4d # no + bsr.l t_operr # yes + bra.b _L17_6d +_L17_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L17_5d # no + bsr.l src_qnan # yes + bra.b _L17_6d +_L17_5d: + bsr.l sacosd # operand is a DENORM +_L17_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _facosx_ +_facosx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L17_2x + bsr.l sacos # operand is a NORM + bra.b _L17_6x +_L17_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L17_3x # no + bsr.l ld_ppi2 # yes + bra.b _L17_6x +_L17_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L17_4x # no + bsr.l t_operr # yes + bra.b _L17_6x +_L17_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L17_5x # no + bsr.l src_qnan # yes + bra.b _L17_6x +_L17_5x: + bsr.l sacosd # operand is a DENORM +_L17_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _fgetexps_ +_fgetexps_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L18_2s + bsr.l sgetexp # operand is a NORM + bra.b _L18_6s +_L18_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L18_3s # no + bsr.l src_zero # yes + bra.b _L18_6s +_L18_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L18_4s # no + bsr.l t_operr # yes + bra.b _L18_6s +_L18_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L18_5s # no + bsr.l src_qnan # yes + bra.b _L18_6s +_L18_5s: + bsr.l sgetexpd # operand is a DENORM +_L18_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fgetexpd_ +_fgetexpd_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L18_2d + bsr.l sgetexp # operand is a NORM + bra.b _L18_6d +_L18_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L18_3d # no + bsr.l src_zero # yes + bra.b _L18_6d +_L18_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L18_4d # no + bsr.l t_operr # yes + bra.b _L18_6d +_L18_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L18_5d # no + bsr.l src_qnan # yes + bra.b _L18_6d +_L18_5d: + bsr.l sgetexpd # operand is a DENORM +_L18_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fgetexpx_ +_fgetexpx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L18_2x + bsr.l sgetexp # operand is a NORM + bra.b _L18_6x +_L18_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L18_3x # no + bsr.l src_zero # yes + bra.b _L18_6x +_L18_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L18_4x # no + bsr.l t_operr # yes + bra.b _L18_6x +_L18_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L18_5x # no + bsr.l src_qnan # yes + bra.b _L18_6x +_L18_5x: + bsr.l sgetexpd # operand is a DENORM +_L18_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _fgetmans_ +_fgetmans_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L19_2s + bsr.l sgetman # operand is a NORM + bra.b _L19_6s +_L19_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L19_3s # no + bsr.l src_zero # yes + bra.b _L19_6s +_L19_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L19_4s # no + bsr.l t_operr # yes + bra.b _L19_6s +_L19_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L19_5s # no + bsr.l src_qnan # yes + bra.b _L19_6s +_L19_5s: + bsr.l sgetmand # operand is a DENORM +_L19_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fgetmand_ +_fgetmand_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L19_2d + bsr.l sgetman # operand is a NORM + bra.b _L19_6d +_L19_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L19_3d # no + bsr.l src_zero # yes + bra.b _L19_6d +_L19_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L19_4d # no + bsr.l t_operr # yes + bra.b _L19_6d +_L19_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L19_5d # no + bsr.l src_qnan # yes + bra.b _L19_6d +_L19_5d: + bsr.l sgetmand # operand is a DENORM +_L19_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fgetmanx_ +_fgetmanx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L19_2x + bsr.l sgetman # operand is a NORM + bra.b _L19_6x +_L19_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L19_3x # no + bsr.l src_zero # yes + bra.b _L19_6x +_L19_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L19_4x # no + bsr.l t_operr # yes + bra.b _L19_6x +_L19_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L19_5x # no + bsr.l src_qnan # yes + bra.b _L19_6x +_L19_5x: + bsr.l sgetmand # operand is a DENORM +_L19_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _fsincoss_ +_fsincoss_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L20_2s + bsr.l ssincos # operand is a NORM + bra.b _L20_6s +_L20_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L20_3s # no + bsr.l ssincosz # yes + bra.b _L20_6s +_L20_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L20_4s # no + bsr.l ssincosi # yes + bra.b _L20_6s +_L20_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L20_5s # no + bsr.l ssincosqnan # yes + bra.b _L20_6s +_L20_5s: + bsr.l ssincosd # operand is a DENORM +_L20_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x &0x03,-(%sp) # store off fp0/fp1 + fmovm.x (%sp)+,&0x40 # fp0 now in fp1 + fmovm.x (%sp)+,&0x80 # fp1 now in fp0 + unlk %a6 + rts + + global _fsincosd_ +_fsincosd_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L20_2d + bsr.l ssincos # operand is a NORM + bra.b _L20_6d +_L20_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L20_3d # no + bsr.l ssincosz # yes + bra.b _L20_6d +_L20_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L20_4d # no + bsr.l ssincosi # yes + bra.b _L20_6d +_L20_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L20_5d # no + bsr.l ssincosqnan # yes + bra.b _L20_6d +_L20_5d: + bsr.l ssincosd # operand is a DENORM +_L20_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x &0x03,-(%sp) # store off fp0/fp1 + fmovm.x (%sp)+,&0x40 # fp0 now in fp1 + fmovm.x (%sp)+,&0x80 # fp1 now in fp0 + unlk %a6 + rts + + global _fsincosx_ +_fsincosx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L20_2x + bsr.l ssincos # operand is a NORM + bra.b _L20_6x +_L20_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L20_3x # no + bsr.l ssincosz # yes + bra.b _L20_6x +_L20_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L20_4x # no + bsr.l ssincosi # yes + bra.b _L20_6x +_L20_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L20_5x # no + bsr.l ssincosqnan # yes + bra.b _L20_6x +_L20_5x: + bsr.l ssincosd # operand is a DENORM +_L20_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x &0x03,-(%sp) # store off fp0/fp1 + fmovm.x (%sp)+,&0x40 # fp0 now in fp1 + fmovm.x (%sp)+,&0x80 # fp1 now in fp0 + unlk %a6 + rts + + +######################################################################### +# DYADIC TEMPLATE # +######################################################################### + global _frems_ +_frems_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl dst + fmov.x %fp0,FP_DST(%a6) + lea FP_DST(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,DTAG(%a6) + + fmov.s 0xc(%a6),%fp0 # load sgl src + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.l %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + lea FP_SRC(%a6),%a0 # pass ptr to src + lea FP_DST(%a6),%a1 # pass ptr to dst + + tst.b %d1 + bne.b _L21_2s + bsr.l srem_snorm # operand is a NORM + bra.b _L21_6s +_L21_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L21_3s # no + bsr.l srem_szero # yes + bra.b _L21_6s +_L21_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L21_4s # no + bsr.l srem_sinf # yes + bra.b _L21_6s +_L21_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L21_5s # no + bsr.l sop_sqnan # yes + bra.b _L21_6s +_L21_5s: + bsr.l srem_sdnrm # operand is a DENORM +_L21_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fremd_ +_fremd_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl dst + fmov.x %fp0,FP_DST(%a6) + lea FP_DST(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,DTAG(%a6) + + fmov.d 0x10(%a6),%fp0 # load dbl src + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.l %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + lea FP_SRC(%a6),%a0 # pass ptr to src + lea FP_DST(%a6),%a1 # pass ptr to dst + + tst.b %d1 + bne.b _L21_2d + bsr.l srem_snorm # operand is a NORM + bra.b _L21_6d +_L21_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L21_3d # no + bsr.l srem_szero # yes + bra.b _L21_6d +_L21_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L21_4d # no + bsr.l srem_sinf # yes + bra.b _L21_6d +_L21_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L21_5d # no + bsr.l sop_sqnan # yes + bra.b _L21_6d +_L21_5d: + bsr.l srem_sdnrm # operand is a DENORM +_L21_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fremx_ +_fremx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_DST(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext dst + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,DTAG(%a6) + + lea FP_SRC(%a6),%a0 + mov.l 0x14+0x0(%a6),0x0(%a0) # load ext src + mov.l 0x14+0x4(%a6),0x4(%a0) + mov.l 0x14+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.l %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + lea FP_SRC(%a6),%a0 # pass ptr to src + lea FP_DST(%a6),%a1 # pass ptr to dst + + tst.b %d1 + bne.b _L21_2x + bsr.l srem_snorm # operand is a NORM + bra.b _L21_6x +_L21_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L21_3x # no + bsr.l srem_szero # yes + bra.b _L21_6x +_L21_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L21_4x # no + bsr.l srem_sinf # yes + bra.b _L21_6x +_L21_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L21_5x # no + bsr.l sop_sqnan # yes + bra.b _L21_6x +_L21_5x: + bsr.l srem_sdnrm # operand is a DENORM +_L21_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# DYADIC TEMPLATE # +######################################################################### + global _fmods_ +_fmods_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl dst + fmov.x %fp0,FP_DST(%a6) + lea FP_DST(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,DTAG(%a6) + + fmov.s 0xc(%a6),%fp0 # load sgl src + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.l %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + lea FP_SRC(%a6),%a0 # pass ptr to src + lea FP_DST(%a6),%a1 # pass ptr to dst + + tst.b %d1 + bne.b _L22_2s + bsr.l smod_snorm # operand is a NORM + bra.b _L22_6s +_L22_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L22_3s # no + bsr.l smod_szero # yes + bra.b _L22_6s +_L22_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L22_4s # no + bsr.l smod_sinf # yes + bra.b _L22_6s +_L22_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L22_5s # no + bsr.l sop_sqnan # yes + bra.b _L22_6s +_L22_5s: + bsr.l smod_sdnrm # operand is a DENORM +_L22_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fmodd_ +_fmodd_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl dst + fmov.x %fp0,FP_DST(%a6) + lea FP_DST(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,DTAG(%a6) + + fmov.d 0x10(%a6),%fp0 # load dbl src + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.l %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + lea FP_SRC(%a6),%a0 # pass ptr to src + lea FP_DST(%a6),%a1 # pass ptr to dst + + tst.b %d1 + bne.b _L22_2d + bsr.l smod_snorm # operand is a NORM + bra.b _L22_6d +_L22_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L22_3d # no + bsr.l smod_szero # yes + bra.b _L22_6d +_L22_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L22_4d # no + bsr.l smod_sinf # yes + bra.b _L22_6d +_L22_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L22_5d # no + bsr.l sop_sqnan # yes + bra.b _L22_6d +_L22_5d: + bsr.l smod_sdnrm # operand is a DENORM +_L22_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fmodx_ +_fmodx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_DST(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext dst + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,DTAG(%a6) + + lea FP_SRC(%a6),%a0 + mov.l 0x14+0x0(%a6),0x0(%a0) # load ext src + mov.l 0x14+0x4(%a6),0x4(%a0) + mov.l 0x14+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.l %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + lea FP_SRC(%a6),%a0 # pass ptr to src + lea FP_DST(%a6),%a1 # pass ptr to dst + + tst.b %d1 + bne.b _L22_2x + bsr.l smod_snorm # operand is a NORM + bra.b _L22_6x +_L22_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L22_3x # no + bsr.l smod_szero # yes + bra.b _L22_6x +_L22_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L22_4x # no + bsr.l smod_sinf # yes + bra.b _L22_6x +_L22_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L22_5x # no + bsr.l sop_sqnan # yes + bra.b _L22_6x +_L22_5x: + bsr.l smod_sdnrm # operand is a DENORM +_L22_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# DYADIC TEMPLATE # +######################################################################### + global _fscales_ +_fscales_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl dst + fmov.x %fp0,FP_DST(%a6) + lea FP_DST(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,DTAG(%a6) + + fmov.s 0xc(%a6),%fp0 # load sgl src + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.l %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + lea FP_SRC(%a6),%a0 # pass ptr to src + lea FP_DST(%a6),%a1 # pass ptr to dst + + tst.b %d1 + bne.b _L23_2s + bsr.l sscale_snorm # operand is a NORM + bra.b _L23_6s +_L23_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L23_3s # no + bsr.l sscale_szero # yes + bra.b _L23_6s +_L23_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L23_4s # no + bsr.l sscale_sinf # yes + bra.b _L23_6s +_L23_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L23_5s # no + bsr.l sop_sqnan # yes + bra.b _L23_6s +_L23_5s: + bsr.l sscale_sdnrm # operand is a DENORM +_L23_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fscaled_ +_fscaled_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl dst + fmov.x %fp0,FP_DST(%a6) + lea FP_DST(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,DTAG(%a6) + + fmov.d 0x10(%a6),%fp0 # load dbl src + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.l %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + lea FP_SRC(%a6),%a0 # pass ptr to src + lea FP_DST(%a6),%a1 # pass ptr to dst + + tst.b %d1 + bne.b _L23_2d + bsr.l sscale_snorm # operand is a NORM + bra.b _L23_6d +_L23_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L23_3d # no + bsr.l sscale_szero # yes + bra.b _L23_6d +_L23_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L23_4d # no + bsr.l sscale_sinf # yes + bra.b _L23_6d +_L23_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L23_5d # no + bsr.l sop_sqnan # yes + bra.b _L23_6d +_L23_5d: + bsr.l sscale_sdnrm # operand is a DENORM +_L23_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fscalex_ +_fscalex_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_DST(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext dst + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,DTAG(%a6) + + lea FP_SRC(%a6),%a0 + mov.l 0x14+0x0(%a6),0x0(%a0) # load ext src + mov.l 0x14+0x4(%a6),0x4(%a0) + mov.l 0x14+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.l %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + lea FP_SRC(%a6),%a0 # pass ptr to src + lea FP_DST(%a6),%a1 # pass ptr to dst + + tst.b %d1 + bne.b _L23_2x + bsr.l sscale_snorm # operand is a NORM + bra.b _L23_6x +_L23_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L23_3x # no + bsr.l sscale_szero # yes + bra.b _L23_6x +_L23_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L23_4x # no + bsr.l sscale_sinf # yes + bra.b _L23_6x +_L23_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L23_5x # no + bsr.l sop_sqnan # yes + bra.b _L23_6x +_L23_5x: + bsr.l sscale_sdnrm # operand is a DENORM +_L23_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# ssin(): computes the sine of a normalized input # +# ssind(): computes the sine of a denormalized input # +# scos(): computes the cosine of a normalized input # +# scosd(): computes the cosine of a denormalized input # +# ssincos(): computes the sine and cosine of a normalized input # +# ssincosd(): computes the sine and cosine of a denormalized input # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input # +# d0 = round precision,mode # +# # +# OUTPUT ************************************************************** # +# fp0 = sin(X) or cos(X) # +# # +# For ssincos(X): # +# fp0 = sin(X) # +# fp1 = cos(X) # +# # +# ACCURACY and MONOTONICITY ******************************************* # +# The returned result is within 1 ulp in 64 significant bit, i.e. # +# within 0.5001 ulp to 53 bits if the result is subsequently # +# rounded to double precision. The result is provably monotonic # +# in double precision. # +# # +# ALGORITHM *********************************************************** # +# # +# SIN and COS: # +# 1. If SIN is invoked, set AdjN := 0; otherwise, set AdjN := 1. # +# # +# 2. If |X| >= 15Pi or |X| < 2**(-40), go to 7. # +# # +# 3. Decompose X as X = N(Pi/2) + r where |r| <= Pi/4. Let # +# k = N mod 4, so in particular, k = 0,1,2,or 3. # +# Overwrite k by k := k + AdjN. # +# # +# 4. If k is even, go to 6. # +# # +# 5. (k is odd) Set j := (k-1)/2, sgn := (-1)**j. # +# Return sgn*cos(r) where cos(r) is approximated by an # +# even polynomial in r, 1 + r*r*(B1+s*(B2+ ... + s*B8)), # +# s = r*r. # +# Exit. # +# # +# 6. (k is even) Set j := k/2, sgn := (-1)**j. Return sgn*sin(r) # +# where sin(r) is approximated by an odd polynomial in r # +# r + r*s*(A1+s*(A2+ ... + s*A7)), s = r*r. # +# Exit. # +# # +# 7. If |X| > 1, go to 9. # +# # +# 8. (|X|<2**(-40)) If SIN is invoked, return X; # +# otherwise return 1. # +# # +# 9. Overwrite X by X := X rem 2Pi. Now that |X| <= Pi, # +# go back to 3. # +# # +# SINCOS: # +# 1. If |X| >= 15Pi or |X| < 2**(-40), go to 6. # +# # +# 2. Decompose X as X = N(Pi/2) + r where |r| <= Pi/4. Let # +# k = N mod 4, so in particular, k = 0,1,2,or 3. # +# # +# 3. If k is even, go to 5. # +# # +# 4. (k is odd) Set j1 := (k-1)/2, j2 := j1 (EOR) (k mod 2), ie. # +# j1 exclusive or with the l.s.b. of k. # +# sgn1 := (-1)**j1, sgn2 := (-1)**j2. # +# SIN(X) = sgn1 * cos(r) and COS(X) = sgn2*sin(r) where # +# sin(r) and cos(r) are computed as odd and even # +# polynomials in r, respectively. Exit # +# # +# 5. (k is even) Set j1 := k/2, sgn1 := (-1)**j1. # +# SIN(X) = sgn1 * sin(r) and COS(X) = sgn1*cos(r) where # +# sin(r) and cos(r) are computed as odd and even # +# polynomials in r, respectively. Exit # +# # +# 6. If |X| > 1, go to 8. # +# # +# 7. (|X|<2**(-40)) SIN(X) = X and COS(X) = 1. Exit. # +# # +# 8. Overwrite X by X := X rem 2Pi. Now that |X| <= Pi, # +# go back to 2. # +# # +######################################################################### + +SINA7: long 0xBD6AAA77,0xCCC994F5 +SINA6: long 0x3DE61209,0x7AAE8DA1 +SINA5: long 0xBE5AE645,0x2A118AE4 +SINA4: long 0x3EC71DE3,0xA5341531 +SINA3: long 0xBF2A01A0,0x1A018B59,0x00000000,0x00000000 +SINA2: long 0x3FF80000,0x88888888,0x888859AF,0x00000000 +SINA1: long 0xBFFC0000,0xAAAAAAAA,0xAAAAAA99,0x00000000 + +COSB8: long 0x3D2AC4D0,0xD6011EE3 +COSB7: long 0xBDA9396F,0x9F45AC19 +COSB6: long 0x3E21EED9,0x0612C972 +COSB5: long 0xBE927E4F,0xB79D9FCF +COSB4: long 0x3EFA01A0,0x1A01D423,0x00000000,0x00000000 +COSB3: long 0xBFF50000,0xB60B60B6,0x0B61D438,0x00000000 +COSB2: long 0x3FFA0000,0xAAAAAAAA,0xAAAAAB5E +COSB1: long 0xBF000000 + + set INARG,FP_SCR0 + + set X,FP_SCR0 +# set XDCARE,X+2 + set XFRAC,X+4 + + set RPRIME,FP_SCR0 + set SPRIME,FP_SCR1 + + set POSNEG1,L_SCR1 + set TWOTO63,L_SCR1 + + set ENDFLAG,L_SCR2 + set INT,L_SCR2 + + set ADJN,L_SCR3 + +############################################ + global ssin +ssin: + mov.l &0,ADJN(%a6) # yes; SET ADJN TO 0 + bra.b SINBGN + +############################################ + global scos +scos: + mov.l &1,ADJN(%a6) # yes; SET ADJN TO 1 + +############################################ +SINBGN: +#--SAVE FPCR, FP1. CHECK IF |X| IS TOO SMALL OR LARGE + + fmov.x (%a0),%fp0 # LOAD INPUT + fmov.x %fp0,X(%a6) # save input at X + +# "COMPACTIFY" X + mov.l (%a0),%d1 # put exp in hi word + mov.w 4(%a0),%d1 # fetch hi(man) + and.l &0x7FFFFFFF,%d1 # strip sign + + cmpi.l %d1,&0x3FD78000 # is |X| >= 2**(-40)? + bge.b SOK1 # no + bra.w SINSM # yes; input is very small + +SOK1: + cmp.l %d1,&0x4004BC7E # is |X| < 15 PI? + blt.b SINMAIN # no + bra.w SREDUCEX # yes; input is very large + +#--THIS IS THE USUAL CASE, |X| <= 15 PI. +#--THE ARGUMENT REDUCTION IS DONE BY TABLE LOOK UP. +SINMAIN: + fmov.x %fp0,%fp1 + fmul.d TWOBYPI(%pc),%fp1 # X*2/PI + + lea PITBL+0x200(%pc),%a1 # TABLE OF N*PI/2, N = -32,...,32 + + fmov.l %fp1,INT(%a6) # CONVERT TO INTEGER + + mov.l INT(%a6),%d1 # make a copy of N + asl.l &4,%d1 # N *= 16 + add.l %d1,%a1 # tbl_addr = a1 + (N*16) + +# A1 IS THE ADDRESS OF N*PIBY2 +# ...WHICH IS IN TWO PIECES Y1 & Y2 + fsub.x (%a1)+,%fp0 # X-Y1 + fsub.s (%a1),%fp0 # fp0 = R = (X-Y1)-Y2 + +SINCONT: +#--continuation from REDUCEX + +#--GET N+ADJN AND SEE IF SIN(R) OR COS(R) IS NEEDED + mov.l INT(%a6),%d1 + add.l ADJN(%a6),%d1 # SEE IF D0 IS ODD OR EVEN + ror.l &1,%d1 # D0 WAS ODD IFF D0 IS NEGATIVE + cmp.l %d1,&0 + blt.w COSPOLY + +#--LET J BE THE LEAST SIG. BIT OF D0, LET SGN := (-1)**J. +#--THEN WE RETURN SGN*SIN(R). SGN*SIN(R) IS COMPUTED BY +#--R' + R'*S*(A1 + S(A2 + S(A3 + S(A4 + ... + SA7)))), WHERE +#--R' = SGN*R, S=R*R. THIS CAN BE REWRITTEN AS +#--R' + R'*S*( [A1+T(A3+T(A5+TA7))] + [S(A2+T(A4+TA6))]) +#--WHERE T=S*S. +#--NOTE THAT A3 THROUGH A7 ARE STORED IN DOUBLE PRECISION +#--WHILE A1 AND A2 ARE IN DOUBLE-EXTENDED FORMAT. +SINPOLY: + fmovm.x &0x0c,-(%sp) # save fp2/fp3 + + fmov.x %fp0,X(%a6) # X IS R + fmul.x %fp0,%fp0 # FP0 IS S + + fmov.d SINA7(%pc),%fp3 + fmov.d SINA6(%pc),%fp2 + + fmov.x %fp0,%fp1 + fmul.x %fp1,%fp1 # FP1 IS T + + ror.l &1,%d1 + and.l &0x80000000,%d1 +# ...LEAST SIG. BIT OF D0 IN SIGN POSITION + eor.l %d1,X(%a6) # X IS NOW R'= SGN*R + + fmul.x %fp1,%fp3 # TA7 + fmul.x %fp1,%fp2 # TA6 + + fadd.d SINA5(%pc),%fp3 # A5+TA7 + fadd.d SINA4(%pc),%fp2 # A4+TA6 + + fmul.x %fp1,%fp3 # T(A5+TA7) + fmul.x %fp1,%fp2 # T(A4+TA6) + + fadd.d SINA3(%pc),%fp3 # A3+T(A5+TA7) + fadd.x SINA2(%pc),%fp2 # A2+T(A4+TA6) + + fmul.x %fp3,%fp1 # T(A3+T(A5+TA7)) + + fmul.x %fp0,%fp2 # S(A2+T(A4+TA6)) + fadd.x SINA1(%pc),%fp1 # A1+T(A3+T(A5+TA7)) + fmul.x X(%a6),%fp0 # R'*S + + fadd.x %fp2,%fp1 # [A1+T(A3+T(A5+TA7))]+[S(A2+T(A4+TA6))] + + fmul.x %fp1,%fp0 # SIN(R')-R' + + fmovm.x (%sp)+,&0x30 # restore fp2/fp3 + + fmov.l %d0,%fpcr # restore users round mode,prec + fadd.x X(%a6),%fp0 # last inst - possible exception set + bra t_inx2 + +#--LET J BE THE LEAST SIG. BIT OF D0, LET SGN := (-1)**J. +#--THEN WE RETURN SGN*COS(R). SGN*COS(R) IS COMPUTED BY +#--SGN + S'*(B1 + S(B2 + S(B3 + S(B4 + ... + SB8)))), WHERE +#--S=R*R AND S'=SGN*S. THIS CAN BE REWRITTEN AS +#--SGN + S'*([B1+T(B3+T(B5+TB7))] + [S(B2+T(B4+T(B6+TB8)))]) +#--WHERE T=S*S. +#--NOTE THAT B4 THROUGH B8 ARE STORED IN DOUBLE PRECISION +#--WHILE B2 AND B3 ARE IN DOUBLE-EXTENDED FORMAT, B1 IS -1/2 +#--AND IS THEREFORE STORED AS SINGLE PRECISION. +COSPOLY: + fmovm.x &0x0c,-(%sp) # save fp2/fp3 + + fmul.x %fp0,%fp0 # FP0 IS S + + fmov.d COSB8(%pc),%fp2 + fmov.d COSB7(%pc),%fp3 + + fmov.x %fp0,%fp1 + fmul.x %fp1,%fp1 # FP1 IS T + + fmov.x %fp0,X(%a6) # X IS S + ror.l &1,%d1 + and.l &0x80000000,%d1 +# ...LEAST SIG. BIT OF D0 IN SIGN POSITION + + fmul.x %fp1,%fp2 # TB8 + + eor.l %d1,X(%a6) # X IS NOW S'= SGN*S + and.l &0x80000000,%d1 + + fmul.x %fp1,%fp3 # TB7 + + or.l &0x3F800000,%d1 # D0 IS SGN IN SINGLE + mov.l %d1,POSNEG1(%a6) + + fadd.d COSB6(%pc),%fp2 # B6+TB8 + fadd.d COSB5(%pc),%fp3 # B5+TB7 + + fmul.x %fp1,%fp2 # T(B6+TB8) + fmul.x %fp1,%fp3 # T(B5+TB7) + + fadd.d COSB4(%pc),%fp2 # B4+T(B6+TB8) + fadd.x COSB3(%pc),%fp3 # B3+T(B5+TB7) + + fmul.x %fp1,%fp2 # T(B4+T(B6+TB8)) + fmul.x %fp3,%fp1 # T(B3+T(B5+TB7)) + + fadd.x COSB2(%pc),%fp2 # B2+T(B4+T(B6+TB8)) + fadd.s COSB1(%pc),%fp1 # B1+T(B3+T(B5+TB7)) + + fmul.x %fp2,%fp0 # S(B2+T(B4+T(B6+TB8))) + + fadd.x %fp1,%fp0 + + fmul.x X(%a6),%fp0 + + fmovm.x (%sp)+,&0x30 # restore fp2/fp3 + + fmov.l %d0,%fpcr # restore users round mode,prec + fadd.s POSNEG1(%a6),%fp0 # last inst - possible exception set + bra t_inx2 + +############################################## + +# SINe: Big OR Small? +#--IF |X| > 15PI, WE USE THE GENERAL ARGUMENT REDUCTION. +#--IF |X| < 2**(-40), RETURN X OR 1. +SINBORS: + cmp.l %d1,&0x3FFF8000 + bgt.l SREDUCEX + +SINSM: + mov.l ADJN(%a6),%d1 + cmp.l %d1,&0 + bgt.b COSTINY + +# here, the operation may underflow iff the precision is sgl or dbl. +# extended denorms are handled through another entry point. +SINTINY: +# mov.w &0x0000,XDCARE(%a6) # JUST IN CASE + + fmov.l %d0,%fpcr # restore users round mode,prec + mov.b &FMOV_OP,%d1 # last inst is MOVE + fmov.x X(%a6),%fp0 # last inst - possible exception set + bra t_catch + +COSTINY: + fmov.s &0x3F800000,%fp0 # fp0 = 1.0 + fmov.l %d0,%fpcr # restore users round mode,prec + fadd.s &0x80800000,%fp0 # last inst - possible exception set + bra t_pinx2 + +################################################ + global ssind +#--SIN(X) = X FOR DENORMALIZED X +ssind: + bra t_extdnrm + +############################################ + global scosd +#--COS(X) = 1 FOR DENORMALIZED X +scosd: + fmov.s &0x3F800000,%fp0 # fp0 = 1.0 + bra t_pinx2 + +################################################## + + global ssincos +ssincos: +#--SET ADJN TO 4 + mov.l &4,ADJN(%a6) + + fmov.x (%a0),%fp0 # LOAD INPUT + fmov.x %fp0,X(%a6) + + mov.l (%a0),%d1 + mov.w 4(%a0),%d1 + and.l &0x7FFFFFFF,%d1 # COMPACTIFY X + + cmp.l %d1,&0x3FD78000 # |X| >= 2**(-40)? + bge.b SCOK1 + bra.w SCSM + +SCOK1: + cmp.l %d1,&0x4004BC7E # |X| < 15 PI? + blt.b SCMAIN + bra.w SREDUCEX + + +#--THIS IS THE USUAL CASE, |X| <= 15 PI. +#--THE ARGUMENT REDUCTION IS DONE BY TABLE LOOK UP. +SCMAIN: + fmov.x %fp0,%fp1 + + fmul.d TWOBYPI(%pc),%fp1 # X*2/PI + + lea PITBL+0x200(%pc),%a1 # TABLE OF N*PI/2, N = -32,...,32 + + fmov.l %fp1,INT(%a6) # CONVERT TO INTEGER + + mov.l INT(%a6),%d1 + asl.l &4,%d1 + add.l %d1,%a1 # ADDRESS OF N*PIBY2, IN Y1, Y2 + + fsub.x (%a1)+,%fp0 # X-Y1 + fsub.s (%a1),%fp0 # FP0 IS R = (X-Y1)-Y2 + +SCCONT: +#--continuation point from REDUCEX + + mov.l INT(%a6),%d1 + ror.l &1,%d1 + cmp.l %d1,&0 # D0 < 0 IFF N IS ODD + bge.w NEVEN + +SNODD: +#--REGISTERS SAVED SO FAR: D0, A0, FP2. + fmovm.x &0x04,-(%sp) # save fp2 + + fmov.x %fp0,RPRIME(%a6) + fmul.x %fp0,%fp0 # FP0 IS S = R*R + fmov.d SINA7(%pc),%fp1 # A7 + fmov.d COSB8(%pc),%fp2 # B8 + fmul.x %fp0,%fp1 # SA7 + fmul.x %fp0,%fp2 # SB8 + + mov.l %d2,-(%sp) + mov.l %d1,%d2 + ror.l &1,%d2 + and.l &0x80000000,%d2 + eor.l %d1,%d2 + and.l &0x80000000,%d2 + + fadd.d SINA6(%pc),%fp1 # A6+SA7 + fadd.d COSB7(%pc),%fp2 # B7+SB8 + + fmul.x %fp0,%fp1 # S(A6+SA7) + eor.l %d2,RPRIME(%a6) + mov.l (%sp)+,%d2 + fmul.x %fp0,%fp2 # S(B7+SB8) + ror.l &1,%d1 + and.l &0x80000000,%d1 + mov.l &0x3F800000,POSNEG1(%a6) + eor.l %d1,POSNEG1(%a6) + + fadd.d SINA5(%pc),%fp1 # A5+S(A6+SA7) + fadd.d COSB6(%pc),%fp2 # B6+S(B7+SB8) + + fmul.x %fp0,%fp1 # S(A5+S(A6+SA7)) + fmul.x %fp0,%fp2 # S(B6+S(B7+SB8)) + fmov.x %fp0,SPRIME(%a6) + + fadd.d SINA4(%pc),%fp1 # A4+S(A5+S(A6+SA7)) + eor.l %d1,SPRIME(%a6) + fadd.d COSB5(%pc),%fp2 # B5+S(B6+S(B7+SB8)) + + fmul.x %fp0,%fp1 # S(A4+...) + fmul.x %fp0,%fp2 # S(B5+...) + + fadd.d SINA3(%pc),%fp1 # A3+S(A4+...) + fadd.d COSB4(%pc),%fp2 # B4+S(B5+...) + + fmul.x %fp0,%fp1 # S(A3+...) + fmul.x %fp0,%fp2 # S(B4+...) + + fadd.x SINA2(%pc),%fp1 # A2+S(A3+...) + fadd.x COSB3(%pc),%fp2 # B3+S(B4+...) + + fmul.x %fp0,%fp1 # S(A2+...) + fmul.x %fp0,%fp2 # S(B3+...) + + fadd.x SINA1(%pc),%fp1 # A1+S(A2+...) + fadd.x COSB2(%pc),%fp2 # B2+S(B3+...) + + fmul.x %fp0,%fp1 # S(A1+...) + fmul.x %fp2,%fp0 # S(B2+...) + + fmul.x RPRIME(%a6),%fp1 # R'S(A1+...) + fadd.s COSB1(%pc),%fp0 # B1+S(B2...) + fmul.x SPRIME(%a6),%fp0 # S'(B1+S(B2+...)) + + fmovm.x (%sp)+,&0x20 # restore fp2 + + fmov.l %d0,%fpcr + fadd.x RPRIME(%a6),%fp1 # COS(X) + bsr sto_cos # store cosine result + fadd.s POSNEG1(%a6),%fp0 # SIN(X) + bra t_inx2 + +NEVEN: +#--REGISTERS SAVED SO FAR: FP2. + fmovm.x &0x04,-(%sp) # save fp2 + + fmov.x %fp0,RPRIME(%a6) + fmul.x %fp0,%fp0 # FP0 IS S = R*R + + fmov.d COSB8(%pc),%fp1 # B8 + fmov.d SINA7(%pc),%fp2 # A7 + + fmul.x %fp0,%fp1 # SB8 + fmov.x %fp0,SPRIME(%a6) + fmul.x %fp0,%fp2 # SA7 + + ror.l &1,%d1 + and.l &0x80000000,%d1 + + fadd.d COSB7(%pc),%fp1 # B7+SB8 + fadd.d SINA6(%pc),%fp2 # A6+SA7 + + eor.l %d1,RPRIME(%a6) + eor.l %d1,SPRIME(%a6) + + fmul.x %fp0,%fp1 # S(B7+SB8) + + or.l &0x3F800000,%d1 + mov.l %d1,POSNEG1(%a6) + + fmul.x %fp0,%fp2 # S(A6+SA7) + + fadd.d COSB6(%pc),%fp1 # B6+S(B7+SB8) + fadd.d SINA5(%pc),%fp2 # A5+S(A6+SA7) + + fmul.x %fp0,%fp1 # S(B6+S(B7+SB8)) + fmul.x %fp0,%fp2 # S(A5+S(A6+SA7)) + + fadd.d COSB5(%pc),%fp1 # B5+S(B6+S(B7+SB8)) + fadd.d SINA4(%pc),%fp2 # A4+S(A5+S(A6+SA7)) + + fmul.x %fp0,%fp1 # S(B5+...) + fmul.x %fp0,%fp2 # S(A4+...) + + fadd.d COSB4(%pc),%fp1 # B4+S(B5+...) + fadd.d SINA3(%pc),%fp2 # A3+S(A4+...) + + fmul.x %fp0,%fp1 # S(B4+...) + fmul.x %fp0,%fp2 # S(A3+...) + + fadd.x COSB3(%pc),%fp1 # B3+S(B4+...) + fadd.x SINA2(%pc),%fp2 # A2+S(A3+...) + + fmul.x %fp0,%fp1 # S(B3+...) + fmul.x %fp0,%fp2 # S(A2+...) + + fadd.x COSB2(%pc),%fp1 # B2+S(B3+...) + fadd.x SINA1(%pc),%fp2 # A1+S(A2+...) + + fmul.x %fp0,%fp1 # S(B2+...) + fmul.x %fp2,%fp0 # s(a1+...) + + + fadd.s COSB1(%pc),%fp1 # B1+S(B2...) + fmul.x RPRIME(%a6),%fp0 # R'S(A1+...) + fmul.x SPRIME(%a6),%fp1 # S'(B1+S(B2+...)) + + fmovm.x (%sp)+,&0x20 # restore fp2 + + fmov.l %d0,%fpcr + fadd.s POSNEG1(%a6),%fp1 # COS(X) + bsr sto_cos # store cosine result + fadd.x RPRIME(%a6),%fp0 # SIN(X) + bra t_inx2 + +################################################ + +SCBORS: + cmp.l %d1,&0x3FFF8000 + bgt.w SREDUCEX + +################################################ + +SCSM: +# mov.w &0x0000,XDCARE(%a6) + fmov.s &0x3F800000,%fp1 + + fmov.l %d0,%fpcr + fsub.s &0x00800000,%fp1 + bsr sto_cos # store cosine result + fmov.l %fpcr,%d0 # d0 must have fpcr,too + mov.b &FMOV_OP,%d1 # last inst is MOVE + fmov.x X(%a6),%fp0 + bra t_catch + +############################################## + + global ssincosd +#--SIN AND COS OF X FOR DENORMALIZED X +ssincosd: + mov.l %d0,-(%sp) # save d0 + fmov.s &0x3F800000,%fp1 + bsr sto_cos # store cosine result + mov.l (%sp)+,%d0 # restore d0 + bra t_extdnrm + +############################################ + +#--WHEN REDUCEX IS USED, THE CODE WILL INEVITABLY BE SLOW. +#--THIS REDUCTION METHOD, HOWEVER, IS MUCH FASTER THAN USING +#--THE REMAINDER INSTRUCTION WHICH IS NOW IN SOFTWARE. +SREDUCEX: + fmovm.x &0x3c,-(%sp) # save {fp2-fp5} + mov.l %d2,-(%sp) # save d2 + fmov.s &0x00000000,%fp1 # fp1 = 0 + +#--If compact form of abs(arg) in d0=$7ffeffff, argument is so large that +#--there is a danger of unwanted overflow in first LOOP iteration. In this +#--case, reduce argument by one remainder step to make subsequent reduction +#--safe. + cmp.l %d1,&0x7ffeffff # is arg dangerously large? + bne.b SLOOP # no + +# yes; create 2**16383*PI/2 + mov.w &0x7ffe,FP_SCR0_EX(%a6) + mov.l &0xc90fdaa2,FP_SCR0_HI(%a6) + clr.l FP_SCR0_LO(%a6) + +# create low half of 2**16383*PI/2 at FP_SCR1 + mov.w &0x7fdc,FP_SCR1_EX(%a6) + mov.l &0x85a308d3,FP_SCR1_HI(%a6) + clr.l FP_SCR1_LO(%a6) + + ftest.x %fp0 # test sign of argument + fblt.w sred_neg + + or.b &0x80,FP_SCR0_EX(%a6) # positive arg + or.b &0x80,FP_SCR1_EX(%a6) +sred_neg: + fadd.x FP_SCR0(%a6),%fp0 # high part of reduction is exact + fmov.x %fp0,%fp1 # save high result in fp1 + fadd.x FP_SCR1(%a6),%fp0 # low part of reduction + fsub.x %fp0,%fp1 # determine low component of result + fadd.x FP_SCR1(%a6),%fp1 # fp0/fp1 are reduced argument. + +#--ON ENTRY, FP0 IS X, ON RETURN, FP0 IS X REM PI/2, |X| <= PI/4. +#--integer quotient will be stored in N +#--Intermeditate remainder is 66-bit long; (R,r) in (FP0,FP1) +SLOOP: + fmov.x %fp0,INARG(%a6) # +-2**K * F, 1 <= F < 2 + mov.w INARG(%a6),%d1 + mov.l %d1,%a1 # save a copy of D0 + and.l &0x00007FFF,%d1 + sub.l &0x00003FFF,%d1 # d0 = K + cmp.l %d1,&28 + ble.b SLASTLOOP +SCONTLOOP: + sub.l &27,%d1 # d0 = L := K-27 + mov.b &0,ENDFLAG(%a6) + bra.b SWORK +SLASTLOOP: + clr.l %d1 # d0 = L := 0 + mov.b &1,ENDFLAG(%a6) + +SWORK: +#--FIND THE REMAINDER OF (R,r) W.R.T. 2**L * (PI/2). L IS SO CHOSEN +#--THAT INT( X * (2/PI) / 2**(L) ) < 2**29. + +#--CREATE 2**(-L) * (2/PI), SIGN(INARG)*2**(63), +#--2**L * (PIby2_1), 2**L * (PIby2_2) + + mov.l &0x00003FFE,%d2 # BIASED EXP OF 2/PI + sub.l %d1,%d2 # BIASED EXP OF 2**(-L)*(2/PI) + + mov.l &0xA2F9836E,FP_SCR0_HI(%a6) + mov.l &0x4E44152A,FP_SCR0_LO(%a6) + mov.w %d2,FP_SCR0_EX(%a6) # FP_SCR0 = 2**(-L)*(2/PI) + + fmov.x %fp0,%fp2 + fmul.x FP_SCR0(%a6),%fp2 # fp2 = X * 2**(-L)*(2/PI) + +#--WE MUST NOW FIND INT(FP2). SINCE WE NEED THIS VALUE IN +#--FLOATING POINT FORMAT, THE TWO FMOVE'S FMOVE.L FP <--> N +#--WILL BE TOO INEFFICIENT. THE WAY AROUND IT IS THAT +#--(SIGN(INARG)*2**63 + FP2) - SIGN(INARG)*2**63 WILL GIVE +#--US THE DESIRED VALUE IN FLOATING POINT. + mov.l %a1,%d2 + swap %d2 + and.l &0x80000000,%d2 + or.l &0x5F000000,%d2 # d2 = SIGN(INARG)*2**63 IN SGL + mov.l %d2,TWOTO63(%a6) + fadd.s TWOTO63(%a6),%fp2 # THE FRACTIONAL PART OF FP1 IS ROUNDED + fsub.s TWOTO63(%a6),%fp2 # fp2 = N +# fint.x %fp2 + +#--CREATING 2**(L)*Piby2_1 and 2**(L)*Piby2_2 + mov.l %d1,%d2 # d2 = L + + add.l &0x00003FFF,%d2 # BIASED EXP OF 2**L * (PI/2) + mov.w %d2,FP_SCR0_EX(%a6) + mov.l &0xC90FDAA2,FP_SCR0_HI(%a6) + clr.l FP_SCR0_LO(%a6) # FP_SCR0 = 2**(L) * Piby2_1 + + add.l &0x00003FDD,%d1 + mov.w %d1,FP_SCR1_EX(%a6) + mov.l &0x85A308D3,FP_SCR1_HI(%a6) + clr.l FP_SCR1_LO(%a6) # FP_SCR1 = 2**(L) * Piby2_2 + + mov.b ENDFLAG(%a6),%d1 + +#--We are now ready to perform (R+r) - N*P1 - N*P2, P1 = 2**(L) * Piby2_1 and +#--P2 = 2**(L) * Piby2_2 + fmov.x %fp2,%fp4 # fp4 = N + fmul.x FP_SCR0(%a6),%fp4 # fp4 = W = N*P1 + fmov.x %fp2,%fp5 # fp5 = N + fmul.x FP_SCR1(%a6),%fp5 # fp5 = w = N*P2 + fmov.x %fp4,%fp3 # fp3 = W = N*P1 + +#--we want P+p = W+w but |p| <= half ulp of P +#--Then, we need to compute A := R-P and a := r-p + fadd.x %fp5,%fp3 # fp3 = P + fsub.x %fp3,%fp4 # fp4 = W-P + + fsub.x %fp3,%fp0 # fp0 = A := R - P + fadd.x %fp5,%fp4 # fp4 = p = (W-P)+w + + fmov.x %fp0,%fp3 # fp3 = A + fsub.x %fp4,%fp1 # fp1 = a := r - p + +#--Now we need to normalize (A,a) to "new (R,r)" where R+r = A+a but +#--|r| <= half ulp of R. + fadd.x %fp1,%fp0 # fp0 = R := A+a +#--No need to calculate r if this is the last loop + cmp.b %d1,&0 + bgt.w SRESTORE + +#--Need to calculate r + fsub.x %fp0,%fp3 # fp3 = A-R + fadd.x %fp3,%fp1 # fp1 = r := (A-R)+a + bra.w SLOOP + +SRESTORE: + fmov.l %fp2,INT(%a6) + mov.l (%sp)+,%d2 # restore d2 + fmovm.x (%sp)+,&0x3c # restore {fp2-fp5} + + mov.l ADJN(%a6),%d1 + cmp.l %d1,&4 + + blt.w SINCONT + bra.w SCCONT + +######################################################################### +# stan(): computes the tangent of a normalized input # +# stand(): computes the tangent of a denormalized input # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input # +# d0 = round precision,mode # +# # +# OUTPUT ************************************************************** # +# fp0 = tan(X) # +# # +# ACCURACY and MONOTONICITY ******************************************* # +# The returned result is within 3 ulp in 64 significant bit, i.e. # +# within 0.5001 ulp to 53 bits if the result is subsequently # +# rounded to double precision. The result is provably monotonic # +# in double precision. # +# # +# ALGORITHM *********************************************************** # +# # +# 1. If |X| >= 15Pi or |X| < 2**(-40), go to 6. # +# # +# 2. Decompose X as X = N(Pi/2) + r where |r| <= Pi/4. Let # +# k = N mod 2, so in particular, k = 0 or 1. # +# # +# 3. If k is odd, go to 5. # +# # +# 4. (k is even) Tan(X) = tan(r) and tan(r) is approximated by a # +# rational function U/V where # +# U = r + r*s*(P1 + s*(P2 + s*P3)), and # +# V = 1 + s*(Q1 + s*(Q2 + s*(Q3 + s*Q4))), s = r*r. # +# Exit. # +# # +# 4. (k is odd) Tan(X) = -cot(r). Since tan(r) is approximated by # +# a rational function U/V where # +# U = r + r*s*(P1 + s*(P2 + s*P3)), and # +# V = 1 + s*(Q1 + s*(Q2 + s*(Q3 + s*Q4))), s = r*r, # +# -Cot(r) = -V/U. Exit. # +# # +# 6. If |X| > 1, go to 8. # +# # +# 7. (|X|<2**(-40)) Tan(X) = X. Exit. # +# # +# 8. Overwrite X by X := X rem 2Pi. Now that |X| <= Pi, go back # +# to 2. # +# # +######################################################################### + +TANQ4: + long 0x3EA0B759,0xF50F8688 +TANP3: + long 0xBEF2BAA5,0xA8924F04 + +TANQ3: + long 0xBF346F59,0xB39BA65F,0x00000000,0x00000000 + +TANP2: + long 0x3FF60000,0xE073D3FC,0x199C4A00,0x00000000 + +TANQ2: + long 0x3FF90000,0xD23CD684,0x15D95FA1,0x00000000 + +TANP1: + long 0xBFFC0000,0x8895A6C5,0xFB423BCA,0x00000000 + +TANQ1: + long 0xBFFD0000,0xEEF57E0D,0xA84BC8CE,0x00000000 + +INVTWOPI: + long 0x3FFC0000,0xA2F9836E,0x4E44152A,0x00000000 + +TWOPI1: + long 0x40010000,0xC90FDAA2,0x00000000,0x00000000 +TWOPI2: + long 0x3FDF0000,0x85A308D4,0x00000000,0x00000000 + +#--N*PI/2, -32 <= N <= 32, IN A LEADING TERM IN EXT. AND TRAILING +#--TERM IN SGL. NOTE THAT PI IS 64-BIT LONG, THUS N*PI/2 IS AT +#--MOST 69 BITS LONG. +# global PITBL +PITBL: + long 0xC0040000,0xC90FDAA2,0x2168C235,0x21800000 + long 0xC0040000,0xC2C75BCD,0x105D7C23,0xA0D00000 + long 0xC0040000,0xBC7EDCF7,0xFF523611,0xA1E80000 + long 0xC0040000,0xB6365E22,0xEE46F000,0x21480000 + long 0xC0040000,0xAFEDDF4D,0xDD3BA9EE,0xA1200000 + long 0xC0040000,0xA9A56078,0xCC3063DD,0x21FC0000 + long 0xC0040000,0xA35CE1A3,0xBB251DCB,0x21100000 + long 0xC0040000,0x9D1462CE,0xAA19D7B9,0xA1580000 + long 0xC0040000,0x96CBE3F9,0x990E91A8,0x21E00000 + long 0xC0040000,0x90836524,0x88034B96,0x20B00000 + long 0xC0040000,0x8A3AE64F,0x76F80584,0xA1880000 + long 0xC0040000,0x83F2677A,0x65ECBF73,0x21C40000 + long 0xC0030000,0xFB53D14A,0xA9C2F2C2,0x20000000 + long 0xC0030000,0xEEC2D3A0,0x87AC669F,0x21380000 + long 0xC0030000,0xE231D5F6,0x6595DA7B,0xA1300000 + long 0xC0030000,0xD5A0D84C,0x437F4E58,0x9FC00000 + long 0xC0030000,0xC90FDAA2,0x2168C235,0x21000000 + long 0xC0030000,0xBC7EDCF7,0xFF523611,0xA1680000 + long 0xC0030000,0xAFEDDF4D,0xDD3BA9EE,0xA0A00000 + long 0xC0030000,0xA35CE1A3,0xBB251DCB,0x20900000 + long 0xC0030000,0x96CBE3F9,0x990E91A8,0x21600000 + long 0xC0030000,0x8A3AE64F,0x76F80584,0xA1080000 + long 0xC0020000,0xFB53D14A,0xA9C2F2C2,0x1F800000 + long 0xC0020000,0xE231D5F6,0x6595DA7B,0xA0B00000 + long 0xC0020000,0xC90FDAA2,0x2168C235,0x20800000 + long 0xC0020000,0xAFEDDF4D,0xDD3BA9EE,0xA0200000 + long 0xC0020000,0x96CBE3F9,0x990E91A8,0x20E00000 + long 0xC0010000,0xFB53D14A,0xA9C2F2C2,0x1F000000 + long 0xC0010000,0xC90FDAA2,0x2168C235,0x20000000 + long 0xC0010000,0x96CBE3F9,0x990E91A8,0x20600000 + long 0xC0000000,0xC90FDAA2,0x2168C235,0x1F800000 + long 0xBFFF0000,0xC90FDAA2,0x2168C235,0x1F000000 + long 0x00000000,0x00000000,0x00000000,0x00000000 + long 0x3FFF0000,0xC90FDAA2,0x2168C235,0x9F000000 + long 0x40000000,0xC90FDAA2,0x2168C235,0x9F800000 + long 0x40010000,0x96CBE3F9,0x990E91A8,0xA0600000 + long 0x40010000,0xC90FDAA2,0x2168C235,0xA0000000 + long 0x40010000,0xFB53D14A,0xA9C2F2C2,0x9F000000 + long 0x40020000,0x96CBE3F9,0x990E91A8,0xA0E00000 + long 0x40020000,0xAFEDDF4D,0xDD3BA9EE,0x20200000 + long 0x40020000,0xC90FDAA2,0x2168C235,0xA0800000 + long 0x40020000,0xE231D5F6,0x6595DA7B,0x20B00000 + long 0x40020000,0xFB53D14A,0xA9C2F2C2,0x9F800000 + long 0x40030000,0x8A3AE64F,0x76F80584,0x21080000 + long 0x40030000,0x96CBE3F9,0x990E91A8,0xA1600000 + long 0x40030000,0xA35CE1A3,0xBB251DCB,0xA0900000 + long 0x40030000,0xAFEDDF4D,0xDD3BA9EE,0x20A00000 + long 0x40030000,0xBC7EDCF7,0xFF523611,0x21680000 + long 0x40030000,0xC90FDAA2,0x2168C235,0xA1000000 + long 0x40030000,0xD5A0D84C,0x437F4E58,0x1FC00000 + long 0x40030000,0xE231D5F6,0x6595DA7B,0x21300000 + long 0x40030000,0xEEC2D3A0,0x87AC669F,0xA1380000 + long 0x40030000,0xFB53D14A,0xA9C2F2C2,0xA0000000 + long 0x40040000,0x83F2677A,0x65ECBF73,0xA1C40000 + long 0x40040000,0x8A3AE64F,0x76F80584,0x21880000 + long 0x40040000,0x90836524,0x88034B96,0xA0B00000 + long 0x40040000,0x96CBE3F9,0x990E91A8,0xA1E00000 + long 0x40040000,0x9D1462CE,0xAA19D7B9,0x21580000 + long 0x40040000,0xA35CE1A3,0xBB251DCB,0xA1100000 + long 0x40040000,0xA9A56078,0xCC3063DD,0xA1FC0000 + long 0x40040000,0xAFEDDF4D,0xDD3BA9EE,0x21200000 + long 0x40040000,0xB6365E22,0xEE46F000,0xA1480000 + long 0x40040000,0xBC7EDCF7,0xFF523611,0x21E80000 + long 0x40040000,0xC2C75BCD,0x105D7C23,0x20D00000 + long 0x40040000,0xC90FDAA2,0x2168C235,0xA1800000 + + set INARG,FP_SCR0 + + set TWOTO63,L_SCR1 + set INT,L_SCR1 + set ENDFLAG,L_SCR2 + + global stan +stan: + fmov.x (%a0),%fp0 # LOAD INPUT + + mov.l (%a0),%d1 + mov.w 4(%a0),%d1 + and.l &0x7FFFFFFF,%d1 + + cmp.l %d1,&0x3FD78000 # |X| >= 2**(-40)? + bge.b TANOK1 + bra.w TANSM +TANOK1: + cmp.l %d1,&0x4004BC7E # |X| < 15 PI? + blt.b TANMAIN + bra.w REDUCEX + +TANMAIN: +#--THIS IS THE USUAL CASE, |X| <= 15 PI. +#--THE ARGUMENT REDUCTION IS DONE BY TABLE LOOK UP. + fmov.x %fp0,%fp1 + fmul.d TWOBYPI(%pc),%fp1 # X*2/PI + + lea.l PITBL+0x200(%pc),%a1 # TABLE OF N*PI/2, N = -32,...,32 + + fmov.l %fp1,%d1 # CONVERT TO INTEGER + + asl.l &4,%d1 + add.l %d1,%a1 # ADDRESS N*PIBY2 IN Y1, Y2 + + fsub.x (%a1)+,%fp0 # X-Y1 + + fsub.s (%a1),%fp0 # FP0 IS R = (X-Y1)-Y2 + + ror.l &5,%d1 + and.l &0x80000000,%d1 # D0 WAS ODD IFF D0 < 0 + +TANCONT: + fmovm.x &0x0c,-(%sp) # save fp2,fp3 + + cmp.l %d1,&0 + blt.w NODD + + fmov.x %fp0,%fp1 + fmul.x %fp1,%fp1 # S = R*R + + fmov.d TANQ4(%pc),%fp3 + fmov.d TANP3(%pc),%fp2 + + fmul.x %fp1,%fp3 # SQ4 + fmul.x %fp1,%fp2 # SP3 + + fadd.d TANQ3(%pc),%fp3 # Q3+SQ4 + fadd.x TANP2(%pc),%fp2 # P2+SP3 + + fmul.x %fp1,%fp3 # S(Q3+SQ4) + fmul.x %fp1,%fp2 # S(P2+SP3) + + fadd.x TANQ2(%pc),%fp3 # Q2+S(Q3+SQ4) + fadd.x TANP1(%pc),%fp2 # P1+S(P2+SP3) + + fmul.x %fp1,%fp3 # S(Q2+S(Q3+SQ4)) + fmul.x %fp1,%fp2 # S(P1+S(P2+SP3)) + + fadd.x TANQ1(%pc),%fp3 # Q1+S(Q2+S(Q3+SQ4)) + fmul.x %fp0,%fp2 # RS(P1+S(P2+SP3)) + + fmul.x %fp3,%fp1 # S(Q1+S(Q2+S(Q3+SQ4))) + + fadd.x %fp2,%fp0 # R+RS(P1+S(P2+SP3)) + + fadd.s &0x3F800000,%fp1 # 1+S(Q1+...) + + fmovm.x (%sp)+,&0x30 # restore fp2,fp3 + + fmov.l %d0,%fpcr # restore users round mode,prec + fdiv.x %fp1,%fp0 # last inst - possible exception set + bra t_inx2 + +NODD: + fmov.x %fp0,%fp1 + fmul.x %fp0,%fp0 # S = R*R + + fmov.d TANQ4(%pc),%fp3 + fmov.d TANP3(%pc),%fp2 + + fmul.x %fp0,%fp3 # SQ4 + fmul.x %fp0,%fp2 # SP3 + + fadd.d TANQ3(%pc),%fp3 # Q3+SQ4 + fadd.x TANP2(%pc),%fp2 # P2+SP3 + + fmul.x %fp0,%fp3 # S(Q3+SQ4) + fmul.x %fp0,%fp2 # S(P2+SP3) + + fadd.x TANQ2(%pc),%fp3 # Q2+S(Q3+SQ4) + fadd.x TANP1(%pc),%fp2 # P1+S(P2+SP3) + + fmul.x %fp0,%fp3 # S(Q2+S(Q3+SQ4)) + fmul.x %fp0,%fp2 # S(P1+S(P2+SP3)) + + fadd.x TANQ1(%pc),%fp3 # Q1+S(Q2+S(Q3+SQ4)) + fmul.x %fp1,%fp2 # RS(P1+S(P2+SP3)) + + fmul.x %fp3,%fp0 # S(Q1+S(Q2+S(Q3+SQ4))) + + fadd.x %fp2,%fp1 # R+RS(P1+S(P2+SP3)) + fadd.s &0x3F800000,%fp0 # 1+S(Q1+...) + + fmovm.x (%sp)+,&0x30 # restore fp2,fp3 + + fmov.x %fp1,-(%sp) + eor.l &0x80000000,(%sp) + + fmov.l %d0,%fpcr # restore users round mode,prec + fdiv.x (%sp)+,%fp0 # last inst - possible exception set + bra t_inx2 + +TANBORS: +#--IF |X| > 15PI, WE USE THE GENERAL ARGUMENT REDUCTION. +#--IF |X| < 2**(-40), RETURN X OR 1. + cmp.l %d1,&0x3FFF8000 + bgt.b REDUCEX + +TANSM: + fmov.x %fp0,-(%sp) + fmov.l %d0,%fpcr # restore users round mode,prec + mov.b &FMOV_OP,%d1 # last inst is MOVE + fmov.x (%sp)+,%fp0 # last inst - posibble exception set + bra t_catch + + global stand +#--TAN(X) = X FOR DENORMALIZED X +stand: + bra t_extdnrm + +#--WHEN REDUCEX IS USED, THE CODE WILL INEVITABLY BE SLOW. +#--THIS REDUCTION METHOD, HOWEVER, IS MUCH FASTER THAN USING +#--THE REMAINDER INSTRUCTION WHICH IS NOW IN SOFTWARE. +REDUCEX: + fmovm.x &0x3c,-(%sp) # save {fp2-fp5} + mov.l %d2,-(%sp) # save d2 + fmov.s &0x00000000,%fp1 # fp1 = 0 + +#--If compact form of abs(arg) in d0=$7ffeffff, argument is so large that +#--there is a danger of unwanted overflow in first LOOP iteration. In this +#--case, reduce argument by one remainder step to make subsequent reduction +#--safe. + cmp.l %d1,&0x7ffeffff # is arg dangerously large? + bne.b LOOP # no + +# yes; create 2**16383*PI/2 + mov.w &0x7ffe,FP_SCR0_EX(%a6) + mov.l &0xc90fdaa2,FP_SCR0_HI(%a6) + clr.l FP_SCR0_LO(%a6) + +# create low half of 2**16383*PI/2 at FP_SCR1 + mov.w &0x7fdc,FP_SCR1_EX(%a6) + mov.l &0x85a308d3,FP_SCR1_HI(%a6) + clr.l FP_SCR1_LO(%a6) + + ftest.x %fp0 # test sign of argument + fblt.w red_neg + + or.b &0x80,FP_SCR0_EX(%a6) # positive arg + or.b &0x80,FP_SCR1_EX(%a6) +red_neg: + fadd.x FP_SCR0(%a6),%fp0 # high part of reduction is exact + fmov.x %fp0,%fp1 # save high result in fp1 + fadd.x FP_SCR1(%a6),%fp0 # low part of reduction + fsub.x %fp0,%fp1 # determine low component of result + fadd.x FP_SCR1(%a6),%fp1 # fp0/fp1 are reduced argument. + +#--ON ENTRY, FP0 IS X, ON RETURN, FP0 IS X REM PI/2, |X| <= PI/4. +#--integer quotient will be stored in N +#--Intermeditate remainder is 66-bit long; (R,r) in (FP0,FP1) +LOOP: + fmov.x %fp0,INARG(%a6) # +-2**K * F, 1 <= F < 2 + mov.w INARG(%a6),%d1 + mov.l %d1,%a1 # save a copy of D0 + and.l &0x00007FFF,%d1 + sub.l &0x00003FFF,%d1 # d0 = K + cmp.l %d1,&28 + ble.b LASTLOOP +CONTLOOP: + sub.l &27,%d1 # d0 = L := K-27 + mov.b &0,ENDFLAG(%a6) + bra.b WORK +LASTLOOP: + clr.l %d1 # d0 = L := 0 + mov.b &1,ENDFLAG(%a6) + +WORK: +#--FIND THE REMAINDER OF (R,r) W.R.T. 2**L * (PI/2). L IS SO CHOSEN +#--THAT INT( X * (2/PI) / 2**(L) ) < 2**29. + +#--CREATE 2**(-L) * (2/PI), SIGN(INARG)*2**(63), +#--2**L * (PIby2_1), 2**L * (PIby2_2) + + mov.l &0x00003FFE,%d2 # BIASED EXP OF 2/PI + sub.l %d1,%d2 # BIASED EXP OF 2**(-L)*(2/PI) + + mov.l &0xA2F9836E,FP_SCR0_HI(%a6) + mov.l &0x4E44152A,FP_SCR0_LO(%a6) + mov.w %d2,FP_SCR0_EX(%a6) # FP_SCR0 = 2**(-L)*(2/PI) + + fmov.x %fp0,%fp2 + fmul.x FP_SCR0(%a6),%fp2 # fp2 = X * 2**(-L)*(2/PI) + +#--WE MUST NOW FIND INT(FP2). SINCE WE NEED THIS VALUE IN +#--FLOATING POINT FORMAT, THE TWO FMOVE'S FMOVE.L FP <--> N +#--WILL BE TOO INEFFICIENT. THE WAY AROUND IT IS THAT +#--(SIGN(INARG)*2**63 + FP2) - SIGN(INARG)*2**63 WILL GIVE +#--US THE DESIRED VALUE IN FLOATING POINT. + mov.l %a1,%d2 + swap %d2 + and.l &0x80000000,%d2 + or.l &0x5F000000,%d2 # d2 = SIGN(INARG)*2**63 IN SGL + mov.l %d2,TWOTO63(%a6) + fadd.s TWOTO63(%a6),%fp2 # THE FRACTIONAL PART OF FP1 IS ROUNDED + fsub.s TWOTO63(%a6),%fp2 # fp2 = N +# fintrz.x %fp2,%fp2 + +#--CREATING 2**(L)*Piby2_1 and 2**(L)*Piby2_2 + mov.l %d1,%d2 # d2 = L + + add.l &0x00003FFF,%d2 # BIASED EXP OF 2**L * (PI/2) + mov.w %d2,FP_SCR0_EX(%a6) + mov.l &0xC90FDAA2,FP_SCR0_HI(%a6) + clr.l FP_SCR0_LO(%a6) # FP_SCR0 = 2**(L) * Piby2_1 + + add.l &0x00003FDD,%d1 + mov.w %d1,FP_SCR1_EX(%a6) + mov.l &0x85A308D3,FP_SCR1_HI(%a6) + clr.l FP_SCR1_LO(%a6) # FP_SCR1 = 2**(L) * Piby2_2 + + mov.b ENDFLAG(%a6),%d1 + +#--We are now ready to perform (R+r) - N*P1 - N*P2, P1 = 2**(L) * Piby2_1 and +#--P2 = 2**(L) * Piby2_2 + fmov.x %fp2,%fp4 # fp4 = N + fmul.x FP_SCR0(%a6),%fp4 # fp4 = W = N*P1 + fmov.x %fp2,%fp5 # fp5 = N + fmul.x FP_SCR1(%a6),%fp5 # fp5 = w = N*P2 + fmov.x %fp4,%fp3 # fp3 = W = N*P1 + +#--we want P+p = W+w but |p| <= half ulp of P +#--Then, we need to compute A := R-P and a := r-p + fadd.x %fp5,%fp3 # fp3 = P + fsub.x %fp3,%fp4 # fp4 = W-P + + fsub.x %fp3,%fp0 # fp0 = A := R - P + fadd.x %fp5,%fp4 # fp4 = p = (W-P)+w + + fmov.x %fp0,%fp3 # fp3 = A + fsub.x %fp4,%fp1 # fp1 = a := r - p + +#--Now we need to normalize (A,a) to "new (R,r)" where R+r = A+a but +#--|r| <= half ulp of R. + fadd.x %fp1,%fp0 # fp0 = R := A+a +#--No need to calculate r if this is the last loop + cmp.b %d1,&0 + bgt.w RESTORE + +#--Need to calculate r + fsub.x %fp0,%fp3 # fp3 = A-R + fadd.x %fp3,%fp1 # fp1 = r := (A-R)+a + bra.w LOOP + +RESTORE: + fmov.l %fp2,INT(%a6) + mov.l (%sp)+,%d2 # restore d2 + fmovm.x (%sp)+,&0x3c # restore {fp2-fp5} + + mov.l INT(%a6),%d1 + ror.l &1,%d1 + + bra.w TANCONT + +######################################################################### +# satan(): computes the arctangent of a normalized number # +# satand(): computes the arctangent of a denormalized number # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input # +# d0 = round precision,mode # +# # +# OUTPUT ************************************************************** # +# fp0 = arctan(X) # +# # +# ACCURACY and MONOTONICITY ******************************************* # +# The returned result is within 2 ulps in 64 significant bit, # +# i.e. within 0.5001 ulp to 53 bits if the result is subsequently # +# rounded to double precision. The result is provably monotonic # +# in double precision. # +# # +# ALGORITHM *********************************************************** # +# Step 1. If |X| >= 16 or |X| < 1/16, go to Step 5. # +# # +# Step 2. Let X = sgn * 2**k * 1.xxxxxxxx...x. # +# Note that k = -4, -3,..., or 3. # +# Define F = sgn * 2**k * 1.xxxx1, i.e. the first 5 # +# significant bits of X with a bit-1 attached at the 6-th # +# bit position. Define u to be u = (X-F) / (1 + X*F). # +# # +# Step 3. Approximate arctan(u) by a polynomial poly. # +# # +# Step 4. Return arctan(F) + poly, arctan(F) is fetched from a # +# table of values calculated beforehand. Exit. # +# # +# Step 5. If |X| >= 16, go to Step 7. # +# # +# Step 6. Approximate arctan(X) by an odd polynomial in X. Exit. # +# # +# Step 7. Define X' = -1/X. Approximate arctan(X') by an odd # +# polynomial in X'. # +# Arctan(X) = sign(X)*Pi/2 + arctan(X'). Exit. # +# # +######################################################################### + +ATANA3: long 0xBFF6687E,0x314987D8 +ATANA2: long 0x4002AC69,0x34A26DB3 +ATANA1: long 0xBFC2476F,0x4E1DA28E + +ATANB6: long 0x3FB34444,0x7F876989 +ATANB5: long 0xBFB744EE,0x7FAF45DB +ATANB4: long 0x3FBC71C6,0x46940220 +ATANB3: long 0xBFC24924,0x921872F9 +ATANB2: long 0x3FC99999,0x99998FA9 +ATANB1: long 0xBFD55555,0x55555555 + +ATANC5: long 0xBFB70BF3,0x98539E6A +ATANC4: long 0x3FBC7187,0x962D1D7D +ATANC3: long 0xBFC24924,0x827107B8 +ATANC2: long 0x3FC99999,0x9996263E +ATANC1: long 0xBFD55555,0x55555536 + +PPIBY2: long 0x3FFF0000,0xC90FDAA2,0x2168C235,0x00000000 +NPIBY2: long 0xBFFF0000,0xC90FDAA2,0x2168C235,0x00000000 + +PTINY: long 0x00010000,0x80000000,0x00000000,0x00000000 +NTINY: long 0x80010000,0x80000000,0x00000000,0x00000000 + +ATANTBL: + long 0x3FFB0000,0x83D152C5,0x060B7A51,0x00000000 + long 0x3FFB0000,0x8BC85445,0x65498B8B,0x00000000 + long 0x3FFB0000,0x93BE4060,0x17626B0D,0x00000000 + long 0x3FFB0000,0x9BB3078D,0x35AEC202,0x00000000 + long 0x3FFB0000,0xA3A69A52,0x5DDCE7DE,0x00000000 + long 0x3FFB0000,0xAB98E943,0x62765619,0x00000000 + long 0x3FFB0000,0xB389E502,0xF9C59862,0x00000000 + long 0x3FFB0000,0xBB797E43,0x6B09E6FB,0x00000000 + long 0x3FFB0000,0xC367A5C7,0x39E5F446,0x00000000 + long 0x3FFB0000,0xCB544C61,0xCFF7D5C6,0x00000000 + long 0x3FFB0000,0xD33F62F8,0x2488533E,0x00000000 + long 0x3FFB0000,0xDB28DA81,0x62404C77,0x00000000 + long 0x3FFB0000,0xE310A407,0x8AD34F18,0x00000000 + long 0x3FFB0000,0xEAF6B0A8,0x188EE1EB,0x00000000 + long 0x3FFB0000,0xF2DAF194,0x9DBE79D5,0x00000000 + long 0x3FFB0000,0xFABD5813,0x61D47E3E,0x00000000 + long 0x3FFC0000,0x8346AC21,0x0959ECC4,0x00000000 + long 0x3FFC0000,0x8B232A08,0x304282D8,0x00000000 + long 0x3FFC0000,0x92FB70B8,0xD29AE2F9,0x00000000 + long 0x3FFC0000,0x9ACF476F,0x5CCD1CB4,0x00000000 + long 0x3FFC0000,0xA29E7630,0x4954F23F,0x00000000 + long 0x3FFC0000,0xAA68C5D0,0x8AB85230,0x00000000 + long 0x3FFC0000,0xB22DFFFD,0x9D539F83,0x00000000 + long 0x3FFC0000,0xB9EDEF45,0x3E900EA5,0x00000000 + long 0x3FFC0000,0xC1A85F1C,0xC75E3EA5,0x00000000 + long 0x3FFC0000,0xC95D1BE8,0x28138DE6,0x00000000 + long 0x3FFC0000,0xD10BF300,0x840D2DE4,0x00000000 + long 0x3FFC0000,0xD8B4B2BA,0x6BC05E7A,0x00000000 + long 0x3FFC0000,0xE0572A6B,0xB42335F6,0x00000000 + long 0x3FFC0000,0xE7F32A70,0xEA9CAA8F,0x00000000 + long 0x3FFC0000,0xEF888432,0x64ECEFAA,0x00000000 + long 0x3FFC0000,0xF7170A28,0xECC06666,0x00000000 + long 0x3FFD0000,0x812FD288,0x332DAD32,0x00000000 + long 0x3FFD0000,0x88A8D1B1,0x218E4D64,0x00000000 + long 0x3FFD0000,0x9012AB3F,0x23E4AEE8,0x00000000 + long 0x3FFD0000,0x976CC3D4,0x11E7F1B9,0x00000000 + long 0x3FFD0000,0x9EB68949,0x3889A227,0x00000000 + long 0x3FFD0000,0xA5EF72C3,0x4487361B,0x00000000 + long 0x3FFD0000,0xAD1700BA,0xF07A7227,0x00000000 + long 0x3FFD0000,0xB42CBCFA,0xFD37EFB7,0x00000000 + long 0x3FFD0000,0xBB303A94,0x0BA80F89,0x00000000 + long 0x3FFD0000,0xC22115C6,0xFCAEBBAF,0x00000000 + long 0x3FFD0000,0xC8FEF3E6,0x86331221,0x00000000 + long 0x3FFD0000,0xCFC98330,0xB4000C70,0x00000000 + long 0x3FFD0000,0xD6807AA1,0x102C5BF9,0x00000000 + long 0x3FFD0000,0xDD2399BC,0x31252AA3,0x00000000 + long 0x3FFD0000,0xE3B2A855,0x6B8FC517,0x00000000 + long 0x3FFD0000,0xEA2D764F,0x64315989,0x00000000 + long 0x3FFD0000,0xF3BF5BF8,0xBAD1A21D,0x00000000 + long 0x3FFE0000,0x801CE39E,0x0D205C9A,0x00000000 + long 0x3FFE0000,0x8630A2DA,0xDA1ED066,0x00000000 + long 0x3FFE0000,0x8C1AD445,0xF3E09B8C,0x00000000 + long 0x3FFE0000,0x91DB8F16,0x64F350E2,0x00000000 + long 0x3FFE0000,0x97731420,0x365E538C,0x00000000 + long 0x3FFE0000,0x9CE1C8E6,0xA0B8CDBA,0x00000000 + long 0x3FFE0000,0xA22832DB,0xCADAAE09,0x00000000 + long 0x3FFE0000,0xA746F2DD,0xB7602294,0x00000000 + long 0x3FFE0000,0xAC3EC0FB,0x997DD6A2,0x00000000 + long 0x3FFE0000,0xB110688A,0xEBDC6F6A,0x00000000 + long 0x3FFE0000,0xB5BCC490,0x59ECC4B0,0x00000000 + long 0x3FFE0000,0xBA44BC7D,0xD470782F,0x00000000 + long 0x3FFE0000,0xBEA94144,0xFD049AAC,0x00000000 + long 0x3FFE0000,0xC2EB4ABB,0x661628B6,0x00000000 + long 0x3FFE0000,0xC70BD54C,0xE602EE14,0x00000000 + long 0x3FFE0000,0xCD000549,0xADEC7159,0x00000000 + long 0x3FFE0000,0xD48457D2,0xD8EA4EA3,0x00000000 + long 0x3FFE0000,0xDB948DA7,0x12DECE3B,0x00000000 + long 0x3FFE0000,0xE23855F9,0x69E8096A,0x00000000 + long 0x3FFE0000,0xE8771129,0xC4353259,0x00000000 + long 0x3FFE0000,0xEE57C16E,0x0D379C0D,0x00000000 + long 0x3FFE0000,0xF3E10211,0xA87C3779,0x00000000 + long 0x3FFE0000,0xF919039D,0x758B8D41,0x00000000 + long 0x3FFE0000,0xFE058B8F,0x64935FB3,0x00000000 + long 0x3FFF0000,0x8155FB49,0x7B685D04,0x00000000 + long 0x3FFF0000,0x83889E35,0x49D108E1,0x00000000 + long 0x3FFF0000,0x859CFA76,0x511D724B,0x00000000 + long 0x3FFF0000,0x87952ECF,0xFF8131E7,0x00000000 + long 0x3FFF0000,0x89732FD1,0x9557641B,0x00000000 + long 0x3FFF0000,0x8B38CAD1,0x01932A35,0x00000000 + long 0x3FFF0000,0x8CE7A8D8,0x301EE6B5,0x00000000 + long 0x3FFF0000,0x8F46A39E,0x2EAE5281,0x00000000 + long 0x3FFF0000,0x922DA7D7,0x91888487,0x00000000 + long 0x3FFF0000,0x94D19FCB,0xDEDF5241,0x00000000 + long 0x3FFF0000,0x973AB944,0x19D2A08B,0x00000000 + long 0x3FFF0000,0x996FF00E,0x08E10B96,0x00000000 + long 0x3FFF0000,0x9B773F95,0x12321DA7,0x00000000 + long 0x3FFF0000,0x9D55CC32,0x0F935624,0x00000000 + long 0x3FFF0000,0x9F100575,0x006CC571,0x00000000 + long 0x3FFF0000,0xA0A9C290,0xD97CC06C,0x00000000 + long 0x3FFF0000,0xA22659EB,0xEBC0630A,0x00000000 + long 0x3FFF0000,0xA388B4AF,0xF6EF0EC9,0x00000000 + long 0x3FFF0000,0xA4D35F10,0x61D292C4,0x00000000 + long 0x3FFF0000,0xA60895DC,0xFBE3187E,0x00000000 + long 0x3FFF0000,0xA72A51DC,0x7367BEAC,0x00000000 + long 0x3FFF0000,0xA83A5153,0x0956168F,0x00000000 + long 0x3FFF0000,0xA93A2007,0x7539546E,0x00000000 + long 0x3FFF0000,0xAA9E7245,0x023B2605,0x00000000 + long 0x3FFF0000,0xAC4C84BA,0x6FE4D58F,0x00000000 + long 0x3FFF0000,0xADCE4A4A,0x606B9712,0x00000000 + long 0x3FFF0000,0xAF2A2DCD,0x8D263C9C,0x00000000 + long 0x3FFF0000,0xB0656F81,0xF22265C7,0x00000000 + long 0x3FFF0000,0xB1846515,0x0F71496A,0x00000000 + long 0x3FFF0000,0xB28AAA15,0x6F9ADA35,0x00000000 + long 0x3FFF0000,0xB37B44FF,0x3766B895,0x00000000 + long 0x3FFF0000,0xB458C3DC,0xE9630433,0x00000000 + long 0x3FFF0000,0xB525529D,0x562246BD,0x00000000 + long 0x3FFF0000,0xB5E2CCA9,0x5F9D88CC,0x00000000 + long 0x3FFF0000,0xB692CADA,0x7ACA1ADA,0x00000000 + long 0x3FFF0000,0xB736AEA7,0xA6925838,0x00000000 + long 0x3FFF0000,0xB7CFAB28,0x7E9F7B36,0x00000000 + long 0x3FFF0000,0xB85ECC66,0xCB219835,0x00000000 + long 0x3FFF0000,0xB8E4FD5A,0x20A593DA,0x00000000 + long 0x3FFF0000,0xB99F41F6,0x4AFF9BB5,0x00000000 + long 0x3FFF0000,0xBA7F1E17,0x842BBE7B,0x00000000 + long 0x3FFF0000,0xBB471285,0x7637E17D,0x00000000 + long 0x3FFF0000,0xBBFABE8A,0x4788DF6F,0x00000000 + long 0x3FFF0000,0xBC9D0FAD,0x2B689D79,0x00000000 + long 0x3FFF0000,0xBD306A39,0x471ECD86,0x00000000 + long 0x3FFF0000,0xBDB6C731,0x856AF18A,0x00000000 + long 0x3FFF0000,0xBE31CAC5,0x02E80D70,0x00000000 + long 0x3FFF0000,0xBEA2D55C,0xE33194E2,0x00000000 + long 0x3FFF0000,0xBF0B10B7,0xC03128F0,0x00000000 + long 0x3FFF0000,0xBF6B7A18,0xDACB778D,0x00000000 + long 0x3FFF0000,0xBFC4EA46,0x63FA18F6,0x00000000 + long 0x3FFF0000,0xC0181BDE,0x8B89A454,0x00000000 + long 0x3FFF0000,0xC065B066,0xCFBF6439,0x00000000 + long 0x3FFF0000,0xC0AE345F,0x56340AE6,0x00000000 + long 0x3FFF0000,0xC0F22291,0x9CB9E6A7,0x00000000 + + set X,FP_SCR0 + set XDCARE,X+2 + set XFRAC,X+4 + set XFRACLO,X+8 + + set ATANF,FP_SCR1 + set ATANFHI,ATANF+4 + set ATANFLO,ATANF+8 + + global satan +#--ENTRY POINT FOR ATAN(X), HERE X IS FINITE, NON-ZERO, AND NOT NAN'S +satan: + fmov.x (%a0),%fp0 # LOAD INPUT + + mov.l (%a0),%d1 + mov.w 4(%a0),%d1 + fmov.x %fp0,X(%a6) + and.l &0x7FFFFFFF,%d1 + + cmp.l %d1,&0x3FFB8000 # |X| >= 1/16? + bge.b ATANOK1 + bra.w ATANSM + +ATANOK1: + cmp.l %d1,&0x4002FFFF # |X| < 16 ? + ble.b ATANMAIN + bra.w ATANBIG + +#--THE MOST LIKELY CASE, |X| IN [1/16, 16). WE USE TABLE TECHNIQUE +#--THE IDEA IS ATAN(X) = ATAN(F) + ATAN( [X-F] / [1+XF] ). +#--SO IF F IS CHOSEN TO BE CLOSE TO X AND ATAN(F) IS STORED IN +#--A TABLE, ALL WE NEED IS TO APPROXIMATE ATAN(U) WHERE +#--U = (X-F)/(1+XF) IS SMALL (REMEMBER F IS CLOSE TO X). IT IS +#--TRUE THAT A DIVIDE IS NOW NEEDED, BUT THE APPROXIMATION FOR +#--ATAN(U) IS A VERY SHORT POLYNOMIAL AND THE INDEXING TO +#--FETCH F AND SAVING OF REGISTERS CAN BE ALL HIDED UNDER THE +#--DIVIDE. IN THE END THIS METHOD IS MUCH FASTER THAN A TRADITIONAL +#--ONE. NOTE ALSO THAT THE TRADITIONAL SCHEME THAT APPROXIMATE +#--ATAN(X) DIRECTLY WILL NEED TO USE A RATIONAL APPROXIMATION +#--(DIVISION NEEDED) ANYWAY BECAUSE A POLYNOMIAL APPROXIMATION +#--WILL INVOLVE A VERY LONG POLYNOMIAL. + +#--NOW WE SEE X AS +-2^K * 1.BBBBBBB....B <- 1. + 63 BITS +#--WE CHOSE F TO BE +-2^K * 1.BBBB1 +#--THAT IS IT MATCHES THE EXPONENT AND FIRST 5 BITS OF X, THE +#--SIXTH BITS IS SET TO BE 1. SINCE K = -4, -3, ..., 3, THERE +#--ARE ONLY 8 TIMES 16 = 2^7 = 128 |F|'S. SINCE ATAN(-|F|) IS +#-- -ATAN(|F|), WE NEED TO STORE ONLY ATAN(|F|). + +ATANMAIN: + + and.l &0xF8000000,XFRAC(%a6) # FIRST 5 BITS + or.l &0x04000000,XFRAC(%a6) # SET 6-TH BIT TO 1 + mov.l &0x00000000,XFRACLO(%a6) # LOCATION OF X IS NOW F + + fmov.x %fp0,%fp1 # FP1 IS X + fmul.x X(%a6),%fp1 # FP1 IS X*F, NOTE THAT X*F > 0 + fsub.x X(%a6),%fp0 # FP0 IS X-F + fadd.s &0x3F800000,%fp1 # FP1 IS 1 + X*F + fdiv.x %fp1,%fp0 # FP0 IS U = (X-F)/(1+X*F) + +#--WHILE THE DIVISION IS TAKING ITS TIME, WE FETCH ATAN(|F|) +#--CREATE ATAN(F) AND STORE IT IN ATANF, AND +#--SAVE REGISTERS FP2. + + mov.l %d2,-(%sp) # SAVE d2 TEMPORARILY + mov.l %d1,%d2 # THE EXP AND 16 BITS OF X + and.l &0x00007800,%d1 # 4 VARYING BITS OF F'S FRACTION + and.l &0x7FFF0000,%d2 # EXPONENT OF F + sub.l &0x3FFB0000,%d2 # K+4 + asr.l &1,%d2 + add.l %d2,%d1 # THE 7 BITS IDENTIFYING F + asr.l &7,%d1 # INDEX INTO TBL OF ATAN(|F|) + lea ATANTBL(%pc),%a1 + add.l %d1,%a1 # ADDRESS OF ATAN(|F|) + mov.l (%a1)+,ATANF(%a6) + mov.l (%a1)+,ATANFHI(%a6) + mov.l (%a1)+,ATANFLO(%a6) # ATANF IS NOW ATAN(|F|) + mov.l X(%a6),%d1 # LOAD SIGN AND EXPO. AGAIN + and.l &0x80000000,%d1 # SIGN(F) + or.l %d1,ATANF(%a6) # ATANF IS NOW SIGN(F)*ATAN(|F|) + mov.l (%sp)+,%d2 # RESTORE d2 + +#--THAT'S ALL I HAVE TO DO FOR NOW, +#--BUT ALAS, THE DIVIDE IS STILL CRANKING! + +#--U IN FP0, WE ARE NOW READY TO COMPUTE ATAN(U) AS +#--U + A1*U*V*(A2 + V*(A3 + V)), V = U*U +#--THE POLYNOMIAL MAY LOOK STRANGE, BUT IS NEVERTHELESS CORRECT. +#--THE NATURAL FORM IS U + U*V*(A1 + V*(A2 + V*A3)) +#--WHAT WE HAVE HERE IS MERELY A1 = A3, A2 = A1/A3, A3 = A2/A3. +#--THE REASON FOR THIS REARRANGEMENT IS TO MAKE THE INDEPENDENT +#--PARTS A1*U*V AND (A2 + ... STUFF) MORE LOAD-BALANCED + + fmovm.x &0x04,-(%sp) # save fp2 + + fmov.x %fp0,%fp1 + fmul.x %fp1,%fp1 + fmov.d ATANA3(%pc),%fp2 + fadd.x %fp1,%fp2 # A3+V + fmul.x %fp1,%fp2 # V*(A3+V) + fmul.x %fp0,%fp1 # U*V + fadd.d ATANA2(%pc),%fp2 # A2+V*(A3+V) + fmul.d ATANA1(%pc),%fp1 # A1*U*V + fmul.x %fp2,%fp1 # A1*U*V*(A2+V*(A3+V)) + fadd.x %fp1,%fp0 # ATAN(U), FP1 RELEASED + + fmovm.x (%sp)+,&0x20 # restore fp2 + + fmov.l %d0,%fpcr # restore users rnd mode,prec + fadd.x ATANF(%a6),%fp0 # ATAN(X) + bra t_inx2 + +ATANBORS: +#--|X| IS IN d0 IN COMPACT FORM. FP1, d0 SAVED. +#--FP0 IS X AND |X| <= 1/16 OR |X| >= 16. + cmp.l %d1,&0x3FFF8000 + bgt.w ATANBIG # I.E. |X| >= 16 + +ATANSM: +#--|X| <= 1/16 +#--IF |X| < 2^(-40), RETURN X AS ANSWER. OTHERWISE, APPROXIMATE +#--ATAN(X) BY X + X*Y*(B1+Y*(B2+Y*(B3+Y*(B4+Y*(B5+Y*B6))))) +#--WHICH IS X + X*Y*( [B1+Z*(B3+Z*B5)] + [Y*(B2+Z*(B4+Z*B6)] ) +#--WHERE Y = X*X, AND Z = Y*Y. + + cmp.l %d1,&0x3FD78000 + blt.w ATANTINY + +#--COMPUTE POLYNOMIAL + fmovm.x &0x0c,-(%sp) # save fp2/fp3 + + fmul.x %fp0,%fp0 # FPO IS Y = X*X + + fmov.x %fp0,%fp1 + fmul.x %fp1,%fp1 # FP1 IS Z = Y*Y + + fmov.d ATANB6(%pc),%fp2 + fmov.d ATANB5(%pc),%fp3 + + fmul.x %fp1,%fp2 # Z*B6 + fmul.x %fp1,%fp3 # Z*B5 + + fadd.d ATANB4(%pc),%fp2 # B4+Z*B6 + fadd.d ATANB3(%pc),%fp3 # B3+Z*B5 + + fmul.x %fp1,%fp2 # Z*(B4+Z*B6) + fmul.x %fp3,%fp1 # Z*(B3+Z*B5) + + fadd.d ATANB2(%pc),%fp2 # B2+Z*(B4+Z*B6) + fadd.d ATANB1(%pc),%fp1 # B1+Z*(B3+Z*B5) + + fmul.x %fp0,%fp2 # Y*(B2+Z*(B4+Z*B6)) + fmul.x X(%a6),%fp0 # X*Y + + fadd.x %fp2,%fp1 # [B1+Z*(B3+Z*B5)]+[Y*(B2+Z*(B4+Z*B6))] + + fmul.x %fp1,%fp0 # X*Y*([B1+Z*(B3+Z*B5)]+[Y*(B2+Z*(B4+Z*B6))]) + + fmovm.x (%sp)+,&0x30 # restore fp2/fp3 + + fmov.l %d0,%fpcr # restore users rnd mode,prec + fadd.x X(%a6),%fp0 + bra t_inx2 + +ATANTINY: +#--|X| < 2^(-40), ATAN(X) = X + + fmov.l %d0,%fpcr # restore users rnd mode,prec + mov.b &FMOV_OP,%d1 # last inst is MOVE + fmov.x X(%a6),%fp0 # last inst - possible exception set + + bra t_catch + +ATANBIG: +#--IF |X| > 2^(100), RETURN SIGN(X)*(PI/2 - TINY). OTHERWISE, +#--RETURN SIGN(X)*PI/2 + ATAN(-1/X). + cmp.l %d1,&0x40638000 + bgt.w ATANHUGE + +#--APPROXIMATE ATAN(-1/X) BY +#--X'+X'*Y*(C1+Y*(C2+Y*(C3+Y*(C4+Y*C5)))), X' = -1/X, Y = X'*X' +#--THIS CAN BE RE-WRITTEN AS +#--X'+X'*Y*( [C1+Z*(C3+Z*C5)] + [Y*(C2+Z*C4)] ), Z = Y*Y. + + fmovm.x &0x0c,-(%sp) # save fp2/fp3 + + fmov.s &0xBF800000,%fp1 # LOAD -1 + fdiv.x %fp0,%fp1 # FP1 IS -1/X + +#--DIVIDE IS STILL CRANKING + + fmov.x %fp1,%fp0 # FP0 IS X' + fmul.x %fp0,%fp0 # FP0 IS Y = X'*X' + fmov.x %fp1,X(%a6) # X IS REALLY X' + + fmov.x %fp0,%fp1 + fmul.x %fp1,%fp1 # FP1 IS Z = Y*Y + + fmov.d ATANC5(%pc),%fp3 + fmov.d ATANC4(%pc),%fp2 + + fmul.x %fp1,%fp3 # Z*C5 + fmul.x %fp1,%fp2 # Z*B4 + + fadd.d ATANC3(%pc),%fp3 # C3+Z*C5 + fadd.d ATANC2(%pc),%fp2 # C2+Z*C4 + + fmul.x %fp3,%fp1 # Z*(C3+Z*C5), FP3 RELEASED + fmul.x %fp0,%fp2 # Y*(C2+Z*C4) + + fadd.d ATANC1(%pc),%fp1 # C1+Z*(C3+Z*C5) + fmul.x X(%a6),%fp0 # X'*Y + + fadd.x %fp2,%fp1 # [Y*(C2+Z*C4)]+[C1+Z*(C3+Z*C5)] + + fmul.x %fp1,%fp0 # X'*Y*([B1+Z*(B3+Z*B5)] +# ... +[Y*(B2+Z*(B4+Z*B6))]) + fadd.x X(%a6),%fp0 + + fmovm.x (%sp)+,&0x30 # restore fp2/fp3 + + fmov.l %d0,%fpcr # restore users rnd mode,prec + tst.b (%a0) + bpl.b pos_big + +neg_big: + fadd.x NPIBY2(%pc),%fp0 + bra t_minx2 + +pos_big: + fadd.x PPIBY2(%pc),%fp0 + bra t_pinx2 + +ATANHUGE: +#--RETURN SIGN(X)*(PIBY2 - TINY) = SIGN(X)*PIBY2 - SIGN(X)*TINY + tst.b (%a0) + bpl.b pos_huge + +neg_huge: + fmov.x NPIBY2(%pc),%fp0 + fmov.l %d0,%fpcr + fadd.x PTINY(%pc),%fp0 + bra t_minx2 + +pos_huge: + fmov.x PPIBY2(%pc),%fp0 + fmov.l %d0,%fpcr + fadd.x NTINY(%pc),%fp0 + bra t_pinx2 + + global satand +#--ENTRY POINT FOR ATAN(X) FOR DENORMALIZED ARGUMENT +satand: + bra t_extdnrm + +######################################################################### +# sasin(): computes the inverse sine of a normalized input # +# sasind(): computes the inverse sine of a denormalized input # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input # +# d0 = round precision,mode # +# # +# OUTPUT ************************************************************** # +# fp0 = arcsin(X) # +# # +# ACCURACY and MONOTONICITY ******************************************* # +# The returned result is within 3 ulps in 64 significant bit, # +# i.e. within 0.5001 ulp to 53 bits if the result is subsequently # +# rounded to double precision. The result is provably monotonic # +# in double precision. # +# # +# ALGORITHM *********************************************************** # +# # +# ASIN # +# 1. If |X| >= 1, go to 3. # +# # +# 2. (|X| < 1) Calculate asin(X) by # +# z := sqrt( [1-X][1+X] ) # +# asin(X) = atan( x / z ). # +# Exit. # +# # +# 3. If |X| > 1, go to 5. # +# # +# 4. (|X| = 1) sgn := sign(X), return asin(X) := sgn * Pi/2. Exit.# +# # +# 5. (|X| > 1) Generate an invalid operation by 0 * infinity. # +# Exit. # +# # +######################################################################### + + global sasin +sasin: + fmov.x (%a0),%fp0 # LOAD INPUT + + mov.l (%a0),%d1 + mov.w 4(%a0),%d1 + and.l &0x7FFFFFFF,%d1 + cmp.l %d1,&0x3FFF8000 + bge.b ASINBIG + +# This catch is added here for the '060 QSP. Originally, the call to +# satan() would handle this case by causing the exception which would +# not be caught until gen_except(). Now, with the exceptions being +# detected inside of satan(), the exception would have been handled there +# instead of inside sasin() as expected. + cmp.l %d1,&0x3FD78000 + blt.w ASINTINY + +#--THIS IS THE USUAL CASE, |X| < 1 +#--ASIN(X) = ATAN( X / SQRT( (1-X)(1+X) ) ) + +ASINMAIN: + fmov.s &0x3F800000,%fp1 + fsub.x %fp0,%fp1 # 1-X + fmovm.x &0x4,-(%sp) # {fp2} + fmov.s &0x3F800000,%fp2 + fadd.x %fp0,%fp2 # 1+X + fmul.x %fp2,%fp1 # (1+X)(1-X) + fmovm.x (%sp)+,&0x20 # {fp2} + fsqrt.x %fp1 # SQRT([1-X][1+X]) + fdiv.x %fp1,%fp0 # X/SQRT([1-X][1+X]) + fmovm.x &0x01,-(%sp) # save X/SQRT(...) + lea (%sp),%a0 # pass ptr to X/SQRT(...) + bsr satan + add.l &0xc,%sp # clear X/SQRT(...) from stack + bra t_inx2 + +ASINBIG: + fabs.x %fp0 # |X| + fcmp.s %fp0,&0x3F800000 + fbgt t_operr # cause an operr exception + +#--|X| = 1, ASIN(X) = +- PI/2. +ASINONE: + fmov.x PIBY2(%pc),%fp0 + mov.l (%a0),%d1 + and.l &0x80000000,%d1 # SIGN BIT OF X + or.l &0x3F800000,%d1 # +-1 IN SGL FORMAT + mov.l %d1,-(%sp) # push SIGN(X) IN SGL-FMT + fmov.l %d0,%fpcr + fmul.s (%sp)+,%fp0 + bra t_inx2 + +#--|X| < 2^(-40), ATAN(X) = X +ASINTINY: + fmov.l %d0,%fpcr # restore users rnd mode,prec + mov.b &FMOV_OP,%d1 # last inst is MOVE + fmov.x (%a0),%fp0 # last inst - possible exception + bra t_catch + + global sasind +#--ASIN(X) = X FOR DENORMALIZED X +sasind: + bra t_extdnrm + +######################################################################### +# sacos(): computes the inverse cosine of a normalized input # +# sacosd(): computes the inverse cosine of a denormalized input # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input # +# d0 = round precision,mode # +# # +# OUTPUT ************************************************************** # +# fp0 = arccos(X) # +# # +# ACCURACY and MONOTONICITY ******************************************* # +# The returned result is within 3 ulps in 64 significant bit, # +# i.e. within 0.5001 ulp to 53 bits if the result is subsequently # +# rounded to double precision. The result is provably monotonic # +# in double precision. # +# # +# ALGORITHM *********************************************************** # +# # +# ACOS # +# 1. If |X| >= 1, go to 3. # +# # +# 2. (|X| < 1) Calculate acos(X) by # +# z := (1-X) / (1+X) # +# acos(X) = 2 * atan( sqrt(z) ). # +# Exit. # +# # +# 3. If |X| > 1, go to 5. # +# # +# 4. (|X| = 1) If X > 0, return 0. Otherwise, return Pi. Exit. # +# # +# 5. (|X| > 1) Generate an invalid operation by 0 * infinity. # +# Exit. # +# # +######################################################################### + + global sacos +sacos: + fmov.x (%a0),%fp0 # LOAD INPUT + + mov.l (%a0),%d1 # pack exp w/ upper 16 fraction + mov.w 4(%a0),%d1 + and.l &0x7FFFFFFF,%d1 + cmp.l %d1,&0x3FFF8000 + bge.b ACOSBIG + +#--THIS IS THE USUAL CASE, |X| < 1 +#--ACOS(X) = 2 * ATAN( SQRT( (1-X)/(1+X) ) ) + +ACOSMAIN: + fmov.s &0x3F800000,%fp1 + fadd.x %fp0,%fp1 # 1+X + fneg.x %fp0 # -X + fadd.s &0x3F800000,%fp0 # 1-X + fdiv.x %fp1,%fp0 # (1-X)/(1+X) + fsqrt.x %fp0 # SQRT((1-X)/(1+X)) + mov.l %d0,-(%sp) # save original users fpcr + clr.l %d0 + fmovm.x &0x01,-(%sp) # save SQRT(...) to stack + lea (%sp),%a0 # pass ptr to sqrt + bsr satan # ATAN(SQRT([1-X]/[1+X])) + add.l &0xc,%sp # clear SQRT(...) from stack + + fmov.l (%sp)+,%fpcr # restore users round prec,mode + fadd.x %fp0,%fp0 # 2 * ATAN( STUFF ) + bra t_pinx2 + +ACOSBIG: + fabs.x %fp0 + fcmp.s %fp0,&0x3F800000 + fbgt t_operr # cause an operr exception + +#--|X| = 1, ACOS(X) = 0 OR PI + tst.b (%a0) # is X positive or negative? + bpl.b ACOSP1 + +#--X = -1 +#Returns PI and inexact exception +ACOSM1: + fmov.x PI(%pc),%fp0 # load PI + fmov.l %d0,%fpcr # load round mode,prec + fadd.s &0x00800000,%fp0 # add a small value + bra t_pinx2 + +ACOSP1: + bra ld_pzero # answer is positive zero + + global sacosd +#--ACOS(X) = PI/2 FOR DENORMALIZED X +sacosd: + fmov.l %d0,%fpcr # load user's rnd mode/prec + fmov.x PIBY2(%pc),%fp0 + bra t_pinx2 + +######################################################################### +# setox(): computes the exponential for a normalized input # +# setoxd(): computes the exponential for a denormalized input # +# setoxm1(): computes the exponential minus 1 for a normalized input # +# setoxm1d(): computes the exponential minus 1 for a denormalized input # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input # +# d0 = round precision,mode # +# # +# OUTPUT ************************************************************** # +# fp0 = exp(X) or exp(X)-1 # +# # +# ACCURACY and MONOTONICITY ******************************************* # +# The returned result is within 0.85 ulps in 64 significant bit, # +# i.e. within 0.5001 ulp to 53 bits if the result is subsequently # +# rounded to double precision. The result is provably monotonic # +# in double precision. # +# # +# ALGORITHM and IMPLEMENTATION **************************************** # +# # +# setoxd # +# ------ # +# Step 1. Set ans := 1.0 # +# # +# Step 2. Return ans := ans + sign(X)*2^(-126). Exit. # +# Notes: This will always generate one exception -- inexact. # +# # +# # +# setox # +# ----- # +# # +# Step 1. Filter out extreme cases of input argument. # +# 1.1 If |X| >= 2^(-65), go to Step 1.3. # +# 1.2 Go to Step 7. # +# 1.3 If |X| < 16380 log(2), go to Step 2. # +# 1.4 Go to Step 8. # +# Notes: The usual case should take the branches 1.1 -> 1.3 -> 2.# +# To avoid the use of floating-point comparisons, a # +# compact representation of |X| is used. This format is a # +# 32-bit integer, the upper (more significant) 16 bits # +# are the sign and biased exponent field of |X|; the # +# lower 16 bits are the 16 most significant fraction # +# (including the explicit bit) bits of |X|. Consequently, # +# the comparisons in Steps 1.1 and 1.3 can be performed # +# by integer comparison. Note also that the constant # +# 16380 log(2) used in Step 1.3 is also in the compact # +# form. Thus taking the branch to Step 2 guarantees # +# |X| < 16380 log(2). There is no harm to have a small # +# number of cases where |X| is less than, but close to, # +# 16380 log(2) and the branch to Step 9 is taken. # +# # +# Step 2. Calculate N = round-to-nearest-int( X * 64/log2 ). # +# 2.1 Set AdjFlag := 0 (indicates the branch 1.3 -> 2 # +# was taken) # +# 2.2 N := round-to-nearest-integer( X * 64/log2 ). # +# 2.3 Calculate J = N mod 64; so J = 0,1,2,..., # +# or 63. # +# 2.4 Calculate M = (N - J)/64; so N = 64M + J. # +# 2.5 Calculate the address of the stored value of # +# 2^(J/64). # +# 2.6 Create the value Scale = 2^M. # +# Notes: The calculation in 2.2 is really performed by # +# Z := X * constant # +# N := round-to-nearest-integer(Z) # +# where # +# constant := single-precision( 64/log 2 ). # +# # +# Using a single-precision constant avoids memory # +# access. Another effect of using a single-precision # +# "constant" is that the calculated value Z is # +# # +# Z = X*(64/log2)*(1+eps), |eps| <= 2^(-24). # +# # +# This error has to be considered later in Steps 3 and 4. # +# # +# Step 3. Calculate X - N*log2/64. # +# 3.1 R := X + N*L1, # +# where L1 := single-precision(-log2/64). # +# 3.2 R := R + N*L2, # +# L2 := extended-precision(-log2/64 - L1).# +# Notes: a) The way L1 and L2 are chosen ensures L1+L2 # +# approximate the value -log2/64 to 88 bits of accuracy. # +# b) N*L1 is exact because N is no longer than 22 bits # +# and L1 is no longer than 24 bits. # +# c) The calculation X+N*L1 is also exact due to # +# cancellation. Thus, R is practically X+N(L1+L2) to full # +# 64 bits. # +# d) It is important to estimate how large can |R| be # +# after Step 3.2. # +# # +# N = rnd-to-int( X*64/log2 (1+eps) ), |eps|<=2^(-24) # +# X*64/log2 (1+eps) = N + f, |f| <= 0.5 # +# X*64/log2 - N = f - eps*X 64/log2 # +# X - N*log2/64 = f*log2/64 - eps*X # +# # +# # +# Now |X| <= 16446 log2, thus # +# # +# |X - N*log2/64| <= (0.5 + 16446/2^(18))*log2/64 # +# <= 0.57 log2/64. # +# This bound will be used in Step 4. # +# # +# Step 4. Approximate exp(R)-1 by a polynomial # +# p = R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*A5)))) # +# Notes: a) In order to reduce memory access, the coefficients # +# are made as "short" as possible: A1 (which is 1/2), A4 # +# and A5 are single precision; A2 and A3 are double # +# precision. # +# b) Even with the restrictions above, # +# |p - (exp(R)-1)| < 2^(-68.8) for all |R| <= 0.0062. # +# Note that 0.0062 is slightly bigger than 0.57 log2/64. # +# c) To fully utilize the pipeline, p is separated into # +# two independent pieces of roughly equal complexities # +# p = [ R + R*S*(A2 + S*A4) ] + # +# [ S*(A1 + S*(A3 + S*A5)) ] # +# where S = R*R. # +# # +# Step 5. Compute 2^(J/64)*exp(R) = 2^(J/64)*(1+p) by # +# ans := T + ( T*p + t) # +# where T and t are the stored values for 2^(J/64). # +# Notes: 2^(J/64) is stored as T and t where T+t approximates # +# 2^(J/64) to roughly 85 bits; T is in extended precision # +# and t is in single precision. Note also that T is # +# rounded to 62 bits so that the last two bits of T are # +# zero. The reason for such a special form is that T-1, # +# T-2, and T-8 will all be exact --- a property that will # +# give much more accurate computation of the function # +# EXPM1. # +# # +# Step 6. Reconstruction of exp(X) # +# exp(X) = 2^M * 2^(J/64) * exp(R). # +# 6.1 If AdjFlag = 0, go to 6.3 # +# 6.2 ans := ans * AdjScale # +# 6.3 Restore the user FPCR # +# 6.4 Return ans := ans * Scale. Exit. # +# Notes: If AdjFlag = 0, we have X = Mlog2 + Jlog2/64 + R, # +# |M| <= 16380, and Scale = 2^M. Moreover, exp(X) will # +# neither overflow nor underflow. If AdjFlag = 1, that # +# means that # +# X = (M1+M)log2 + Jlog2/64 + R, |M1+M| >= 16380. # +# Hence, exp(X) may overflow or underflow or neither. # +# When that is the case, AdjScale = 2^(M1) where M1 is # +# approximately M. Thus 6.2 will never cause # +# over/underflow. Possible exception in 6.4 is overflow # +# or underflow. The inexact exception is not generated in # +# 6.4. Although one can argue that the inexact flag # +# should always be raised, to simulate that exception # +# cost to much than the flag is worth in practical uses. # +# # +# Step 7. Return 1 + X. # +# 7.1 ans := X # +# 7.2 Restore user FPCR. # +# 7.3 Return ans := 1 + ans. Exit # +# Notes: For non-zero X, the inexact exception will always be # +# raised by 7.3. That is the only exception raised by 7.3.# +# Note also that we use the FMOVEM instruction to move X # +# in Step 7.1 to avoid unnecessary trapping. (Although # +# the FMOVEM may not seem relevant since X is normalized, # +# the precaution will be useful in the library version of # +# this code where the separate entry for denormalized # +# inputs will be done away with.) # +# # +# Step 8. Handle exp(X) where |X| >= 16380log2. # +# 8.1 If |X| > 16480 log2, go to Step 9. # +# (mimic 2.2 - 2.6) # +# 8.2 N := round-to-integer( X * 64/log2 ) # +# 8.3 Calculate J = N mod 64, J = 0,1,...,63 # +# 8.4 K := (N-J)/64, M1 := truncate(K/2), M = K-M1, # +# AdjFlag := 1. # +# 8.5 Calculate the address of the stored value # +# 2^(J/64). # +# 8.6 Create the values Scale = 2^M, AdjScale = 2^M1. # +# 8.7 Go to Step 3. # +# Notes: Refer to notes for 2.2 - 2.6. # +# # +# Step 9. Handle exp(X), |X| > 16480 log2. # +# 9.1 If X < 0, go to 9.3 # +# 9.2 ans := Huge, go to 9.4 # +# 9.3 ans := Tiny. # +# 9.4 Restore user FPCR. # +# 9.5 Return ans := ans * ans. Exit. # +# Notes: Exp(X) will surely overflow or underflow, depending on # +# X's sign. "Huge" and "Tiny" are respectively large/tiny # +# extended-precision numbers whose square over/underflow # +# with an inexact result. Thus, 9.5 always raises the # +# inexact together with either overflow or underflow. # +# # +# setoxm1d # +# -------- # +# # +# Step 1. Set ans := 0 # +# # +# Step 2. Return ans := X + ans. Exit. # +# Notes: This will return X with the appropriate rounding # +# precision prescribed by the user FPCR. # +# # +# setoxm1 # +# ------- # +# # +# Step 1. Check |X| # +# 1.1 If |X| >= 1/4, go to Step 1.3. # +# 1.2 Go to Step 7. # +# 1.3 If |X| < 70 log(2), go to Step 2. # +# 1.4 Go to Step 10. # +# Notes: The usual case should take the branches 1.1 -> 1.3 -> 2.# +# However, it is conceivable |X| can be small very often # +# because EXPM1 is intended to evaluate exp(X)-1 # +# accurately when |X| is small. For further details on # +# the comparisons, see the notes on Step 1 of setox. # +# # +# Step 2. Calculate N = round-to-nearest-int( X * 64/log2 ). # +# 2.1 N := round-to-nearest-integer( X * 64/log2 ). # +# 2.2 Calculate J = N mod 64; so J = 0,1,2,..., # +# or 63. # +# 2.3 Calculate M = (N - J)/64; so N = 64M + J. # +# 2.4 Calculate the address of the stored value of # +# 2^(J/64). # +# 2.5 Create the values Sc = 2^M and # +# OnebySc := -2^(-M). # +# Notes: See the notes on Step 2 of setox. # +# # +# Step 3. Calculate X - N*log2/64. # +# 3.1 R := X + N*L1, # +# where L1 := single-precision(-log2/64). # +# 3.2 R := R + N*L2, # +# L2 := extended-precision(-log2/64 - L1).# +# Notes: Applying the analysis of Step 3 of setox in this case # +# shows that |R| <= 0.0055 (note that |X| <= 70 log2 in # +# this case). # +# # +# Step 4. Approximate exp(R)-1 by a polynomial # +# p = R+R*R*(A1+R*(A2+R*(A3+R*(A4+R*(A5+R*A6))))) # +# Notes: a) In order to reduce memory access, the coefficients # +# are made as "short" as possible: A1 (which is 1/2), A5 # +# and A6 are single precision; A2, A3 and A4 are double # +# precision. # +# b) Even with the restriction above, # +# |p - (exp(R)-1)| < |R| * 2^(-72.7) # +# for all |R| <= 0.0055. # +# c) To fully utilize the pipeline, p is separated into # +# two independent pieces of roughly equal complexity # +# p = [ R*S*(A2 + S*(A4 + S*A6)) ] + # +# [ R + S*(A1 + S*(A3 + S*A5)) ] # +# where S = R*R. # +# # +# Step 5. Compute 2^(J/64)*p by # +# p := T*p # +# where T and t are the stored values for 2^(J/64). # +# Notes: 2^(J/64) is stored as T and t where T+t approximates # +# 2^(J/64) to roughly 85 bits; T is in extended precision # +# and t is in single precision. Note also that T is # +# rounded to 62 bits so that the last two bits of T are # +# zero. The reason for such a special form is that T-1, # +# T-2, and T-8 will all be exact --- a property that will # +# be exploited in Step 6 below. The total relative error # +# in p is no bigger than 2^(-67.7) compared to the final # +# result. # +# # +# Step 6. Reconstruction of exp(X)-1 # +# exp(X)-1 = 2^M * ( 2^(J/64) + p - 2^(-M) ). # +# 6.1 If M <= 63, go to Step 6.3. # +# 6.2 ans := T + (p + (t + OnebySc)). Go to 6.6 # +# 6.3 If M >= -3, go to 6.5. # +# 6.4 ans := (T + (p + t)) + OnebySc. Go to 6.6 # +# 6.5 ans := (T + OnebySc) + (p + t). # +# 6.6 Restore user FPCR. # +# 6.7 Return ans := Sc * ans. Exit. # +# Notes: The various arrangements of the expressions give # +# accurate evaluations. # +# # +# Step 7. exp(X)-1 for |X| < 1/4. # +# 7.1 If |X| >= 2^(-65), go to Step 9. # +# 7.2 Go to Step 8. # +# # +# Step 8. Calculate exp(X)-1, |X| < 2^(-65). # +# 8.1 If |X| < 2^(-16312), goto 8.3 # +# 8.2 Restore FPCR; return ans := X - 2^(-16382). # +# Exit. # +# 8.3 X := X * 2^(140). # +# 8.4 Restore FPCR; ans := ans - 2^(-16382). # +# Return ans := ans*2^(140). Exit # +# Notes: The idea is to return "X - tiny" under the user # +# precision and rounding modes. To avoid unnecessary # +# inefficiency, we stay away from denormalized numbers # +# the best we can. For |X| >= 2^(-16312), the # +# straightforward 8.2 generates the inexact exception as # +# the case warrants. # +# # +# Step 9. Calculate exp(X)-1, |X| < 1/4, by a polynomial # +# p = X + X*X*(B1 + X*(B2 + ... + X*B12)) # +# Notes: a) In order to reduce memory access, the coefficients # +# are made as "short" as possible: B1 (which is 1/2), B9 # +# to B12 are single precision; B3 to B8 are double # +# precision; and B2 is double extended. # +# b) Even with the restriction above, # +# |p - (exp(X)-1)| < |X| 2^(-70.6) # +# for all |X| <= 0.251. # +# Note that 0.251 is slightly bigger than 1/4. # +# c) To fully preserve accuracy, the polynomial is # +# computed as # +# X + ( S*B1 + Q ) where S = X*X and # +# Q = X*S*(B2 + X*(B3 + ... + X*B12)) # +# d) To fully utilize the pipeline, Q is separated into # +# two independent pieces of roughly equal complexity # +# Q = [ X*S*(B2 + S*(B4 + ... + S*B12)) ] + # +# [ S*S*(B3 + S*(B5 + ... + S*B11)) ] # +# # +# Step 10. Calculate exp(X)-1 for |X| >= 70 log 2. # +# 10.1 If X >= 70log2 , exp(X) - 1 = exp(X) for all # +# practical purposes. Therefore, go to Step 1 of setox. # +# 10.2 If X <= -70log2, exp(X) - 1 = -1 for all practical # +# purposes. # +# ans := -1 # +# Restore user FPCR # +# Return ans := ans + 2^(-126). Exit. # +# Notes: 10.2 will always create an inexact and return -1 + tiny # +# in the user rounding precision and mode. # +# # +######################################################################### + +L2: long 0x3FDC0000,0x82E30865,0x4361C4C6,0x00000000 + +EEXPA3: long 0x3FA55555,0x55554CC1 +EEXPA2: long 0x3FC55555,0x55554A54 + +EM1A4: long 0x3F811111,0x11174385 +EM1A3: long 0x3FA55555,0x55554F5A + +EM1A2: long 0x3FC55555,0x55555555,0x00000000,0x00000000 + +EM1B8: long 0x3EC71DE3,0xA5774682 +EM1B7: long 0x3EFA01A0,0x19D7CB68 + +EM1B6: long 0x3F2A01A0,0x1A019DF3 +EM1B5: long 0x3F56C16C,0x16C170E2 + +EM1B4: long 0x3F811111,0x11111111 +EM1B3: long 0x3FA55555,0x55555555 + +EM1B2: long 0x3FFC0000,0xAAAAAAAA,0xAAAAAAAB + long 0x00000000 + +TWO140: long 0x48B00000,0x00000000 +TWON140: + long 0x37300000,0x00000000 + +EEXPTBL: + long 0x3FFF0000,0x80000000,0x00000000,0x00000000 + long 0x3FFF0000,0x8164D1F3,0xBC030774,0x9F841A9B + long 0x3FFF0000,0x82CD8698,0xAC2BA1D8,0x9FC1D5B9 + long 0x3FFF0000,0x843A28C3,0xACDE4048,0xA0728369 + long 0x3FFF0000,0x85AAC367,0xCC487B14,0x1FC5C95C + long 0x3FFF0000,0x871F6196,0x9E8D1010,0x1EE85C9F + long 0x3FFF0000,0x88980E80,0x92DA8528,0x9FA20729 + long 0x3FFF0000,0x8A14D575,0x496EFD9C,0xA07BF9AF + long 0x3FFF0000,0x8B95C1E3,0xEA8BD6E8,0xA0020DCF + long 0x3FFF0000,0x8D1ADF5B,0x7E5BA9E4,0x205A63DA + long 0x3FFF0000,0x8EA4398B,0x45CD53C0,0x1EB70051 + long 0x3FFF0000,0x9031DC43,0x1466B1DC,0x1F6EB029 + long 0x3FFF0000,0x91C3D373,0xAB11C338,0xA0781494 + long 0x3FFF0000,0x935A2B2F,0x13E6E92C,0x9EB319B0 + long 0x3FFF0000,0x94F4EFA8,0xFEF70960,0x2017457D + long 0x3FFF0000,0x96942D37,0x20185A00,0x1F11D537 + long 0x3FFF0000,0x9837F051,0x8DB8A970,0x9FB952DD + long 0x3FFF0000,0x99E04593,0x20B7FA64,0x1FE43087 + long 0x3FFF0000,0x9B8D39B9,0xD54E5538,0x1FA2A818 + long 0x3FFF0000,0x9D3ED9A7,0x2CFFB750,0x1FDE494D + long 0x3FFF0000,0x9EF53260,0x91A111AC,0x20504890 + long 0x3FFF0000,0xA0B0510F,0xB9714FC4,0xA073691C + long 0x3FFF0000,0xA2704303,0x0C496818,0x1F9B7A05 + long 0x3FFF0000,0xA43515AE,0x09E680A0,0xA0797126 + long 0x3FFF0000,0xA5FED6A9,0xB15138EC,0xA071A140 + long 0x3FFF0000,0xA7CD93B4,0xE9653568,0x204F62DA + long 0x3FFF0000,0xA9A15AB4,0xEA7C0EF8,0x1F283C4A + long 0x3FFF0000,0xAB7A39B5,0xA93ED338,0x9F9A7FDC + long 0x3FFF0000,0xAD583EEA,0x42A14AC8,0xA05B3FAC + long 0x3FFF0000,0xAF3B78AD,0x690A4374,0x1FDF2610 + long 0x3FFF0000,0xB123F581,0xD2AC2590,0x9F705F90 + long 0x3FFF0000,0xB311C412,0xA9112488,0x201F678A + long 0x3FFF0000,0xB504F333,0xF9DE6484,0x1F32FB13 + long 0x3FFF0000,0xB6FD91E3,0x28D17790,0x20038B30 + long 0x3FFF0000,0xB8FBAF47,0x62FB9EE8,0x200DC3CC + long 0x3FFF0000,0xBAFF5AB2,0x133E45FC,0x9F8B2AE6 + long 0x3FFF0000,0xBD08A39F,0x580C36C0,0xA02BBF70 + long 0x3FFF0000,0xBF1799B6,0x7A731084,0xA00BF518 + long 0x3FFF0000,0xC12C4CCA,0x66709458,0xA041DD41 + long 0x3FFF0000,0xC346CCDA,0x24976408,0x9FDF137B + long 0x3FFF0000,0xC5672A11,0x5506DADC,0x201F1568 + long 0x3FFF0000,0xC78D74C8,0xABB9B15C,0x1FC13A2E + long 0x3FFF0000,0xC9B9BD86,0x6E2F27A4,0xA03F8F03 + long 0x3FFF0000,0xCBEC14FE,0xF2727C5C,0x1FF4907D + long 0x3FFF0000,0xCE248C15,0x1F8480E4,0x9E6E53E4 + long 0x3FFF0000,0xD06333DA,0xEF2B2594,0x1FD6D45C + long 0x3FFF0000,0xD2A81D91,0xF12AE45C,0xA076EDB9 + long 0x3FFF0000,0xD4F35AAB,0xCFEDFA20,0x9FA6DE21 + long 0x3FFF0000,0xD744FCCA,0xD69D6AF4,0x1EE69A2F + long 0x3FFF0000,0xD99D15C2,0x78AFD7B4,0x207F439F + long 0x3FFF0000,0xDBFBB797,0xDAF23754,0x201EC207 + long 0x3FFF0000,0xDE60F482,0x5E0E9124,0x9E8BE175 + long 0x3FFF0000,0xE0CCDEEC,0x2A94E110,0x20032C4B + long 0x3FFF0000,0xE33F8972,0xBE8A5A50,0x2004DFF5 + long 0x3FFF0000,0xE5B906E7,0x7C8348A8,0x1E72F47A + long 0x3FFF0000,0xE8396A50,0x3C4BDC68,0x1F722F22 + long 0x3FFF0000,0xEAC0C6E7,0xDD243930,0xA017E945 + long 0x3FFF0000,0xED4F301E,0xD9942B84,0x1F401A5B + long 0x3FFF0000,0xEFE4B99B,0xDCDAF5CC,0x9FB9A9E3 + long 0x3FFF0000,0xF281773C,0x59FFB138,0x20744C05 + long 0x3FFF0000,0xF5257D15,0x2486CC2C,0x1F773A19 + long 0x3FFF0000,0xF7D0DF73,0x0AD13BB8,0x1FFE90D5 + long 0x3FFF0000,0xFA83B2DB,0x722A033C,0xA041ED22 + long 0x3FFF0000,0xFD3E0C0C,0xF486C174,0x1F853F3A + + set ADJFLAG,L_SCR2 + set SCALE,FP_SCR0 + set ADJSCALE,FP_SCR1 + set SC,FP_SCR0 + set ONEBYSC,FP_SCR1 + + global setox +setox: +#--entry point for EXP(X), here X is finite, non-zero, and not NaN's + +#--Step 1. + mov.l (%a0),%d1 # load part of input X + and.l &0x7FFF0000,%d1 # biased expo. of X + cmp.l %d1,&0x3FBE0000 # 2^(-65) + bge.b EXPC1 # normal case + bra EXPSM + +EXPC1: +#--The case |X| >= 2^(-65) + mov.w 4(%a0),%d1 # expo. and partial sig. of |X| + cmp.l %d1,&0x400CB167 # 16380 log2 trunc. 16 bits + blt.b EXPMAIN # normal case + bra EEXPBIG + +EXPMAIN: +#--Step 2. +#--This is the normal branch: 2^(-65) <= |X| < 16380 log2. + fmov.x (%a0),%fp0 # load input from (a0) + + fmov.x %fp0,%fp1 + fmul.s &0x42B8AA3B,%fp0 # 64/log2 * X + fmovm.x &0xc,-(%sp) # save fp2 {%fp2/%fp3} + mov.l &0,ADJFLAG(%a6) + fmov.l %fp0,%d1 # N = int( X * 64/log2 ) + lea EEXPTBL(%pc),%a1 + fmov.l %d1,%fp0 # convert to floating-format + + mov.l %d1,L_SCR1(%a6) # save N temporarily + and.l &0x3F,%d1 # D0 is J = N mod 64 + lsl.l &4,%d1 + add.l %d1,%a1 # address of 2^(J/64) + mov.l L_SCR1(%a6),%d1 + asr.l &6,%d1 # D0 is M + add.w &0x3FFF,%d1 # biased expo. of 2^(M) + mov.w L2(%pc),L_SCR1(%a6) # prefetch L2, no need in CB + +EXPCONT1: +#--Step 3. +#--fp1,fp2 saved on the stack. fp0 is N, fp1 is X, +#--a0 points to 2^(J/64), D0 is biased expo. of 2^(M) + fmov.x %fp0,%fp2 + fmul.s &0xBC317218,%fp0 # N * L1, L1 = lead(-log2/64) + fmul.x L2(%pc),%fp2 # N * L2, L1+L2 = -log2/64 + fadd.x %fp1,%fp0 # X + N*L1 + fadd.x %fp2,%fp0 # fp0 is R, reduced arg. + +#--Step 4. +#--WE NOW COMPUTE EXP(R)-1 BY A POLYNOMIAL +#-- R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*A5)))) +#--TO FULLY UTILIZE THE PIPELINE, WE COMPUTE S = R*R +#--[R+R*S*(A2+S*A4)] + [S*(A1+S*(A3+S*A5))] + + fmov.x %fp0,%fp1 + fmul.x %fp1,%fp1 # fp1 IS S = R*R + + fmov.s &0x3AB60B70,%fp2 # fp2 IS A5 + + fmul.x %fp1,%fp2 # fp2 IS S*A5 + fmov.x %fp1,%fp3 + fmul.s &0x3C088895,%fp3 # fp3 IS S*A4 + + fadd.d EEXPA3(%pc),%fp2 # fp2 IS A3+S*A5 + fadd.d EEXPA2(%pc),%fp3 # fp3 IS A2+S*A4 + + fmul.x %fp1,%fp2 # fp2 IS S*(A3+S*A5) + mov.w %d1,SCALE(%a6) # SCALE is 2^(M) in extended + mov.l &0x80000000,SCALE+4(%a6) + clr.l SCALE+8(%a6) + + fmul.x %fp1,%fp3 # fp3 IS S*(A2+S*A4) + + fadd.s &0x3F000000,%fp2 # fp2 IS A1+S*(A3+S*A5) + fmul.x %fp0,%fp3 # fp3 IS R*S*(A2+S*A4) + + fmul.x %fp1,%fp2 # fp2 IS S*(A1+S*(A3+S*A5)) + fadd.x %fp3,%fp0 # fp0 IS R+R*S*(A2+S*A4), + + fmov.x (%a1)+,%fp1 # fp1 is lead. pt. of 2^(J/64) + fadd.x %fp2,%fp0 # fp0 is EXP(R) - 1 + +#--Step 5 +#--final reconstruction process +#--EXP(X) = 2^M * ( 2^(J/64) + 2^(J/64)*(EXP(R)-1) ) + + fmul.x %fp1,%fp0 # 2^(J/64)*(Exp(R)-1) + fmovm.x (%sp)+,&0x30 # fp2 restored {%fp2/%fp3} + fadd.s (%a1),%fp0 # accurate 2^(J/64) + + fadd.x %fp1,%fp0 # 2^(J/64) + 2^(J/64)*... + mov.l ADJFLAG(%a6),%d1 + +#--Step 6 + tst.l %d1 + beq.b NORMAL +ADJUST: + fmul.x ADJSCALE(%a6),%fp0 +NORMAL: + fmov.l %d0,%fpcr # restore user FPCR + mov.b &FMUL_OP,%d1 # last inst is MUL + fmul.x SCALE(%a6),%fp0 # multiply 2^(M) + bra t_catch + +EXPSM: +#--Step 7 + fmovm.x (%a0),&0x80 # load X + fmov.l %d0,%fpcr + fadd.s &0x3F800000,%fp0 # 1+X in user mode + bra t_pinx2 + +EEXPBIG: +#--Step 8 + cmp.l %d1,&0x400CB27C # 16480 log2 + bgt.b EXP2BIG +#--Steps 8.2 -- 8.6 + fmov.x (%a0),%fp0 # load input from (a0) + + fmov.x %fp0,%fp1 + fmul.s &0x42B8AA3B,%fp0 # 64/log2 * X + fmovm.x &0xc,-(%sp) # save fp2 {%fp2/%fp3} + mov.l &1,ADJFLAG(%a6) + fmov.l %fp0,%d1 # N = int( X * 64/log2 ) + lea EEXPTBL(%pc),%a1 + fmov.l %d1,%fp0 # convert to floating-format + mov.l %d1,L_SCR1(%a6) # save N temporarily + and.l &0x3F,%d1 # D0 is J = N mod 64 + lsl.l &4,%d1 + add.l %d1,%a1 # address of 2^(J/64) + mov.l L_SCR1(%a6),%d1 + asr.l &6,%d1 # D0 is K + mov.l %d1,L_SCR1(%a6) # save K temporarily + asr.l &1,%d1 # D0 is M1 + sub.l %d1,L_SCR1(%a6) # a1 is M + add.w &0x3FFF,%d1 # biased expo. of 2^(M1) + mov.w %d1,ADJSCALE(%a6) # ADJSCALE := 2^(M1) + mov.l &0x80000000,ADJSCALE+4(%a6) + clr.l ADJSCALE+8(%a6) + mov.l L_SCR1(%a6),%d1 # D0 is M + add.w &0x3FFF,%d1 # biased expo. of 2^(M) + bra.w EXPCONT1 # go back to Step 3 + +EXP2BIG: +#--Step 9 + tst.b (%a0) # is X positive or negative? + bmi t_unfl2 + bra t_ovfl2 + + global setoxd +setoxd: +#--entry point for EXP(X), X is denormalized + mov.l (%a0),-(%sp) + andi.l &0x80000000,(%sp) + ori.l &0x00800000,(%sp) # sign(X)*2^(-126) + + fmov.s &0x3F800000,%fp0 + + fmov.l %d0,%fpcr + fadd.s (%sp)+,%fp0 + bra t_pinx2 + + global setoxm1 +setoxm1: +#--entry point for EXPM1(X), here X is finite, non-zero, non-NaN + +#--Step 1. +#--Step 1.1 + mov.l (%a0),%d1 # load part of input X + and.l &0x7FFF0000,%d1 # biased expo. of X + cmp.l %d1,&0x3FFD0000 # 1/4 + bge.b EM1CON1 # |X| >= 1/4 + bra EM1SM + +EM1CON1: +#--Step 1.3 +#--The case |X| >= 1/4 + mov.w 4(%a0),%d1 # expo. and partial sig. of |X| + cmp.l %d1,&0x4004C215 # 70log2 rounded up to 16 bits + ble.b EM1MAIN # 1/4 <= |X| <= 70log2 + bra EM1BIG + +EM1MAIN: +#--Step 2. +#--This is the case: 1/4 <= |X| <= 70 log2. + fmov.x (%a0),%fp0 # load input from (a0) + + fmov.x %fp0,%fp1 + fmul.s &0x42B8AA3B,%fp0 # 64/log2 * X + fmovm.x &0xc,-(%sp) # save fp2 {%fp2/%fp3} + fmov.l %fp0,%d1 # N = int( X * 64/log2 ) + lea EEXPTBL(%pc),%a1 + fmov.l %d1,%fp0 # convert to floating-format + + mov.l %d1,L_SCR1(%a6) # save N temporarily + and.l &0x3F,%d1 # D0 is J = N mod 64 + lsl.l &4,%d1 + add.l %d1,%a1 # address of 2^(J/64) + mov.l L_SCR1(%a6),%d1 + asr.l &6,%d1 # D0 is M + mov.l %d1,L_SCR1(%a6) # save a copy of M + +#--Step 3. +#--fp1,fp2 saved on the stack. fp0 is N, fp1 is X, +#--a0 points to 2^(J/64), D0 and a1 both contain M + fmov.x %fp0,%fp2 + fmul.s &0xBC317218,%fp0 # N * L1, L1 = lead(-log2/64) + fmul.x L2(%pc),%fp2 # N * L2, L1+L2 = -log2/64 + fadd.x %fp1,%fp0 # X + N*L1 + fadd.x %fp2,%fp0 # fp0 is R, reduced arg. + add.w &0x3FFF,%d1 # D0 is biased expo. of 2^M + +#--Step 4. +#--WE NOW COMPUTE EXP(R)-1 BY A POLYNOMIAL +#-- R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*(A5 + R*A6))))) +#--TO FULLY UTILIZE THE PIPELINE, WE COMPUTE S = R*R +#--[R*S*(A2+S*(A4+S*A6))] + [R+S*(A1+S*(A3+S*A5))] + + fmov.x %fp0,%fp1 + fmul.x %fp1,%fp1 # fp1 IS S = R*R + + fmov.s &0x3950097B,%fp2 # fp2 IS a6 + + fmul.x %fp1,%fp2 # fp2 IS S*A6 + fmov.x %fp1,%fp3 + fmul.s &0x3AB60B6A,%fp3 # fp3 IS S*A5 + + fadd.d EM1A4(%pc),%fp2 # fp2 IS A4+S*A6 + fadd.d EM1A3(%pc),%fp3 # fp3 IS A3+S*A5 + mov.w %d1,SC(%a6) # SC is 2^(M) in extended + mov.l &0x80000000,SC+4(%a6) + clr.l SC+8(%a6) + + fmul.x %fp1,%fp2 # fp2 IS S*(A4+S*A6) + mov.l L_SCR1(%a6),%d1 # D0 is M + neg.w %d1 # D0 is -M + fmul.x %fp1,%fp3 # fp3 IS S*(A3+S*A5) + add.w &0x3FFF,%d1 # biased expo. of 2^(-M) + fadd.d EM1A2(%pc),%fp2 # fp2 IS A2+S*(A4+S*A6) + fadd.s &0x3F000000,%fp3 # fp3 IS A1+S*(A3+S*A5) + + fmul.x %fp1,%fp2 # fp2 IS S*(A2+S*(A4+S*A6)) + or.w &0x8000,%d1 # signed/expo. of -2^(-M) + mov.w %d1,ONEBYSC(%a6) # OnebySc is -2^(-M) + mov.l &0x80000000,ONEBYSC+4(%a6) + clr.l ONEBYSC+8(%a6) + fmul.x %fp3,%fp1 # fp1 IS S*(A1+S*(A3+S*A5)) + + fmul.x %fp0,%fp2 # fp2 IS R*S*(A2+S*(A4+S*A6)) + fadd.x %fp1,%fp0 # fp0 IS R+S*(A1+S*(A3+S*A5)) + + fadd.x %fp2,%fp0 # fp0 IS EXP(R)-1 + + fmovm.x (%sp)+,&0x30 # fp2 restored {%fp2/%fp3} + +#--Step 5 +#--Compute 2^(J/64)*p + + fmul.x (%a1),%fp0 # 2^(J/64)*(Exp(R)-1) + +#--Step 6 +#--Step 6.1 + mov.l L_SCR1(%a6),%d1 # retrieve M + cmp.l %d1,&63 + ble.b MLE63 +#--Step 6.2 M >= 64 + fmov.s 12(%a1),%fp1 # fp1 is t + fadd.x ONEBYSC(%a6),%fp1 # fp1 is t+OnebySc + fadd.x %fp1,%fp0 # p+(t+OnebySc), fp1 released + fadd.x (%a1),%fp0 # T+(p+(t+OnebySc)) + bra EM1SCALE +MLE63: +#--Step 6.3 M <= 63 + cmp.l %d1,&-3 + bge.b MGEN3 +MLTN3: +#--Step 6.4 M <= -4 + fadd.s 12(%a1),%fp0 # p+t + fadd.x (%a1),%fp0 # T+(p+t) + fadd.x ONEBYSC(%a6),%fp0 # OnebySc + (T+(p+t)) + bra EM1SCALE +MGEN3: +#--Step 6.5 -3 <= M <= 63 + fmov.x (%a1)+,%fp1 # fp1 is T + fadd.s (%a1),%fp0 # fp0 is p+t + fadd.x ONEBYSC(%a6),%fp1 # fp1 is T+OnebySc + fadd.x %fp1,%fp0 # (T+OnebySc)+(p+t) + +EM1SCALE: +#--Step 6.6 + fmov.l %d0,%fpcr + fmul.x SC(%a6),%fp0 + bra t_inx2 + +EM1SM: +#--Step 7 |X| < 1/4. + cmp.l %d1,&0x3FBE0000 # 2^(-65) + bge.b EM1POLY + +EM1TINY: +#--Step 8 |X| < 2^(-65) + cmp.l %d1,&0x00330000 # 2^(-16312) + blt.b EM12TINY +#--Step 8.2 + mov.l &0x80010000,SC(%a6) # SC is -2^(-16382) + mov.l &0x80000000,SC+4(%a6) + clr.l SC+8(%a6) + fmov.x (%a0),%fp0 + fmov.l %d0,%fpcr + mov.b &FADD_OP,%d1 # last inst is ADD + fadd.x SC(%a6),%fp0 + bra t_catch + +EM12TINY: +#--Step 8.3 + fmov.x (%a0),%fp0 + fmul.d TWO140(%pc),%fp0 + mov.l &0x80010000,SC(%a6) + mov.l &0x80000000,SC+4(%a6) + clr.l SC+8(%a6) + fadd.x SC(%a6),%fp0 + fmov.l %d0,%fpcr + mov.b &FMUL_OP,%d1 # last inst is MUL + fmul.d TWON140(%pc),%fp0 + bra t_catch + +EM1POLY: +#--Step 9 exp(X)-1 by a simple polynomial + fmov.x (%a0),%fp0 # fp0 is X + fmul.x %fp0,%fp0 # fp0 is S := X*X + fmovm.x &0xc,-(%sp) # save fp2 {%fp2/%fp3} + fmov.s &0x2F30CAA8,%fp1 # fp1 is B12 + fmul.x %fp0,%fp1 # fp1 is S*B12 + fmov.s &0x310F8290,%fp2 # fp2 is B11 + fadd.s &0x32D73220,%fp1 # fp1 is B10+S*B12 + + fmul.x %fp0,%fp2 # fp2 is S*B11 + fmul.x %fp0,%fp1 # fp1 is S*(B10 + ... + + fadd.s &0x3493F281,%fp2 # fp2 is B9+S*... + fadd.d EM1B8(%pc),%fp1 # fp1 is B8+S*... + + fmul.x %fp0,%fp2 # fp2 is S*(B9+... + fmul.x %fp0,%fp1 # fp1 is S*(B8+... + + fadd.d EM1B7(%pc),%fp2 # fp2 is B7+S*... + fadd.d EM1B6(%pc),%fp1 # fp1 is B6+S*... + + fmul.x %fp0,%fp2 # fp2 is S*(B7+... + fmul.x %fp0,%fp1 # fp1 is S*(B6+... + + fadd.d EM1B5(%pc),%fp2 # fp2 is B5+S*... + fadd.d EM1B4(%pc),%fp1 # fp1 is B4+S*... + + fmul.x %fp0,%fp2 # fp2 is S*(B5+... + fmul.x %fp0,%fp1 # fp1 is S*(B4+... + + fadd.d EM1B3(%pc),%fp2 # fp2 is B3+S*... + fadd.x EM1B2(%pc),%fp1 # fp1 is B2+S*... + + fmul.x %fp0,%fp2 # fp2 is S*(B3+... + fmul.x %fp0,%fp1 # fp1 is S*(B2+... + + fmul.x %fp0,%fp2 # fp2 is S*S*(B3+...) + fmul.x (%a0),%fp1 # fp1 is X*S*(B2... + + fmul.s &0x3F000000,%fp0 # fp0 is S*B1 + fadd.x %fp2,%fp1 # fp1 is Q + + fmovm.x (%sp)+,&0x30 # fp2 restored {%fp2/%fp3} + + fadd.x %fp1,%fp0 # fp0 is S*B1+Q + + fmov.l %d0,%fpcr + fadd.x (%a0),%fp0 + bra t_inx2 + +EM1BIG: +#--Step 10 |X| > 70 log2 + mov.l (%a0),%d1 + cmp.l %d1,&0 + bgt.w EXPC1 +#--Step 10.2 + fmov.s &0xBF800000,%fp0 # fp0 is -1 + fmov.l %d0,%fpcr + fadd.s &0x00800000,%fp0 # -1 + 2^(-126) + bra t_minx2 + + global setoxm1d +setoxm1d: +#--entry point for EXPM1(X), here X is denormalized +#--Step 0. + bra t_extdnrm + +######################################################################### +# sgetexp(): returns the exponent portion of the input argument. # +# The exponent bias is removed and the exponent value is # +# returned as an extended precision number in fp0. # +# sgetexpd(): handles denormalized numbers. # +# # +# sgetman(): extracts the mantissa of the input argument. The # +# mantissa is converted to an extended precision number w/ # +# an exponent of $3fff and is returned in fp0. The range of # +# the result is [1.0 - 2.0). # +# sgetmand(): handles denormalized numbers. # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input # +# # +# OUTPUT ************************************************************** # +# fp0 = exponent(X) or mantissa(X) # +# # +######################################################################### + + global sgetexp +sgetexp: + mov.w SRC_EX(%a0),%d0 # get the exponent + bclr &0xf,%d0 # clear the sign bit + subi.w &0x3fff,%d0 # subtract off the bias + fmov.w %d0,%fp0 # return exp in fp0 + blt.b sgetexpn # it's negative + rts + +sgetexpn: + mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit + rts + + global sgetexpd +sgetexpd: + bsr.l norm # normalize + neg.w %d0 # new exp = -(shft amt) + subi.w &0x3fff,%d0 # subtract off the bias + fmov.w %d0,%fp0 # return exp in fp0 + mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit + rts + + global sgetman +sgetman: + mov.w SRC_EX(%a0),%d0 # get the exp + ori.w &0x7fff,%d0 # clear old exp + bclr &0xe,%d0 # make it the new exp +-3fff + +# here, we build the result in a tmp location so as not to disturb the input + mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) # copy to tmp loc + mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) # copy to tmp loc + mov.w %d0,FP_SCR0_EX(%a6) # insert new exponent + fmov.x FP_SCR0(%a6),%fp0 # put new value back in fp0 + bmi.b sgetmann # it's negative + rts + +sgetmann: + mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit + rts + +# +# For denormalized numbers, shift the mantissa until the j-bit = 1, +# then load the exponent with +/1 $3fff. +# + global sgetmand +sgetmand: + bsr.l norm # normalize exponent + bra.b sgetman + +######################################################################### +# scosh(): computes the hyperbolic cosine of a normalized input # +# scoshd(): computes the hyperbolic cosine of a denormalized input # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input # +# d0 = round precision,mode # +# # +# OUTPUT ************************************************************** # +# fp0 = cosh(X) # +# # +# ACCURACY and MONOTONICITY ******************************************* # +# The returned result is within 3 ulps in 64 significant bit, # +# i.e. within 0.5001 ulp to 53 bits if the result is subsequently # +# rounded to double precision. The result is provably monotonic # +# in double precision. # +# # +# ALGORITHM *********************************************************** # +# # +# COSH # +# 1. If |X| > 16380 log2, go to 3. # +# # +# 2. (|X| <= 16380 log2) Cosh(X) is obtained by the formulae # +# y = |X|, z = exp(Y), and # +# cosh(X) = (1/2)*( z + 1/z ). # +# Exit. # +# # +# 3. (|X| > 16380 log2). If |X| > 16480 log2, go to 5. # +# # +# 4. (16380 log2 < |X| <= 16480 log2) # +# cosh(X) = sign(X) * exp(|X|)/2. # +# However, invoking exp(|X|) may cause premature # +# overflow. Thus, we calculate sinh(X) as follows: # +# Y := |X| # +# Fact := 2**(16380) # +# Y' := Y - 16381 log2 # +# cosh(X) := Fact * exp(Y'). # +# Exit. # +# # +# 5. (|X| > 16480 log2) sinh(X) must overflow. Return # +# Huge*Huge to generate overflow and an infinity with # +# the appropriate sign. Huge is the largest finite number # +# in extended format. Exit. # +# # +######################################################################### + +TWO16380: + long 0x7FFB0000,0x80000000,0x00000000,0x00000000 + + global scosh +scosh: + fmov.x (%a0),%fp0 # LOAD INPUT + + mov.l (%a0),%d1 + mov.w 4(%a0),%d1 + and.l &0x7FFFFFFF,%d1 + cmp.l %d1,&0x400CB167 + bgt.b COSHBIG + +#--THIS IS THE USUAL CASE, |X| < 16380 LOG2 +#--COSH(X) = (1/2) * ( EXP(X) + 1/EXP(X) ) + + fabs.x %fp0 # |X| + + mov.l %d0,-(%sp) + clr.l %d0 + fmovm.x &0x01,-(%sp) # save |X| to stack + lea (%sp),%a0 # pass ptr to |X| + bsr setox # FP0 IS EXP(|X|) + add.l &0xc,%sp # erase |X| from stack + fmul.s &0x3F000000,%fp0 # (1/2)EXP(|X|) + mov.l (%sp)+,%d0 + + fmov.s &0x3E800000,%fp1 # (1/4) + fdiv.x %fp0,%fp1 # 1/(2 EXP(|X|)) + + fmov.l %d0,%fpcr + mov.b &FADD_OP,%d1 # last inst is ADD + fadd.x %fp1,%fp0 + bra t_catch + +COSHBIG: + cmp.l %d1,&0x400CB2B3 + bgt.b COSHHUGE + + fabs.x %fp0 + fsub.d T1(%pc),%fp0 # (|X|-16381LOG2_LEAD) + fsub.d T2(%pc),%fp0 # |X| - 16381 LOG2, ACCURATE + + mov.l %d0,-(%sp) + clr.l %d0 + fmovm.x &0x01,-(%sp) # save fp0 to stack + lea (%sp),%a0 # pass ptr to fp0 + bsr setox + add.l &0xc,%sp # clear fp0 from stack + mov.l (%sp)+,%d0 + + fmov.l %d0,%fpcr + mov.b &FMUL_OP,%d1 # last inst is MUL + fmul.x TWO16380(%pc),%fp0 + bra t_catch + +COSHHUGE: + bra t_ovfl2 + + global scoshd +#--COSH(X) = 1 FOR DENORMALIZED X +scoshd: + fmov.s &0x3F800000,%fp0 + + fmov.l %d0,%fpcr + fadd.s &0x00800000,%fp0 + bra t_pinx2 + +######################################################################### +# ssinh(): computes the hyperbolic sine of a normalized input # +# ssinhd(): computes the hyperbolic sine of a denormalized input # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input # +# d0 = round precision,mode # +# # +# OUTPUT ************************************************************** # +# fp0 = sinh(X) # +# # +# ACCURACY and MONOTONICITY ******************************************* # +# The returned result is within 3 ulps in 64 significant bit, # +# i.e. within 0.5001 ulp to 53 bits if the result is subsequently # +# rounded to double precision. The result is provably monotonic # +# in double precision. # +# # +# ALGORITHM *********************************************************** # +# # +# SINH # +# 1. If |X| > 16380 log2, go to 3. # +# # +# 2. (|X| <= 16380 log2) Sinh(X) is obtained by the formula # +# y = |X|, sgn = sign(X), and z = expm1(Y), # +# sinh(X) = sgn*(1/2)*( z + z/(1+z) ). # +# Exit. # +# # +# 3. If |X| > 16480 log2, go to 5. # +# # +# 4. (16380 log2 < |X| <= 16480 log2) # +# sinh(X) = sign(X) * exp(|X|)/2. # +# However, invoking exp(|X|) may cause premature overflow. # +# Thus, we calculate sinh(X) as follows: # +# Y := |X| # +# sgn := sign(X) # +# sgnFact := sgn * 2**(16380) # +# Y' := Y - 16381 log2 # +# sinh(X) := sgnFact * exp(Y'). # +# Exit. # +# # +# 5. (|X| > 16480 log2) sinh(X) must overflow. Return # +# sign(X)*Huge*Huge to generate overflow and an infinity with # +# the appropriate sign. Huge is the largest finite number in # +# extended format. Exit. # +# # +######################################################################### + + global ssinh +ssinh: + fmov.x (%a0),%fp0 # LOAD INPUT + + mov.l (%a0),%d1 + mov.w 4(%a0),%d1 + mov.l %d1,%a1 # save (compacted) operand + and.l &0x7FFFFFFF,%d1 + cmp.l %d1,&0x400CB167 + bgt.b SINHBIG + +#--THIS IS THE USUAL CASE, |X| < 16380 LOG2 +#--Y = |X|, Z = EXPM1(Y), SINH(X) = SIGN(X)*(1/2)*( Z + Z/(1+Z) ) + + fabs.x %fp0 # Y = |X| + + movm.l &0x8040,-(%sp) # {a1/d0} + fmovm.x &0x01,-(%sp) # save Y on stack + lea (%sp),%a0 # pass ptr to Y + clr.l %d0 + bsr setoxm1 # FP0 IS Z = EXPM1(Y) + add.l &0xc,%sp # clear Y from stack + fmov.l &0,%fpcr + movm.l (%sp)+,&0x0201 # {a1/d0} + + fmov.x %fp0,%fp1 + fadd.s &0x3F800000,%fp1 # 1+Z + fmov.x %fp0,-(%sp) + fdiv.x %fp1,%fp0 # Z/(1+Z) + mov.l %a1,%d1 + and.l &0x80000000,%d1 + or.l &0x3F000000,%d1 + fadd.x (%sp)+,%fp0 + mov.l %d1,-(%sp) + + fmov.l %d0,%fpcr + mov.b &FMUL_OP,%d1 # last inst is MUL + fmul.s (%sp)+,%fp0 # last fp inst - possible exceptions set + bra t_catch + +SINHBIG: + cmp.l %d1,&0x400CB2B3 + bgt t_ovfl + fabs.x %fp0 + fsub.d T1(%pc),%fp0 # (|X|-16381LOG2_LEAD) + mov.l &0,-(%sp) + mov.l &0x80000000,-(%sp) + mov.l %a1,%d1 + and.l &0x80000000,%d1 + or.l &0x7FFB0000,%d1 + mov.l %d1,-(%sp) # EXTENDED FMT + fsub.d T2(%pc),%fp0 # |X| - 16381 LOG2, ACCURATE + + mov.l %d0,-(%sp) + clr.l %d0 + fmovm.x &0x01,-(%sp) # save fp0 on stack + lea (%sp),%a0 # pass ptr to fp0 + bsr setox + add.l &0xc,%sp # clear fp0 from stack + + mov.l (%sp)+,%d0 + fmov.l %d0,%fpcr + mov.b &FMUL_OP,%d1 # last inst is MUL + fmul.x (%sp)+,%fp0 # possible exception + bra t_catch + + global ssinhd +#--SINH(X) = X FOR DENORMALIZED X +ssinhd: + bra t_extdnrm + +######################################################################### +# stanh(): computes the hyperbolic tangent of a normalized input # +# stanhd(): computes the hyperbolic tangent of a denormalized input # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input # +# d0 = round precision,mode # +# # +# OUTPUT ************************************************************** # +# fp0 = tanh(X) # +# # +# ACCURACY and MONOTONICITY ******************************************* # +# The returned result is within 3 ulps in 64 significant bit, # +# i.e. within 0.5001 ulp to 53 bits if the result is subsequently # +# rounded to double precision. The result is provably monotonic # +# in double precision. # +# # +# ALGORITHM *********************************************************** # +# # +# TANH # +# 1. If |X| >= (5/2) log2 or |X| <= 2**(-40), go to 3. # +# # +# 2. (2**(-40) < |X| < (5/2) log2) Calculate tanh(X) by # +# sgn := sign(X), y := 2|X|, z := expm1(Y), and # +# tanh(X) = sgn*( z/(2+z) ). # +# Exit. # +# # +# 3. (|X| <= 2**(-40) or |X| >= (5/2) log2). If |X| < 1, # +# go to 7. # +# # +# 4. (|X| >= (5/2) log2) If |X| >= 50 log2, go to 6. # +# # +# 5. ((5/2) log2 <= |X| < 50 log2) Calculate tanh(X) by # +# sgn := sign(X), y := 2|X|, z := exp(Y), # +# tanh(X) = sgn - [ sgn*2/(1+z) ]. # +# Exit. # +# # +# 6. (|X| >= 50 log2) Tanh(X) = +-1 (round to nearest). Thus, we # +# calculate Tanh(X) by # +# sgn := sign(X), Tiny := 2**(-126), # +# tanh(X) := sgn - sgn*Tiny. # +# Exit. # +# # +# 7. (|X| < 2**(-40)). Tanh(X) = X. Exit. # +# # +######################################################################### + + set X,FP_SCR0 + set XFRAC,X+4 + + set SGN,L_SCR3 + + set V,FP_SCR0 + + global stanh +stanh: + fmov.x (%a0),%fp0 # LOAD INPUT + + fmov.x %fp0,X(%a6) + mov.l (%a0),%d1 + mov.w 4(%a0),%d1 + mov.l %d1,X(%a6) + and.l &0x7FFFFFFF,%d1 + cmp.l %d1, &0x3fd78000 # is |X| < 2^(-40)? + blt.w TANHBORS # yes + cmp.l %d1, &0x3fffddce # is |X| > (5/2)LOG2? + bgt.w TANHBORS # yes + +#--THIS IS THE USUAL CASE +#--Y = 2|X|, Z = EXPM1(Y), TANH(X) = SIGN(X) * Z / (Z+2). + + mov.l X(%a6),%d1 + mov.l %d1,SGN(%a6) + and.l &0x7FFF0000,%d1 + add.l &0x00010000,%d1 # EXPONENT OF 2|X| + mov.l %d1,X(%a6) + and.l &0x80000000,SGN(%a6) + fmov.x X(%a6),%fp0 # FP0 IS Y = 2|X| + + mov.l %d0,-(%sp) + clr.l %d0 + fmovm.x &0x1,-(%sp) # save Y on stack + lea (%sp),%a0 # pass ptr to Y + bsr setoxm1 # FP0 IS Z = EXPM1(Y) + add.l &0xc,%sp # clear Y from stack + mov.l (%sp)+,%d0 + + fmov.x %fp0,%fp1 + fadd.s &0x40000000,%fp1 # Z+2 + mov.l SGN(%a6),%d1 + fmov.x %fp1,V(%a6) + eor.l %d1,V(%a6) + + fmov.l %d0,%fpcr # restore users round prec,mode + fdiv.x V(%a6),%fp0 + bra t_inx2 + +TANHBORS: + cmp.l %d1,&0x3FFF8000 + blt.w TANHSM + + cmp.l %d1,&0x40048AA1 + bgt.w TANHHUGE + +#-- (5/2) LOG2 < |X| < 50 LOG2, +#--TANH(X) = 1 - (2/[EXP(2X)+1]). LET Y = 2|X|, SGN = SIGN(X), +#--TANH(X) = SGN - SGN*2/[EXP(Y)+1]. + + mov.l X(%a6),%d1 + mov.l %d1,SGN(%a6) + and.l &0x7FFF0000,%d1 + add.l &0x00010000,%d1 # EXPO OF 2|X| + mov.l %d1,X(%a6) # Y = 2|X| + and.l &0x80000000,SGN(%a6) + mov.l SGN(%a6),%d1 + fmov.x X(%a6),%fp0 # Y = 2|X| + + mov.l %d0,-(%sp) + clr.l %d0 + fmovm.x &0x01,-(%sp) # save Y on stack + lea (%sp),%a0 # pass ptr to Y + bsr setox # FP0 IS EXP(Y) + add.l &0xc,%sp # clear Y from stack + mov.l (%sp)+,%d0 + mov.l SGN(%a6),%d1 + fadd.s &0x3F800000,%fp0 # EXP(Y)+1 + + eor.l &0xC0000000,%d1 # -SIGN(X)*2 + fmov.s %d1,%fp1 # -SIGN(X)*2 IN SGL FMT + fdiv.x %fp0,%fp1 # -SIGN(X)2 / [EXP(Y)+1 ] + + mov.l SGN(%a6),%d1 + or.l &0x3F800000,%d1 # SGN + fmov.s %d1,%fp0 # SGN IN SGL FMT + + fmov.l %d0,%fpcr # restore users round prec,mode + mov.b &FADD_OP,%d1 # last inst is ADD + fadd.x %fp1,%fp0 + bra t_inx2 + +TANHSM: + fmov.l %d0,%fpcr # restore users round prec,mode + mov.b &FMOV_OP,%d1 # last inst is MOVE + fmov.x X(%a6),%fp0 # last inst - possible exception set + bra t_catch + +#---RETURN SGN(X) - SGN(X)EPS +TANHHUGE: + mov.l X(%a6),%d1 + and.l &0x80000000,%d1 + or.l &0x3F800000,%d1 + fmov.s %d1,%fp0 + and.l &0x80000000,%d1 + eor.l &0x80800000,%d1 # -SIGN(X)*EPS + + fmov.l %d0,%fpcr # restore users round prec,mode + fadd.s %d1,%fp0 + bra t_inx2 + + global stanhd +#--TANH(X) = X FOR DENORMALIZED X +stanhd: + bra t_extdnrm + +######################################################################### +# slogn(): computes the natural logarithm of a normalized input # +# slognd(): computes the natural logarithm of a denormalized input # +# slognp1(): computes the log(1+X) of a normalized input # +# slognp1d(): computes the log(1+X) of a denormalized input # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input # +# d0 = round precision,mode # +# # +# OUTPUT ************************************************************** # +# fp0 = log(X) or log(1+X) # +# # +# ACCURACY and MONOTONICITY ******************************************* # +# The returned result is within 2 ulps in 64 significant bit, # +# i.e. within 0.5001 ulp to 53 bits if the result is subsequently # +# rounded to double precision. The result is provably monotonic # +# in double precision. # +# # +# ALGORITHM *********************************************************** # +# LOGN: # +# Step 1. If |X-1| < 1/16, approximate log(X) by an odd # +# polynomial in u, where u = 2(X-1)/(X+1). Otherwise, # +# move on to Step 2. # +# # +# Step 2. X = 2**k * Y where 1 <= Y < 2. Define F to be the first # +# seven significant bits of Y plus 2**(-7), i.e. # +# F = 1.xxxxxx1 in base 2 where the six "x" match those # +# of Y. Note that |Y-F| <= 2**(-7). # +# # +# Step 3. Define u = (Y-F)/F. Approximate log(1+u) by a # +# polynomial in u, log(1+u) = poly. # +# # +# Step 4. Reconstruct # +# log(X) = log( 2**k * Y ) = k*log(2) + log(F) + log(1+u) # +# by k*log(2) + (log(F) + poly). The values of log(F) are # +# calculated beforehand and stored in the program. # +# # +# lognp1: # +# Step 1: If |X| < 1/16, approximate log(1+X) by an odd # +# polynomial in u where u = 2X/(2+X). Otherwise, move on # +# to Step 2. # +# # +# Step 2: Let 1+X = 2**k * Y, where 1 <= Y < 2. Define F as done # +# in Step 2 of the algorithm for LOGN and compute # +# log(1+X) as k*log(2) + log(F) + poly where poly # +# approximates log(1+u), u = (Y-F)/F. # +# # +# Implementation Notes: # +# Note 1. There are 64 different possible values for F, thus 64 # +# log(F)'s need to be tabulated. Moreover, the values of # +# 1/F are also tabulated so that the division in (Y-F)/F # +# can be performed by a multiplication. # +# # +# Note 2. In Step 2 of lognp1, in order to preserved accuracy, # +# the value Y-F has to be calculated carefully when # +# 1/2 <= X < 3/2. # +# # +# Note 3. To fully exploit the pipeline, polynomials are usually # +# separated into two parts evaluated independently before # +# being added up. # +# # +######################################################################### +LOGOF2: + long 0x3FFE0000,0xB17217F7,0xD1CF79AC,0x00000000 + +one: + long 0x3F800000 +zero: + long 0x00000000 +infty: + long 0x7F800000 +negone: + long 0xBF800000 + +LOGA6: + long 0x3FC2499A,0xB5E4040B +LOGA5: + long 0xBFC555B5,0x848CB7DB + +LOGA4: + long 0x3FC99999,0x987D8730 +LOGA3: + long 0xBFCFFFFF,0xFF6F7E97 + +LOGA2: + long 0x3FD55555,0x555555A4 +LOGA1: + long 0xBFE00000,0x00000008 + +LOGB5: + long 0x3F175496,0xADD7DAD6 +LOGB4: + long 0x3F3C71C2,0xFE80C7E0 + +LOGB3: + long 0x3F624924,0x928BCCFF +LOGB2: + long 0x3F899999,0x999995EC + +LOGB1: + long 0x3FB55555,0x55555555 +TWO: + long 0x40000000,0x00000000 + +LTHOLD: + long 0x3f990000,0x80000000,0x00000000,0x00000000 + +LOGTBL: + long 0x3FFE0000,0xFE03F80F,0xE03F80FE,0x00000000 + long 0x3FF70000,0xFF015358,0x833C47E2,0x00000000 + long 0x3FFE0000,0xFA232CF2,0x52138AC0,0x00000000 + long 0x3FF90000,0xBDC8D83E,0xAD88D549,0x00000000 + long 0x3FFE0000,0xF6603D98,0x0F6603DA,0x00000000 + long 0x3FFA0000,0x9CF43DCF,0xF5EAFD48,0x00000000 + long 0x3FFE0000,0xF2B9D648,0x0F2B9D65,0x00000000 + long 0x3FFA0000,0xDA16EB88,0xCB8DF614,0x00000000 + long 0x3FFE0000,0xEF2EB71F,0xC4345238,0x00000000 + long 0x3FFB0000,0x8B29B775,0x1BD70743,0x00000000 + long 0x3FFE0000,0xEBBDB2A5,0xC1619C8C,0x00000000 + long 0x3FFB0000,0xA8D839F8,0x30C1FB49,0x00000000 + long 0x3FFE0000,0xE865AC7B,0x7603A197,0x00000000 + long 0x3FFB0000,0xC61A2EB1,0x8CD907AD,0x00000000 + long 0x3FFE0000,0xE525982A,0xF70C880E,0x00000000 + long 0x3FFB0000,0xE2F2A47A,0xDE3A18AF,0x00000000 + long 0x3FFE0000,0xE1FC780E,0x1FC780E2,0x00000000 + long 0x3FFB0000,0xFF64898E,0xDF55D551,0x00000000 + long 0x3FFE0000,0xDEE95C4C,0xA037BA57,0x00000000 + long 0x3FFC0000,0x8DB956A9,0x7B3D0148,0x00000000 + long 0x3FFE0000,0xDBEB61EE,0xD19C5958,0x00000000 + long 0x3FFC0000,0x9B8FE100,0xF47BA1DE,0x00000000 + long 0x3FFE0000,0xD901B203,0x6406C80E,0x00000000 + long 0x3FFC0000,0xA9372F1D,0x0DA1BD17,0x00000000 + long 0x3FFE0000,0xD62B80D6,0x2B80D62C,0x00000000 + long 0x3FFC0000,0xB6B07F38,0xCE90E46B,0x00000000 + long 0x3FFE0000,0xD3680D36,0x80D3680D,0x00000000 + long 0x3FFC0000,0xC3FD0329,0x06488481,0x00000000 + long 0x3FFE0000,0xD0B69FCB,0xD2580D0B,0x00000000 + long 0x3FFC0000,0xD11DE0FF,0x15AB18CA,0x00000000 + long 0x3FFE0000,0xCE168A77,0x25080CE1,0x00000000 + long 0x3FFC0000,0xDE1433A1,0x6C66B150,0x00000000 + long 0x3FFE0000,0xCB8727C0,0x65C393E0,0x00000000 + long 0x3FFC0000,0xEAE10B5A,0x7DDC8ADD,0x00000000 + long 0x3FFE0000,0xC907DA4E,0x871146AD,0x00000000 + long 0x3FFC0000,0xF7856E5E,0xE2C9B291,0x00000000 + long 0x3FFE0000,0xC6980C69,0x80C6980C,0x00000000 + long 0x3FFD0000,0x82012CA5,0xA68206D7,0x00000000 + long 0x3FFE0000,0xC4372F85,0x5D824CA6,0x00000000 + long 0x3FFD0000,0x882C5FCD,0x7256A8C5,0x00000000 + long 0x3FFE0000,0xC1E4BBD5,0x95F6E947,0x00000000 + long 0x3FFD0000,0x8E44C60B,0x4CCFD7DE,0x00000000 + long 0x3FFE0000,0xBFA02FE8,0x0BFA02FF,0x00000000 + long 0x3FFD0000,0x944AD09E,0xF4351AF6,0x00000000 + long 0x3FFE0000,0xBD691047,0x07661AA3,0x00000000 + long 0x3FFD0000,0x9A3EECD4,0xC3EAA6B2,0x00000000 + long 0x3FFE0000,0xBB3EE721,0xA54D880C,0x00000000 + long 0x3FFD0000,0xA0218434,0x353F1DE8,0x00000000 + long 0x3FFE0000,0xB92143FA,0x36F5E02E,0x00000000 + long 0x3FFD0000,0xA5F2FCAB,0xBBC506DA,0x00000000 + long 0x3FFE0000,0xB70FBB5A,0x19BE3659,0x00000000 + long 0x3FFD0000,0xABB3B8BA,0x2AD362A5,0x00000000 + long 0x3FFE0000,0xB509E68A,0x9B94821F,0x00000000 + long 0x3FFD0000,0xB1641795,0xCE3CA97B,0x00000000 + long 0x3FFE0000,0xB30F6352,0x8917C80B,0x00000000 + long 0x3FFD0000,0xB7047551,0x5D0F1C61,0x00000000 + long 0x3FFE0000,0xB11FD3B8,0x0B11FD3C,0x00000000 + long 0x3FFD0000,0xBC952AFE,0xEA3D13E1,0x00000000 + long 0x3FFE0000,0xAF3ADDC6,0x80AF3ADE,0x00000000 + long 0x3FFD0000,0xC2168ED0,0xF458BA4A,0x00000000 + long 0x3FFE0000,0xAD602B58,0x0AD602B6,0x00000000 + long 0x3FFD0000,0xC788F439,0xB3163BF1,0x00000000 + long 0x3FFE0000,0xAB8F69E2,0x8359CD11,0x00000000 + long 0x3FFD0000,0xCCECAC08,0xBF04565D,0x00000000 + long 0x3FFE0000,0xA9C84A47,0xA07F5638,0x00000000 + long 0x3FFD0000,0xD2420487,0x2DD85160,0x00000000 + long 0x3FFE0000,0xA80A80A8,0x0A80A80B,0x00000000 + long 0x3FFD0000,0xD7894992,0x3BC3588A,0x00000000 + long 0x3FFE0000,0xA655C439,0x2D7B73A8,0x00000000 + long 0x3FFD0000,0xDCC2C4B4,0x9887DACC,0x00000000 + long 0x3FFE0000,0xA4A9CF1D,0x96833751,0x00000000 + long 0x3FFD0000,0xE1EEBD3E,0x6D6A6B9E,0x00000000 + long 0x3FFE0000,0xA3065E3F,0xAE7CD0E0,0x00000000 + long 0x3FFD0000,0xE70D785C,0x2F9F5BDC,0x00000000 + long 0x3FFE0000,0xA16B312E,0xA8FC377D,0x00000000 + long 0x3FFD0000,0xEC1F392C,0x5179F283,0x00000000 + long 0x3FFE0000,0x9FD809FD,0x809FD80A,0x00000000 + long 0x3FFD0000,0xF12440D3,0xE36130E6,0x00000000 + long 0x3FFE0000,0x9E4CAD23,0xDD5F3A20,0x00000000 + long 0x3FFD0000,0xF61CCE92,0x346600BB,0x00000000 + long 0x3FFE0000,0x9CC8E160,0xC3FB19B9,0x00000000 + long 0x3FFD0000,0xFB091FD3,0x8145630A,0x00000000 + long 0x3FFE0000,0x9B4C6F9E,0xF03A3CAA,0x00000000 + long 0x3FFD0000,0xFFE97042,0xBFA4C2AD,0x00000000 + long 0x3FFE0000,0x99D722DA,0xBDE58F06,0x00000000 + long 0x3FFE0000,0x825EFCED,0x49369330,0x00000000 + long 0x3FFE0000,0x9868C809,0x868C8098,0x00000000 + long 0x3FFE0000,0x84C37A7A,0xB9A905C9,0x00000000 + long 0x3FFE0000,0x97012E02,0x5C04B809,0x00000000 + long 0x3FFE0000,0x87224C2E,0x8E645FB7,0x00000000 + long 0x3FFE0000,0x95A02568,0x095A0257,0x00000000 + long 0x3FFE0000,0x897B8CAC,0x9F7DE298,0x00000000 + long 0x3FFE0000,0x94458094,0x45809446,0x00000000 + long 0x3FFE0000,0x8BCF55DE,0xC4CD05FE,0x00000000 + long 0x3FFE0000,0x92F11384,0x0497889C,0x00000000 + long 0x3FFE0000,0x8E1DC0FB,0x89E125E5,0x00000000 + long 0x3FFE0000,0x91A2B3C4,0xD5E6F809,0x00000000 + long 0x3FFE0000,0x9066E68C,0x955B6C9B,0x00000000 + long 0x3FFE0000,0x905A3863,0x3E06C43B,0x00000000 + long 0x3FFE0000,0x92AADE74,0xC7BE59E0,0x00000000 + long 0x3FFE0000,0x8F1779D9,0xFDC3A219,0x00000000 + long 0x3FFE0000,0x94E9BFF6,0x15845643,0x00000000 + long 0x3FFE0000,0x8DDA5202,0x37694809,0x00000000 + long 0x3FFE0000,0x9723A1B7,0x20134203,0x00000000 + long 0x3FFE0000,0x8CA29C04,0x6514E023,0x00000000 + long 0x3FFE0000,0x995899C8,0x90EB8990,0x00000000 + long 0x3FFE0000,0x8B70344A,0x139BC75A,0x00000000 + long 0x3FFE0000,0x9B88BDAA,0x3A3DAE2F,0x00000000 + long 0x3FFE0000,0x8A42F870,0x5669DB46,0x00000000 + long 0x3FFE0000,0x9DB4224F,0xFFE1157C,0x00000000 + long 0x3FFE0000,0x891AC73A,0xE9819B50,0x00000000 + long 0x3FFE0000,0x9FDADC26,0x8B7A12DA,0x00000000 + long 0x3FFE0000,0x87F78087,0xF78087F8,0x00000000 + long 0x3FFE0000,0xA1FCFF17,0xCE733BD4,0x00000000 + long 0x3FFE0000,0x86D90544,0x7A34ACC6,0x00000000 + long 0x3FFE0000,0xA41A9E8F,0x5446FB9F,0x00000000 + long 0x3FFE0000,0x85BF3761,0x2CEE3C9B,0x00000000 + long 0x3FFE0000,0xA633CD7E,0x6771CD8B,0x00000000 + long 0x3FFE0000,0x84A9F9C8,0x084A9F9D,0x00000000 + long 0x3FFE0000,0xA8489E60,0x0B435A5E,0x00000000 + long 0x3FFE0000,0x83993052,0x3FBE3368,0x00000000 + long 0x3FFE0000,0xAA59233C,0xCCA4BD49,0x00000000 + long 0x3FFE0000,0x828CBFBE,0xB9A020A3,0x00000000 + long 0x3FFE0000,0xAC656DAE,0x6BCC4985,0x00000000 + long 0x3FFE0000,0x81848DA8,0xFAF0D277,0x00000000 + long 0x3FFE0000,0xAE6D8EE3,0x60BB2468,0x00000000 + long 0x3FFE0000,0x80808080,0x80808081,0x00000000 + long 0x3FFE0000,0xB07197A2,0x3C46C654,0x00000000 + + set ADJK,L_SCR1 + + set X,FP_SCR0 + set XDCARE,X+2 + set XFRAC,X+4 + + set F,FP_SCR1 + set FFRAC,F+4 + + set KLOG2,FP_SCR0 + + set SAVEU,FP_SCR0 + + global slogn +#--ENTRY POINT FOR LOG(X) FOR X FINITE, NON-ZERO, NOT NAN'S +slogn: + fmov.x (%a0),%fp0 # LOAD INPUT + mov.l &0x00000000,ADJK(%a6) + +LOGBGN: +#--FPCR SAVED AND CLEARED, INPUT IS 2^(ADJK)*FP0, FP0 CONTAINS +#--A FINITE, NON-ZERO, NORMALIZED NUMBER. + + mov.l (%a0),%d1 + mov.w 4(%a0),%d1 + + mov.l (%a0),X(%a6) + mov.l 4(%a0),X+4(%a6) + mov.l 8(%a0),X+8(%a6) + + cmp.l %d1,&0 # CHECK IF X IS NEGATIVE + blt.w LOGNEG # LOG OF NEGATIVE ARGUMENT IS INVALID +# X IS POSITIVE, CHECK IF X IS NEAR 1 + cmp.l %d1,&0x3ffef07d # IS X < 15/16? + blt.b LOGMAIN # YES + cmp.l %d1,&0x3fff8841 # IS X > 17/16? + ble.w LOGNEAR1 # NO + +LOGMAIN: +#--THIS SHOULD BE THE USUAL CASE, X NOT VERY CLOSE TO 1 + +#--X = 2^(K) * Y, 1 <= Y < 2. THUS, Y = 1.XXXXXXXX....XX IN BINARY. +#--WE DEFINE F = 1.XXXXXX1, I.E. FIRST 7 BITS OF Y AND ATTACH A 1. +#--THE IDEA IS THAT LOG(X) = K*LOG2 + LOG(Y) +#-- = K*LOG2 + LOG(F) + LOG(1 + (Y-F)/F). +#--NOTE THAT U = (Y-F)/F IS VERY SMALL AND THUS APPROXIMATING +#--LOG(1+U) CAN BE VERY EFFICIENT. +#--ALSO NOTE THAT THE VALUE 1/F IS STORED IN A TABLE SO THAT NO +#--DIVISION IS NEEDED TO CALCULATE (Y-F)/F. + +#--GET K, Y, F, AND ADDRESS OF 1/F. + asr.l &8,%d1 + asr.l &8,%d1 # SHIFTED 16 BITS, BIASED EXPO. OF X + sub.l &0x3FFF,%d1 # THIS IS K + add.l ADJK(%a6),%d1 # ADJUST K, ORIGINAL INPUT MAY BE DENORM. + lea LOGTBL(%pc),%a0 # BASE ADDRESS OF 1/F AND LOG(F) + fmov.l %d1,%fp1 # CONVERT K TO FLOATING-POINT FORMAT + +#--WHILE THE CONVERSION IS GOING ON, WE GET F AND ADDRESS OF 1/F + mov.l &0x3FFF0000,X(%a6) # X IS NOW Y, I.E. 2^(-K)*X + mov.l XFRAC(%a6),FFRAC(%a6) + and.l &0xFE000000,FFRAC(%a6) # FIRST 7 BITS OF Y + or.l &0x01000000,FFRAC(%a6) # GET F: ATTACH A 1 AT THE EIGHTH BIT + mov.l FFRAC(%a6),%d1 # READY TO GET ADDRESS OF 1/F + and.l &0x7E000000,%d1 + asr.l &8,%d1 + asr.l &8,%d1 + asr.l &4,%d1 # SHIFTED 20, D0 IS THE DISPLACEMENT + add.l %d1,%a0 # A0 IS THE ADDRESS FOR 1/F + + fmov.x X(%a6),%fp0 + mov.l &0x3fff0000,F(%a6) + clr.l F+8(%a6) + fsub.x F(%a6),%fp0 # Y-F + fmovm.x &0xc,-(%sp) # SAVE FP2-3 WHILE FP0 IS NOT READY +#--SUMMARY: FP0 IS Y-F, A0 IS ADDRESS OF 1/F, FP1 IS K +#--REGISTERS SAVED: FPCR, FP1, FP2 + +LP1CONT1: +#--AN RE-ENTRY POINT FOR LOGNP1 + fmul.x (%a0),%fp0 # FP0 IS U = (Y-F)/F + fmul.x LOGOF2(%pc),%fp1 # GET K*LOG2 WHILE FP0 IS NOT READY + fmov.x %fp0,%fp2 + fmul.x %fp2,%fp2 # FP2 IS V=U*U + fmov.x %fp1,KLOG2(%a6) # PUT K*LOG2 IN MEMEORY, FREE FP1 + +#--LOG(1+U) IS APPROXIMATED BY +#--U + V*(A1+U*(A2+U*(A3+U*(A4+U*(A5+U*A6))))) WHICH IS +#--[U + V*(A1+V*(A3+V*A5))] + [U*V*(A2+V*(A4+V*A6))] + + fmov.x %fp2,%fp3 + fmov.x %fp2,%fp1 + + fmul.d LOGA6(%pc),%fp1 # V*A6 + fmul.d LOGA5(%pc),%fp2 # V*A5 + + fadd.d LOGA4(%pc),%fp1 # A4+V*A6 + fadd.d LOGA3(%pc),%fp2 # A3+V*A5 + + fmul.x %fp3,%fp1 # V*(A4+V*A6) + fmul.x %fp3,%fp2 # V*(A3+V*A5) + + fadd.d LOGA2(%pc),%fp1 # A2+V*(A4+V*A6) + fadd.d LOGA1(%pc),%fp2 # A1+V*(A3+V*A5) + + fmul.x %fp3,%fp1 # V*(A2+V*(A4+V*A6)) + add.l &16,%a0 # ADDRESS OF LOG(F) + fmul.x %fp3,%fp2 # V*(A1+V*(A3+V*A5)) + + fmul.x %fp0,%fp1 # U*V*(A2+V*(A4+V*A6)) + fadd.x %fp2,%fp0 # U+V*(A1+V*(A3+V*A5)) + + fadd.x (%a0),%fp1 # LOG(F)+U*V*(A2+V*(A4+V*A6)) + fmovm.x (%sp)+,&0x30 # RESTORE FP2-3 + fadd.x %fp1,%fp0 # FP0 IS LOG(F) + LOG(1+U) + + fmov.l %d0,%fpcr + fadd.x KLOG2(%a6),%fp0 # FINAL ADD + bra t_inx2 + + +LOGNEAR1: + +# if the input is exactly equal to one, then exit through ld_pzero. +# if these 2 lines weren't here, the correct answer would be returned +# but the INEX2 bit would be set. + fcmp.b %fp0,&0x1 # is it equal to one? + fbeq.l ld_pzero # yes + +#--REGISTERS SAVED: FPCR, FP1. FP0 CONTAINS THE INPUT. + fmov.x %fp0,%fp1 + fsub.s one(%pc),%fp1 # FP1 IS X-1 + fadd.s one(%pc),%fp0 # FP0 IS X+1 + fadd.x %fp1,%fp1 # FP1 IS 2(X-1) +#--LOG(X) = LOG(1+U/2)-LOG(1-U/2) WHICH IS AN ODD POLYNOMIAL +#--IN U, U = 2(X-1)/(X+1) = FP1/FP0 + +LP1CONT2: +#--THIS IS AN RE-ENTRY POINT FOR LOGNP1 + fdiv.x %fp0,%fp1 # FP1 IS U + fmovm.x &0xc,-(%sp) # SAVE FP2-3 +#--REGISTERS SAVED ARE NOW FPCR,FP1,FP2,FP3 +#--LET V=U*U, W=V*V, CALCULATE +#--U + U*V*(B1 + V*(B2 + V*(B3 + V*(B4 + V*B5)))) BY +#--U + U*V*( [B1 + W*(B3 + W*B5)] + [V*(B2 + W*B4)] ) + fmov.x %fp1,%fp0 + fmul.x %fp0,%fp0 # FP0 IS V + fmov.x %fp1,SAVEU(%a6) # STORE U IN MEMORY, FREE FP1 + fmov.x %fp0,%fp1 + fmul.x %fp1,%fp1 # FP1 IS W + + fmov.d LOGB5(%pc),%fp3 + fmov.d LOGB4(%pc),%fp2 + + fmul.x %fp1,%fp3 # W*B5 + fmul.x %fp1,%fp2 # W*B4 + + fadd.d LOGB3(%pc),%fp3 # B3+W*B5 + fadd.d LOGB2(%pc),%fp2 # B2+W*B4 + + fmul.x %fp3,%fp1 # W*(B3+W*B5), FP3 RELEASED + + fmul.x %fp0,%fp2 # V*(B2+W*B4) + + fadd.d LOGB1(%pc),%fp1 # B1+W*(B3+W*B5) + fmul.x SAVEU(%a6),%fp0 # FP0 IS U*V + + fadd.x %fp2,%fp1 # B1+W*(B3+W*B5) + V*(B2+W*B4), FP2 RELEASED + fmovm.x (%sp)+,&0x30 # FP2-3 RESTORED + + fmul.x %fp1,%fp0 # U*V*( [B1+W*(B3+W*B5)] + [V*(B2+W*B4)] ) + + fmov.l %d0,%fpcr + fadd.x SAVEU(%a6),%fp0 + bra t_inx2 + +#--REGISTERS SAVED FPCR. LOG(-VE) IS INVALID +LOGNEG: + bra t_operr + + global slognd +slognd: +#--ENTRY POINT FOR LOG(X) FOR DENORMALIZED INPUT + + mov.l &-100,ADJK(%a6) # INPUT = 2^(ADJK) * FP0 + +#----normalize the input value by left shifting k bits (k to be determined +#----below), adjusting exponent and storing -k to ADJK +#----the value TWOTO100 is no longer needed. +#----Note that this code assumes the denormalized input is NON-ZERO. + + movm.l &0x3f00,-(%sp) # save some registers {d2-d7} + mov.l (%a0),%d3 # D3 is exponent of smallest norm. # + mov.l 4(%a0),%d4 + mov.l 8(%a0),%d5 # (D4,D5) is (Hi_X,Lo_X) + clr.l %d2 # D2 used for holding K + + tst.l %d4 + bne.b Hi_not0 + +Hi_0: + mov.l %d5,%d4 + clr.l %d5 + mov.l &32,%d2 + clr.l %d6 + bfffo %d4{&0:&32},%d6 + lsl.l %d6,%d4 + add.l %d6,%d2 # (D3,D4,D5) is normalized + + mov.l %d3,X(%a6) + mov.l %d4,XFRAC(%a6) + mov.l %d5,XFRAC+4(%a6) + neg.l %d2 + mov.l %d2,ADJK(%a6) + fmov.x X(%a6),%fp0 + movm.l (%sp)+,&0xfc # restore registers {d2-d7} + lea X(%a6),%a0 + bra.w LOGBGN # begin regular log(X) + +Hi_not0: + clr.l %d6 + bfffo %d4{&0:&32},%d6 # find first 1 + mov.l %d6,%d2 # get k + lsl.l %d6,%d4 + mov.l %d5,%d7 # a copy of D5 + lsl.l %d6,%d5 + neg.l %d6 + add.l &32,%d6 + lsr.l %d6,%d7 + or.l %d7,%d4 # (D3,D4,D5) normalized + + mov.l %d3,X(%a6) + mov.l %d4,XFRAC(%a6) + mov.l %d5,XFRAC+4(%a6) + neg.l %d2 + mov.l %d2,ADJK(%a6) + fmov.x X(%a6),%fp0 + movm.l (%sp)+,&0xfc # restore registers {d2-d7} + lea X(%a6),%a0 + bra.w LOGBGN # begin regular log(X) + + global slognp1 +#--ENTRY POINT FOR LOG(1+X) FOR X FINITE, NON-ZERO, NOT NAN'S +slognp1: + fmov.x (%a0),%fp0 # LOAD INPUT + fabs.x %fp0 # test magnitude + fcmp.x %fp0,LTHOLD(%pc) # compare with min threshold + fbgt.w LP1REAL # if greater, continue + fmov.l %d0,%fpcr + mov.b &FMOV_OP,%d1 # last inst is MOVE + fmov.x (%a0),%fp0 # return signed argument + bra t_catch + +LP1REAL: + fmov.x (%a0),%fp0 # LOAD INPUT + mov.l &0x00000000,ADJK(%a6) + fmov.x %fp0,%fp1 # FP1 IS INPUT Z + fadd.s one(%pc),%fp0 # X := ROUND(1+Z) + fmov.x %fp0,X(%a6) + mov.w XFRAC(%a6),XDCARE(%a6) + mov.l X(%a6),%d1 + cmp.l %d1,&0 + ble.w LP1NEG0 # LOG OF ZERO OR -VE + cmp.l %d1,&0x3ffe8000 # IS BOUNDS [1/2,3/2]? + blt.w LOGMAIN + cmp.l %d1,&0x3fffc000 + bgt.w LOGMAIN +#--IF 1+Z > 3/2 OR 1+Z < 1/2, THEN X, WHICH IS ROUNDING 1+Z, +#--CONTAINS AT LEAST 63 BITS OF INFORMATION OF Z. IN THAT CASE, +#--SIMPLY INVOKE LOG(X) FOR LOG(1+Z). + +LP1NEAR1: +#--NEXT SEE IF EXP(-1/16) < X < EXP(1/16) + cmp.l %d1,&0x3ffef07d + blt.w LP1CARE + cmp.l %d1,&0x3fff8841 + bgt.w LP1CARE + +LP1ONE16: +#--EXP(-1/16) < X < EXP(1/16). LOG(1+Z) = LOG(1+U/2) - LOG(1-U/2) +#--WHERE U = 2Z/(2+Z) = 2Z/(1+X). + fadd.x %fp1,%fp1 # FP1 IS 2Z + fadd.s one(%pc),%fp0 # FP0 IS 1+X +#--U = FP1/FP0 + bra.w LP1CONT2 + +LP1CARE: +#--HERE WE USE THE USUAL TABLE DRIVEN APPROACH. CARE HAS TO BE +#--TAKEN BECAUSE 1+Z CAN HAVE 67 BITS OF INFORMATION AND WE MUST +#--PRESERVE ALL THE INFORMATION. BECAUSE 1+Z IS IN [1/2,3/2], +#--THERE ARE ONLY TWO CASES. +#--CASE 1: 1+Z < 1, THEN K = -1 AND Y-F = (2-F) + 2Z +#--CASE 2: 1+Z > 1, THEN K = 0 AND Y-F = (1-F) + Z +#--ON RETURNING TO LP1CONT1, WE MUST HAVE K IN FP1, ADDRESS OF +#--(1/F) IN A0, Y-F IN FP0, AND FP2 SAVED. + + mov.l XFRAC(%a6),FFRAC(%a6) + and.l &0xFE000000,FFRAC(%a6) + or.l &0x01000000,FFRAC(%a6) # F OBTAINED + cmp.l %d1,&0x3FFF8000 # SEE IF 1+Z > 1 + bge.b KISZERO + +KISNEG1: + fmov.s TWO(%pc),%fp0 + mov.l &0x3fff0000,F(%a6) + clr.l F+8(%a6) + fsub.x F(%a6),%fp0 # 2-F + mov.l FFRAC(%a6),%d1 + and.l &0x7E000000,%d1 + asr.l &8,%d1 + asr.l &8,%d1 + asr.l &4,%d1 # D0 CONTAINS DISPLACEMENT FOR 1/F + fadd.x %fp1,%fp1 # GET 2Z + fmovm.x &0xc,-(%sp) # SAVE FP2 {%fp2/%fp3} + fadd.x %fp1,%fp0 # FP0 IS Y-F = (2-F)+2Z + lea LOGTBL(%pc),%a0 # A0 IS ADDRESS OF 1/F + add.l %d1,%a0 + fmov.s negone(%pc),%fp1 # FP1 IS K = -1 + bra.w LP1CONT1 + +KISZERO: + fmov.s one(%pc),%fp0 + mov.l &0x3fff0000,F(%a6) + clr.l F+8(%a6) + fsub.x F(%a6),%fp0 # 1-F + mov.l FFRAC(%a6),%d1 + and.l &0x7E000000,%d1 + asr.l &8,%d1 + asr.l &8,%d1 + asr.l &4,%d1 + fadd.x %fp1,%fp0 # FP0 IS Y-F + fmovm.x &0xc,-(%sp) # FP2 SAVED {%fp2/%fp3} + lea LOGTBL(%pc),%a0 + add.l %d1,%a0 # A0 IS ADDRESS OF 1/F + fmov.s zero(%pc),%fp1 # FP1 IS K = 0 + bra.w LP1CONT1 + +LP1NEG0: +#--FPCR SAVED. D0 IS X IN COMPACT FORM. + cmp.l %d1,&0 + blt.b LP1NEG +LP1ZERO: + fmov.s negone(%pc),%fp0 + + fmov.l %d0,%fpcr + bra t_dz + +LP1NEG: + fmov.s zero(%pc),%fp0 + + fmov.l %d0,%fpcr + bra t_operr + + global slognp1d +#--ENTRY POINT FOR LOG(1+Z) FOR DENORMALIZED INPUT +# Simply return the denorm +slognp1d: + bra t_extdnrm + +######################################################################### +# satanh(): computes the inverse hyperbolic tangent of a norm input # +# satanhd(): computes the inverse hyperbolic tangent of a denorm input # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input # +# d0 = round precision,mode # +# # +# OUTPUT ************************************************************** # +# fp0 = arctanh(X) # +# # +# ACCURACY and MONOTONICITY ******************************************* # +# The returned result is within 3 ulps in 64 significant bit, # +# i.e. within 0.5001 ulp to 53 bits if the result is subsequently # +# rounded to double precision. The result is provably monotonic # +# in double precision. # +# # +# ALGORITHM *********************************************************** # +# # +# ATANH # +# 1. If |X| >= 1, go to 3. # +# # +# 2. (|X| < 1) Calculate atanh(X) by # +# sgn := sign(X) # +# y := |X| # +# z := 2y/(1-y) # +# atanh(X) := sgn * (1/2) * logp1(z) # +# Exit. # +# # +# 3. If |X| > 1, go to 5. # +# # +# 4. (|X| = 1) Generate infinity with an appropriate sign and # +# divide-by-zero by # +# sgn := sign(X) # +# atan(X) := sgn / (+0). # +# Exit. # +# # +# 5. (|X| > 1) Generate an invalid operation by 0 * infinity. # +# Exit. # +# # +######################################################################### + + global satanh +satanh: + mov.l (%a0),%d1 + mov.w 4(%a0),%d1 + and.l &0x7FFFFFFF,%d1 + cmp.l %d1,&0x3FFF8000 + bge.b ATANHBIG + +#--THIS IS THE USUAL CASE, |X| < 1 +#--Y = |X|, Z = 2Y/(1-Y), ATANH(X) = SIGN(X) * (1/2) * LOG1P(Z). + + fabs.x (%a0),%fp0 # Y = |X| + fmov.x %fp0,%fp1 + fneg.x %fp1 # -Y + fadd.x %fp0,%fp0 # 2Y + fadd.s &0x3F800000,%fp1 # 1-Y + fdiv.x %fp1,%fp0 # 2Y/(1-Y) + mov.l (%a0),%d1 + and.l &0x80000000,%d1 + or.l &0x3F000000,%d1 # SIGN(X)*HALF + mov.l %d1,-(%sp) + + mov.l %d0,-(%sp) # save rnd prec,mode + clr.l %d0 # pass ext prec,RN + fmovm.x &0x01,-(%sp) # save Z on stack + lea (%sp),%a0 # pass ptr to Z + bsr slognp1 # LOG1P(Z) + add.l &0xc,%sp # clear Z from stack + + mov.l (%sp)+,%d0 # fetch old prec,mode + fmov.l %d0,%fpcr # load it + mov.b &FMUL_OP,%d1 # last inst is MUL + fmul.s (%sp)+,%fp0 + bra t_catch + +ATANHBIG: + fabs.x (%a0),%fp0 # |X| + fcmp.s %fp0,&0x3F800000 + fbgt t_operr + bra t_dz + + global satanhd +#--ATANH(X) = X FOR DENORMALIZED X +satanhd: + bra t_extdnrm + +######################################################################### +# slog10(): computes the base-10 logarithm of a normalized input # +# slog10d(): computes the base-10 logarithm of a denormalized input # +# slog2(): computes the base-2 logarithm of a normalized input # +# slog2d(): computes the base-2 logarithm of a denormalized input # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input # +# d0 = round precision,mode # +# # +# OUTPUT ************************************************************** # +# fp0 = log_10(X) or log_2(X) # +# # +# ACCURACY and MONOTONICITY ******************************************* # +# The returned result is within 1.7 ulps in 64 significant bit, # +# i.e. within 0.5003 ulp to 53 bits if the result is subsequently # +# rounded to double precision. The result is provably monotonic # +# in double precision. # +# # +# ALGORITHM *********************************************************** # +# # +# slog10d: # +# # +# Step 0. If X < 0, create a NaN and raise the invalid operation # +# flag. Otherwise, save FPCR in D1; set FpCR to default. # +# Notes: Default means round-to-nearest mode, no floating-point # +# traps, and precision control = double extended. # +# # +# Step 1. Call slognd to obtain Y = log(X), the natural log of X. # +# Notes: Even if X is denormalized, log(X) is always normalized. # +# # +# Step 2. Compute log_10(X) = log(X) * (1/log(10)). # +# 2.1 Restore the user FPCR # +# 2.2 Return ans := Y * INV_L10. # +# # +# slog10: # +# # +# Step 0. If X < 0, create a NaN and raise the invalid operation # +# flag. Otherwise, save FPCR in D1; set FpCR to default. # +# Notes: Default means round-to-nearest mode, no floating-point # +# traps, and precision control = double extended. # +# # +# Step 1. Call sLogN to obtain Y = log(X), the natural log of X. # +# # +# Step 2. Compute log_10(X) = log(X) * (1/log(10)). # +# 2.1 Restore the user FPCR # +# 2.2 Return ans := Y * INV_L10. # +# # +# sLog2d: # +# # +# Step 0. If X < 0, create a NaN and raise the invalid operation # +# flag. Otherwise, save FPCR in D1; set FpCR to default. # +# Notes: Default means round-to-nearest mode, no floating-point # +# traps, and precision control = double extended. # +# # +# Step 1. Call slognd to obtain Y = log(X), the natural log of X. # +# Notes: Even if X is denormalized, log(X) is always normalized. # +# # +# Step 2. Compute log_10(X) = log(X) * (1/log(2)). # +# 2.1 Restore the user FPCR # +# 2.2 Return ans := Y * INV_L2. # +# # +# sLog2: # +# # +# Step 0. If X < 0, create a NaN and raise the invalid operation # +# flag. Otherwise, save FPCR in D1; set FpCR to default. # +# Notes: Default means round-to-nearest mode, no floating-point # +# traps, and precision control = double extended. # +# # +# Step 1. If X is not an integer power of two, i.e., X != 2^k, # +# go to Step 3. # +# # +# Step 2. Return k. # +# 2.1 Get integer k, X = 2^k. # +# 2.2 Restore the user FPCR. # +# 2.3 Return ans := convert-to-double-extended(k). # +# # +# Step 3. Call sLogN to obtain Y = log(X), the natural log of X. # +# # +# Step 4. Compute log_2(X) = log(X) * (1/log(2)). # +# 4.1 Restore the user FPCR # +# 4.2 Return ans := Y * INV_L2. # +# # +######################################################################### + +INV_L10: + long 0x3FFD0000,0xDE5BD8A9,0x37287195,0x00000000 + +INV_L2: + long 0x3FFF0000,0xB8AA3B29,0x5C17F0BC,0x00000000 + + global slog10 +#--entry point for Log10(X), X is normalized +slog10: + fmov.b &0x1,%fp0 + fcmp.x %fp0,(%a0) # if operand == 1, + fbeq.l ld_pzero # return an EXACT zero + + mov.l (%a0),%d1 + blt.w invalid + mov.l %d0,-(%sp) + clr.l %d0 + bsr slogn # log(X), X normal. + fmov.l (%sp)+,%fpcr + fmul.x INV_L10(%pc),%fp0 + bra t_inx2 + + global slog10d +#--entry point for Log10(X), X is denormalized +slog10d: + mov.l (%a0),%d1 + blt.w invalid + mov.l %d0,-(%sp) + clr.l %d0 + bsr slognd # log(X), X denorm. + fmov.l (%sp)+,%fpcr + fmul.x INV_L10(%pc),%fp0 + bra t_minx2 + + global slog2 +#--entry point for Log2(X), X is normalized +slog2: + mov.l (%a0),%d1 + blt.w invalid + + mov.l 8(%a0),%d1 + bne.b continue # X is not 2^k + + mov.l 4(%a0),%d1 + and.l &0x7FFFFFFF,%d1 + bne.b continue + +#--X = 2^k. + mov.w (%a0),%d1 + and.l &0x00007FFF,%d1 + sub.l &0x3FFF,%d1 + beq.l ld_pzero + fmov.l %d0,%fpcr + fmov.l %d1,%fp0 + bra t_inx2 + +continue: + mov.l %d0,-(%sp) + clr.l %d0 + bsr slogn # log(X), X normal. + fmov.l (%sp)+,%fpcr + fmul.x INV_L2(%pc),%fp0 + bra t_inx2 + +invalid: + bra t_operr + + global slog2d +#--entry point for Log2(X), X is denormalized +slog2d: + mov.l (%a0),%d1 + blt.w invalid + mov.l %d0,-(%sp) + clr.l %d0 + bsr slognd # log(X), X denorm. + fmov.l (%sp)+,%fpcr + fmul.x INV_L2(%pc),%fp0 + bra t_minx2 + +######################################################################### +# stwotox(): computes 2**X for a normalized input # +# stwotoxd(): computes 2**X for a denormalized input # +# stentox(): computes 10**X for a normalized input # +# stentoxd(): computes 10**X for a denormalized input # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input # +# d0 = round precision,mode # +# # +# OUTPUT ************************************************************** # +# fp0 = 2**X or 10**X # +# # +# ACCURACY and MONOTONICITY ******************************************* # +# The returned result is within 2 ulps in 64 significant bit, # +# i.e. within 0.5001 ulp to 53 bits if the result is subsequently # +# rounded to double precision. The result is provably monotonic # +# in double precision. # +# # +# ALGORITHM *********************************************************** # +# # +# twotox # +# 1. If |X| > 16480, go to ExpBig. # +# # +# 2. If |X| < 2**(-70), go to ExpSm. # +# # +# 3. Decompose X as X = N/64 + r where |r| <= 1/128. Furthermore # +# decompose N as # +# N = 64(M + M') + j, j = 0,1,2,...,63. # +# # +# 4. Overwrite r := r * log2. Then # +# 2**X = 2**(M') * 2**(M) * 2**(j/64) * exp(r). # +# Go to expr to compute that expression. # +# # +# tentox # +# 1. If |X| > 16480*log_10(2) (base 10 log of 2), go to ExpBig. # +# # +# 2. If |X| < 2**(-70), go to ExpSm. # +# # +# 3. Set y := X*log_2(10)*64 (base 2 log of 10). Set # +# N := round-to-int(y). Decompose N as # +# N = 64(M + M') + j, j = 0,1,2,...,63. # +# # +# 4. Define r as # +# r := ((X - N*L1)-N*L2) * L10 # +# where L1, L2 are the leading and trailing parts of # +# log_10(2)/64 and L10 is the natural log of 10. Then # +# 10**X = 2**(M') * 2**(M) * 2**(j/64) * exp(r). # +# Go to expr to compute that expression. # +# # +# expr # +# 1. Fetch 2**(j/64) from table as Fact1 and Fact2. # +# # +# 2. Overwrite Fact1 and Fact2 by # +# Fact1 := 2**(M) * Fact1 # +# Fact2 := 2**(M) * Fact2 # +# Thus Fact1 + Fact2 = 2**(M) * 2**(j/64). # +# # +# 3. Calculate P where 1 + P approximates exp(r): # +# P = r + r*r*(A1+r*(A2+...+r*A5)). # +# # +# 4. Let AdjFact := 2**(M'). Return # +# AdjFact * ( Fact1 + ((Fact1*P) + Fact2) ). # +# Exit. # +# # +# ExpBig # +# 1. Generate overflow by Huge * Huge if X > 0; otherwise, # +# generate underflow by Tiny * Tiny. # +# # +# ExpSm # +# 1. Return 1 + X. # +# # +######################################################################### + +L2TEN64: + long 0x406A934F,0x0979A371 # 64LOG10/LOG2 +L10TWO1: + long 0x3F734413,0x509F8000 # LOG2/64LOG10 + +L10TWO2: + long 0xBFCD0000,0xC0219DC1,0xDA994FD2,0x00000000 + +LOG10: long 0x40000000,0x935D8DDD,0xAAA8AC17,0x00000000 + +LOG2: long 0x3FFE0000,0xB17217F7,0xD1CF79AC,0x00000000 + +EXPA5: long 0x3F56C16D,0x6F7BD0B2 +EXPA4: long 0x3F811112,0x302C712C +EXPA3: long 0x3FA55555,0x55554CC1 +EXPA2: long 0x3FC55555,0x55554A54 +EXPA1: long 0x3FE00000,0x00000000,0x00000000,0x00000000 + +TEXPTBL: + long 0x3FFF0000,0x80000000,0x00000000,0x3F738000 + long 0x3FFF0000,0x8164D1F3,0xBC030773,0x3FBEF7CA + long 0x3FFF0000,0x82CD8698,0xAC2BA1D7,0x3FBDF8A9 + long 0x3FFF0000,0x843A28C3,0xACDE4046,0x3FBCD7C9 + long 0x3FFF0000,0x85AAC367,0xCC487B15,0xBFBDE8DA + long 0x3FFF0000,0x871F6196,0x9E8D1010,0x3FBDE85C + long 0x3FFF0000,0x88980E80,0x92DA8527,0x3FBEBBF1 + long 0x3FFF0000,0x8A14D575,0x496EFD9A,0x3FBB80CA + long 0x3FFF0000,0x8B95C1E3,0xEA8BD6E7,0xBFBA8373 + long 0x3FFF0000,0x8D1ADF5B,0x7E5BA9E6,0xBFBE9670 + long 0x3FFF0000,0x8EA4398B,0x45CD53C0,0x3FBDB700 + long 0x3FFF0000,0x9031DC43,0x1466B1DC,0x3FBEEEB0 + long 0x3FFF0000,0x91C3D373,0xAB11C336,0x3FBBFD6D + long 0x3FFF0000,0x935A2B2F,0x13E6E92C,0xBFBDB319 + long 0x3FFF0000,0x94F4EFA8,0xFEF70961,0x3FBDBA2B + long 0x3FFF0000,0x96942D37,0x20185A00,0x3FBE91D5 + long 0x3FFF0000,0x9837F051,0x8DB8A96F,0x3FBE8D5A + long 0x3FFF0000,0x99E04593,0x20B7FA65,0xBFBCDE7B + long 0x3FFF0000,0x9B8D39B9,0xD54E5539,0xBFBEBAAF + long 0x3FFF0000,0x9D3ED9A7,0x2CFFB751,0xBFBD86DA + long 0x3FFF0000,0x9EF53260,0x91A111AE,0xBFBEBEDD + long 0x3FFF0000,0xA0B0510F,0xB9714FC2,0x3FBCC96E + long 0x3FFF0000,0xA2704303,0x0C496819,0xBFBEC90B + long 0x3FFF0000,0xA43515AE,0x09E6809E,0x3FBBD1DB + long 0x3FFF0000,0xA5FED6A9,0xB15138EA,0x3FBCE5EB + long 0x3FFF0000,0xA7CD93B4,0xE965356A,0xBFBEC274 + long 0x3FFF0000,0xA9A15AB4,0xEA7C0EF8,0x3FBEA83C + long 0x3FFF0000,0xAB7A39B5,0xA93ED337,0x3FBECB00 + long 0x3FFF0000,0xAD583EEA,0x42A14AC6,0x3FBE9301 + long 0x3FFF0000,0xAF3B78AD,0x690A4375,0xBFBD8367 + long 0x3FFF0000,0xB123F581,0xD2AC2590,0xBFBEF05F + long 0x3FFF0000,0xB311C412,0xA9112489,0x3FBDFB3C + long 0x3FFF0000,0xB504F333,0xF9DE6484,0x3FBEB2FB + long 0x3FFF0000,0xB6FD91E3,0x28D17791,0x3FBAE2CB + long 0x3FFF0000,0xB8FBAF47,0x62FB9EE9,0x3FBCDC3C + long 0x3FFF0000,0xBAFF5AB2,0x133E45FB,0x3FBEE9AA + long 0x3FFF0000,0xBD08A39F,0x580C36BF,0xBFBEAEFD + long 0x3FFF0000,0xBF1799B6,0x7A731083,0xBFBCBF51 + long 0x3FFF0000,0xC12C4CCA,0x66709456,0x3FBEF88A + long 0x3FFF0000,0xC346CCDA,0x24976407,0x3FBD83B2 + long 0x3FFF0000,0xC5672A11,0x5506DADD,0x3FBDF8AB + long 0x3FFF0000,0xC78D74C8,0xABB9B15D,0xBFBDFB17 + long 0x3FFF0000,0xC9B9BD86,0x6E2F27A3,0xBFBEFE3C + long 0x3FFF0000,0xCBEC14FE,0xF2727C5D,0xBFBBB6F8 + long 0x3FFF0000,0xCE248C15,0x1F8480E4,0xBFBCEE53 + long 0x3FFF0000,0xD06333DA,0xEF2B2595,0xBFBDA4AE + long 0x3FFF0000,0xD2A81D91,0xF12AE45A,0x3FBC9124 + long 0x3FFF0000,0xD4F35AAB,0xCFEDFA1F,0x3FBEB243 + long 0x3FFF0000,0xD744FCCA,0xD69D6AF4,0x3FBDE69A + long 0x3FFF0000,0xD99D15C2,0x78AFD7B6,0xBFB8BC61 + long 0x3FFF0000,0xDBFBB797,0xDAF23755,0x3FBDF610 + long 0x3FFF0000,0xDE60F482,0x5E0E9124,0xBFBD8BE1 + long 0x3FFF0000,0xE0CCDEEC,0x2A94E111,0x3FBACB12 + long 0x3FFF0000,0xE33F8972,0xBE8A5A51,0x3FBB9BFE + long 0x3FFF0000,0xE5B906E7,0x7C8348A8,0x3FBCF2F4 + long 0x3FFF0000,0xE8396A50,0x3C4BDC68,0x3FBEF22F + long 0x3FFF0000,0xEAC0C6E7,0xDD24392F,0xBFBDBF4A + long 0x3FFF0000,0xED4F301E,0xD9942B84,0x3FBEC01A + long 0x3FFF0000,0xEFE4B99B,0xDCDAF5CB,0x3FBE8CAC + long 0x3FFF0000,0xF281773C,0x59FFB13A,0xBFBCBB3F + long 0x3FFF0000,0xF5257D15,0x2486CC2C,0x3FBEF73A + long 0x3FFF0000,0xF7D0DF73,0x0AD13BB9,0xBFB8B795 + long 0x3FFF0000,0xFA83B2DB,0x722A033A,0x3FBEF84B + long 0x3FFF0000,0xFD3E0C0C,0xF486C175,0xBFBEF581 + + set INT,L_SCR1 + + set X,FP_SCR0 + set XDCARE,X+2 + set XFRAC,X+4 + + set ADJFACT,FP_SCR0 + + set FACT1,FP_SCR0 + set FACT1HI,FACT1+4 + set FACT1LOW,FACT1+8 + + set FACT2,FP_SCR1 + set FACT2HI,FACT2+4 + set FACT2LOW,FACT2+8 + + global stwotox +#--ENTRY POINT FOR 2**(X), HERE X IS FINITE, NON-ZERO, AND NOT NAN'S +stwotox: + fmovm.x (%a0),&0x80 # LOAD INPUT + + mov.l (%a0),%d1 + mov.w 4(%a0),%d1 + fmov.x %fp0,X(%a6) + and.l &0x7FFFFFFF,%d1 + + cmp.l %d1,&0x3FB98000 # |X| >= 2**(-70)? + bge.b TWOOK1 + bra.w EXPBORS + +TWOOK1: + cmp.l %d1,&0x400D80C0 # |X| > 16480? + ble.b TWOMAIN + bra.w EXPBORS + +TWOMAIN: +#--USUAL CASE, 2^(-70) <= |X| <= 16480 + + fmov.x %fp0,%fp1 + fmul.s &0x42800000,%fp1 # 64 * X + fmov.l %fp1,INT(%a6) # N = ROUND-TO-INT(64 X) + mov.l %d2,-(%sp) + lea TEXPTBL(%pc),%a1 # LOAD ADDRESS OF TABLE OF 2^(J/64) + fmov.l INT(%a6),%fp1 # N --> FLOATING FMT + mov.l INT(%a6),%d1 + mov.l %d1,%d2 + and.l &0x3F,%d1 # D0 IS J + asl.l &4,%d1 # DISPLACEMENT FOR 2^(J/64) + add.l %d1,%a1 # ADDRESS FOR 2^(J/64) + asr.l &6,%d2 # d2 IS L, N = 64L + J + mov.l %d2,%d1 + asr.l &1,%d1 # D0 IS M + sub.l %d1,%d2 # d2 IS M', N = 64(M+M') + J + add.l &0x3FFF,%d2 + +#--SUMMARY: a1 IS ADDRESS FOR THE LEADING PORTION OF 2^(J/64), +#--D0 IS M WHERE N = 64(M+M') + J. NOTE THAT |M| <= 16140 BY DESIGN. +#--ADJFACT = 2^(M'). +#--REGISTERS SAVED SO FAR ARE (IN ORDER) FPCR, D0, FP1, a1, AND FP2. + + fmovm.x &0x0c,-(%sp) # save fp2/fp3 + + fmul.s &0x3C800000,%fp1 # (1/64)*N + mov.l (%a1)+,FACT1(%a6) + mov.l (%a1)+,FACT1HI(%a6) + mov.l (%a1)+,FACT1LOW(%a6) + mov.w (%a1)+,FACT2(%a6) + + fsub.x %fp1,%fp0 # X - (1/64)*INT(64 X) + + mov.w (%a1)+,FACT2HI(%a6) + clr.w FACT2HI+2(%a6) + clr.l FACT2LOW(%a6) + add.w %d1,FACT1(%a6) + fmul.x LOG2(%pc),%fp0 # FP0 IS R + add.w %d1,FACT2(%a6) + + bra.w expr + +EXPBORS: +#--FPCR, D0 SAVED + cmp.l %d1,&0x3FFF8000 + bgt.b TEXPBIG + +#--|X| IS SMALL, RETURN 1 + X + + fmov.l %d0,%fpcr # restore users round prec,mode + fadd.s &0x3F800000,%fp0 # RETURN 1 + X + bra t_pinx2 + +TEXPBIG: +#--|X| IS LARGE, GENERATE OVERFLOW IF X > 0; ELSE GENERATE UNDERFLOW +#--REGISTERS SAVE SO FAR ARE FPCR AND D0 + mov.l X(%a6),%d1 + cmp.l %d1,&0 + blt.b EXPNEG + + bra t_ovfl2 # t_ovfl expects positive value + +EXPNEG: + bra t_unfl2 # t_unfl expects positive value + + global stwotoxd +stwotoxd: +#--ENTRY POINT FOR 2**(X) FOR DENORMALIZED ARGUMENT + + fmov.l %d0,%fpcr # set user's rounding mode/precision + fmov.s &0x3F800000,%fp0 # RETURN 1 + X + mov.l (%a0),%d1 + or.l &0x00800001,%d1 + fadd.s %d1,%fp0 + bra t_pinx2 + + global stentox +#--ENTRY POINT FOR 10**(X), HERE X IS FINITE, NON-ZERO, AND NOT NAN'S +stentox: + fmovm.x (%a0),&0x80 # LOAD INPUT + + mov.l (%a0),%d1 + mov.w 4(%a0),%d1 + fmov.x %fp0,X(%a6) + and.l &0x7FFFFFFF,%d1 + + cmp.l %d1,&0x3FB98000 # |X| >= 2**(-70)? + bge.b TENOK1 + bra.w EXPBORS + +TENOK1: + cmp.l %d1,&0x400B9B07 # |X| <= 16480*log2/log10 ? + ble.b TENMAIN + bra.w EXPBORS + +TENMAIN: +#--USUAL CASE, 2^(-70) <= |X| <= 16480 LOG 2 / LOG 10 + + fmov.x %fp0,%fp1 + fmul.d L2TEN64(%pc),%fp1 # X*64*LOG10/LOG2 + fmov.l %fp1,INT(%a6) # N=INT(X*64*LOG10/LOG2) + mov.l %d2,-(%sp) + lea TEXPTBL(%pc),%a1 # LOAD ADDRESS OF TABLE OF 2^(J/64) + fmov.l INT(%a6),%fp1 # N --> FLOATING FMT + mov.l INT(%a6),%d1 + mov.l %d1,%d2 + and.l &0x3F,%d1 # D0 IS J + asl.l &4,%d1 # DISPLACEMENT FOR 2^(J/64) + add.l %d1,%a1 # ADDRESS FOR 2^(J/64) + asr.l &6,%d2 # d2 IS L, N = 64L + J + mov.l %d2,%d1 + asr.l &1,%d1 # D0 IS M + sub.l %d1,%d2 # d2 IS M', N = 64(M+M') + J + add.l &0x3FFF,%d2 + +#--SUMMARY: a1 IS ADDRESS FOR THE LEADING PORTION OF 2^(J/64), +#--D0 IS M WHERE N = 64(M+M') + J. NOTE THAT |M| <= 16140 BY DESIGN. +#--ADJFACT = 2^(M'). +#--REGISTERS SAVED SO FAR ARE (IN ORDER) FPCR, D0, FP1, a1, AND FP2. + fmovm.x &0x0c,-(%sp) # save fp2/fp3 + + fmov.x %fp1,%fp2 + + fmul.d L10TWO1(%pc),%fp1 # N*(LOG2/64LOG10)_LEAD + mov.l (%a1)+,FACT1(%a6) + + fmul.x L10TWO2(%pc),%fp2 # N*(LOG2/64LOG10)_TRAIL + + mov.l (%a1)+,FACT1HI(%a6) + mov.l (%a1)+,FACT1LOW(%a6) + fsub.x %fp1,%fp0 # X - N L_LEAD + mov.w (%a1)+,FACT2(%a6) + + fsub.x %fp2,%fp0 # X - N L_TRAIL + + mov.w (%a1)+,FACT2HI(%a6) + clr.w FACT2HI+2(%a6) + clr.l FACT2LOW(%a6) + + fmul.x LOG10(%pc),%fp0 # FP0 IS R + add.w %d1,FACT1(%a6) + add.w %d1,FACT2(%a6) + +expr: +#--FPCR, FP2, FP3 ARE SAVED IN ORDER AS SHOWN. +#--ADJFACT CONTAINS 2**(M'), FACT1 + FACT2 = 2**(M) * 2**(J/64). +#--FP0 IS R. THE FOLLOWING CODE COMPUTES +#-- 2**(M'+M) * 2**(J/64) * EXP(R) + + fmov.x %fp0,%fp1 + fmul.x %fp1,%fp1 # FP1 IS S = R*R + + fmov.d EXPA5(%pc),%fp2 # FP2 IS A5 + fmov.d EXPA4(%pc),%fp3 # FP3 IS A4 + + fmul.x %fp1,%fp2 # FP2 IS S*A5 + fmul.x %fp1,%fp3 # FP3 IS S*A4 + + fadd.d EXPA3(%pc),%fp2 # FP2 IS A3+S*A5 + fadd.d EXPA2(%pc),%fp3 # FP3 IS A2+S*A4 + + fmul.x %fp1,%fp2 # FP2 IS S*(A3+S*A5) + fmul.x %fp1,%fp3 # FP3 IS S*(A2+S*A4) + + fadd.d EXPA1(%pc),%fp2 # FP2 IS A1+S*(A3+S*A5) + fmul.x %fp0,%fp3 # FP3 IS R*S*(A2+S*A4) + + fmul.x %fp1,%fp2 # FP2 IS S*(A1+S*(A3+S*A5)) + fadd.x %fp3,%fp0 # FP0 IS R+R*S*(A2+S*A4) + fadd.x %fp2,%fp0 # FP0 IS EXP(R) - 1 + + fmovm.x (%sp)+,&0x30 # restore fp2/fp3 + +#--FINAL RECONSTRUCTION PROCESS +#--EXP(X) = 2^M*2^(J/64) + 2^M*2^(J/64)*(EXP(R)-1) - (1 OR 0) + + fmul.x FACT1(%a6),%fp0 + fadd.x FACT2(%a6),%fp0 + fadd.x FACT1(%a6),%fp0 + + fmov.l %d0,%fpcr # restore users round prec,mode + mov.w %d2,ADJFACT(%a6) # INSERT EXPONENT + mov.l (%sp)+,%d2 + mov.l &0x80000000,ADJFACT+4(%a6) + clr.l ADJFACT+8(%a6) + mov.b &FMUL_OP,%d1 # last inst is MUL + fmul.x ADJFACT(%a6),%fp0 # FINAL ADJUSTMENT + bra t_catch + + global stentoxd +stentoxd: +#--ENTRY POINT FOR 10**(X) FOR DENORMALIZED ARGUMENT + + fmov.l %d0,%fpcr # set user's rounding mode/precision + fmov.s &0x3F800000,%fp0 # RETURN 1 + X + mov.l (%a0),%d1 + or.l &0x00800001,%d1 + fadd.s %d1,%fp0 + bra t_pinx2 + +######################################################################### +# sscale(): computes the destination operand scaled by the source # +# operand. If the absoulute value of the source operand is # +# >= 2^14, an overflow or underflow is returned. # +# # +# INPUT *************************************************************** # +# a0 = pointer to double-extended source operand X # +# a1 = pointer to double-extended destination operand Y # +# # +# OUTPUT ************************************************************** # +# fp0 = scale(X,Y) # +# # +######################################################################### + +set SIGN, L_SCR1 + + global sscale +sscale: + mov.l %d0,-(%sp) # store off ctrl bits for now + + mov.w DST_EX(%a1),%d1 # get dst exponent + smi.b SIGN(%a6) # use SIGN to hold dst sign + andi.l &0x00007fff,%d1 # strip sign from dst exp + + mov.w SRC_EX(%a0),%d0 # check src bounds + andi.w &0x7fff,%d0 # clr src sign bit + cmpi.w %d0,&0x3fff # is src ~ ZERO? + blt.w src_small # yes + cmpi.w %d0,&0x400c # no; is src too big? + bgt.w src_out # yes + +# +# Source is within 2^14 range. +# +src_ok: + fintrz.x SRC(%a0),%fp0 # calc int of src + fmov.l %fp0,%d0 # int src to d0 +# don't want any accrued bits from the fintrz showing up later since +# we may need to read the fpsr for the last fp op in t_catch2(). + fmov.l &0x0,%fpsr + + tst.b DST_HI(%a1) # is dst denormalized? + bmi.b sok_norm + +# the dst is a DENORM. normalize the DENORM and add the adjustment to +# the src value. then, jump to the norm part of the routine. +sok_dnrm: + mov.l %d0,-(%sp) # save src for now + + mov.w DST_EX(%a1),FP_SCR0_EX(%a6) # make a copy + mov.l DST_HI(%a1),FP_SCR0_HI(%a6) + mov.l DST_LO(%a1),FP_SCR0_LO(%a6) + + lea FP_SCR0(%a6),%a0 # pass ptr to DENORM + bsr.l norm # normalize the DENORM + neg.l %d0 + add.l (%sp)+,%d0 # add adjustment to src + + fmovm.x FP_SCR0(%a6),&0x80 # load normalized DENORM + + cmpi.w %d0,&-0x3fff # is the shft amt really low? + bge.b sok_norm2 # thank goodness no + +# the multiply factor that we're trying to create should be a denorm +# for the multiply to work. therefore, we're going to actually do a +# multiply with a denorm which will cause an unimplemented data type +# exception to be put into the machine which will be caught and corrected +# later. we don't do this with the DENORMs above because this method +# is slower. but, don't fret, I don't see it being used much either. + fmov.l (%sp)+,%fpcr # restore user fpcr + mov.l &0x80000000,%d1 # load normalized mantissa + subi.l &-0x3fff,%d0 # how many should we shift? + neg.l %d0 # make it positive + cmpi.b %d0,&0x20 # is it > 32? + bge.b sok_dnrm_32 # yes + lsr.l %d0,%d1 # no; bit stays in upper lw + clr.l -(%sp) # insert zero low mantissa + mov.l %d1,-(%sp) # insert new high mantissa + clr.l -(%sp) # make zero exponent + bra.b sok_norm_cont +sok_dnrm_32: + subi.b &0x20,%d0 # get shift count + lsr.l %d0,%d1 # make low mantissa longword + mov.l %d1,-(%sp) # insert new low mantissa + clr.l -(%sp) # insert zero high mantissa + clr.l -(%sp) # make zero exponent + bra.b sok_norm_cont + +# the src will force the dst to a DENORM value or worse. so, let's +# create an fp multiply that will create the result. +sok_norm: + fmovm.x DST(%a1),&0x80 # load fp0 with normalized src +sok_norm2: + fmov.l (%sp)+,%fpcr # restore user fpcr + + addi.w &0x3fff,%d0 # turn src amt into exp value + swap %d0 # put exponent in high word + clr.l -(%sp) # insert new exponent + mov.l &0x80000000,-(%sp) # insert new high mantissa + mov.l %d0,-(%sp) # insert new lo mantissa + +sok_norm_cont: + fmov.l %fpcr,%d0 # d0 needs fpcr for t_catch2 + mov.b &FMUL_OP,%d1 # last inst is MUL + fmul.x (%sp)+,%fp0 # do the multiply + bra t_catch2 # catch any exceptions + +# +# Source is outside of 2^14 range. Test the sign and branch +# to the appropriate exception handler. +# +src_out: + mov.l (%sp)+,%d0 # restore ctrl bits + exg %a0,%a1 # swap src,dst ptrs + tst.b SRC_EX(%a1) # is src negative? + bmi t_unfl # yes; underflow + bra t_ovfl_sc # no; overflow + +# +# The source input is below 1, so we check for denormalized numbers +# and set unfl. +# +src_small: + tst.b DST_HI(%a1) # is dst denormalized? + bpl.b ssmall_done # yes + + mov.l (%sp)+,%d0 + fmov.l %d0,%fpcr # no; load control bits + mov.b &FMOV_OP,%d1 # last inst is MOVE + fmov.x DST(%a1),%fp0 # simply return dest + bra t_catch2 +ssmall_done: + mov.l (%sp)+,%d0 # load control bits into d1 + mov.l %a1,%a0 # pass ptr to dst + bra t_resdnrm + +######################################################################### +# smod(): computes the fp MOD of the input values X,Y. # +# srem(): computes the fp (IEEE) REM of the input values X,Y. # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input X # +# a1 = pointer to extended precision input Y # +# d0 = round precision,mode # +# # +# The input operands X and Y can be either normalized or # +# denormalized. # +# # +# OUTPUT ************************************************************** # +# fp0 = FREM(X,Y) or FMOD(X,Y) # +# # +# ALGORITHM *********************************************************** # +# # +# Step 1. Save and strip signs of X and Y: signX := sign(X), # +# signY := sign(Y), X := |X|, Y := |Y|, # +# signQ := signX EOR signY. Record whether MOD or REM # +# is requested. # +# # +# Step 2. Set L := expo(X)-expo(Y), k := 0, Q := 0. # +# If (L < 0) then # +# R := X, go to Step 4. # +# else # +# R := 2^(-L)X, j := L. # +# endif # +# # +# Step 3. Perform MOD(X,Y) # +# 3.1 If R = Y, go to Step 9. # +# 3.2 If R > Y, then { R := R - Y, Q := Q + 1} # +# 3.3 If j = 0, go to Step 4. # +# 3.4 k := k + 1, j := j - 1, Q := 2Q, R := 2R. Go to # +# Step 3.1. # +# # +# Step 4. At this point, R = X - QY = MOD(X,Y). Set # +# Last_Subtract := false (used in Step 7 below). If # +# MOD is requested, go to Step 6. # +# # +# Step 5. R = MOD(X,Y), but REM(X,Y) is requested. # +# 5.1 If R < Y/2, then R = MOD(X,Y) = REM(X,Y). Go to # +# Step 6. # +# 5.2 If R > Y/2, then { set Last_Subtract := true, # +# Q := Q + 1, Y := signY*Y }. Go to Step 6. # +# 5.3 This is the tricky case of R = Y/2. If Q is odd, # +# then { Q := Q + 1, signX := -signX }. # +# # +# Step 6. R := signX*R. # +# # +# Step 7. If Last_Subtract = true, R := R - Y. # +# # +# Step 8. Return signQ, last 7 bits of Q, and R as required. # +# # +# Step 9. At this point, R = 2^(-j)*X - Q Y = Y. Thus, # +# X = 2^(j)*(Q+1)Y. set Q := 2^(j)*(Q+1), # +# R := 0. Return signQ, last 7 bits of Q, and R. # +# # +######################################################################### + + set Mod_Flag,L_SCR3 + set Sc_Flag,L_SCR3+1 + + set SignY,L_SCR2 + set SignX,L_SCR2+2 + set SignQ,L_SCR3+2 + + set Y,FP_SCR0 + set Y_Hi,Y+4 + set Y_Lo,Y+8 + + set R,FP_SCR1 + set R_Hi,R+4 + set R_Lo,R+8 + +Scale: + long 0x00010000,0x80000000,0x00000000,0x00000000 + + global smod +smod: + clr.b FPSR_QBYTE(%a6) + mov.l %d0,-(%sp) # save ctrl bits + clr.b Mod_Flag(%a6) + bra.b Mod_Rem + + global srem +srem: + clr.b FPSR_QBYTE(%a6) + mov.l %d0,-(%sp) # save ctrl bits + mov.b &0x1,Mod_Flag(%a6) + +Mod_Rem: +#..Save sign of X and Y + movm.l &0x3f00,-(%sp) # save data registers + mov.w SRC_EX(%a0),%d3 + mov.w %d3,SignY(%a6) + and.l &0x00007FFF,%d3 # Y := |Y| + +# + mov.l SRC_HI(%a0),%d4 + mov.l SRC_LO(%a0),%d5 # (D3,D4,D5) is |Y| + + tst.l %d3 + bne.b Y_Normal + + mov.l &0x00003FFE,%d3 # $3FFD + 1 + tst.l %d4 + bne.b HiY_not0 + +HiY_0: + mov.l %d5,%d4 + clr.l %d5 + sub.l &32,%d3 + clr.l %d6 + bfffo %d4{&0:&32},%d6 + lsl.l %d6,%d4 + sub.l %d6,%d3 # (D3,D4,D5) is normalized +# ...with bias $7FFD + bra.b Chk_X + +HiY_not0: + clr.l %d6 + bfffo %d4{&0:&32},%d6 + sub.l %d6,%d3 + lsl.l %d6,%d4 + mov.l %d5,%d7 # a copy of D5 + lsl.l %d6,%d5 + neg.l %d6 + add.l &32,%d6 + lsr.l %d6,%d7 + or.l %d7,%d4 # (D3,D4,D5) normalized +# ...with bias $7FFD + bra.b Chk_X + +Y_Normal: + add.l &0x00003FFE,%d3 # (D3,D4,D5) normalized +# ...with bias $7FFD + +Chk_X: + mov.w DST_EX(%a1),%d0 + mov.w %d0,SignX(%a6) + mov.w SignY(%a6),%d1 + eor.l %d0,%d1 + and.l &0x00008000,%d1 + mov.w %d1,SignQ(%a6) # sign(Q) obtained + and.l &0x00007FFF,%d0 + mov.l DST_HI(%a1),%d1 + mov.l DST_LO(%a1),%d2 # (D0,D1,D2) is |X| + tst.l %d0 + bne.b X_Normal + mov.l &0x00003FFE,%d0 + tst.l %d1 + bne.b HiX_not0 + +HiX_0: + mov.l %d2,%d1 + clr.l %d2 + sub.l &32,%d0 + clr.l %d6 + bfffo %d1{&0:&32},%d6 + lsl.l %d6,%d1 + sub.l %d6,%d0 # (D0,D1,D2) is normalized +# ...with bias $7FFD + bra.b Init + +HiX_not0: + clr.l %d6 + bfffo %d1{&0:&32},%d6 + sub.l %d6,%d0 + lsl.l %d6,%d1 + mov.l %d2,%d7 # a copy of D2 + lsl.l %d6,%d2 + neg.l %d6 + add.l &32,%d6 + lsr.l %d6,%d7 + or.l %d7,%d1 # (D0,D1,D2) normalized +# ...with bias $7FFD + bra.b Init + +X_Normal: + add.l &0x00003FFE,%d0 # (D0,D1,D2) normalized +# ...with bias $7FFD + +Init: +# + mov.l %d3,L_SCR1(%a6) # save biased exp(Y) + mov.l %d0,-(%sp) # save biased exp(X) + sub.l %d3,%d0 # L := expo(X)-expo(Y) + + clr.l %d6 # D6 := carry <- 0 + clr.l %d3 # D3 is Q + mov.l &0,%a1 # A1 is k; j+k=L, Q=0 + +#..(Carry,D1,D2) is R + tst.l %d0 + bge.b Mod_Loop_pre + +#..expo(X) < expo(Y). Thus X = mod(X,Y) +# + mov.l (%sp)+,%d0 # restore d0 + bra.w Get_Mod + +Mod_Loop_pre: + addq.l &0x4,%sp # erase exp(X) +#..At this point R = 2^(-L)X; Q = 0; k = 0; and k+j = L +Mod_Loop: + tst.l %d6 # test carry bit + bgt.b R_GT_Y + +#..At this point carry = 0, R = (D1,D2), Y = (D4,D5) + cmp.l %d1,%d4 # compare hi(R) and hi(Y) + bne.b R_NE_Y + cmp.l %d2,%d5 # compare lo(R) and lo(Y) + bne.b R_NE_Y + +#..At this point, R = Y + bra.w Rem_is_0 + +R_NE_Y: +#..use the borrow of the previous compare + bcs.b R_LT_Y # borrow is set iff R < Y + +R_GT_Y: +#..If Carry is set, then Y < (Carry,D1,D2) < 2Y. Otherwise, Carry = 0 +#..and Y < (D1,D2) < 2Y. Either way, perform R - Y + sub.l %d5,%d2 # lo(R) - lo(Y) + subx.l %d4,%d1 # hi(R) - hi(Y) + clr.l %d6 # clear carry + addq.l &1,%d3 # Q := Q + 1 + +R_LT_Y: +#..At this point, Carry=0, R < Y. R = 2^(k-L)X - QY; k+j = L; j >= 0. + tst.l %d0 # see if j = 0. + beq.b PostLoop + + add.l %d3,%d3 # Q := 2Q + add.l %d2,%d2 # lo(R) = 2lo(R) + roxl.l &1,%d1 # hi(R) = 2hi(R) + carry + scs %d6 # set Carry if 2(R) overflows + addq.l &1,%a1 # k := k+1 + subq.l &1,%d0 # j := j - 1 +#..At this point, R=(Carry,D1,D2) = 2^(k-L)X - QY, j+k=L, j >= 0, R < 2Y. + + bra.b Mod_Loop + +PostLoop: +#..k = L, j = 0, Carry = 0, R = (D1,D2) = X - QY, R < Y. + +#..normalize R. + mov.l L_SCR1(%a6),%d0 # new biased expo of R + tst.l %d1 + bne.b HiR_not0 + +HiR_0: + mov.l %d2,%d1 + clr.l %d2 + sub.l &32,%d0 + clr.l %d6 + bfffo %d1{&0:&32},%d6 + lsl.l %d6,%d1 + sub.l %d6,%d0 # (D0,D1,D2) is normalized +# ...with bias $7FFD + bra.b Get_Mod + +HiR_not0: + clr.l %d6 + bfffo %d1{&0:&32},%d6 + bmi.b Get_Mod # already normalized + sub.l %d6,%d0 + lsl.l %d6,%d1 + mov.l %d2,%d7 # a copy of D2 + lsl.l %d6,%d2 + neg.l %d6 + add.l &32,%d6 + lsr.l %d6,%d7 + or.l %d7,%d1 # (D0,D1,D2) normalized + +# +Get_Mod: + cmp.l %d0,&0x000041FE + bge.b No_Scale +Do_Scale: + mov.w %d0,R(%a6) + mov.l %d1,R_Hi(%a6) + mov.l %d2,R_Lo(%a6) + mov.l L_SCR1(%a6),%d6 + mov.w %d6,Y(%a6) + mov.l %d4,Y_Hi(%a6) + mov.l %d5,Y_Lo(%a6) + fmov.x R(%a6),%fp0 # no exception + mov.b &1,Sc_Flag(%a6) + bra.b ModOrRem +No_Scale: + mov.l %d1,R_Hi(%a6) + mov.l %d2,R_Lo(%a6) + sub.l &0x3FFE,%d0 + mov.w %d0,R(%a6) + mov.l L_SCR1(%a6),%d6 + sub.l &0x3FFE,%d6 + mov.l %d6,L_SCR1(%a6) + fmov.x R(%a6),%fp0 + mov.w %d6,Y(%a6) + mov.l %d4,Y_Hi(%a6) + mov.l %d5,Y_Lo(%a6) + clr.b Sc_Flag(%a6) + +# +ModOrRem: + tst.b Mod_Flag(%a6) + beq.b Fix_Sign + + mov.l L_SCR1(%a6),%d6 # new biased expo(Y) + subq.l &1,%d6 # biased expo(Y/2) + cmp.l %d0,%d6 + blt.b Fix_Sign + bgt.b Last_Sub + + cmp.l %d1,%d4 + bne.b Not_EQ + cmp.l %d2,%d5 + bne.b Not_EQ + bra.w Tie_Case + +Not_EQ: + bcs.b Fix_Sign + +Last_Sub: +# + fsub.x Y(%a6),%fp0 # no exceptions + addq.l &1,%d3 # Q := Q + 1 + +# +Fix_Sign: +#..Get sign of X + mov.w SignX(%a6),%d6 + bge.b Get_Q + fneg.x %fp0 + +#..Get Q +# +Get_Q: + clr.l %d6 + mov.w SignQ(%a6),%d6 # D6 is sign(Q) + mov.l &8,%d7 + lsr.l %d7,%d6 + and.l &0x0000007F,%d3 # 7 bits of Q + or.l %d6,%d3 # sign and bits of Q +# swap %d3 +# fmov.l %fpsr,%d6 +# and.l &0xFF00FFFF,%d6 +# or.l %d3,%d6 +# fmov.l %d6,%fpsr # put Q in fpsr + mov.b %d3,FPSR_QBYTE(%a6) # put Q in fpsr + +# +Restore: + movm.l (%sp)+,&0xfc # {%d2-%d7} + mov.l (%sp)+,%d0 + fmov.l %d0,%fpcr + tst.b Sc_Flag(%a6) + beq.b Finish + mov.b &FMUL_OP,%d1 # last inst is MUL + fmul.x Scale(%pc),%fp0 # may cause underflow + bra t_catch2 +# the '040 package did this apparently to see if the dst operand for the +# preceding fmul was a denorm. but, it better not have been since the +# algorithm just got done playing with fp0 and expected no exceptions +# as a result. trust me... +# bra t_avoid_unsupp # check for denorm as a +# ;result of the scaling + +Finish: + mov.b &FMOV_OP,%d1 # last inst is MOVE + fmov.x %fp0,%fp0 # capture exceptions & round + bra t_catch2 + +Rem_is_0: +#..R = 2^(-j)X - Q Y = Y, thus R = 0 and quotient = 2^j (Q+1) + addq.l &1,%d3 + cmp.l %d0,&8 # D0 is j + bge.b Q_Big + + lsl.l %d0,%d3 + bra.b Set_R_0 + +Q_Big: + clr.l %d3 + +Set_R_0: + fmov.s &0x00000000,%fp0 + clr.b Sc_Flag(%a6) + bra.w Fix_Sign + +Tie_Case: +#..Check parity of Q + mov.l %d3,%d6 + and.l &0x00000001,%d6 + tst.l %d6 + beq.w Fix_Sign # Q is even + +#..Q is odd, Q := Q + 1, signX := -signX + addq.l &1,%d3 + mov.w SignX(%a6),%d6 + eor.l &0x00008000,%d6 + mov.w %d6,SignX(%a6) + bra.w Fix_Sign + +######################################################################### +# XDEF **************************************************************** # +# tag(): return the optype of the input ext fp number # +# # +# This routine is used by the 060FPLSP. # +# # +# XREF **************************************************************** # +# None # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision operand # +# # +# OUTPUT ************************************************************** # +# d0 = value of type tag # +# one of: NORM, INF, QNAN, SNAN, DENORM, ZERO # +# # +# ALGORITHM *********************************************************** # +# Simply test the exponent, j-bit, and mantissa values to # +# determine the type of operand. # +# If it's an unnormalized zero, alter the operand and force it # +# to be a normal zero. # +# # +######################################################################### + + global tag +tag: + mov.w FTEMP_EX(%a0), %d0 # extract exponent + andi.w &0x7fff, %d0 # strip off sign + cmpi.w %d0, &0x7fff # is (EXP == MAX)? + beq.b inf_or_nan_x +not_inf_or_nan_x: + btst &0x7,FTEMP_HI(%a0) + beq.b not_norm_x +is_norm_x: + mov.b &NORM, %d0 + rts +not_norm_x: + tst.w %d0 # is exponent = 0? + bne.b is_unnorm_x +not_unnorm_x: + tst.l FTEMP_HI(%a0) + bne.b is_denorm_x + tst.l FTEMP_LO(%a0) + bne.b is_denorm_x +is_zero_x: + mov.b &ZERO, %d0 + rts +is_denorm_x: + mov.b &DENORM, %d0 + rts +is_unnorm_x: + bsr.l unnorm_fix # convert to norm,denorm,or zero + rts +is_unnorm_reg_x: + mov.b &UNNORM, %d0 + rts +inf_or_nan_x: + tst.l FTEMP_LO(%a0) + bne.b is_nan_x + mov.l FTEMP_HI(%a0), %d0 + and.l &0x7fffffff, %d0 # msb is a don't care! + bne.b is_nan_x +is_inf_x: + mov.b &INF, %d0 + rts +is_nan_x: + mov.b &QNAN, %d0 + rts + +############################################################# + +qnan: long 0x7fff0000, 0xffffffff, 0xffffffff + +######################################################################### +# XDEF **************************************************************** # +# t_dz(): Handle 060FPLSP dz exception for "flogn" emulation. # +# t_dz2(): Handle 060FPLSP dz exception for "fatanh" emulation. # +# # +# These rouitnes are used by the 060FPLSP package. # +# # +# XREF **************************************************************** # +# None # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision source operand. # +# # +# OUTPUT ************************************************************** # +# fp0 = default DZ result. # +# # +# ALGORITHM *********************************************************** # +# Transcendental emulation for the 060FPLSP has detected that # +# a DZ exception should occur for the instruction. If DZ is disabled, # +# return the default result. # +# If DZ is enabled, the dst operand should be returned unscathed # +# in fp0 while fp1 is used to create a DZ exception so that the # +# operating system can log that such an event occurred. # +# # +######################################################################### + + global t_dz +t_dz: + tst.b SRC_EX(%a0) # check sign for neg or pos + bpl.b dz_pinf # branch if pos sign + + global t_dz2 +t_dz2: + ori.l &dzinf_mask+neg_mask,USER_FPSR(%a6) # set N/I/DZ/ADZ + + btst &dz_bit,FPCR_ENABLE(%a6) + bne.b dz_minf_ena + +# dz is disabled. return a -INF. + fmov.s &0xff800000,%fp0 # return -INF + rts + +# dz is enabled. create a dz exception so the user can record it +# but use fp1 instead. return the dst operand unscathed in fp0. +dz_minf_ena: + fmovm.x EXC_FP0(%a6),&0x80 # return fp0 unscathed + fmov.l USER_FPCR(%a6),%fpcr + fmov.s &0xbf800000,%fp1 # load -1 + fdiv.s &0x00000000,%fp1 # -1 / 0 + rts + +dz_pinf: + ori.l &dzinf_mask,USER_FPSR(%a6) # set I/DZ/ADZ + + btst &dz_bit,FPCR_ENABLE(%a6) + bne.b dz_pinf_ena + +# dz is disabled. return a +INF. + fmov.s &0x7f800000,%fp0 # return +INF + rts + +# dz is enabled. create a dz exception so the user can record it +# but use fp1 instead. return the dst operand unscathed in fp0. +dz_pinf_ena: + fmovm.x EXC_FP0(%a6),&0x80 # return fp0 unscathed + fmov.l USER_FPCR(%a6),%fpcr + fmov.s &0x3f800000,%fp1 # load +1 + fdiv.s &0x00000000,%fp1 # +1 / 0 + rts + +######################################################################### +# XDEF **************************************************************** # +# t_operr(): Handle 060FPLSP OPERR exception during emulation. # +# # +# This routine is used by the 060FPLSP package. # +# # +# XREF **************************************************************** # +# None. # +# # +# INPUT *************************************************************** # +# fp1 = source operand # +# # +# OUTPUT ************************************************************** # +# fp0 = default result # +# fp1 = unchanged # +# # +# ALGORITHM *********************************************************** # +# An operand error should occur as the result of transcendental # +# emulation in the 060FPLSP. If OPERR is disabled, just return a NAN # +# in fp0. If OPERR is enabled, return the dst operand unscathed in fp0 # +# and the source operand in fp1. Use fp2 to create an OPERR exception # +# so that the operating system can log the event. # +# # +######################################################################### + + global t_operr +t_operr: + ori.l &opnan_mask,USER_FPSR(%a6) # set NAN/OPERR/AIOP + + btst &operr_bit,FPCR_ENABLE(%a6) + bne.b operr_ena + +# operr is disabled. return a QNAN in fp0 + fmovm.x qnan(%pc),&0x80 # return QNAN + rts + +# operr is enabled. create an operr exception so the user can record it +# but use fp2 instead. return the dst operand unscathed in fp0. +operr_ena: + fmovm.x EXC_FP0(%a6),&0x80 # return fp0 unscathed + fmov.l USER_FPCR(%a6),%fpcr + fmovm.x &0x04,-(%sp) # save fp2 + fmov.s &0x7f800000,%fp2 # load +INF + fmul.s &0x00000000,%fp2 # +INF x 0 + fmovm.x (%sp)+,&0x20 # restore fp2 + rts + +pls_huge: + long 0x7ffe0000,0xffffffff,0xffffffff +mns_huge: + long 0xfffe0000,0xffffffff,0xffffffff +pls_tiny: + long 0x00000000,0x80000000,0x00000000 +mns_tiny: + long 0x80000000,0x80000000,0x00000000 + +######################################################################### +# XDEF **************************************************************** # +# t_unfl(): Handle 060FPLSP underflow exception during emulation. # +# t_unfl2(): Handle 060FPLSP underflow exception during # +# emulation. result always positive. # +# # +# This routine is used by the 060FPLSP package. # +# # +# XREF **************************************************************** # +# None. # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision source operand # +# # +# OUTPUT ************************************************************** # +# fp0 = default underflow result # +# # +# ALGORITHM *********************************************************** # +# An underflow should occur as the result of transcendental # +# emulation in the 060FPLSP. Create an underflow by using "fmul" # +# and two very small numbers of appropriate sign so the operating # +# system can log the event. # +# # +######################################################################### + + global t_unfl +t_unfl: + tst.b SRC_EX(%a0) + bpl.b unf_pos + + global t_unfl2 +t_unfl2: + ori.l &unfinx_mask+neg_mask,USER_FPSR(%a6) # set N/UNFL/INEX2/AUNFL/AINEX + + fmov.l USER_FPCR(%a6),%fpcr + fmovm.x mns_tiny(%pc),&0x80 + fmul.x pls_tiny(%pc),%fp0 + + fmov.l %fpsr,%d0 + rol.l &0x8,%d0 + mov.b %d0,FPSR_CC(%a6) + rts +unf_pos: + ori.w &unfinx_mask,FPSR_EXCEPT(%a6) # set UNFL/INEX2/AUNFL/AINEX + + fmov.l USER_FPCR(%a6),%fpcr + fmovm.x pls_tiny(%pc),&0x80 + fmul.x %fp0,%fp0 + + fmov.l %fpsr,%d0 + rol.l &0x8,%d0 + mov.b %d0,FPSR_CC(%a6) + rts + +######################################################################### +# XDEF **************************************************************** # +# t_ovfl(): Handle 060FPLSP overflow exception during emulation. # +# (monadic) # +# t_ovfl2(): Handle 060FPLSP overflow exception during # +# emulation. result always positive. (dyadic) # +# t_ovfl_sc(): Handle 060FPLSP overflow exception during # +# emulation for "fscale". # +# # +# This routine is used by the 060FPLSP package. # +# # +# XREF **************************************************************** # +# None. # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision source operand # +# # +# OUTPUT ************************************************************** # +# fp0 = default underflow result # +# # +# ALGORITHM *********************************************************** # +# An overflow should occur as the result of transcendental # +# emulation in the 060FPLSP. Create an overflow by using "fmul" # +# and two very lareg numbers of appropriate sign so the operating # +# system can log the event. # +# For t_ovfl_sc() we take special care not to lose the INEX2 bit. # +# # +######################################################################### + + global t_ovfl_sc +t_ovfl_sc: + ori.l &ovfl_inx_mask,USER_FPSR(%a6) # set OVFL/AOVFL/AINEX + + mov.b %d0,%d1 # fetch rnd prec,mode + andi.b &0xc0,%d1 # extract prec + beq.w ovfl_work + +# dst op is a DENORM. we have to normalize the mantissa to see if the +# result would be inexact for the given precision. make a copy of the +# dst so we don't screw up the version passed to us. + mov.w LOCAL_EX(%a0),FP_SCR0_EX(%a6) + mov.l LOCAL_HI(%a0),FP_SCR0_HI(%a6) + mov.l LOCAL_LO(%a0),FP_SCR0_LO(%a6) + lea FP_SCR0(%a6),%a0 # pass ptr to FP_SCR0 + movm.l &0xc080,-(%sp) # save d0-d1/a0 + bsr.l norm # normalize mantissa + movm.l (%sp)+,&0x0103 # restore d0-d1/a0 + + cmpi.b %d1,&0x40 # is precision sgl? + bne.b ovfl_sc_dbl # no; dbl +ovfl_sc_sgl: + tst.l LOCAL_LO(%a0) # is lo lw of sgl set? + bne.b ovfl_sc_inx # yes + tst.b 3+LOCAL_HI(%a0) # is lo byte of hi lw set? + bne.b ovfl_sc_inx # yes + bra.w ovfl_work # don't set INEX2 +ovfl_sc_dbl: + mov.l LOCAL_LO(%a0),%d1 # are any of lo 11 bits of + andi.l &0x7ff,%d1 # dbl mantissa set? + beq.w ovfl_work # no; don't set INEX2 +ovfl_sc_inx: + ori.l &inex2_mask,USER_FPSR(%a6) # set INEX2 + bra.b ovfl_work # continue + + global t_ovfl +t_ovfl: + ori.w &ovfinx_mask,FPSR_EXCEPT(%a6) # set OVFL/INEX2/AOVFL/AINEX +ovfl_work: + tst.b SRC_EX(%a0) + bpl.b ovfl_p +ovfl_m: + fmov.l USER_FPCR(%a6),%fpcr + fmovm.x mns_huge(%pc),&0x80 + fmul.x pls_huge(%pc),%fp0 + + fmov.l %fpsr,%d0 + rol.l &0x8,%d0 + ori.b &neg_mask,%d0 + mov.b %d0,FPSR_CC(%a6) + rts +ovfl_p: + fmov.l USER_FPCR(%a6),%fpcr + fmovm.x pls_huge(%pc),&0x80 + fmul.x pls_huge(%pc),%fp0 + + fmov.l %fpsr,%d0 + rol.l &0x8,%d0 + mov.b %d0,FPSR_CC(%a6) + rts + + global t_ovfl2 +t_ovfl2: + ori.w &ovfinx_mask,FPSR_EXCEPT(%a6) # set OVFL/INEX2/AOVFL/AINEX + fmov.l USER_FPCR(%a6),%fpcr + fmovm.x pls_huge(%pc),&0x80 + fmul.x pls_huge(%pc),%fp0 + + fmov.l %fpsr,%d0 + rol.l &0x8,%d0 + mov.b %d0,FPSR_CC(%a6) + rts + +######################################################################### +# XDEF **************************************************************** # +# t_catch(): Handle 060FPLSP OVFL,UNFL,or INEX2 exception during # +# emulation. # +# t_catch2(): Handle 060FPLSP OVFL,UNFL,or INEX2 exception during # +# emulation. # +# # +# These routines are used by the 060FPLSP package. # +# # +# XREF **************************************************************** # +# None. # +# # +# INPUT *************************************************************** # +# fp0 = default underflow or overflow result # +# # +# OUTPUT ************************************************************** # +# fp0 = default result # +# # +# ALGORITHM *********************************************************** # +# If an overflow or underflow occurred during the last # +# instruction of transcendental 060FPLSP emulation, then it has already # +# occurred and has been logged. Now we need to see if an inexact # +# exception should occur. # +# # +######################################################################### + + global t_catch2 +t_catch2: + fmov.l %fpsr,%d0 + or.l %d0,USER_FPSR(%a6) + bra.b inx2_work + + global t_catch +t_catch: + fmov.l %fpsr,%d0 + or.l %d0,USER_FPSR(%a6) + +######################################################################### +# XDEF **************************************************************** # +# t_inx2(): Handle inexact 060FPLSP exception during emulation. # +# t_pinx2(): Handle inexact 060FPLSP exception for "+" results. # +# t_minx2(): Handle inexact 060FPLSP exception for "-" results. # +# # +# XREF **************************************************************** # +# None. # +# # +# INPUT *************************************************************** # +# fp0 = default result # +# # +# OUTPUT ************************************************************** # +# fp0 = default result # +# # +# ALGORITHM *********************************************************** # +# The last instruction of transcendental emulation for the # +# 060FPLSP should be inexact. So, if inexact is enabled, then we create # +# the event here by adding a large and very small number together # +# so that the operating system can log the event. # +# Must check, too, if the result was zero, in which case we just # +# set the FPSR bits and return. # +# # +######################################################################### + + global t_inx2 +t_inx2: + fblt.w t_minx2 + fbeq.w inx2_zero + + global t_pinx2 +t_pinx2: + ori.w &inx2a_mask,FPSR_EXCEPT(%a6) # set INEX2/AINEX + bra.b inx2_work + + global t_minx2 +t_minx2: + ori.l &inx2a_mask+neg_mask,USER_FPSR(%a6) + +inx2_work: + btst &inex2_bit,FPCR_ENABLE(%a6) # is inexact enabled? + bne.b inx2_work_ena # yes + rts +inx2_work_ena: + fmov.l USER_FPCR(%a6),%fpcr # insert user's exceptions + fmov.s &0x3f800000,%fp1 # load +1 + fadd.x pls_tiny(%pc),%fp1 # cause exception + rts + +inx2_zero: + mov.b &z_bmask,FPSR_CC(%a6) + ori.w &inx2a_mask,2+USER_FPSR(%a6) # set INEX/AINEX + rts + +######################################################################### +# XDEF **************************************************************** # +# t_extdnrm(): Handle DENORM inputs in 060FPLSP. # +# t_resdnrm(): Handle DENORM inputs in 060FPLSP for "fscale". # +# # +# This routine is used by the 060FPLSP package. # +# # +# XREF **************************************************************** # +# None. # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input operand # +# # +# OUTPUT ************************************************************** # +# fp0 = default result # +# # +# ALGORITHM *********************************************************** # +# For all functions that have a denormalized input and that # +# f(x)=x, this is the entry point. # +# DENORM value is moved using "fmove" which triggers an exception # +# if enabled so the operating system can log the event. # +# # +######################################################################### + + global t_extdnrm +t_extdnrm: + fmov.l USER_FPCR(%a6),%fpcr + fmov.x SRC_EX(%a0),%fp0 + fmov.l %fpsr,%d0 + ori.l &unfinx_mask,%d0 + or.l %d0,USER_FPSR(%a6) + rts + + global t_resdnrm +t_resdnrm: + fmov.l USER_FPCR(%a6),%fpcr + fmov.x SRC_EX(%a0),%fp0 + fmov.l %fpsr,%d0 + or.l %d0,USER_FPSR(%a6) + rts + +########################################## + +# +# sto_cos: +# This is used by fsincos library emulation. The correct +# values are already in fp0 and fp1 so we do nothing here. +# + global sto_cos +sto_cos: + rts + +########################################## + +# +# dst_qnan --- force result when destination is a NaN +# + global dst_qnan +dst_qnan: + fmov.x DST(%a1),%fp0 + tst.b DST_EX(%a1) + bmi.b dst_qnan_m +dst_qnan_p: + mov.b &nan_bmask,FPSR_CC(%a6) + rts +dst_qnan_m: + mov.b &nan_bmask+neg_bmask,FPSR_CC(%a6) + rts + +# +# src_qnan --- force result when source is a NaN +# + global src_qnan +src_qnan: + fmov.x SRC(%a0),%fp0 + tst.b SRC_EX(%a0) + bmi.b src_qnan_m +src_qnan_p: + mov.b &nan_bmask,FPSR_CC(%a6) + rts +src_qnan_m: + mov.b &nan_bmask+neg_bmask,FPSR_CC(%a6) + rts + +########################################## + +# +# Native instruction support +# +# Some systems may need entry points even for 68060 native +# instructions. These routines are provided for +# convenience. +# + global _fadds_ +_fadds_: + fmov.l %fpcr,-(%sp) # save fpcr + fmov.l &0x00000000,%fpcr # clear fpcr for load + fmov.s 0x8(%sp),%fp0 # load sgl dst + fmov.l (%sp)+,%fpcr # restore fpcr + fadd.s 0x8(%sp),%fp0 # fadd w/ sgl src + rts + + global _faddd_ +_faddd_: + fmov.l %fpcr,-(%sp) # save fpcr + fmov.l &0x00000000,%fpcr # clear fpcr for load + fmov.d 0x8(%sp),%fp0 # load dbl dst + fmov.l (%sp)+,%fpcr # restore fpcr + fadd.d 0xc(%sp),%fp0 # fadd w/ dbl src + rts + + global _faddx_ +_faddx_: + fmovm.x 0x4(%sp),&0x80 # load ext dst + fadd.x 0x10(%sp),%fp0 # fadd w/ ext src + rts + + global _fsubs_ +_fsubs_: + fmov.l %fpcr,-(%sp) # save fpcr + fmov.l &0x00000000,%fpcr # clear fpcr for load + fmov.s 0x8(%sp),%fp0 # load sgl dst + fmov.l (%sp)+,%fpcr # restore fpcr + fsub.s 0x8(%sp),%fp0 # fsub w/ sgl src + rts + + global _fsubd_ +_fsubd_: + fmov.l %fpcr,-(%sp) # save fpcr + fmov.l &0x00000000,%fpcr # clear fpcr for load + fmov.d 0x8(%sp),%fp0 # load dbl dst + fmov.l (%sp)+,%fpcr # restore fpcr + fsub.d 0xc(%sp),%fp0 # fsub w/ dbl src + rts + + global _fsubx_ +_fsubx_: + fmovm.x 0x4(%sp),&0x80 # load ext dst + fsub.x 0x10(%sp),%fp0 # fsub w/ ext src + rts + + global _fmuls_ +_fmuls_: + fmov.l %fpcr,-(%sp) # save fpcr + fmov.l &0x00000000,%fpcr # clear fpcr for load + fmov.s 0x8(%sp),%fp0 # load sgl dst + fmov.l (%sp)+,%fpcr # restore fpcr + fmul.s 0x8(%sp),%fp0 # fmul w/ sgl src + rts + + global _fmuld_ +_fmuld_: + fmov.l %fpcr,-(%sp) # save fpcr + fmov.l &0x00000000,%fpcr # clear fpcr for load + fmov.d 0x8(%sp),%fp0 # load dbl dst + fmov.l (%sp)+,%fpcr # restore fpcr + fmul.d 0xc(%sp),%fp0 # fmul w/ dbl src + rts + + global _fmulx_ +_fmulx_: + fmovm.x 0x4(%sp),&0x80 # load ext dst + fmul.x 0x10(%sp),%fp0 # fmul w/ ext src + rts + + global _fdivs_ +_fdivs_: + fmov.l %fpcr,-(%sp) # save fpcr + fmov.l &0x00000000,%fpcr # clear fpcr for load + fmov.s 0x8(%sp),%fp0 # load sgl dst + fmov.l (%sp)+,%fpcr # restore fpcr + fdiv.s 0x8(%sp),%fp0 # fdiv w/ sgl src + rts + + global _fdivd_ +_fdivd_: + fmov.l %fpcr,-(%sp) # save fpcr + fmov.l &0x00000000,%fpcr # clear fpcr for load + fmov.d 0x8(%sp),%fp0 # load dbl dst + fmov.l (%sp)+,%fpcr # restore fpcr + fdiv.d 0xc(%sp),%fp0 # fdiv w/ dbl src + rts + + global _fdivx_ +_fdivx_: + fmovm.x 0x4(%sp),&0x80 # load ext dst + fdiv.x 0x10(%sp),%fp0 # fdiv w/ ext src + rts + + global _fabss_ +_fabss_: + fabs.s 0x4(%sp),%fp0 # fabs w/ sgl src + rts + + global _fabsd_ +_fabsd_: + fabs.d 0x4(%sp),%fp0 # fabs w/ dbl src + rts + + global _fabsx_ +_fabsx_: + fabs.x 0x4(%sp),%fp0 # fabs w/ ext src + rts + + global _fnegs_ +_fnegs_: + fneg.s 0x4(%sp),%fp0 # fneg w/ sgl src + rts + + global _fnegd_ +_fnegd_: + fneg.d 0x4(%sp),%fp0 # fneg w/ dbl src + rts + + global _fnegx_ +_fnegx_: + fneg.x 0x4(%sp),%fp0 # fneg w/ ext src + rts + + global _fsqrts_ +_fsqrts_: + fsqrt.s 0x4(%sp),%fp0 # fsqrt w/ sgl src + rts + + global _fsqrtd_ +_fsqrtd_: + fsqrt.d 0x4(%sp),%fp0 # fsqrt w/ dbl src + rts + + global _fsqrtx_ +_fsqrtx_: + fsqrt.x 0x4(%sp),%fp0 # fsqrt w/ ext src + rts + + global _fints_ +_fints_: + fint.s 0x4(%sp),%fp0 # fint w/ sgl src + rts + + global _fintd_ +_fintd_: + fint.d 0x4(%sp),%fp0 # fint w/ dbl src + rts + + global _fintx_ +_fintx_: + fint.x 0x4(%sp),%fp0 # fint w/ ext src + rts + + global _fintrzs_ +_fintrzs_: + fintrz.s 0x4(%sp),%fp0 # fintrz w/ sgl src + rts + + global _fintrzd_ +_fintrzd_: + fintrz.d 0x4(%sp),%fp0 # fintrx w/ dbl src + rts + + global _fintrzx_ +_fintrzx_: + fintrz.x 0x4(%sp),%fp0 # fintrz w/ ext src + rts + +######################################################################## + +######################################################################### +# src_zero(): Return signed zero according to sign of src operand. # +######################################################################### + global src_zero +src_zero: + tst.b SRC_EX(%a0) # get sign of src operand + bmi.b ld_mzero # if neg, load neg zero + +# +# ld_pzero(): return a positive zero. +# + global ld_pzero +ld_pzero: + fmov.s &0x00000000,%fp0 # load +0 + mov.b &z_bmask,FPSR_CC(%a6) # set 'Z' ccode bit + rts + +# ld_mzero(): return a negative zero. + global ld_mzero +ld_mzero: + fmov.s &0x80000000,%fp0 # load -0 + mov.b &neg_bmask+z_bmask,FPSR_CC(%a6) # set 'N','Z' ccode bits + rts + +######################################################################### +# dst_zero(): Return signed zero according to sign of dst operand. # +######################################################################### + global dst_zero +dst_zero: + tst.b DST_EX(%a1) # get sign of dst operand + bmi.b ld_mzero # if neg, load neg zero + bra.b ld_pzero # load positive zero + +######################################################################### +# src_inf(): Return signed inf according to sign of src operand. # +######################################################################### + global src_inf +src_inf: + tst.b SRC_EX(%a0) # get sign of src operand + bmi.b ld_minf # if negative branch + +# +# ld_pinf(): return a positive infinity. +# + global ld_pinf +ld_pinf: + fmov.s &0x7f800000,%fp0 # load +INF + mov.b &inf_bmask,FPSR_CC(%a6) # set 'INF' ccode bit + rts + +# +# ld_minf():return a negative infinity. +# + global ld_minf +ld_minf: + fmov.s &0xff800000,%fp0 # load -INF + mov.b &neg_bmask+inf_bmask,FPSR_CC(%a6) # set 'N','I' ccode bits + rts + +######################################################################### +# dst_inf(): Return signed inf according to sign of dst operand. # +######################################################################### + global dst_inf +dst_inf: + tst.b DST_EX(%a1) # get sign of dst operand + bmi.b ld_minf # if negative branch + bra.b ld_pinf + + global szr_inf +################################################################# +# szr_inf(): Return +ZERO for a negative src operand or # +# +INF for a positive src operand. # +# Routine used for fetox, ftwotox, and ftentox. # +################################################################# +szr_inf: + tst.b SRC_EX(%a0) # check sign of source + bmi.b ld_pzero + bra.b ld_pinf + +######################################################################### +# sopr_inf(): Return +INF for a positive src operand or # +# jump to operand error routine for a negative src operand. # +# Routine used for flogn, flognp1, flog10, and flog2. # +######################################################################### + global sopr_inf +sopr_inf: + tst.b SRC_EX(%a0) # check sign of source + bmi.w t_operr + bra.b ld_pinf + +################################################################# +# setoxm1i(): Return minus one for a negative src operand or # +# positive infinity for a positive src operand. # +# Routine used for fetoxm1. # +################################################################# + global setoxm1i +setoxm1i: + tst.b SRC_EX(%a0) # check sign of source + bmi.b ld_mone + bra.b ld_pinf + +######################################################################### +# src_one(): Return signed one according to sign of src operand. # +######################################################################### + global src_one +src_one: + tst.b SRC_EX(%a0) # check sign of source + bmi.b ld_mone + +# +# ld_pone(): return positive one. +# + global ld_pone +ld_pone: + fmov.s &0x3f800000,%fp0 # load +1 + clr.b FPSR_CC(%a6) + rts + +# +# ld_mone(): return negative one. +# + global ld_mone +ld_mone: + fmov.s &0xbf800000,%fp0 # load -1 + mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit + rts + +ppiby2: long 0x3fff0000, 0xc90fdaa2, 0x2168c235 +mpiby2: long 0xbfff0000, 0xc90fdaa2, 0x2168c235 + +################################################################# +# spi_2(): Return signed PI/2 according to sign of src operand. # +################################################################# + global spi_2 +spi_2: + tst.b SRC_EX(%a0) # check sign of source + bmi.b ld_mpi2 + +# +# ld_ppi2(): return positive PI/2. +# + global ld_ppi2 +ld_ppi2: + fmov.l %d0,%fpcr + fmov.x ppiby2(%pc),%fp0 # load +pi/2 + bra.w t_pinx2 # set INEX2 + +# +# ld_mpi2(): return negative PI/2. +# + global ld_mpi2 +ld_mpi2: + fmov.l %d0,%fpcr + fmov.x mpiby2(%pc),%fp0 # load -pi/2 + bra.w t_minx2 # set INEX2 + +#################################################### +# The following routines give support for fsincos. # +#################################################### + +# +# ssincosz(): When the src operand is ZERO, store a one in the +# cosine register and return a ZERO in fp0 w/ the same sign +# as the src operand. +# + global ssincosz +ssincosz: + fmov.s &0x3f800000,%fp1 + tst.b SRC_EX(%a0) # test sign + bpl.b sincoszp + fmov.s &0x80000000,%fp0 # return sin result in fp0 + mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) + rts +sincoszp: + fmov.s &0x00000000,%fp0 # return sin result in fp0 + mov.b &z_bmask,FPSR_CC(%a6) + rts + +# +# ssincosi(): When the src operand is INF, store a QNAN in the cosine +# register and jump to the operand error routine for negative +# src operands. +# + global ssincosi +ssincosi: + fmov.x qnan(%pc),%fp1 # load NAN + bra.w t_operr + +# +# ssincosqnan(): When the src operand is a QNAN, store the QNAN in the cosine +# register and branch to the src QNAN routine. +# + global ssincosqnan +ssincosqnan: + fmov.x LOCAL_EX(%a0),%fp1 + bra.w src_qnan + +######################################################################## + + global smod_sdnrm + global smod_snorm +smod_sdnrm: +smod_snorm: + mov.b DTAG(%a6),%d1 + beq.l smod + cmpi.b %d1,&ZERO + beq.w smod_zro + cmpi.b %d1,&INF + beq.l t_operr + cmpi.b %d1,&DENORM + beq.l smod + bra.l dst_qnan + + global smod_szero +smod_szero: + mov.b DTAG(%a6),%d1 + beq.l t_operr + cmpi.b %d1,&ZERO + beq.l t_operr + cmpi.b %d1,&INF + beq.l t_operr + cmpi.b %d1,&DENORM + beq.l t_operr + bra.l dst_qnan + + global smod_sinf +smod_sinf: + mov.b DTAG(%a6),%d1 + beq.l smod_fpn + cmpi.b %d1,&ZERO + beq.l smod_zro + cmpi.b %d1,&INF + beq.l t_operr + cmpi.b %d1,&DENORM + beq.l smod_fpn + bra.l dst_qnan + +smod_zro: +srem_zro: + mov.b SRC_EX(%a0),%d1 # get src sign + mov.b DST_EX(%a1),%d0 # get dst sign + eor.b %d0,%d1 # get qbyte sign + andi.b &0x80,%d1 + mov.b %d1,FPSR_QBYTE(%a6) + tst.b %d0 + bpl.w ld_pzero + bra.w ld_mzero + +smod_fpn: +srem_fpn: + clr.b FPSR_QBYTE(%a6) + mov.l %d0,-(%sp) + mov.b SRC_EX(%a0),%d1 # get src sign + mov.b DST_EX(%a1),%d0 # get dst sign + eor.b %d0,%d1 # get qbyte sign + andi.b &0x80,%d1 + mov.b %d1,FPSR_QBYTE(%a6) + cmpi.b DTAG(%a6),&DENORM + bne.b smod_nrm + lea DST(%a1),%a0 + mov.l (%sp)+,%d0 + bra t_resdnrm +smod_nrm: + fmov.l (%sp)+,%fpcr + fmov.x DST(%a1),%fp0 + tst.b DST_EX(%a1) + bmi.b smod_nrm_neg + rts + +smod_nrm_neg: + mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' code + rts + +######################################################################### + global srem_snorm + global srem_sdnrm +srem_sdnrm: +srem_snorm: + mov.b DTAG(%a6),%d1 + beq.l srem + cmpi.b %d1,&ZERO + beq.w srem_zro + cmpi.b %d1,&INF + beq.l t_operr + cmpi.b %d1,&DENORM + beq.l srem + bra.l dst_qnan + + global srem_szero +srem_szero: + mov.b DTAG(%a6),%d1 + beq.l t_operr + cmpi.b %d1,&ZERO + beq.l t_operr + cmpi.b %d1,&INF + beq.l t_operr + cmpi.b %d1,&DENORM + beq.l t_operr + bra.l dst_qnan + + global srem_sinf +srem_sinf: + mov.b DTAG(%a6),%d1 + beq.w srem_fpn + cmpi.b %d1,&ZERO + beq.w srem_zro + cmpi.b %d1,&INF + beq.l t_operr + cmpi.b %d1,&DENORM + beq.l srem_fpn + bra.l dst_qnan + +######################################################################### + + global sscale_snorm + global sscale_sdnrm +sscale_snorm: +sscale_sdnrm: + mov.b DTAG(%a6),%d1 + beq.l sscale + cmpi.b %d1,&ZERO + beq.l dst_zero + cmpi.b %d1,&INF + beq.l dst_inf + cmpi.b %d1,&DENORM + beq.l sscale + bra.l dst_qnan + + global sscale_szero +sscale_szero: + mov.b DTAG(%a6),%d1 + beq.l sscale + cmpi.b %d1,&ZERO + beq.l dst_zero + cmpi.b %d1,&INF + beq.l dst_inf + cmpi.b %d1,&DENORM + beq.l sscale + bra.l dst_qnan + + global sscale_sinf +sscale_sinf: + mov.b DTAG(%a6),%d1 + beq.l t_operr + cmpi.b %d1,&QNAN + beq.l dst_qnan + bra.l t_operr + +######################################################################## + + global sop_sqnan +sop_sqnan: + mov.b DTAG(%a6),%d1 + cmpi.b %d1,&QNAN + beq.l dst_qnan + bra.l src_qnan + +######################################################################### +# norm(): normalize the mantissa of an extended precision input. the # +# input operand should not be normalized already. # +# # +# XDEF **************************************************************** # +# norm() # +# # +# XREF **************************************************************** # +# none # +# # +# INPUT *************************************************************** # +# a0 = pointer fp extended precision operand to normalize # +# # +# OUTPUT ************************************************************** # +# d0 = number of bit positions the mantissa was shifted # +# a0 = the input operand's mantissa is normalized; the exponent # +# is unchanged. # +# # +######################################################################### + global norm +norm: + mov.l %d2, -(%sp) # create some temp regs + mov.l %d3, -(%sp) + + mov.l FTEMP_HI(%a0), %d0 # load hi(mantissa) + mov.l FTEMP_LO(%a0), %d1 # load lo(mantissa) + + bfffo %d0{&0:&32}, %d2 # how many places to shift? + beq.b norm_lo # hi(man) is all zeroes! + +norm_hi: + lsl.l %d2, %d0 # left shift hi(man) + bfextu %d1{&0:%d2}, %d3 # extract lo bits + + or.l %d3, %d0 # create hi(man) + lsl.l %d2, %d1 # create lo(man) + + mov.l %d0, FTEMP_HI(%a0) # store new hi(man) + mov.l %d1, FTEMP_LO(%a0) # store new lo(man) + + mov.l %d2, %d0 # return shift amount + + mov.l (%sp)+, %d3 # restore temp regs + mov.l (%sp)+, %d2 + + rts + +norm_lo: + bfffo %d1{&0:&32}, %d2 # how many places to shift? + lsl.l %d2, %d1 # shift lo(man) + add.l &32, %d2 # add 32 to shft amount + + mov.l %d1, FTEMP_HI(%a0) # store hi(man) + clr.l FTEMP_LO(%a0) # lo(man) is now zero + + mov.l %d2, %d0 # return shift amount + + mov.l (%sp)+, %d3 # restore temp regs + mov.l (%sp)+, %d2 + + rts + +######################################################################### +# unnorm_fix(): - changes an UNNORM to one of NORM, DENORM, or ZERO # +# - returns corresponding optype tag # +# # +# XDEF **************************************************************** # +# unnorm_fix() # +# # +# XREF **************************************************************** # +# norm() - normalize the mantissa # +# # +# INPUT *************************************************************** # +# a0 = pointer to unnormalized extended precision number # +# # +# OUTPUT ************************************************************** # +# d0 = optype tag - is corrected to one of NORM, DENORM, or ZERO # +# a0 = input operand has been converted to a norm, denorm, or # +# zero; both the exponent and mantissa are changed. # +# # +######################################################################### + + global unnorm_fix +unnorm_fix: + bfffo FTEMP_HI(%a0){&0:&32}, %d0 # how many shifts are needed? + bne.b unnorm_shift # hi(man) is not all zeroes + +# +# hi(man) is all zeroes so see if any bits in lo(man) are set +# +unnorm_chk_lo: + bfffo FTEMP_LO(%a0){&0:&32}, %d0 # is operand really a zero? + beq.w unnorm_zero # yes + + add.w &32, %d0 # no; fix shift distance + +# +# d0 = # shifts needed for complete normalization +# +unnorm_shift: + clr.l %d1 # clear top word + mov.w FTEMP_EX(%a0), %d1 # extract exponent + and.w &0x7fff, %d1 # strip off sgn + + cmp.w %d0, %d1 # will denorm push exp < 0? + bgt.b unnorm_nrm_zero # yes; denorm only until exp = 0 + +# +# exponent would not go < 0. therefore, number stays normalized +# + sub.w %d0, %d1 # shift exponent value + mov.w FTEMP_EX(%a0), %d0 # load old exponent + and.w &0x8000, %d0 # save old sign + or.w %d0, %d1 # {sgn,new exp} + mov.w %d1, FTEMP_EX(%a0) # insert new exponent + + bsr.l norm # normalize UNNORM + + mov.b &NORM, %d0 # return new optype tag + rts + +# +# exponent would go < 0, so only denormalize until exp = 0 +# +unnorm_nrm_zero: + cmp.b %d1, &32 # is exp <= 32? + bgt.b unnorm_nrm_zero_lrg # no; go handle large exponent + + bfextu FTEMP_HI(%a0){%d1:&32}, %d0 # extract new hi(man) + mov.l %d0, FTEMP_HI(%a0) # save new hi(man) + + mov.l FTEMP_LO(%a0), %d0 # fetch old lo(man) + lsl.l %d1, %d0 # extract new lo(man) + mov.l %d0, FTEMP_LO(%a0) # save new lo(man) + + and.w &0x8000, FTEMP_EX(%a0) # set exp = 0 + + mov.b &DENORM, %d0 # return new optype tag + rts + +# +# only mantissa bits set are in lo(man) +# +unnorm_nrm_zero_lrg: + sub.w &32, %d1 # adjust shft amt by 32 + + mov.l FTEMP_LO(%a0), %d0 # fetch old lo(man) + lsl.l %d1, %d0 # left shift lo(man) + + mov.l %d0, FTEMP_HI(%a0) # store new hi(man) + clr.l FTEMP_LO(%a0) # lo(man) = 0 + + and.w &0x8000, FTEMP_EX(%a0) # set exp = 0 + + mov.b &DENORM, %d0 # return new optype tag + rts + +# +# whole mantissa is zero so this UNNORM is actually a zero +# +unnorm_zero: + and.w &0x8000, FTEMP_EX(%a0) # force exponent to zero + + mov.b &ZERO, %d0 # fix optype tag + rts diff --git a/arch/m68k/ifpsp060/src/fpsp.S b/arch/m68k/ifpsp060/src/fpsp.S new file mode 100644 index 000000000..9bbffebe3 --- /dev/null +++ b/arch/m68k/ifpsp060/src/fpsp.S @@ -0,0 +1,24785 @@ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP +M68000 Hi-Performance Microprocessor Division +M68060 Software Package +Production Release P1.00 -- October 10, 1994 + +M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. + +THE SOFTWARE is provided on an "AS IS" basis and without warranty. +To the maximum extent permitted by applicable law, +MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, +INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE +and any warranty against infringement with regard to the SOFTWARE +(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. + +To the maximum extent permitted by applicable law, +IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, +BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) +ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. +Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. + +You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE +so long as this entire notice is retained without alteration in any modified and/or +redistributed versions, and that such modified versions are clearly identified as such. +No licenses are granted by implication, estoppel or otherwise under any patents +or trademarks of Motorola, Inc. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +# +# freal.s: +# This file is appended to the top of the 060FPSP package +# and contains the entry points into the package. The user, in +# effect, branches to one of the branch table entries located +# after _060FPSP_TABLE. +# Also, subroutine stubs exist in this file (_fpsp_done for +# example) that are referenced by the FPSP package itself in order +# to call a given routine. The stub routine actually performs the +# callout. The FPSP code does a "bsr" to the stub routine. This +# extra layer of hierarchy adds a slight performance penalty but +# it makes the FPSP code easier to read and more mainatinable. +# + +set _off_bsun, 0x00 +set _off_snan, 0x04 +set _off_operr, 0x08 +set _off_ovfl, 0x0c +set _off_unfl, 0x10 +set _off_dz, 0x14 +set _off_inex, 0x18 +set _off_fline, 0x1c +set _off_fpu_dis, 0x20 +set _off_trap, 0x24 +set _off_trace, 0x28 +set _off_access, 0x2c +set _off_done, 0x30 + +set _off_imr, 0x40 +set _off_dmr, 0x44 +set _off_dmw, 0x48 +set _off_irw, 0x4c +set _off_irl, 0x50 +set _off_drb, 0x54 +set _off_drw, 0x58 +set _off_drl, 0x5c +set _off_dwb, 0x60 +set _off_dww, 0x64 +set _off_dwl, 0x68 + +_060FPSP_TABLE: + +############################################################### + +# Here's the table of ENTRY POINTS for those linking the package. + bra.l _fpsp_snan + short 0x0000 + bra.l _fpsp_operr + short 0x0000 + bra.l _fpsp_ovfl + short 0x0000 + bra.l _fpsp_unfl + short 0x0000 + bra.l _fpsp_dz + short 0x0000 + bra.l _fpsp_inex + short 0x0000 + bra.l _fpsp_fline + short 0x0000 + bra.l _fpsp_unsupp + short 0x0000 + bra.l _fpsp_effadd + short 0x0000 + + space 56 + +############################################################### + global _fpsp_done +_fpsp_done: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_done,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _real_ovfl +_real_ovfl: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_ovfl,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _real_unfl +_real_unfl: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_unfl,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _real_inex +_real_inex: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_inex,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _real_bsun +_real_bsun: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_bsun,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _real_operr +_real_operr: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_operr,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _real_snan +_real_snan: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_snan,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _real_dz +_real_dz: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_dz,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _real_fline +_real_fline: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_fline,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _real_fpu_disabled +_real_fpu_disabled: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_fpu_dis,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _real_trap +_real_trap: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_trap,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _real_trace +_real_trace: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_trace,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _real_access +_real_access: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_access,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + +####################################### + + global _imem_read +_imem_read: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_imr,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _dmem_read +_dmem_read: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_dmr,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _dmem_write +_dmem_write: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_dmw,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _imem_read_word +_imem_read_word: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_irw,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _imem_read_long +_imem_read_long: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_irl,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _dmem_read_byte +_dmem_read_byte: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_drb,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _dmem_read_word +_dmem_read_word: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_drw,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _dmem_read_long +_dmem_read_long: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_drl,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _dmem_write_byte +_dmem_write_byte: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_dwb,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _dmem_write_word +_dmem_write_word: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_dww,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _dmem_write_long +_dmem_write_long: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_dwl,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + +# +# This file contains a set of define statements for constants +# in order to promote readability within the corecode itself. +# + +set LOCAL_SIZE, 192 # stack frame size(bytes) +set LV, -LOCAL_SIZE # stack offset + +set EXC_SR, 0x4 # stack status register +set EXC_PC, 0x6 # stack pc +set EXC_VOFF, 0xa # stacked vector offset +set EXC_EA, 0xc # stacked + +set EXC_FP, 0x0 # frame pointer + +set EXC_AREGS, -68 # offset of all address regs +set EXC_DREGS, -100 # offset of all data regs +set EXC_FPREGS, -36 # offset of all fp regs + +set EXC_A7, EXC_AREGS+(7*4) # offset of saved a7 +set OLD_A7, EXC_AREGS+(6*4) # extra copy of saved a7 +set EXC_A6, EXC_AREGS+(6*4) # offset of saved a6 +set EXC_A5, EXC_AREGS+(5*4) +set EXC_A4, EXC_AREGS+(4*4) +set EXC_A3, EXC_AREGS+(3*4) +set EXC_A2, EXC_AREGS+(2*4) +set EXC_A1, EXC_AREGS+(1*4) +set EXC_A0, EXC_AREGS+(0*4) +set EXC_D7, EXC_DREGS+(7*4) +set EXC_D6, EXC_DREGS+(6*4) +set EXC_D5, EXC_DREGS+(5*4) +set EXC_D4, EXC_DREGS+(4*4) +set EXC_D3, EXC_DREGS+(3*4) +set EXC_D2, EXC_DREGS+(2*4) +set EXC_D1, EXC_DREGS+(1*4) +set EXC_D0, EXC_DREGS+(0*4) + +set EXC_FP0, EXC_FPREGS+(0*12) # offset of saved fp0 +set EXC_FP1, EXC_FPREGS+(1*12) # offset of saved fp1 +set EXC_FP2, EXC_FPREGS+(2*12) # offset of saved fp2 (not used) + +set FP_SCR1, LV+80 # fp scratch 1 +set FP_SCR1_EX, FP_SCR1+0 +set FP_SCR1_SGN, FP_SCR1+2 +set FP_SCR1_HI, FP_SCR1+4 +set FP_SCR1_LO, FP_SCR1+8 + +set FP_SCR0, LV+68 # fp scratch 0 +set FP_SCR0_EX, FP_SCR0+0 +set FP_SCR0_SGN, FP_SCR0+2 +set FP_SCR0_HI, FP_SCR0+4 +set FP_SCR0_LO, FP_SCR0+8 + +set FP_DST, LV+56 # fp destination operand +set FP_DST_EX, FP_DST+0 +set FP_DST_SGN, FP_DST+2 +set FP_DST_HI, FP_DST+4 +set FP_DST_LO, FP_DST+8 + +set FP_SRC, LV+44 # fp source operand +set FP_SRC_EX, FP_SRC+0 +set FP_SRC_SGN, FP_SRC+2 +set FP_SRC_HI, FP_SRC+4 +set FP_SRC_LO, FP_SRC+8 + +set USER_FPIAR, LV+40 # FP instr address register + +set USER_FPSR, LV+36 # FP status register +set FPSR_CC, USER_FPSR+0 # FPSR condition codes +set FPSR_QBYTE, USER_FPSR+1 # FPSR qoutient byte +set FPSR_EXCEPT, USER_FPSR+2 # FPSR exception status byte +set FPSR_AEXCEPT, USER_FPSR+3 # FPSR accrued exception byte + +set USER_FPCR, LV+32 # FP control register +set FPCR_ENABLE, USER_FPCR+2 # FPCR exception enable +set FPCR_MODE, USER_FPCR+3 # FPCR rounding mode control + +set L_SCR3, LV+28 # integer scratch 3 +set L_SCR2, LV+24 # integer scratch 2 +set L_SCR1, LV+20 # integer scratch 1 + +set STORE_FLG, LV+19 # flag: operand store (ie. not fcmp/ftst) + +set EXC_TEMP2, LV+24 # temporary space +set EXC_TEMP, LV+16 # temporary space + +set DTAG, LV+15 # destination operand type +set STAG, LV+14 # source operand type + +set SPCOND_FLG, LV+10 # flag: special case (see below) + +set EXC_CC, LV+8 # saved condition codes +set EXC_EXTWPTR, LV+4 # saved current PC (active) +set EXC_EXTWORD, LV+2 # saved extension word +set EXC_CMDREG, LV+2 # saved extension word +set EXC_OPWORD, LV+0 # saved operation word + +################################ + +# Helpful macros + +set FTEMP, 0 # offsets within an +set FTEMP_EX, 0 # extended precision +set FTEMP_SGN, 2 # value saved in memory. +set FTEMP_HI, 4 +set FTEMP_LO, 8 +set FTEMP_GRS, 12 + +set LOCAL, 0 # offsets within an +set LOCAL_EX, 0 # extended precision +set LOCAL_SGN, 2 # value saved in memory. +set LOCAL_HI, 4 +set LOCAL_LO, 8 +set LOCAL_GRS, 12 + +set DST, 0 # offsets within an +set DST_EX, 0 # extended precision +set DST_HI, 4 # value saved in memory. +set DST_LO, 8 + +set SRC, 0 # offsets within an +set SRC_EX, 0 # extended precision +set SRC_HI, 4 # value saved in memory. +set SRC_LO, 8 + +set SGL_LO, 0x3f81 # min sgl prec exponent +set SGL_HI, 0x407e # max sgl prec exponent +set DBL_LO, 0x3c01 # min dbl prec exponent +set DBL_HI, 0x43fe # max dbl prec exponent +set EXT_LO, 0x0 # min ext prec exponent +set EXT_HI, 0x7ffe # max ext prec exponent + +set EXT_BIAS, 0x3fff # extended precision bias +set SGL_BIAS, 0x007f # single precision bias +set DBL_BIAS, 0x03ff # double precision bias + +set NORM, 0x00 # operand type for STAG/DTAG +set ZERO, 0x01 # operand type for STAG/DTAG +set INF, 0x02 # operand type for STAG/DTAG +set QNAN, 0x03 # operand type for STAG/DTAG +set DENORM, 0x04 # operand type for STAG/DTAG +set SNAN, 0x05 # operand type for STAG/DTAG +set UNNORM, 0x06 # operand type for STAG/DTAG + +################## +# FPSR/FPCR bits # +################## +set neg_bit, 0x3 # negative result +set z_bit, 0x2 # zero result +set inf_bit, 0x1 # infinite result +set nan_bit, 0x0 # NAN result + +set q_sn_bit, 0x7 # sign bit of quotient byte + +set bsun_bit, 7 # branch on unordered +set snan_bit, 6 # signalling NAN +set operr_bit, 5 # operand error +set ovfl_bit, 4 # overflow +set unfl_bit, 3 # underflow +set dz_bit, 2 # divide by zero +set inex2_bit, 1 # inexact result 2 +set inex1_bit, 0 # inexact result 1 + +set aiop_bit, 7 # accrued inexact operation bit +set aovfl_bit, 6 # accrued overflow bit +set aunfl_bit, 5 # accrued underflow bit +set adz_bit, 4 # accrued dz bit +set ainex_bit, 3 # accrued inexact bit + +############################# +# FPSR individual bit masks # +############################# +set neg_mask, 0x08000000 # negative bit mask (lw) +set inf_mask, 0x02000000 # infinity bit mask (lw) +set z_mask, 0x04000000 # zero bit mask (lw) +set nan_mask, 0x01000000 # nan bit mask (lw) + +set neg_bmask, 0x08 # negative bit mask (byte) +set inf_bmask, 0x02 # infinity bit mask (byte) +set z_bmask, 0x04 # zero bit mask (byte) +set nan_bmask, 0x01 # nan bit mask (byte) + +set bsun_mask, 0x00008000 # bsun exception mask +set snan_mask, 0x00004000 # snan exception mask +set operr_mask, 0x00002000 # operr exception mask +set ovfl_mask, 0x00001000 # overflow exception mask +set unfl_mask, 0x00000800 # underflow exception mask +set dz_mask, 0x00000400 # dz exception mask +set inex2_mask, 0x00000200 # inex2 exception mask +set inex1_mask, 0x00000100 # inex1 exception mask + +set aiop_mask, 0x00000080 # accrued illegal operation +set aovfl_mask, 0x00000040 # accrued overflow +set aunfl_mask, 0x00000020 # accrued underflow +set adz_mask, 0x00000010 # accrued divide by zero +set ainex_mask, 0x00000008 # accrued inexact + +###################################### +# FPSR combinations used in the FPSP # +###################################### +set dzinf_mask, inf_mask+dz_mask+adz_mask +set opnan_mask, nan_mask+operr_mask+aiop_mask +set nzi_mask, 0x01ffffff #clears N, Z, and I +set unfinx_mask, unfl_mask+inex2_mask+aunfl_mask+ainex_mask +set unf2inx_mask, unfl_mask+inex2_mask+ainex_mask +set ovfinx_mask, ovfl_mask+inex2_mask+aovfl_mask+ainex_mask +set inx1a_mask, inex1_mask+ainex_mask +set inx2a_mask, inex2_mask+ainex_mask +set snaniop_mask, nan_mask+snan_mask+aiop_mask +set snaniop2_mask, snan_mask+aiop_mask +set naniop_mask, nan_mask+aiop_mask +set neginf_mask, neg_mask+inf_mask +set infaiop_mask, inf_mask+aiop_mask +set negz_mask, neg_mask+z_mask +set opaop_mask, operr_mask+aiop_mask +set unfl_inx_mask, unfl_mask+aunfl_mask+ainex_mask +set ovfl_inx_mask, ovfl_mask+aovfl_mask+ainex_mask + +######### +# misc. # +######### +set rnd_stky_bit, 29 # stky bit pos in longword + +set sign_bit, 0x7 # sign bit +set signan_bit, 0x6 # signalling nan bit + +set sgl_thresh, 0x3f81 # minimum sgl exponent +set dbl_thresh, 0x3c01 # minimum dbl exponent + +set x_mode, 0x0 # extended precision +set s_mode, 0x4 # single precision +set d_mode, 0x8 # double precision + +set rn_mode, 0x0 # round-to-nearest +set rz_mode, 0x1 # round-to-zero +set rm_mode, 0x2 # round-tp-minus-infinity +set rp_mode, 0x3 # round-to-plus-infinity + +set mantissalen, 64 # length of mantissa in bits + +set BYTE, 1 # len(byte) == 1 byte +set WORD, 2 # len(word) == 2 bytes +set LONG, 4 # len(longword) == 2 bytes + +set BSUN_VEC, 0xc0 # bsun vector offset +set INEX_VEC, 0xc4 # inexact vector offset +set DZ_VEC, 0xc8 # dz vector offset +set UNFL_VEC, 0xcc # unfl vector offset +set OPERR_VEC, 0xd0 # operr vector offset +set OVFL_VEC, 0xd4 # ovfl vector offset +set SNAN_VEC, 0xd8 # snan vector offset + +########################### +# SPecial CONDition FLaGs # +########################### +set ftrapcc_flg, 0x01 # flag bit: ftrapcc exception +set fbsun_flg, 0x02 # flag bit: bsun exception +set mia7_flg, 0x04 # flag bit: (a7)+ +set mda7_flg, 0x08 # flag bit: -(a7) +set fmovm_flg, 0x40 # flag bit: fmovm instruction +set immed_flg, 0x80 # flag bit: & + +set ftrapcc_bit, 0x0 +set fbsun_bit, 0x1 +set mia7_bit, 0x2 +set mda7_bit, 0x3 +set immed_bit, 0x7 + +################################## +# TRANSCENDENTAL "LAST-OP" FLAGS # +################################## +set FMUL_OP, 0x0 # fmul instr performed last +set FDIV_OP, 0x1 # fdiv performed last +set FADD_OP, 0x2 # fadd performed last +set FMOV_OP, 0x3 # fmov performed last + +############# +# CONSTANTS # +############# +T1: long 0x40C62D38,0xD3D64634 # 16381 LOG2 LEAD +T2: long 0x3D6F90AE,0xB1E75CC7 # 16381 LOG2 TRAIL + +PI: long 0x40000000,0xC90FDAA2,0x2168C235,0x00000000 +PIBY2: long 0x3FFF0000,0xC90FDAA2,0x2168C235,0x00000000 + +TWOBYPI: + long 0x3FE45F30,0x6DC9C883 + +######################################################################### +# XDEF **************************************************************** # +# _fpsp_ovfl(): 060FPSP entry point for FP Overflow exception. # +# # +# This handler should be the first code executed upon taking the # +# FP Overflow exception in an operating system. # +# # +# XREF **************************************************************** # +# _imem_read_long() - read instruction longword # +# fix_skewed_ops() - adjust src operand in fsave frame # +# set_tag_x() - determine optype of src/dst operands # +# store_fpreg() - store opclass 0 or 2 result to FP regfile # +# unnorm_fix() - change UNNORM operands to NORM or ZERO # +# load_fpn2() - load dst operand from FP regfile # +# fout() - emulate an opclass 3 instruction # +# tbl_unsupp - add of table of emulation routines for opclass 0,2 # +# _fpsp_done() - "callout" for 060FPSP exit (all work done!) # +# _real_ovfl() - "callout" for Overflow exception enabled code # +# _real_inex() - "callout" for Inexact exception enabled code # +# _real_trace() - "callout" for Trace exception code # +# # +# INPUT *************************************************************** # +# - The system stack contains the FP Ovfl exception stack frame # +# - The fsave frame contains the source operand # +# # +# OUTPUT ************************************************************** # +# Overflow Exception enabled: # +# - The system stack is unchanged # +# - The fsave frame contains the adjusted src op for opclass 0,2 # +# Overflow Exception disabled: # +# - The system stack is unchanged # +# - The "exception present" flag in the fsave frame is cleared # +# # +# ALGORITHM *********************************************************** # +# On the 060, if an FP overflow is present as the result of any # +# instruction, the 060 will take an overflow exception whether the # +# exception is enabled or disabled in the FPCR. For the disabled case, # +# This handler emulates the instruction to determine what the correct # +# default result should be for the operation. This default result is # +# then stored in either the FP regfile, data regfile, or memory. # +# Finally, the handler exits through the "callout" _fpsp_done() # +# denoting that no exceptional conditions exist within the machine. # +# If the exception is enabled, then this handler must create the # +# exceptional operand and plave it in the fsave state frame, and store # +# the default result (only if the instruction is opclass 3). For # +# exceptions enabled, this handler must exit through the "callout" # +# _real_ovfl() so that the operating system enabled overflow handler # +# can handle this case. # +# Two other conditions exist. First, if overflow was disabled # +# but the inexact exception was enabled, this handler must exit # +# through the "callout" _real_inex() regardless of whether the result # +# was inexact. # +# Also, in the case of an opclass three instruction where # +# overflow was disabled and the trace exception was enabled, this # +# handler must exit through the "callout" _real_trace(). # +# # +######################################################################### + + global _fpsp_ovfl +_fpsp_ovfl: + +#$# sub.l &24,%sp # make room for src/dst + + link.w %a6,&-LOCAL_SIZE # init stack frame + + fsave FP_SRC(%a6) # grab the "busy" frame + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack + +# the FPIAR holds the "current PC" of the faulting instruction + mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) + mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr + addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr + bsr.l _imem_read_long # fetch the instruction words + mov.l %d0,EXC_OPWORD(%a6) + +############################################################################## + + btst &0x5,EXC_CMDREG(%a6) # is instr an fmove out? + bne.w fovfl_out + + + lea FP_SRC(%a6),%a0 # pass: ptr to src op + bsr.l fix_skewed_ops # fix src op + +# since, I believe, only NORMs and DENORMs can come through here, +# maybe we can avoid the subroutine call. + lea FP_SRC(%a6),%a0 # pass: ptr to src op + bsr.l set_tag_x # tag the operand type + mov.b %d0,STAG(%a6) # maybe NORM,DENORM + +# bit five of the fp extension word separates the monadic and dyadic operations +# that can pass through fpsp_ovfl(). remember that fcmp, ftst, and fsincos +# will never take this exception. + btst &0x5,1+EXC_CMDREG(%a6) # is operation monadic or dyadic? + beq.b fovfl_extract # monadic + + bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg + bsr.l load_fpn2 # load dst into FP_DST + + lea FP_DST(%a6),%a0 # pass: ptr to dst op + bsr.l set_tag_x # tag the operand type + cmpi.b %d0,&UNNORM # is operand an UNNORM? + bne.b fovfl_op2_done # no + bsr.l unnorm_fix # yes; convert to NORM,DENORM,or ZERO +fovfl_op2_done: + mov.b %d0,DTAG(%a6) # save dst optype tag + +fovfl_extract: + +#$# mov.l FP_SRC_EX(%a6),TRAP_SRCOP_EX(%a6) +#$# mov.l FP_SRC_HI(%a6),TRAP_SRCOP_HI(%a6) +#$# mov.l FP_SRC_LO(%a6),TRAP_SRCOP_LO(%a6) +#$# mov.l FP_DST_EX(%a6),TRAP_DSTOP_EX(%a6) +#$# mov.l FP_DST_HI(%a6),TRAP_DSTOP_HI(%a6) +#$# mov.l FP_DST_LO(%a6),TRAP_DSTOP_LO(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode + + mov.b 1+EXC_CMDREG(%a6),%d1 + andi.w &0x007f,%d1 # extract extension + + andi.l &0x00ff01ff,USER_FPSR(%a6) # zero all but accured field + + fmov.l &0x0,%fpcr # zero current control regs + fmov.l &0x0,%fpsr + + lea FP_SRC(%a6),%a0 + lea FP_DST(%a6),%a1 + +# maybe we can make these entry points ONLY the OVFL entry points of each routine. + mov.l (tbl_unsupp.l,%pc,%d1.w*4),%d1 # fetch routine addr + jsr (tbl_unsupp.l,%pc,%d1.l*1) + +# the operation has been emulated. the result is in fp0. +# the EXOP, if an exception occurred, is in fp1. +# we must save the default result regardless of whether +# traps are enabled or disabled. + bfextu EXC_CMDREG(%a6){&6:&3},%d0 + bsr.l store_fpreg + +# the exceptional possibilities we have left ourselves with are ONLY overflow +# and inexact. and, the inexact is such that overflow occurred and was disabled +# but inexact was enabled. + btst &ovfl_bit,FPCR_ENABLE(%a6) + bne.b fovfl_ovfl_on + + btst &inex2_bit,FPCR_ENABLE(%a6) + bne.b fovfl_inex_on + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 +#$# add.l &24,%sp + bra.l _fpsp_done + +# overflow is enabled AND overflow, of course, occurred. so, we have the EXOP +# in fp1. now, simply jump to _real_ovfl()! +fovfl_ovfl_on: + fmovm.x &0x40,FP_SRC(%a6) # save EXOP (fp1) to stack + + mov.w &0xe005,2+FP_SRC(%a6) # save exc status + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + frestore FP_SRC(%a6) # do this after fmovm,other fs! + + unlk %a6 + + bra.l _real_ovfl + +# overflow occurred but is disabled. meanwhile, inexact is enabled. Therefore, +# we must jump to real_inex(). +fovfl_inex_on: + + fmovm.x &0x40,FP_SRC(%a6) # save EXOP (fp1) to stack + + mov.b &0xc4,1+EXC_VOFF(%a6) # vector offset = 0xc4 + mov.w &0xe001,2+FP_SRC(%a6) # save exc status + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + frestore FP_SRC(%a6) # do this after fmovm,other fs! + + unlk %a6 + + bra.l _real_inex + +######################################################################## +fovfl_out: + + +#$# mov.l FP_SRC_EX(%a6),TRAP_SRCOP_EX(%a6) +#$# mov.l FP_SRC_HI(%a6),TRAP_SRCOP_HI(%a6) +#$# mov.l FP_SRC_LO(%a6),TRAP_SRCOP_LO(%a6) + +# the src operand is definitely a NORM(!), so tag it as such + mov.b &NORM,STAG(%a6) # set src optype tag + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode + + and.l &0xffff00ff,USER_FPSR(%a6) # zero all but accured field + + fmov.l &0x0,%fpcr # zero current control regs + fmov.l &0x0,%fpsr + + lea FP_SRC(%a6),%a0 # pass ptr to src operand + + bsr.l fout + + btst &ovfl_bit,FPCR_ENABLE(%a6) + bne.w fovfl_ovfl_on + + btst &inex2_bit,FPCR_ENABLE(%a6) + bne.w fovfl_inex_on + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 +#$# add.l &24,%sp + + btst &0x7,(%sp) # is trace on? + beq.l _fpsp_done # no + + fmov.l %fpiar,0x8(%sp) # "Current PC" is in FPIAR + mov.w &0x2024,0x6(%sp) # stk fmt = 0x2; voff = 0x024 + bra.l _real_trace + +######################################################################### +# XDEF **************************************************************** # +# _fpsp_unfl(): 060FPSP entry point for FP Underflow exception. # +# # +# This handler should be the first code executed upon taking the # +# FP Underflow exception in an operating system. # +# # +# XREF **************************************************************** # +# _imem_read_long() - read instruction longword # +# fix_skewed_ops() - adjust src operand in fsave frame # +# set_tag_x() - determine optype of src/dst operands # +# store_fpreg() - store opclass 0 or 2 result to FP regfile # +# unnorm_fix() - change UNNORM operands to NORM or ZERO # +# load_fpn2() - load dst operand from FP regfile # +# fout() - emulate an opclass 3 instruction # +# tbl_unsupp - add of table of emulation routines for opclass 0,2 # +# _fpsp_done() - "callout" for 060FPSP exit (all work done!) # +# _real_ovfl() - "callout" for Overflow exception enabled code # +# _real_inex() - "callout" for Inexact exception enabled code # +# _real_trace() - "callout" for Trace exception code # +# # +# INPUT *************************************************************** # +# - The system stack contains the FP Unfl exception stack frame # +# - The fsave frame contains the source operand # +# # +# OUTPUT ************************************************************** # +# Underflow Exception enabled: # +# - The system stack is unchanged # +# - The fsave frame contains the adjusted src op for opclass 0,2 # +# Underflow Exception disabled: # +# - The system stack is unchanged # +# - The "exception present" flag in the fsave frame is cleared # +# # +# ALGORITHM *********************************************************** # +# On the 060, if an FP underflow is present as the result of any # +# instruction, the 060 will take an underflow exception whether the # +# exception is enabled or disabled in the FPCR. For the disabled case, # +# This handler emulates the instruction to determine what the correct # +# default result should be for the operation. This default result is # +# then stored in either the FP regfile, data regfile, or memory. # +# Finally, the handler exits through the "callout" _fpsp_done() # +# denoting that no exceptional conditions exist within the machine. # +# If the exception is enabled, then this handler must create the # +# exceptional operand and plave it in the fsave state frame, and store # +# the default result (only if the instruction is opclass 3). For # +# exceptions enabled, this handler must exit through the "callout" # +# _real_unfl() so that the operating system enabled overflow handler # +# can handle this case. # +# Two other conditions exist. First, if underflow was disabled # +# but the inexact exception was enabled and the result was inexact, # +# this handler must exit through the "callout" _real_inex(). # +# was inexact. # +# Also, in the case of an opclass three instruction where # +# underflow was disabled and the trace exception was enabled, this # +# handler must exit through the "callout" _real_trace(). # +# # +######################################################################### + + global _fpsp_unfl +_fpsp_unfl: + +#$# sub.l &24,%sp # make room for src/dst + + link.w %a6,&-LOCAL_SIZE # init stack frame + + fsave FP_SRC(%a6) # grab the "busy" frame + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack + +# the FPIAR holds the "current PC" of the faulting instruction + mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) + mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr + addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr + bsr.l _imem_read_long # fetch the instruction words + mov.l %d0,EXC_OPWORD(%a6) + +############################################################################## + + btst &0x5,EXC_CMDREG(%a6) # is instr an fmove out? + bne.w funfl_out + + + lea FP_SRC(%a6),%a0 # pass: ptr to src op + bsr.l fix_skewed_ops # fix src op + + lea FP_SRC(%a6),%a0 # pass: ptr to src op + bsr.l set_tag_x # tag the operand type + mov.b %d0,STAG(%a6) # maybe NORM,DENORM + +# bit five of the fp ext word separates the monadic and dyadic operations +# that can pass through fpsp_unfl(). remember that fcmp, and ftst +# will never take this exception. + btst &0x5,1+EXC_CMDREG(%a6) # is op monadic or dyadic? + beq.b funfl_extract # monadic + +# now, what's left that's not dyadic is fsincos. we can distinguish it +# from all dyadics by the '0110xxx pattern + btst &0x4,1+EXC_CMDREG(%a6) # is op an fsincos? + bne.b funfl_extract # yes + + bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg + bsr.l load_fpn2 # load dst into FP_DST + + lea FP_DST(%a6),%a0 # pass: ptr to dst op + bsr.l set_tag_x # tag the operand type + cmpi.b %d0,&UNNORM # is operand an UNNORM? + bne.b funfl_op2_done # no + bsr.l unnorm_fix # yes; convert to NORM,DENORM,or ZERO +funfl_op2_done: + mov.b %d0,DTAG(%a6) # save dst optype tag + +funfl_extract: + +#$# mov.l FP_SRC_EX(%a6),TRAP_SRCOP_EX(%a6) +#$# mov.l FP_SRC_HI(%a6),TRAP_SRCOP_HI(%a6) +#$# mov.l FP_SRC_LO(%a6),TRAP_SRCOP_LO(%a6) +#$# mov.l FP_DST_EX(%a6),TRAP_DSTOP_EX(%a6) +#$# mov.l FP_DST_HI(%a6),TRAP_DSTOP_HI(%a6) +#$# mov.l FP_DST_LO(%a6),TRAP_DSTOP_LO(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode + + mov.b 1+EXC_CMDREG(%a6),%d1 + andi.w &0x007f,%d1 # extract extension + + andi.l &0x00ff01ff,USER_FPSR(%a6) + + fmov.l &0x0,%fpcr # zero current control regs + fmov.l &0x0,%fpsr + + lea FP_SRC(%a6),%a0 + lea FP_DST(%a6),%a1 + +# maybe we can make these entry points ONLY the OVFL entry points of each routine. + mov.l (tbl_unsupp.l,%pc,%d1.w*4),%d1 # fetch routine addr + jsr (tbl_unsupp.l,%pc,%d1.l*1) + + bfextu EXC_CMDREG(%a6){&6:&3},%d0 + bsr.l store_fpreg + +# The `060 FPU multiplier hardware is such that if the result of a +# multiply operation is the smallest possible normalized number +# (0x00000000_80000000_00000000), then the machine will take an +# underflow exception. Since this is incorrect, we need to check +# if our emulation, after re-doing the operation, decided that +# no underflow was called for. We do these checks only in +# funfl_{unfl,inex}_on() because w/ both exceptions disabled, this +# special case will simply exit gracefully with the correct result. + +# the exceptional possibilities we have left ourselves with are ONLY overflow +# and inexact. and, the inexact is such that overflow occurred and was disabled +# but inexact was enabled. + btst &unfl_bit,FPCR_ENABLE(%a6) + bne.b funfl_unfl_on + +funfl_chkinex: + btst &inex2_bit,FPCR_ENABLE(%a6) + bne.b funfl_inex_on + +funfl_exit: + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 +#$# add.l &24,%sp + bra.l _fpsp_done + +# overflow is enabled AND overflow, of course, occurred. so, we have the EXOP +# in fp1 (don't forget to save fp0). what to do now? +# well, we simply have to get to go to _real_unfl()! +funfl_unfl_on: + +# The `060 FPU multiplier hardware is such that if the result of a +# multiply operation is the smallest possible normalized number +# (0x00000000_80000000_00000000), then the machine will take an +# underflow exception. Since this is incorrect, we check here to see +# if our emulation, after re-doing the operation, decided that +# no underflow was called for. + btst &unfl_bit,FPSR_EXCEPT(%a6) + beq.w funfl_chkinex + +funfl_unfl_on2: + fmovm.x &0x40,FP_SRC(%a6) # save EXOP (fp1) to stack + + mov.w &0xe003,2+FP_SRC(%a6) # save exc status + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + frestore FP_SRC(%a6) # do this after fmovm,other fs! + + unlk %a6 + + bra.l _real_unfl + +# underflow occurred but is disabled. meanwhile, inexact is enabled. Therefore, +# we must jump to real_inex(). +funfl_inex_on: + +# The `060 FPU multiplier hardware is such that if the result of a +# multiply operation is the smallest possible normalized number +# (0x00000000_80000000_00000000), then the machine will take an +# underflow exception. +# But, whether bogus or not, if inexact is enabled AND it occurred, +# then we have to branch to real_inex. + + btst &inex2_bit,FPSR_EXCEPT(%a6) + beq.w funfl_exit + +funfl_inex_on2: + + fmovm.x &0x40,FP_SRC(%a6) # save EXOP to stack + + mov.b &0xc4,1+EXC_VOFF(%a6) # vector offset = 0xc4 + mov.w &0xe001,2+FP_SRC(%a6) # save exc status + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + frestore FP_SRC(%a6) # do this after fmovm,other fs! + + unlk %a6 + + bra.l _real_inex + +####################################################################### +funfl_out: + + +#$# mov.l FP_SRC_EX(%a6),TRAP_SRCOP_EX(%a6) +#$# mov.l FP_SRC_HI(%a6),TRAP_SRCOP_HI(%a6) +#$# mov.l FP_SRC_LO(%a6),TRAP_SRCOP_LO(%a6) + +# the src operand is definitely a NORM(!), so tag it as such + mov.b &NORM,STAG(%a6) # set src optype tag + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode + + and.l &0xffff00ff,USER_FPSR(%a6) # zero all but accured field + + fmov.l &0x0,%fpcr # zero current control regs + fmov.l &0x0,%fpsr + + lea FP_SRC(%a6),%a0 # pass ptr to src operand + + bsr.l fout + + btst &unfl_bit,FPCR_ENABLE(%a6) + bne.w funfl_unfl_on2 + + btst &inex2_bit,FPCR_ENABLE(%a6) + bne.w funfl_inex_on2 + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 +#$# add.l &24,%sp + + btst &0x7,(%sp) # is trace on? + beq.l _fpsp_done # no + + fmov.l %fpiar,0x8(%sp) # "Current PC" is in FPIAR + mov.w &0x2024,0x6(%sp) # stk fmt = 0x2; voff = 0x024 + bra.l _real_trace + +######################################################################### +# XDEF **************************************************************** # +# _fpsp_unsupp(): 060FPSP entry point for FP "Unimplemented # +# Data Type" exception. # +# # +# This handler should be the first code executed upon taking the # +# FP Unimplemented Data Type exception in an operating system. # +# # +# XREF **************************************************************** # +# _imem_read_{word,long}() - read instruction word/longword # +# fix_skewed_ops() - adjust src operand in fsave frame # +# set_tag_x() - determine optype of src/dst operands # +# store_fpreg() - store opclass 0 or 2 result to FP regfile # +# unnorm_fix() - change UNNORM operands to NORM or ZERO # +# load_fpn2() - load dst operand from FP regfile # +# load_fpn1() - load src operand from FP regfile # +# fout() - emulate an opclass 3 instruction # +# tbl_unsupp - add of table of emulation routines for opclass 0,2 # +# _real_inex() - "callout" to operating system inexact handler # +# _fpsp_done() - "callout" for exit; work all done # +# _real_trace() - "callout" for Trace enabled exception # +# funimp_skew() - adjust fsave src ops to "incorrect" value # +# _real_snan() - "callout" for SNAN exception # +# _real_operr() - "callout" for OPERR exception # +# _real_ovfl() - "callout" for OVFL exception # +# _real_unfl() - "callout" for UNFL exception # +# get_packed() - fetch packed operand from memory # +# # +# INPUT *************************************************************** # +# - The system stack contains the "Unimp Data Type" stk frame # +# - The fsave frame contains the ssrc op (for UNNORM/DENORM) # +# # +# OUTPUT ************************************************************** # +# If Inexact exception (opclass 3): # +# - The system stack is changed to an Inexact exception stk frame # +# If SNAN exception (opclass 3): # +# - The system stack is changed to an SNAN exception stk frame # +# If OPERR exception (opclass 3): # +# - The system stack is changed to an OPERR exception stk frame # +# If OVFL exception (opclass 3): # +# - The system stack is changed to an OVFL exception stk frame # +# If UNFL exception (opclass 3): # +# - The system stack is changed to an UNFL exception stack frame # +# If Trace exception enabled: # +# - The system stack is changed to a Trace exception stack frame # +# Else: (normal case) # +# - Correct result has been stored as appropriate # +# # +# ALGORITHM *********************************************************** # +# Two main instruction types can enter here: (1) DENORM or UNNORM # +# unimplemented data types. These can be either opclass 0,2 or 3 # +# instructions, and (2) PACKED unimplemented data format instructions # +# also of opclasses 0,2, or 3. # +# For UNNORM/DENORM opclass 0 and 2, the handler fetches the src # +# operand from the fsave state frame and the dst operand (if dyadic) # +# from the FP register file. The instruction is then emulated by # +# choosing an emulation routine from a table of routines indexed by # +# instruction type. Once the instruction has been emulated and result # +# saved, then we check to see if any enabled exceptions resulted from # +# instruction emulation. If none, then we exit through the "callout" # +# _fpsp_done(). If there is an enabled FP exception, then we insert # +# this exception into the FPU in the fsave state frame and then exit # +# through _fpsp_done(). # +# PACKED opclass 0 and 2 is similar in how the instruction is # +# emulated and exceptions handled. The differences occur in how the # +# handler loads the packed op (by calling get_packed() routine) and # +# by the fact that a Trace exception could be pending for PACKED ops. # +# If a Trace exception is pending, then the current exception stack # +# frame is changed to a Trace exception stack frame and an exit is # +# made through _real_trace(). # +# For UNNORM/DENORM opclass 3, the actual move out to memory is # +# performed by calling the routine fout(). If no exception should occur # +# as the result of emulation, then an exit either occurs through # +# _fpsp_done() or through _real_trace() if a Trace exception is pending # +# (a Trace stack frame must be created here, too). If an FP exception # +# should occur, then we must create an exception stack frame of that # +# type and jump to either _real_snan(), _real_operr(), _real_inex(), # +# _real_unfl(), or _real_ovfl() as appropriate. PACKED opclass 3 # +# emulation is performed in a similar manner. # +# # +######################################################################### + +# +# (1) DENORM and UNNORM (unimplemented) data types: +# +# post-instruction +# ***************** +# * EA * +# pre-instruction * * +# ***************** ***************** +# * 0x0 * 0x0dc * * 0x3 * 0x0dc * +# ***************** ***************** +# * Next * * Next * +# * PC * * PC * +# ***************** ***************** +# * SR * * SR * +# ***************** ***************** +# +# (2) PACKED format (unsupported) opclasses two and three: +# ***************** +# * EA * +# * * +# ***************** +# * 0x2 * 0x0dc * +# ***************** +# * Next * +# * PC * +# ***************** +# * SR * +# ***************** +# + global _fpsp_unsupp +_fpsp_unsupp: + + link.w %a6,&-LOCAL_SIZE # init stack frame + + fsave FP_SRC(%a6) # save fp state + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack + + btst &0x5,EXC_SR(%a6) # user or supervisor mode? + bne.b fu_s +fu_u: + mov.l %usp,%a0 # fetch user stack pointer + mov.l %a0,EXC_A7(%a6) # save on stack + bra.b fu_cont +# if the exception is an opclass zero or two unimplemented data type +# exception, then the a7' calculated here is wrong since it doesn't +# stack an ea. however, we don't need an a7' for this case anyways. +fu_s: + lea 0x4+EXC_EA(%a6),%a0 # load old a7' + mov.l %a0,EXC_A7(%a6) # save on stack + +fu_cont: + +# the FPIAR holds the "current PC" of the faulting instruction +# the FPIAR should be set correctly for ALL exceptions passing through +# this point. + mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) + mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr + addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr + bsr.l _imem_read_long # fetch the instruction words + mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD + +############################ + + clr.b SPCOND_FLG(%a6) # clear special condition flag + +# Separate opclass three (fpn-to-mem) ops since they have a different +# stack frame and protocol. + btst &0x5,EXC_CMDREG(%a6) # is it an fmove out? + bne.w fu_out # yes + +# Separate packed opclass two instructions. + bfextu EXC_CMDREG(%a6){&0:&6},%d0 + cmpi.b %d0,&0x13 + beq.w fu_in_pack + + +# I'm not sure at this point what FPSR bits are valid for this instruction. +# so, since the emulation routines re-create them anyways, zero exception field + andi.l &0x00ff00ff,USER_FPSR(%a6) # zero exception field + + fmov.l &0x0,%fpcr # zero current control regs + fmov.l &0x0,%fpsr + +# Opclass two w/ memory-to-fpn operation will have an incorrect extended +# precision format if the src format was single or double and the +# source data type was an INF, NAN, DENORM, or UNNORM + lea FP_SRC(%a6),%a0 # pass ptr to input + bsr.l fix_skewed_ops + +# we don't know whether the src operand or the dst operand (or both) is the +# UNNORM or DENORM. call the function that tags the operand type. if the +# input is an UNNORM, then convert it to a NORM, DENORM, or ZERO. + lea FP_SRC(%a6),%a0 # pass: ptr to src op + bsr.l set_tag_x # tag the operand type + cmpi.b %d0,&UNNORM # is operand an UNNORM? + bne.b fu_op2 # no + bsr.l unnorm_fix # yes; convert to NORM,DENORM,or ZERO + +fu_op2: + mov.b %d0,STAG(%a6) # save src optype tag + + bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg + +# bit five of the fp extension word separates the monadic and dyadic operations +# at this point + btst &0x5,1+EXC_CMDREG(%a6) # is operation monadic or dyadic? + beq.b fu_extract # monadic + cmpi.b 1+EXC_CMDREG(%a6),&0x3a # is operation an ftst? + beq.b fu_extract # yes, so it's monadic, too + + bsr.l load_fpn2 # load dst into FP_DST + + lea FP_DST(%a6),%a0 # pass: ptr to dst op + bsr.l set_tag_x # tag the operand type + cmpi.b %d0,&UNNORM # is operand an UNNORM? + bne.b fu_op2_done # no + bsr.l unnorm_fix # yes; convert to NORM,DENORM,or ZERO +fu_op2_done: + mov.b %d0,DTAG(%a6) # save dst optype tag + +fu_extract: + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec + + bfextu 1+EXC_CMDREG(%a6){&1:&7},%d1 # extract extension + + lea FP_SRC(%a6),%a0 + lea FP_DST(%a6),%a1 + + mov.l (tbl_unsupp.l,%pc,%d1.l*4),%d1 # fetch routine addr + jsr (tbl_unsupp.l,%pc,%d1.l*1) + +# +# Exceptions in order of precedence: +# BSUN : none +# SNAN : all dyadic ops +# OPERR : fsqrt(-NORM) +# OVFL : all except ftst,fcmp +# UNFL : all except ftst,fcmp +# DZ : fdiv +# INEX2 : all except ftst,fcmp +# INEX1 : none (packed doesn't go through here) +# + +# we determine the highest priority exception(if any) set by the +# emulation routine that has also been enabled by the user. + mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions set + bne.b fu_in_ena # some are enabled + +fu_in_cont: +# fcmp and ftst do not store any result. + mov.b 1+EXC_CMDREG(%a6),%d0 # fetch extension + andi.b &0x38,%d0 # extract bits 3-5 + cmpi.b %d0,&0x38 # is instr fcmp or ftst? + beq.b fu_in_exit # yes + + bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg + bsr.l store_fpreg # store the result + +fu_in_exit: + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 + + bra.l _fpsp_done + +fu_in_ena: + and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled + bfffo %d0{&24:&8},%d0 # find highest priority exception + bne.b fu_in_exc # there is at least one set + +# +# No exceptions occurred that were also enabled. Now: +# +# if (OVFL && ovfl_disabled && inexact_enabled) { +# branch to _real_inex() (even if the result was exact!); +# } else { +# save the result in the proper fp reg (unless the op is fcmp or ftst); +# return; +# } +# + btst &ovfl_bit,FPSR_EXCEPT(%a6) # was overflow set? + beq.b fu_in_cont # no + +fu_in_ovflchk: + btst &inex2_bit,FPCR_ENABLE(%a6) # was inexact enabled? + beq.b fu_in_cont # no + bra.w fu_in_exc_ovfl # go insert overflow frame + +# +# An exception occurred and that exception was enabled: +# +# shift enabled exception field into lo byte of d0; +# if (((INEX2 || INEX1) && inex_enabled && OVFL && ovfl_disabled) || +# ((INEX2 || INEX1) && inex_enabled && UNFL && unfl_disabled)) { +# /* +# * this is the case where we must call _real_inex() now or else +# * there will be no other way to pass it the exceptional operand +# */ +# call _real_inex(); +# } else { +# restore exc state (SNAN||OPERR||OVFL||UNFL||DZ||INEX) into the FPU; +# } +# +fu_in_exc: + subi.l &24,%d0 # fix offset to be 0-8 + cmpi.b %d0,&0x6 # is exception INEX? (6) + bne.b fu_in_exc_exit # no + +# the enabled exception was inexact + btst &unfl_bit,FPSR_EXCEPT(%a6) # did disabled underflow occur? + bne.w fu_in_exc_unfl # yes + btst &ovfl_bit,FPSR_EXCEPT(%a6) # did disabled overflow occur? + bne.w fu_in_exc_ovfl # yes + +# here, we insert the correct fsave status value into the fsave frame for the +# corresponding exception. the operand in the fsave frame should be the original +# src operand. +fu_in_exc_exit: + mov.l %d0,-(%sp) # save d0 + bsr.l funimp_skew # skew sgl or dbl inputs + mov.l (%sp)+,%d0 # restore d0 + + mov.w (tbl_except.b,%pc,%d0.w*2),2+FP_SRC(%a6) # create exc status + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + frestore FP_SRC(%a6) # restore src op + + unlk %a6 + + bra.l _fpsp_done + +tbl_except: + short 0xe000,0xe006,0xe004,0xe005 + short 0xe003,0xe002,0xe001,0xe001 + +fu_in_exc_unfl: + mov.w &0x4,%d0 + bra.b fu_in_exc_exit +fu_in_exc_ovfl: + mov.w &0x03,%d0 + bra.b fu_in_exc_exit + +# If the input operand to this operation was opclass two and a single +# or double precision denorm, inf, or nan, the operand needs to be +# "corrected" in order to have the proper equivalent extended precision +# number. + global fix_skewed_ops +fix_skewed_ops: + bfextu EXC_CMDREG(%a6){&0:&6},%d0 # extract opclass,src fmt + cmpi.b %d0,&0x11 # is class = 2 & fmt = sgl? + beq.b fso_sgl # yes + cmpi.b %d0,&0x15 # is class = 2 & fmt = dbl? + beq.b fso_dbl # yes + rts # no + +fso_sgl: + mov.w LOCAL_EX(%a0),%d0 # fetch src exponent + andi.w &0x7fff,%d0 # strip sign + cmpi.w %d0,&0x3f80 # is |exp| == $3f80? + beq.b fso_sgl_dnrm_zero # yes + cmpi.w %d0,&0x407f # no; is |exp| == $407f? + beq.b fso_infnan # yes + rts # no + +fso_sgl_dnrm_zero: + andi.l &0x7fffffff,LOCAL_HI(%a0) # clear j-bit + beq.b fso_zero # it's a skewed zero +fso_sgl_dnrm: +# here, we count on norm not to alter a0... + bsr.l norm # normalize mantissa + neg.w %d0 # -shft amt + addi.w &0x3f81,%d0 # adjust new exponent + andi.w &0x8000,LOCAL_EX(%a0) # clear old exponent + or.w %d0,LOCAL_EX(%a0) # insert new exponent + rts + +fso_zero: + andi.w &0x8000,LOCAL_EX(%a0) # clear bogus exponent + rts + +fso_infnan: + andi.b &0x7f,LOCAL_HI(%a0) # clear j-bit + ori.w &0x7fff,LOCAL_EX(%a0) # make exponent = $7fff + rts + +fso_dbl: + mov.w LOCAL_EX(%a0),%d0 # fetch src exponent + andi.w &0x7fff,%d0 # strip sign + cmpi.w %d0,&0x3c00 # is |exp| == $3c00? + beq.b fso_dbl_dnrm_zero # yes + cmpi.w %d0,&0x43ff # no; is |exp| == $43ff? + beq.b fso_infnan # yes + rts # no + +fso_dbl_dnrm_zero: + andi.l &0x7fffffff,LOCAL_HI(%a0) # clear j-bit + bne.b fso_dbl_dnrm # it's a skewed denorm + tst.l LOCAL_LO(%a0) # is it a zero? + beq.b fso_zero # yes +fso_dbl_dnrm: +# here, we count on norm not to alter a0... + bsr.l norm # normalize mantissa + neg.w %d0 # -shft amt + addi.w &0x3c01,%d0 # adjust new exponent + andi.w &0x8000,LOCAL_EX(%a0) # clear old exponent + or.w %d0,LOCAL_EX(%a0) # insert new exponent + rts + +################################################################# + +# fmove out took an unimplemented data type exception. +# the src operand is in FP_SRC. Call _fout() to write out the result and +# to determine which exceptions, if any, to take. +fu_out: + +# Separate packed move outs from the UNNORM and DENORM move outs. + bfextu EXC_CMDREG(%a6){&3:&3},%d0 + cmpi.b %d0,&0x3 + beq.w fu_out_pack + cmpi.b %d0,&0x7 + beq.w fu_out_pack + + +# I'm not sure at this point what FPSR bits are valid for this instruction. +# so, since the emulation routines re-create them anyways, zero exception field. +# fmove out doesn't affect ccodes. + and.l &0xffff00ff,USER_FPSR(%a6) # zero exception field + + fmov.l &0x0,%fpcr # zero current control regs + fmov.l &0x0,%fpsr + +# the src can ONLY be a DENORM or an UNNORM! so, don't make any big subroutine +# call here. just figure out what it is... + mov.w FP_SRC_EX(%a6),%d0 # get exponent + andi.w &0x7fff,%d0 # strip sign + beq.b fu_out_denorm # it's a DENORM + + lea FP_SRC(%a6),%a0 + bsr.l unnorm_fix # yes; fix it + + mov.b %d0,STAG(%a6) + + bra.b fu_out_cont +fu_out_denorm: + mov.b &DENORM,STAG(%a6) +fu_out_cont: + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec + + lea FP_SRC(%a6),%a0 # pass ptr to src operand + + mov.l (%a6),EXC_A6(%a6) # in case a6 changes + bsr.l fout # call fmove out routine + +# Exceptions in order of precedence: +# BSUN : none +# SNAN : none +# OPERR : fmove.{b,w,l} out of large UNNORM +# OVFL : fmove.{s,d} +# UNFL : fmove.{s,d,x} +# DZ : none +# INEX2 : all +# INEX1 : none (packed doesn't travel through here) + +# determine the highest priority exception(if any) set by the +# emulation routine that has also been enabled by the user. + mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled + bne.w fu_out_ena # some are enabled + +fu_out_done: + + mov.l EXC_A6(%a6),(%a6) # in case a6 changed + +# on extended precision opclass three instructions using pre-decrement or +# post-increment addressing mode, the address register is not updated. is the +# address register was the stack pointer used from user mode, then let's update +# it here. if it was used from supervisor mode, then we have to handle this +# as a special case. + btst &0x5,EXC_SR(%a6) + bne.b fu_out_done_s + + mov.l EXC_A7(%a6),%a0 # restore a7 + mov.l %a0,%usp + +fu_out_done_cont: + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 + + btst &0x7,(%sp) # is trace on? + bne.b fu_out_trace # yes + + bra.l _fpsp_done + +# is the ea mode pre-decrement of the stack pointer from supervisor mode? +# ("fmov.x fpm,-(a7)") if so, +fu_out_done_s: + cmpi.b SPCOND_FLG(%a6),&mda7_flg + bne.b fu_out_done_cont + +# the extended precision result is still in fp0. but, we need to save it +# somewhere on the stack until we can copy it to its final resting place. +# here, we're counting on the top of the stack to be the old place-holders +# for fp0/fp1 which have already been restored. that way, we can write +# over those destinations with the shifted stack frame. + fmovm.x &0x80,FP_SRC(%a6) # put answer on stack + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + mov.l (%a6),%a6 # restore frame pointer + + mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp) + mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) + +# now, copy the result to the proper place on the stack + mov.l LOCAL_SIZE+FP_SRC_EX(%sp),LOCAL_SIZE+EXC_SR+0x0(%sp) + mov.l LOCAL_SIZE+FP_SRC_HI(%sp),LOCAL_SIZE+EXC_SR+0x4(%sp) + mov.l LOCAL_SIZE+FP_SRC_LO(%sp),LOCAL_SIZE+EXC_SR+0x8(%sp) + + add.l &LOCAL_SIZE-0x8,%sp + + btst &0x7,(%sp) + bne.b fu_out_trace + + bra.l _fpsp_done + +fu_out_ena: + and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled + bfffo %d0{&24:&8},%d0 # find highest priority exception + bne.b fu_out_exc # there is at least one set + +# no exceptions were set. +# if a disabled overflow occurred and inexact was enabled but the result +# was exact, then a branch to _real_inex() is made. + btst &ovfl_bit,FPSR_EXCEPT(%a6) # was overflow set? + beq.w fu_out_done # no + +fu_out_ovflchk: + btst &inex2_bit,FPCR_ENABLE(%a6) # was inexact enabled? + beq.w fu_out_done # no + bra.w fu_inex # yes + +# +# The fp move out that took the "Unimplemented Data Type" exception was +# being traced. Since the stack frames are similar, get the "current" PC +# from FPIAR and put it in the trace stack frame then jump to _real_trace(). +# +# UNSUPP FRAME TRACE FRAME +# ***************** ***************** +# * EA * * Current * +# * * * PC * +# ***************** ***************** +# * 0x3 * 0x0dc * * 0x2 * 0x024 * +# ***************** ***************** +# * Next * * Next * +# * PC * * PC * +# ***************** ***************** +# * SR * * SR * +# ***************** ***************** +# +fu_out_trace: + mov.w &0x2024,0x6(%sp) + fmov.l %fpiar,0x8(%sp) + bra.l _real_trace + +# an exception occurred and that exception was enabled. +fu_out_exc: + subi.l &24,%d0 # fix offset to be 0-8 + +# we don't mess with the existing fsave frame. just re-insert it and +# jump to the "_real_{}()" handler... + mov.w (tbl_fu_out.b,%pc,%d0.w*2),%d0 + jmp (tbl_fu_out.b,%pc,%d0.w*1) + + swbeg &0x8 +tbl_fu_out: + short tbl_fu_out - tbl_fu_out # BSUN can't happen + short tbl_fu_out - tbl_fu_out # SNAN can't happen + short fu_operr - tbl_fu_out # OPERR + short fu_ovfl - tbl_fu_out # OVFL + short fu_unfl - tbl_fu_out # UNFL + short tbl_fu_out - tbl_fu_out # DZ can't happen + short fu_inex - tbl_fu_out # INEX2 + short tbl_fu_out - tbl_fu_out # INEX1 won't make it here + +# for snan,operr,ovfl,unfl, src op is still in FP_SRC so just +# frestore it. +fu_snan: + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + mov.w &0x30d8,EXC_VOFF(%a6) # vector offset = 0xd8 + mov.w &0xe006,2+FP_SRC(%a6) + + frestore FP_SRC(%a6) + + unlk %a6 + + + bra.l _real_snan + +fu_operr: + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + mov.w &0x30d0,EXC_VOFF(%a6) # vector offset = 0xd0 + mov.w &0xe004,2+FP_SRC(%a6) + + frestore FP_SRC(%a6) + + unlk %a6 + + + bra.l _real_operr + +fu_ovfl: + fmovm.x &0x40,FP_SRC(%a6) # save EXOP to the stack + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + mov.w &0x30d4,EXC_VOFF(%a6) # vector offset = 0xd4 + mov.w &0xe005,2+FP_SRC(%a6) + + frestore FP_SRC(%a6) # restore EXOP + + unlk %a6 + + bra.l _real_ovfl + +# underflow can happen for extended precision. extended precision opclass +# three instruction exceptions don't update the stack pointer. so, if the +# exception occurred from user mode, then simply update a7 and exit normally. +# if the exception occurred from supervisor mode, check if +fu_unfl: + mov.l EXC_A6(%a6),(%a6) # restore a6 + + btst &0x5,EXC_SR(%a6) + bne.w fu_unfl_s + + mov.l EXC_A7(%a6),%a0 # restore a7 whether we need + mov.l %a0,%usp # to or not... + +fu_unfl_cont: + fmovm.x &0x40,FP_SRC(%a6) # save EXOP to the stack + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + mov.w &0x30cc,EXC_VOFF(%a6) # vector offset = 0xcc + mov.w &0xe003,2+FP_SRC(%a6) + + frestore FP_SRC(%a6) # restore EXOP + + unlk %a6 + + bra.l _real_unfl + +fu_unfl_s: + cmpi.b SPCOND_FLG(%a6),&mda7_flg # was the mode -(sp)? + bne.b fu_unfl_cont + +# the extended precision result is still in fp0. but, we need to save it +# somewhere on the stack until we can copy it to its final resting place +# (where the exc frame is currently). make sure it's not at the top of the +# frame or it will get overwritten when the exc stack frame is shifted "down". + fmovm.x &0x80,FP_SRC(%a6) # put answer on stack + fmovm.x &0x40,FP_DST(%a6) # put EXOP on stack + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + mov.w &0x30cc,EXC_VOFF(%a6) # vector offset = 0xcc + mov.w &0xe003,2+FP_DST(%a6) + + frestore FP_DST(%a6) # restore EXOP + + mov.l (%a6),%a6 # restore frame pointer + + mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp) + mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) + mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp) + +# now, copy the result to the proper place on the stack + mov.l LOCAL_SIZE+FP_SRC_EX(%sp),LOCAL_SIZE+EXC_SR+0x0(%sp) + mov.l LOCAL_SIZE+FP_SRC_HI(%sp),LOCAL_SIZE+EXC_SR+0x4(%sp) + mov.l LOCAL_SIZE+FP_SRC_LO(%sp),LOCAL_SIZE+EXC_SR+0x8(%sp) + + add.l &LOCAL_SIZE-0x8,%sp + + bra.l _real_unfl + +# fmove in and out enter here. +fu_inex: + fmovm.x &0x40,FP_SRC(%a6) # save EXOP to the stack + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + mov.w &0x30c4,EXC_VOFF(%a6) # vector offset = 0xc4 + mov.w &0xe001,2+FP_SRC(%a6) + + frestore FP_SRC(%a6) # restore EXOP + + unlk %a6 + + + bra.l _real_inex + +######################################################################### +######################################################################### +fu_in_pack: + + +# I'm not sure at this point what FPSR bits are valid for this instruction. +# so, since the emulation routines re-create them anyways, zero exception field + andi.l &0x0ff00ff,USER_FPSR(%a6) # zero exception field + + fmov.l &0x0,%fpcr # zero current control regs + fmov.l &0x0,%fpsr + + bsr.l get_packed # fetch packed src operand + + lea FP_SRC(%a6),%a0 # pass ptr to src + bsr.l set_tag_x # set src optype tag + + mov.b %d0,STAG(%a6) # save src optype tag + + bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg + +# bit five of the fp extension word separates the monadic and dyadic operations +# at this point + btst &0x5,1+EXC_CMDREG(%a6) # is operation monadic or dyadic? + beq.b fu_extract_p # monadic + cmpi.b 1+EXC_CMDREG(%a6),&0x3a # is operation an ftst? + beq.b fu_extract_p # yes, so it's monadic, too + + bsr.l load_fpn2 # load dst into FP_DST + + lea FP_DST(%a6),%a0 # pass: ptr to dst op + bsr.l set_tag_x # tag the operand type + cmpi.b %d0,&UNNORM # is operand an UNNORM? + bne.b fu_op2_done_p # no + bsr.l unnorm_fix # yes; convert to NORM,DENORM,or ZERO +fu_op2_done_p: + mov.b %d0,DTAG(%a6) # save dst optype tag + +fu_extract_p: + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec + + bfextu 1+EXC_CMDREG(%a6){&1:&7},%d1 # extract extension + + lea FP_SRC(%a6),%a0 + lea FP_DST(%a6),%a1 + + mov.l (tbl_unsupp.l,%pc,%d1.l*4),%d1 # fetch routine addr + jsr (tbl_unsupp.l,%pc,%d1.l*1) + +# +# Exceptions in order of precedence: +# BSUN : none +# SNAN : all dyadic ops +# OPERR : fsqrt(-NORM) +# OVFL : all except ftst,fcmp +# UNFL : all except ftst,fcmp +# DZ : fdiv +# INEX2 : all except ftst,fcmp +# INEX1 : all +# + +# we determine the highest priority exception(if any) set by the +# emulation routine that has also been enabled by the user. + mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled + bne.w fu_in_ena_p # some are enabled + +fu_in_cont_p: +# fcmp and ftst do not store any result. + mov.b 1+EXC_CMDREG(%a6),%d0 # fetch extension + andi.b &0x38,%d0 # extract bits 3-5 + cmpi.b %d0,&0x38 # is instr fcmp or ftst? + beq.b fu_in_exit_p # yes + + bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg + bsr.l store_fpreg # store the result + +fu_in_exit_p: + + btst &0x5,EXC_SR(%a6) # user or supervisor? + bne.w fu_in_exit_s_p # supervisor + + mov.l EXC_A7(%a6),%a0 # update user a7 + mov.l %a0,%usp + +fu_in_exit_cont_p: + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 # unravel stack frame + + btst &0x7,(%sp) # is trace on? + bne.w fu_trace_p # yes + + bra.l _fpsp_done # exit to os + +# the exception occurred in supervisor mode. check to see if the +# addressing mode was (a7)+. if so, we'll need to shift the +# stack frame "up". +fu_in_exit_s_p: + btst &mia7_bit,SPCOND_FLG(%a6) # was ea mode (a7)+ + beq.b fu_in_exit_cont_p # no + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 # unravel stack frame + +# shift the stack frame "up". we don't really care about the field. + mov.l 0x4(%sp),0x10(%sp) + mov.l 0x0(%sp),0xc(%sp) + add.l &0xc,%sp + + btst &0x7,(%sp) # is trace on? + bne.w fu_trace_p # yes + + bra.l _fpsp_done # exit to os + +fu_in_ena_p: + and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled & set + bfffo %d0{&24:&8},%d0 # find highest priority exception + bne.b fu_in_exc_p # at least one was set + +# +# No exceptions occurred that were also enabled. Now: +# +# if (OVFL && ovfl_disabled && inexact_enabled) { +# branch to _real_inex() (even if the result was exact!); +# } else { +# save the result in the proper fp reg (unless the op is fcmp or ftst); +# return; +# } +# + btst &ovfl_bit,FPSR_EXCEPT(%a6) # was overflow set? + beq.w fu_in_cont_p # no + +fu_in_ovflchk_p: + btst &inex2_bit,FPCR_ENABLE(%a6) # was inexact enabled? + beq.w fu_in_cont_p # no + bra.w fu_in_exc_ovfl_p # do _real_inex() now + +# +# An exception occurred and that exception was enabled: +# +# shift enabled exception field into lo byte of d0; +# if (((INEX2 || INEX1) && inex_enabled && OVFL && ovfl_disabled) || +# ((INEX2 || INEX1) && inex_enabled && UNFL && unfl_disabled)) { +# /* +# * this is the case where we must call _real_inex() now or else +# * there will be no other way to pass it the exceptional operand +# */ +# call _real_inex(); +# } else { +# restore exc state (SNAN||OPERR||OVFL||UNFL||DZ||INEX) into the FPU; +# } +# +fu_in_exc_p: + subi.l &24,%d0 # fix offset to be 0-8 + cmpi.b %d0,&0x6 # is exception INEX? (6 or 7) + blt.b fu_in_exc_exit_p # no + +# the enabled exception was inexact + btst &unfl_bit,FPSR_EXCEPT(%a6) # did disabled underflow occur? + bne.w fu_in_exc_unfl_p # yes + btst &ovfl_bit,FPSR_EXCEPT(%a6) # did disabled overflow occur? + bne.w fu_in_exc_ovfl_p # yes + +# here, we insert the correct fsave status value into the fsave frame for the +# corresponding exception. the operand in the fsave frame should be the original +# src operand. +# as a reminder for future predicted pain and agony, we are passing in fsave the +# "non-skewed" operand for cases of sgl and dbl src INFs,NANs, and DENORMs. +# this is INCORRECT for enabled SNAN which would give to the user the skewed SNAN!!! +fu_in_exc_exit_p: + btst &0x5,EXC_SR(%a6) # user or supervisor? + bne.w fu_in_exc_exit_s_p # supervisor + + mov.l EXC_A7(%a6),%a0 # update user a7 + mov.l %a0,%usp + +fu_in_exc_exit_cont_p: + mov.w (tbl_except_p.b,%pc,%d0.w*2),2+FP_SRC(%a6) + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + frestore FP_SRC(%a6) # restore src op + + unlk %a6 + + btst &0x7,(%sp) # is trace enabled? + bne.w fu_trace_p # yes + + bra.l _fpsp_done + +tbl_except_p: + short 0xe000,0xe006,0xe004,0xe005 + short 0xe003,0xe002,0xe001,0xe001 + +fu_in_exc_ovfl_p: + mov.w &0x3,%d0 + bra.w fu_in_exc_exit_p + +fu_in_exc_unfl_p: + mov.w &0x4,%d0 + bra.w fu_in_exc_exit_p + +fu_in_exc_exit_s_p: + btst &mia7_bit,SPCOND_FLG(%a6) + beq.b fu_in_exc_exit_cont_p + + mov.w (tbl_except_p.b,%pc,%d0.w*2),2+FP_SRC(%a6) + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + frestore FP_SRC(%a6) # restore src op + + unlk %a6 # unravel stack frame + +# shift stack frame "up". who cares about field. + mov.l 0x4(%sp),0x10(%sp) + mov.l 0x0(%sp),0xc(%sp) + add.l &0xc,%sp + + btst &0x7,(%sp) # is trace on? + bne.b fu_trace_p # yes + + bra.l _fpsp_done # exit to os + +# +# The opclass two PACKED instruction that took an "Unimplemented Data Type" +# exception was being traced. Make the "current" PC the FPIAR and put it in the +# trace stack frame then jump to _real_trace(). +# +# UNSUPP FRAME TRACE FRAME +# ***************** ***************** +# * EA * * Current * +# * * * PC * +# ***************** ***************** +# * 0x2 * 0x0dc * * 0x2 * 0x024 * +# ***************** ***************** +# * Next * * Next * +# * PC * * PC * +# ***************** ***************** +# * SR * * SR * +# ***************** ***************** +fu_trace_p: + mov.w &0x2024,0x6(%sp) + fmov.l %fpiar,0x8(%sp) + + bra.l _real_trace + +######################################################### +######################################################### +fu_out_pack: + + +# I'm not sure at this point what FPSR bits are valid for this instruction. +# so, since the emulation routines re-create them anyways, zero exception field. +# fmove out doesn't affect ccodes. + and.l &0xffff00ff,USER_FPSR(%a6) # zero exception field + + fmov.l &0x0,%fpcr # zero current control regs + fmov.l &0x0,%fpsr + + bfextu EXC_CMDREG(%a6){&6:&3},%d0 + bsr.l load_fpn1 + +# unlike other opclass 3, unimplemented data type exceptions, packed must be +# able to detect all operand types. + lea FP_SRC(%a6),%a0 + bsr.l set_tag_x # tag the operand type + cmpi.b %d0,&UNNORM # is operand an UNNORM? + bne.b fu_op2_p # no + bsr.l unnorm_fix # yes; convert to NORM,DENORM,or ZERO + +fu_op2_p: + mov.b %d0,STAG(%a6) # save src optype tag + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec + + lea FP_SRC(%a6),%a0 # pass ptr to src operand + + mov.l (%a6),EXC_A6(%a6) # in case a6 changes + bsr.l fout # call fmove out routine + +# Exceptions in order of precedence: +# BSUN : no +# SNAN : yes +# OPERR : if ((k_factor > +17) || (dec. exp exceeds 3 digits)) +# OVFL : no +# UNFL : no +# DZ : no +# INEX2 : yes +# INEX1 : no + +# determine the highest priority exception(if any) set by the +# emulation routine that has also been enabled by the user. + mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled + bne.w fu_out_ena_p # some are enabled + +fu_out_exit_p: + mov.l EXC_A6(%a6),(%a6) # restore a6 + + btst &0x5,EXC_SR(%a6) # user or supervisor? + bne.b fu_out_exit_s_p # supervisor + + mov.l EXC_A7(%a6),%a0 # update user a7 + mov.l %a0,%usp + +fu_out_exit_cont_p: + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 # unravel stack frame + + btst &0x7,(%sp) # is trace on? + bne.w fu_trace_p # yes + + bra.l _fpsp_done # exit to os + +# the exception occurred in supervisor mode. check to see if the +# addressing mode was -(a7). if so, we'll need to shift the +# stack frame "down". +fu_out_exit_s_p: + btst &mda7_bit,SPCOND_FLG(%a6) # was ea mode -(a7) + beq.b fu_out_exit_cont_p # no + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + mov.l (%a6),%a6 # restore frame pointer + + mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp) + mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) + +# now, copy the result to the proper place on the stack + mov.l LOCAL_SIZE+FP_DST_EX(%sp),LOCAL_SIZE+EXC_SR+0x0(%sp) + mov.l LOCAL_SIZE+FP_DST_HI(%sp),LOCAL_SIZE+EXC_SR+0x4(%sp) + mov.l LOCAL_SIZE+FP_DST_LO(%sp),LOCAL_SIZE+EXC_SR+0x8(%sp) + + add.l &LOCAL_SIZE-0x8,%sp + + btst &0x7,(%sp) + bne.w fu_trace_p + + bra.l _fpsp_done + +fu_out_ena_p: + and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled + bfffo %d0{&24:&8},%d0 # find highest priority exception + beq.w fu_out_exit_p + + mov.l EXC_A6(%a6),(%a6) # restore a6 + +# an exception occurred and that exception was enabled. +# the only exception possible on packed move out are INEX, OPERR, and SNAN. +fu_out_exc_p: + cmpi.b %d0,&0x1a + bgt.w fu_inex_p2 + beq.w fu_operr_p + +fu_snan_p: + btst &0x5,EXC_SR(%a6) + bne.b fu_snan_s_p + + mov.l EXC_A7(%a6),%a0 + mov.l %a0,%usp + bra.w fu_snan + +fu_snan_s_p: + cmpi.b SPCOND_FLG(%a6),&mda7_flg + bne.w fu_snan + +# the instruction was "fmove.p fpn,-(a7)" from supervisor mode. +# the strategy is to move the exception frame "down" 12 bytes. then, we +# can store the default result where the exception frame was. + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + mov.w &0x30d8,EXC_VOFF(%a6) # vector offset = 0xd0 + mov.w &0xe006,2+FP_SRC(%a6) # set fsave status + + frestore FP_SRC(%a6) # restore src operand + + mov.l (%a6),%a6 # restore frame pointer + + mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp) + mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) + mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp) + +# now, we copy the default result to its proper location + mov.l LOCAL_SIZE+FP_DST_EX(%sp),LOCAL_SIZE+0x4(%sp) + mov.l LOCAL_SIZE+FP_DST_HI(%sp),LOCAL_SIZE+0x8(%sp) + mov.l LOCAL_SIZE+FP_DST_LO(%sp),LOCAL_SIZE+0xc(%sp) + + add.l &LOCAL_SIZE-0x8,%sp + + + bra.l _real_snan + +fu_operr_p: + btst &0x5,EXC_SR(%a6) + bne.w fu_operr_p_s + + mov.l EXC_A7(%a6),%a0 + mov.l %a0,%usp + bra.w fu_operr + +fu_operr_p_s: + cmpi.b SPCOND_FLG(%a6),&mda7_flg + bne.w fu_operr + +# the instruction was "fmove.p fpn,-(a7)" from supervisor mode. +# the strategy is to move the exception frame "down" 12 bytes. then, we +# can store the default result where the exception frame was. + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + mov.w &0x30d0,EXC_VOFF(%a6) # vector offset = 0xd0 + mov.w &0xe004,2+FP_SRC(%a6) # set fsave status + + frestore FP_SRC(%a6) # restore src operand + + mov.l (%a6),%a6 # restore frame pointer + + mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp) + mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) + mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp) + +# now, we copy the default result to its proper location + mov.l LOCAL_SIZE+FP_DST_EX(%sp),LOCAL_SIZE+0x4(%sp) + mov.l LOCAL_SIZE+FP_DST_HI(%sp),LOCAL_SIZE+0x8(%sp) + mov.l LOCAL_SIZE+FP_DST_LO(%sp),LOCAL_SIZE+0xc(%sp) + + add.l &LOCAL_SIZE-0x8,%sp + + + bra.l _real_operr + +fu_inex_p2: + btst &0x5,EXC_SR(%a6) + bne.w fu_inex_s_p2 + + mov.l EXC_A7(%a6),%a0 + mov.l %a0,%usp + bra.w fu_inex + +fu_inex_s_p2: + cmpi.b SPCOND_FLG(%a6),&mda7_flg + bne.w fu_inex + +# the instruction was "fmove.p fpn,-(a7)" from supervisor mode. +# the strategy is to move the exception frame "down" 12 bytes. then, we +# can store the default result where the exception frame was. + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + mov.w &0x30c4,EXC_VOFF(%a6) # vector offset = 0xc4 + mov.w &0xe001,2+FP_SRC(%a6) # set fsave status + + frestore FP_SRC(%a6) # restore src operand + + mov.l (%a6),%a6 # restore frame pointer + + mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp) + mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) + mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp) + +# now, we copy the default result to its proper location + mov.l LOCAL_SIZE+FP_DST_EX(%sp),LOCAL_SIZE+0x4(%sp) + mov.l LOCAL_SIZE+FP_DST_HI(%sp),LOCAL_SIZE+0x8(%sp) + mov.l LOCAL_SIZE+FP_DST_LO(%sp),LOCAL_SIZE+0xc(%sp) + + add.l &LOCAL_SIZE-0x8,%sp + + + bra.l _real_inex + +######################################################################### + +# +# if we're stuffing a source operand back into an fsave frame then we +# have to make sure that for single or double source operands that the +# format stuffed is as weird as the hardware usually makes it. +# + global funimp_skew +funimp_skew: + bfextu EXC_EXTWORD(%a6){&3:&3},%d0 # extract src specifier + cmpi.b %d0,&0x1 # was src sgl? + beq.b funimp_skew_sgl # yes + cmpi.b %d0,&0x5 # was src dbl? + beq.b funimp_skew_dbl # yes + rts + +funimp_skew_sgl: + mov.w FP_SRC_EX(%a6),%d0 # fetch DENORM exponent + andi.w &0x7fff,%d0 # strip sign + beq.b funimp_skew_sgl_not + cmpi.w %d0,&0x3f80 + bgt.b funimp_skew_sgl_not + neg.w %d0 # make exponent negative + addi.w &0x3f81,%d0 # find amt to shift + mov.l FP_SRC_HI(%a6),%d1 # fetch DENORM hi(man) + lsr.l %d0,%d1 # shift it + bset &31,%d1 # set j-bit + mov.l %d1,FP_SRC_HI(%a6) # insert new hi(man) + andi.w &0x8000,FP_SRC_EX(%a6) # clear old exponent + ori.w &0x3f80,FP_SRC_EX(%a6) # insert new "skewed" exponent +funimp_skew_sgl_not: + rts + +funimp_skew_dbl: + mov.w FP_SRC_EX(%a6),%d0 # fetch DENORM exponent + andi.w &0x7fff,%d0 # strip sign + beq.b funimp_skew_dbl_not + cmpi.w %d0,&0x3c00 + bgt.b funimp_skew_dbl_not + + tst.b FP_SRC_EX(%a6) # make "internal format" + smi.b 0x2+FP_SRC(%a6) + mov.w %d0,FP_SRC_EX(%a6) # insert exponent with cleared sign + clr.l %d0 # clear g,r,s + lea FP_SRC(%a6),%a0 # pass ptr to src op + mov.w &0x3c01,%d1 # pass denorm threshold + bsr.l dnrm_lp # denorm it + mov.w &0x3c00,%d0 # new exponent + tst.b 0x2+FP_SRC(%a6) # is sign set? + beq.b fss_dbl_denorm_done # no + bset &15,%d0 # set sign +fss_dbl_denorm_done: + bset &0x7,FP_SRC_HI(%a6) # set j-bit + mov.w %d0,FP_SRC_EX(%a6) # insert new exponent +funimp_skew_dbl_not: + rts + +######################################################################### + global _mem_write2 +_mem_write2: + btst &0x5,EXC_SR(%a6) + beq.l _dmem_write + mov.l 0x0(%a0),FP_DST_EX(%a6) + mov.l 0x4(%a0),FP_DST_HI(%a6) + mov.l 0x8(%a0),FP_DST_LO(%a6) + clr.l %d1 + rts + +######################################################################### +# XDEF **************************************************************** # +# _fpsp_effadd(): 060FPSP entry point for FP "Unimplemented # +# effective address" exception. # +# # +# This handler should be the first code executed upon taking the # +# FP Unimplemented Effective Address exception in an operating # +# system. # +# # +# XREF **************************************************************** # +# _imem_read_long() - read instruction longword # +# fix_skewed_ops() - adjust src operand in fsave frame # +# set_tag_x() - determine optype of src/dst operands # +# store_fpreg() - store opclass 0 or 2 result to FP regfile # +# unnorm_fix() - change UNNORM operands to NORM or ZERO # +# load_fpn2() - load dst operand from FP regfile # +# tbl_unsupp - add of table of emulation routines for opclass 0,2 # +# decbin() - convert packed data to FP binary data # +# _real_fpu_disabled() - "callout" for "FPU disabled" exception # +# _real_access() - "callout" for access error exception # +# _mem_read() - read extended immediate operand from memory # +# _fpsp_done() - "callout" for exit; work all done # +# _real_trace() - "callout" for Trace enabled exception # +# fmovm_dynamic() - emulate dynamic fmovm instruction # +# fmovm_ctrl() - emulate fmovm control instruction # +# # +# INPUT *************************************************************** # +# - The system stack contains the "Unimplemented " stk frame # +# # +# OUTPUT ************************************************************** # +# If access error: # +# - The system stack is changed to an access error stack frame # +# If FPU disabled: # +# - The system stack is changed to an FPU disabled stack frame # +# If Trace exception enabled: # +# - The system stack is changed to a Trace exception stack frame # +# Else: (normal case) # +# - None (correct result has been stored as appropriate) # +# # +# ALGORITHM *********************************************************** # +# This exception handles 3 types of operations: # +# (1) FP Instructions using extended precision or packed immediate # +# addressing mode. # +# (2) The "fmovm.x" instruction w/ dynamic register specification. # +# (3) The "fmovm.l" instruction w/ 2 or 3 control registers. # +# # +# For immediate data operations, the data is read in w/ a # +# _mem_read() "callout", converted to FP binary (if packed), and used # +# as the source operand to the instruction specified by the instruction # +# word. If no FP exception should be reported ads a result of the # +# emulation, then the result is stored to the destination register and # +# the handler exits through _fpsp_done(). If an enabled exc has been # +# signalled as a result of emulation, then an fsave state frame # +# corresponding to the FP exception type must be entered into the 060 # +# FPU before exiting. In either the enabled or disabled cases, we # +# must also check if a Trace exception is pending, in which case, we # +# must create a Trace exception stack frame from the current exception # +# stack frame. If no Trace is pending, we simply exit through # +# _fpsp_done(). # +# For "fmovm.x", call the routine fmovm_dynamic() which will # +# decode and emulate the instruction. No FP exceptions can be pending # +# as a result of this operation emulation. A Trace exception can be # +# pending, though, which means the current stack frame must be changed # +# to a Trace stack frame and an exit made through _real_trace(). # +# For the case of "fmovm.x Dn,-(a7)", where the offending instruction # +# was executed from supervisor mode, this handler must store the FP # +# register file values to the system stack by itself since # +# fmovm_dynamic() can't handle this. A normal exit is made through # +# fpsp_done(). # +# For "fmovm.l", fmovm_ctrl() is used to emulate the instruction. # +# Again, a Trace exception may be pending and an exit made through # +# _real_trace(). Else, a normal exit is made through _fpsp_done(). # +# # +# Before any of the above is attempted, it must be checked to # +# see if the FPU is disabled. Since the "Unimp " exception is taken # +# before the "FPU disabled" exception, but the "FPU disabled" exception # +# has higher priority, we check the disabled bit in the PCR. If set, # +# then we must create an 8 word "FPU disabled" exception stack frame # +# from the current 4 word exception stack frame. This includes # +# reproducing the effective address of the instruction to put on the # +# new stack frame. # +# # +# In the process of all emulation work, if a _mem_read() # +# "callout" returns a failing result indicating an access error, then # +# we must create an access error stack frame from the current stack # +# frame. This information includes a faulting address and a fault- # +# status-longword. These are created within this handler. # +# # +######################################################################### + + global _fpsp_effadd +_fpsp_effadd: + +# This exception type takes priority over the "Line F Emulator" +# exception. Therefore, the FPU could be disabled when entering here. +# So, we must check to see if it's disabled and handle that case separately. + mov.l %d0,-(%sp) # save d0 + movc %pcr,%d0 # load proc cr + btst &0x1,%d0 # is FPU disabled? + bne.w iea_disabled # yes + mov.l (%sp)+,%d0 # restore d0 + + link %a6,&-LOCAL_SIZE # init stack frame + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack + +# PC of instruction that took the exception is the PC in the frame + mov.l EXC_PC(%a6),EXC_EXTWPTR(%a6) + + mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr + addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr + bsr.l _imem_read_long # fetch the instruction words + mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD + +######################################################################### + + tst.w %d0 # is operation fmovem? + bmi.w iea_fmovm # yes + +# +# here, we will have: +# fabs fdabs fsabs facos fmod +# fadd fdadd fsadd fasin frem +# fcmp fatan fscale +# fdiv fddiv fsdiv fatanh fsin +# fint fcos fsincos +# fintrz fcosh fsinh +# fmove fdmove fsmove fetox ftan +# fmul fdmul fsmul fetoxm1 ftanh +# fneg fdneg fsneg fgetexp ftentox +# fsgldiv fgetman ftwotox +# fsglmul flog10 +# fsqrt flog2 +# fsub fdsub fssub flogn +# ftst flognp1 +# which can all use f.{x,p} +# so, now it's immediate data extended precision AND PACKED FORMAT! +# +iea_op: + andi.l &0x00ff00ff,USER_FPSR(%a6) + + btst &0xa,%d0 # is src fmt x or p? + bne.b iea_op_pack # packed + + + mov.l EXC_EXTWPTR(%a6),%a0 # pass: ptr to # + lea FP_SRC(%a6),%a1 # pass: ptr to super addr + mov.l &0xc,%d0 # pass: 12 bytes + bsr.l _imem_read # read extended immediate + + tst.l %d1 # did ifetch fail? + bne.w iea_iacc # yes + + bra.b iea_op_setsrc + +iea_op_pack: + + mov.l EXC_EXTWPTR(%a6),%a0 # pass: ptr to # + lea FP_SRC(%a6),%a1 # pass: ptr to super dst + mov.l &0xc,%d0 # pass: 12 bytes + bsr.l _imem_read # read packed operand + + tst.l %d1 # did ifetch fail? + bne.w iea_iacc # yes + +# The packed operand is an INF or a NAN if the exponent field is all ones. + bfextu FP_SRC(%a6){&1:&15},%d0 # get exp + cmpi.w %d0,&0x7fff # INF or NAN? + beq.b iea_op_setsrc # operand is an INF or NAN + +# The packed operand is a zero if the mantissa is all zero, else it's +# a normal packed op. + mov.b 3+FP_SRC(%a6),%d0 # get byte 4 + andi.b &0x0f,%d0 # clear all but last nybble + bne.b iea_op_gp_not_spec # not a zero + tst.l FP_SRC_HI(%a6) # is lw 2 zero? + bne.b iea_op_gp_not_spec # not a zero + tst.l FP_SRC_LO(%a6) # is lw 3 zero? + beq.b iea_op_setsrc # operand is a ZERO +iea_op_gp_not_spec: + lea FP_SRC(%a6),%a0 # pass: ptr to packed op + bsr.l decbin # convert to extended + fmovm.x &0x80,FP_SRC(%a6) # make this the srcop + +iea_op_setsrc: + addi.l &0xc,EXC_EXTWPTR(%a6) # update extension word pointer + +# FP_SRC now holds the src operand. + lea FP_SRC(%a6),%a0 # pass: ptr to src op + bsr.l set_tag_x # tag the operand type + mov.b %d0,STAG(%a6) # could be ANYTHING!!! + cmpi.b %d0,&UNNORM # is operand an UNNORM? + bne.b iea_op_getdst # no + bsr.l unnorm_fix # yes; convert to NORM/DENORM/ZERO + mov.b %d0,STAG(%a6) # set new optype tag +iea_op_getdst: + clr.b STORE_FLG(%a6) # clear "store result" boolean + + btst &0x5,1+EXC_CMDREG(%a6) # is operation monadic or dyadic? + beq.b iea_op_extract # monadic + btst &0x4,1+EXC_CMDREG(%a6) # is operation fsincos,ftst,fcmp? + bne.b iea_op_spec # yes + +iea_op_loaddst: + bfextu EXC_CMDREG(%a6){&6:&3},%d0 # fetch dst regno + bsr.l load_fpn2 # load dst operand + + lea FP_DST(%a6),%a0 # pass: ptr to dst op + bsr.l set_tag_x # tag the operand type + mov.b %d0,DTAG(%a6) # could be ANYTHING!!! + cmpi.b %d0,&UNNORM # is operand an UNNORM? + bne.b iea_op_extract # no + bsr.l unnorm_fix # yes; convert to NORM/DENORM/ZERO + mov.b %d0,DTAG(%a6) # set new optype tag + bra.b iea_op_extract + +# the operation is fsincos, ftst, or fcmp. only fcmp is dyadic +iea_op_spec: + btst &0x3,1+EXC_CMDREG(%a6) # is operation fsincos? + beq.b iea_op_extract # yes +# now, we're left with ftst and fcmp. so, first let's tag them so that they don't +# store a result. then, only fcmp will branch back and pick up a dst operand. + st STORE_FLG(%a6) # don't store a final result + btst &0x1,1+EXC_CMDREG(%a6) # is operation fcmp? + beq.b iea_op_loaddst # yes + +iea_op_extract: + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass: rnd mode,prec + + mov.b 1+EXC_CMDREG(%a6),%d1 + andi.w &0x007f,%d1 # extract extension + + fmov.l &0x0,%fpcr + fmov.l &0x0,%fpsr + + lea FP_SRC(%a6),%a0 + lea FP_DST(%a6),%a1 + + mov.l (tbl_unsupp.l,%pc,%d1.w*4),%d1 # fetch routine addr + jsr (tbl_unsupp.l,%pc,%d1.l*1) + +# +# Exceptions in order of precedence: +# BSUN : none +# SNAN : all operations +# OPERR : all reg-reg or mem-reg operations that can normally operr +# OVFL : same as OPERR +# UNFL : same as OPERR +# DZ : same as OPERR +# INEX2 : same as OPERR +# INEX1 : all packed immediate operations +# + +# we determine the highest priority exception(if any) set by the +# emulation routine that has also been enabled by the user. + mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled + bne.b iea_op_ena # some are enabled + +# now, we save the result, unless, of course, the operation was ftst or fcmp. +# these don't save results. +iea_op_save: + tst.b STORE_FLG(%a6) # does this op store a result? + bne.b iea_op_exit1 # exit with no frestore + +iea_op_store: + bfextu EXC_CMDREG(%a6){&6:&3},%d0 # fetch dst regno + bsr.l store_fpreg # store the result + +iea_op_exit1: + mov.l EXC_PC(%a6),USER_FPIAR(%a6) # set FPIAR to "Current PC" + mov.l EXC_EXTWPTR(%a6),EXC_PC(%a6) # set "Next PC" in exc frame + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 # unravel the frame + + btst &0x7,(%sp) # is trace on? + bne.w iea_op_trace # yes + + bra.l _fpsp_done # exit to os + +iea_op_ena: + and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enable and set + bfffo %d0{&24:&8},%d0 # find highest priority exception + bne.b iea_op_exc # at least one was set + +# no exception occurred. now, did a disabled, exact overflow occur with inexact +# enabled? if so, then we have to stuff an overflow frame into the FPU. + btst &ovfl_bit,FPSR_EXCEPT(%a6) # did overflow occur? + beq.b iea_op_save + +iea_op_ovfl: + btst &inex2_bit,FPCR_ENABLE(%a6) # is inexact enabled? + beq.b iea_op_store # no + bra.b iea_op_exc_ovfl # yes + +# an enabled exception occurred. we have to insert the exception type back into +# the machine. +iea_op_exc: + subi.l &24,%d0 # fix offset to be 0-8 + cmpi.b %d0,&0x6 # is exception INEX? + bne.b iea_op_exc_force # no + +# the enabled exception was inexact. so, if it occurs with an overflow +# or underflow that was disabled, then we have to force an overflow or +# underflow frame. + btst &ovfl_bit,FPSR_EXCEPT(%a6) # did overflow occur? + bne.b iea_op_exc_ovfl # yes + btst &unfl_bit,FPSR_EXCEPT(%a6) # did underflow occur? + bne.b iea_op_exc_unfl # yes + +iea_op_exc_force: + mov.w (tbl_iea_except.b,%pc,%d0.w*2),2+FP_SRC(%a6) + bra.b iea_op_exit2 # exit with frestore + +tbl_iea_except: + short 0xe002, 0xe006, 0xe004, 0xe005 + short 0xe003, 0xe002, 0xe001, 0xe001 + +iea_op_exc_ovfl: + mov.w &0xe005,2+FP_SRC(%a6) + bra.b iea_op_exit2 + +iea_op_exc_unfl: + mov.w &0xe003,2+FP_SRC(%a6) + +iea_op_exit2: + mov.l EXC_PC(%a6),USER_FPIAR(%a6) # set FPIAR to "Current PC" + mov.l EXC_EXTWPTR(%a6),EXC_PC(%a6) # set "Next PC" in exc frame + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + frestore FP_SRC(%a6) # restore exceptional state + + unlk %a6 # unravel the frame + + btst &0x7,(%sp) # is trace on? + bne.b iea_op_trace # yes + + bra.l _fpsp_done # exit to os + +# +# The opclass two instruction that took an "Unimplemented Effective Address" +# exception was being traced. Make the "current" PC the FPIAR and put it in +# the trace stack frame then jump to _real_trace(). +# +# UNIMP EA FRAME TRACE FRAME +# ***************** ***************** +# * 0x0 * 0x0f0 * * Current * +# ***************** * PC * +# * Current * ***************** +# * PC * * 0x2 * 0x024 * +# ***************** ***************** +# * SR * * Next * +# ***************** * PC * +# ***************** +# * SR * +# ***************** +iea_op_trace: + mov.l (%sp),-(%sp) # shift stack frame "down" + mov.w 0x8(%sp),0x4(%sp) + mov.w &0x2024,0x6(%sp) # stk fmt = 0x2; voff = 0x024 + fmov.l %fpiar,0x8(%sp) # "Current PC" is in FPIAR + + bra.l _real_trace + +######################################################################### +iea_fmovm: + btst &14,%d0 # ctrl or data reg + beq.w iea_fmovm_ctrl + +iea_fmovm_data: + + btst &0x5,EXC_SR(%a6) # user or supervisor mode + bne.b iea_fmovm_data_s + +iea_fmovm_data_u: + mov.l %usp,%a0 + mov.l %a0,EXC_A7(%a6) # store current a7 + bsr.l fmovm_dynamic # do dynamic fmovm + mov.l EXC_A7(%a6),%a0 # load possibly new a7 + mov.l %a0,%usp # update usp + bra.w iea_fmovm_exit + +iea_fmovm_data_s: + clr.b SPCOND_FLG(%a6) + lea 0x2+EXC_VOFF(%a6),%a0 + mov.l %a0,EXC_A7(%a6) + bsr.l fmovm_dynamic # do dynamic fmovm + + cmpi.b SPCOND_FLG(%a6),&mda7_flg + beq.w iea_fmovm_data_predec + cmpi.b SPCOND_FLG(%a6),&mia7_flg + bne.w iea_fmovm_exit + +# right now, d0 = the size. +# the data has been fetched from the supervisor stack, but we have not +# incremented the stack pointer by the appropriate number of bytes. +# do it here. +iea_fmovm_data_postinc: + btst &0x7,EXC_SR(%a6) + bne.b iea_fmovm_data_pi_trace + + mov.w EXC_SR(%a6),(EXC_SR,%a6,%d0) + mov.l EXC_EXTWPTR(%a6),(EXC_PC,%a6,%d0) + mov.w &0x00f0,(EXC_VOFF,%a6,%d0) + + lea (EXC_SR,%a6,%d0),%a0 + mov.l %a0,EXC_SR(%a6) + + fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 + mov.l (%sp)+,%sp + bra.l _fpsp_done + +iea_fmovm_data_pi_trace: + mov.w EXC_SR(%a6),(EXC_SR-0x4,%a6,%d0) + mov.l EXC_EXTWPTR(%a6),(EXC_PC-0x4,%a6,%d0) + mov.w &0x2024,(EXC_VOFF-0x4,%a6,%d0) + mov.l EXC_PC(%a6),(EXC_VOFF+0x2-0x4,%a6,%d0) + + lea (EXC_SR-0x4,%a6,%d0),%a0 + mov.l %a0,EXC_SR(%a6) + + fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 + mov.l (%sp)+,%sp + bra.l _real_trace + +# right now, d1 = size and d0 = the strg. +iea_fmovm_data_predec: + mov.b %d1,EXC_VOFF(%a6) # store strg + mov.b %d0,0x1+EXC_VOFF(%a6) # store size + + fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + mov.l (%a6),-(%sp) # make a copy of a6 + mov.l %d0,-(%sp) # save d0 + mov.l %d1,-(%sp) # save d1 + mov.l EXC_EXTWPTR(%a6),-(%sp) # make a copy of Next PC + + clr.l %d0 + mov.b 0x1+EXC_VOFF(%a6),%d0 # fetch size + neg.l %d0 # get negative of size + + btst &0x7,EXC_SR(%a6) # is trace enabled? + beq.b iea_fmovm_data_p2 + + mov.w EXC_SR(%a6),(EXC_SR-0x4,%a6,%d0) + mov.l EXC_PC(%a6),(EXC_VOFF-0x2,%a6,%d0) + mov.l (%sp)+,(EXC_PC-0x4,%a6,%d0) + mov.w &0x2024,(EXC_VOFF-0x4,%a6,%d0) + + pea (%a6,%d0) # create final sp + bra.b iea_fmovm_data_p3 + +iea_fmovm_data_p2: + mov.w EXC_SR(%a6),(EXC_SR,%a6,%d0) + mov.l (%sp)+,(EXC_PC,%a6,%d0) + mov.w &0x00f0,(EXC_VOFF,%a6,%d0) + + pea (0x4,%a6,%d0) # create final sp + +iea_fmovm_data_p3: + clr.l %d1 + mov.b EXC_VOFF(%a6),%d1 # fetch strg + + tst.b %d1 + bpl.b fm_1 + fmovm.x &0x80,(0x4+0x8,%a6,%d0) + addi.l &0xc,%d0 +fm_1: + lsl.b &0x1,%d1 + bpl.b fm_2 + fmovm.x &0x40,(0x4+0x8,%a6,%d0) + addi.l &0xc,%d0 +fm_2: + lsl.b &0x1,%d1 + bpl.b fm_3 + fmovm.x &0x20,(0x4+0x8,%a6,%d0) + addi.l &0xc,%d0 +fm_3: + lsl.b &0x1,%d1 + bpl.b fm_4 + fmovm.x &0x10,(0x4+0x8,%a6,%d0) + addi.l &0xc,%d0 +fm_4: + lsl.b &0x1,%d1 + bpl.b fm_5 + fmovm.x &0x08,(0x4+0x8,%a6,%d0) + addi.l &0xc,%d0 +fm_5: + lsl.b &0x1,%d1 + bpl.b fm_6 + fmovm.x &0x04,(0x4+0x8,%a6,%d0) + addi.l &0xc,%d0 +fm_6: + lsl.b &0x1,%d1 + bpl.b fm_7 + fmovm.x &0x02,(0x4+0x8,%a6,%d0) + addi.l &0xc,%d0 +fm_7: + lsl.b &0x1,%d1 + bpl.b fm_end + fmovm.x &0x01,(0x4+0x8,%a6,%d0) +fm_end: + mov.l 0x4(%sp),%d1 + mov.l 0x8(%sp),%d0 + mov.l 0xc(%sp),%a6 + mov.l (%sp)+,%sp + + btst &0x7,(%sp) # is trace enabled? + beq.l _fpsp_done + bra.l _real_trace + +######################################################################### +iea_fmovm_ctrl: + + bsr.l fmovm_ctrl # load ctrl regs + +iea_fmovm_exit: + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + btst &0x7,EXC_SR(%a6) # is trace on? + bne.b iea_fmovm_trace # yes + + mov.l EXC_EXTWPTR(%a6),EXC_PC(%a6) # set Next PC + + unlk %a6 # unravel the frame + + bra.l _fpsp_done # exit to os + +# +# The control reg instruction that took an "Unimplemented Effective Address" +# exception was being traced. The "Current PC" for the trace frame is the +# PC stacked for Unimp EA. The "Next PC" is in EXC_EXTWPTR. +# After fixing the stack frame, jump to _real_trace(). +# +# UNIMP EA FRAME TRACE FRAME +# ***************** ***************** +# * 0x0 * 0x0f0 * * Current * +# ***************** * PC * +# * Current * ***************** +# * PC * * 0x2 * 0x024 * +# ***************** ***************** +# * SR * * Next * +# ***************** * PC * +# ***************** +# * SR * +# ***************** +# this ain't a pretty solution, but it works: +# -restore a6 (not with unlk) +# -shift stack frame down over where old a6 used to be +# -add LOCAL_SIZE to stack pointer +iea_fmovm_trace: + mov.l (%a6),%a6 # restore frame pointer + mov.w EXC_SR+LOCAL_SIZE(%sp),0x0+LOCAL_SIZE(%sp) + mov.l EXC_PC+LOCAL_SIZE(%sp),0x8+LOCAL_SIZE(%sp) + mov.l EXC_EXTWPTR+LOCAL_SIZE(%sp),0x2+LOCAL_SIZE(%sp) + mov.w &0x2024,0x6+LOCAL_SIZE(%sp) # stk fmt = 0x2; voff = 0x024 + add.l &LOCAL_SIZE,%sp # clear stack frame + + bra.l _real_trace + +######################################################################### +# The FPU is disabled and so we should really have taken the "Line +# F Emulator" exception. So, here we create an 8-word stack frame +# from our 4-word stack frame. This means we must calculate the length +# the faulting instruction to get the "next PC". This is trivial for +# immediate operands but requires some extra work for fmovm dynamic +# which can use most addressing modes. +iea_disabled: + mov.l (%sp)+,%d0 # restore d0 + + link %a6,&-LOCAL_SIZE # init stack frame + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + +# PC of instruction that took the exception is the PC in the frame + mov.l EXC_PC(%a6),EXC_EXTWPTR(%a6) + mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr + addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr + bsr.l _imem_read_long # fetch the instruction words + mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD + + tst.w %d0 # is instr fmovm? + bmi.b iea_dis_fmovm # yes +# instruction is using an extended precision immediate operand. Therefore, +# the total instruction length is 16 bytes. +iea_dis_immed: + mov.l &0x10,%d0 # 16 bytes of instruction + bra.b iea_dis_cont +iea_dis_fmovm: + btst &0xe,%d0 # is instr fmovm ctrl + bne.b iea_dis_fmovm_data # no +# the instruction is a fmovm.l with 2 or 3 registers. + bfextu %d0{&19:&3},%d1 + mov.l &0xc,%d0 + cmpi.b %d1,&0x7 # move all regs? + bne.b iea_dis_cont + addq.l &0x4,%d0 + bra.b iea_dis_cont +# the instruction is an fmovm.x dynamic which can use many addressing +# modes and thus can have several different total instruction lengths. +# call fmovm_calc_ea which will go through the ea calc process and, +# as a by-product, will tell us how long the instruction is. +iea_dis_fmovm_data: + clr.l %d0 + bsr.l fmovm_calc_ea + mov.l EXC_EXTWPTR(%a6),%d0 + sub.l EXC_PC(%a6),%d0 +iea_dis_cont: + mov.w %d0,EXC_VOFF(%a6) # store stack shift value + + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 + +# here, we actually create the 8-word frame from the 4-word frame, +# with the "next PC" as additional info. +# the field is let as undefined. + subq.l &0x8,%sp # make room for new stack + mov.l %d0,-(%sp) # save d0 + mov.w 0xc(%sp),0x4(%sp) # move SR + mov.l 0xe(%sp),0x6(%sp) # move Current PC + clr.l %d0 + mov.w 0x12(%sp),%d0 + mov.l 0x6(%sp),0x10(%sp) # move Current PC + add.l %d0,0x6(%sp) # make Next PC + mov.w &0x402c,0xa(%sp) # insert offset,frame format + mov.l (%sp)+,%d0 # restore d0 + + bra.l _real_fpu_disabled + +########## + +iea_iacc: + movc %pcr,%d0 + btst &0x1,%d0 + bne.b iea_iacc_cont + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 on stack +iea_iacc_cont: + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 + + subq.w &0x8,%sp # make stack frame bigger + mov.l 0x8(%sp),(%sp) # store SR,hi(PC) + mov.w 0xc(%sp),0x4(%sp) # store lo(PC) + mov.w &0x4008,0x6(%sp) # store voff + mov.l 0x2(%sp),0x8(%sp) # store ea + mov.l &0x09428001,0xc(%sp) # store fslw + +iea_acc_done: + btst &0x5,(%sp) # user or supervisor mode? + beq.b iea_acc_done2 # user + bset &0x2,0xd(%sp) # set supervisor TM bit + +iea_acc_done2: + bra.l _real_access + +iea_dacc: + lea -LOCAL_SIZE(%a6),%sp + + movc %pcr,%d1 + btst &0x1,%d1 + bne.b iea_dacc_cont + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 on stack + fmovm.l LOCAL_SIZE+USER_FPCR(%sp),%fpcr,%fpsr,%fpiar # restore ctrl regs +iea_dacc_cont: + mov.l (%a6),%a6 + + mov.l 0x4+LOCAL_SIZE(%sp),-0x8+0x4+LOCAL_SIZE(%sp) + mov.w 0x8+LOCAL_SIZE(%sp),-0x8+0x8+LOCAL_SIZE(%sp) + mov.w &0x4008,-0x8+0xa+LOCAL_SIZE(%sp) + mov.l %a0,-0x8+0xc+LOCAL_SIZE(%sp) + mov.w %d0,-0x8+0x10+LOCAL_SIZE(%sp) + mov.w &0x0001,-0x8+0x12+LOCAL_SIZE(%sp) + + movm.l LOCAL_SIZE+EXC_DREGS(%sp),&0x0303 # restore d0-d1/a0-a1 + add.w &LOCAL_SIZE-0x4,%sp + + bra.b iea_acc_done + +######################################################################### +# XDEF **************************************************************** # +# _fpsp_operr(): 060FPSP entry point for FP Operr exception. # +# # +# This handler should be the first code executed upon taking the # +# FP Operand Error exception in an operating system. # +# # +# XREF **************************************************************** # +# _imem_read_long() - read instruction longword # +# fix_skewed_ops() - adjust src operand in fsave frame # +# _real_operr() - "callout" to operating system operr handler # +# _dmem_write_{byte,word,long}() - store data to mem (opclass 3) # +# store_dreg_{b,w,l}() - store data to data regfile (opclass 3) # +# facc_out_{b,w,l}() - store to memory took access error (opcl 3) # +# # +# INPUT *************************************************************** # +# - The system stack contains the FP Operr exception frame # +# - The fsave frame contains the source operand # +# # +# OUTPUT ************************************************************** # +# No access error: # +# - The system stack is unchanged # +# - The fsave frame contains the adjusted src op for opclass 0,2 # +# # +# ALGORITHM *********************************************************** # +# In a system where the FP Operr exception is enabled, the goal # +# is to get to the handler specified at _real_operr(). But, on the 060, # +# for opclass zero and two instruction taking this exception, the # +# input operand in the fsave frame may be incorrect for some cases # +# and needs to be corrected. This handler calls fix_skewed_ops() to # +# do just this and then exits through _real_operr(). # +# For opclass 3 instructions, the 060 doesn't store the default # +# operr result out to memory or data register file as it should. # +# This code must emulate the move out before finally exiting through # +# _real_inex(). The move out, if to memory, is performed using # +# _mem_write() "callout" routines that may return a failing result. # +# In this special case, the handler must exit through facc_out() # +# which creates an access error stack frame from the current operr # +# stack frame. # +# # +######################################################################### + + global _fpsp_operr +_fpsp_operr: + + link.w %a6,&-LOCAL_SIZE # init stack frame + + fsave FP_SRC(%a6) # grab the "busy" frame + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack + +# the FPIAR holds the "current PC" of the faulting instruction + mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) + + mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr + addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr + bsr.l _imem_read_long # fetch the instruction words + mov.l %d0,EXC_OPWORD(%a6) + +############################################################################## + + btst &13,%d0 # is instr an fmove out? + bne.b foperr_out # fmove out + + +# here, we simply see if the operand in the fsave frame needs to be "unskewed". +# this would be the case for opclass two operations with a source infinity or +# denorm operand in the sgl or dbl format. NANs also become skewed, but can't +# cause an operr so we don't need to check for them here. + lea FP_SRC(%a6),%a0 # pass: ptr to src op + bsr.l fix_skewed_ops # fix src op + +foperr_exit: + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + frestore FP_SRC(%a6) + + unlk %a6 + bra.l _real_operr + +######################################################################## + +# +# the hardware does not save the default result to memory on enabled +# operand error exceptions. we do this here before passing control to +# the user operand error handler. +# +# byte, word, and long destination format operations can pass +# through here. we simply need to test the sign of the src +# operand and save the appropriate minimum or maximum integer value +# to the effective address as pointed to by the stacked effective address. +# +# although packed opclass three operations can take operand error +# exceptions, they won't pass through here since they are caught +# first by the unsupported data format exception handler. that handler +# sends them directly to _real_operr() if necessary. +# +foperr_out: + + mov.w FP_SRC_EX(%a6),%d1 # fetch exponent + andi.w &0x7fff,%d1 + cmpi.w %d1,&0x7fff + bne.b foperr_out_not_qnan +# the operand is either an infinity or a QNAN. + tst.l FP_SRC_LO(%a6) + bne.b foperr_out_qnan + mov.l FP_SRC_HI(%a6),%d1 + andi.l &0x7fffffff,%d1 + beq.b foperr_out_not_qnan +foperr_out_qnan: + mov.l FP_SRC_HI(%a6),L_SCR1(%a6) + bra.b foperr_out_jmp + +foperr_out_not_qnan: + mov.l &0x7fffffff,%d1 + tst.b FP_SRC_EX(%a6) + bpl.b foperr_out_not_qnan2 + addq.l &0x1,%d1 +foperr_out_not_qnan2: + mov.l %d1,L_SCR1(%a6) + +foperr_out_jmp: + bfextu %d0{&19:&3},%d0 # extract dst format field + mov.b 1+EXC_OPWORD(%a6),%d1 # extract mode,reg + mov.w (tbl_operr.b,%pc,%d0.w*2),%a0 + jmp (tbl_operr.b,%pc,%a0) + +tbl_operr: + short foperr_out_l - tbl_operr # long word integer + short tbl_operr - tbl_operr # sgl prec shouldn't happen + short tbl_operr - tbl_operr # ext prec shouldn't happen + short foperr_exit - tbl_operr # packed won't enter here + short foperr_out_w - tbl_operr # word integer + short tbl_operr - tbl_operr # dbl prec shouldn't happen + short foperr_out_b - tbl_operr # byte integer + short tbl_operr - tbl_operr # packed won't enter here + +foperr_out_b: + mov.b L_SCR1(%a6),%d0 # load positive default result + cmpi.b %d1,&0x7 # is mode a data reg? + ble.b foperr_out_b_save_dn # yes + mov.l EXC_EA(%a6),%a0 # pass: of default result + bsr.l _dmem_write_byte # write the default result + + tst.l %d1 # did dstore fail? + bne.l facc_out_b # yes + + bra.w foperr_exit +foperr_out_b_save_dn: + andi.w &0x0007,%d1 + bsr.l store_dreg_b # store result to regfile + bra.w foperr_exit + +foperr_out_w: + mov.w L_SCR1(%a6),%d0 # load positive default result + cmpi.b %d1,&0x7 # is mode a data reg? + ble.b foperr_out_w_save_dn # yes + mov.l EXC_EA(%a6),%a0 # pass: of default result + bsr.l _dmem_write_word # write the default result + + tst.l %d1 # did dstore fail? + bne.l facc_out_w # yes + + bra.w foperr_exit +foperr_out_w_save_dn: + andi.w &0x0007,%d1 + bsr.l store_dreg_w # store result to regfile + bra.w foperr_exit + +foperr_out_l: + mov.l L_SCR1(%a6),%d0 # load positive default result + cmpi.b %d1,&0x7 # is mode a data reg? + ble.b foperr_out_l_save_dn # yes + mov.l EXC_EA(%a6),%a0 # pass: of default result + bsr.l _dmem_write_long # write the default result + + tst.l %d1 # did dstore fail? + bne.l facc_out_l # yes + + bra.w foperr_exit +foperr_out_l_save_dn: + andi.w &0x0007,%d1 + bsr.l store_dreg_l # store result to regfile + bra.w foperr_exit + +######################################################################### +# XDEF **************************************************************** # +# _fpsp_snan(): 060FPSP entry point for FP SNAN exception. # +# # +# This handler should be the first code executed upon taking the # +# FP Signalling NAN exception in an operating system. # +# # +# XREF **************************************************************** # +# _imem_read_long() - read instruction longword # +# fix_skewed_ops() - adjust src operand in fsave frame # +# _real_snan() - "callout" to operating system SNAN handler # +# _dmem_write_{byte,word,long}() - store data to mem (opclass 3) # +# store_dreg_{b,w,l}() - store data to data regfile (opclass 3) # +# facc_out_{b,w,l,d,x}() - store to mem took acc error (opcl 3) # +# _calc_ea_fout() - fix An if is -() or ()+; also get # +# # +# INPUT *************************************************************** # +# - The system stack contains the FP SNAN exception frame # +# - The fsave frame contains the source operand # +# # +# OUTPUT ************************************************************** # +# No access error: # +# - The system stack is unchanged # +# - The fsave frame contains the adjusted src op for opclass 0,2 # +# # +# ALGORITHM *********************************************************** # +# In a system where the FP SNAN exception is enabled, the goal # +# is to get to the handler specified at _real_snan(). But, on the 060, # +# for opclass zero and two instructions taking this exception, the # +# input operand in the fsave frame may be incorrect for some cases # +# and needs to be corrected. This handler calls fix_skewed_ops() to # +# do just this and then exits through _real_snan(). # +# For opclass 3 instructions, the 060 doesn't store the default # +# SNAN result out to memory or data register file as it should. # +# This code must emulate the move out before finally exiting through # +# _real_snan(). The move out, if to memory, is performed using # +# _mem_write() "callout" routines that may return a failing result. # +# In this special case, the handler must exit through facc_out() # +# which creates an access error stack frame from the current SNAN # +# stack frame. # +# For the case of an extended precision opclass 3 instruction, # +# if the effective addressing mode was -() or ()+, then the address # +# register must get updated by calling _calc_ea_fout(). If the # +# was -(a7) from supervisor mode, then the exception frame currently # +# on the system stack must be carefully moved "down" to make room # +# for the operand being moved. # +# # +######################################################################### + + global _fpsp_snan +_fpsp_snan: + + link.w %a6,&-LOCAL_SIZE # init stack frame + + fsave FP_SRC(%a6) # grab the "busy" frame + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack + +# the FPIAR holds the "current PC" of the faulting instruction + mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) + + mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr + addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr + bsr.l _imem_read_long # fetch the instruction words + mov.l %d0,EXC_OPWORD(%a6) + +############################################################################## + + btst &13,%d0 # is instr an fmove out? + bne.w fsnan_out # fmove out + + +# here, we simply see if the operand in the fsave frame needs to be "unskewed". +# this would be the case for opclass two operations with a source infinity or +# denorm operand in the sgl or dbl format. NANs also become skewed and must be +# fixed here. + lea FP_SRC(%a6),%a0 # pass: ptr to src op + bsr.l fix_skewed_ops # fix src op + +fsnan_exit: + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + frestore FP_SRC(%a6) + + unlk %a6 + bra.l _real_snan + +######################################################################## + +# +# the hardware does not save the default result to memory on enabled +# snan exceptions. we do this here before passing control to +# the user snan handler. +# +# byte, word, long, and packed destination format operations can pass +# through here. since packed format operations already were handled by +# fpsp_unsupp(), then we need to do nothing else for them here. +# for byte, word, and long, we simply need to test the sign of the src +# operand and save the appropriate minimum or maximum integer value +# to the effective address as pointed to by the stacked effective address. +# +fsnan_out: + + bfextu %d0{&19:&3},%d0 # extract dst format field + mov.b 1+EXC_OPWORD(%a6),%d1 # extract mode,reg + mov.w (tbl_snan.b,%pc,%d0.w*2),%a0 + jmp (tbl_snan.b,%pc,%a0) + +tbl_snan: + short fsnan_out_l - tbl_snan # long word integer + short fsnan_out_s - tbl_snan # sgl prec shouldn't happen + short fsnan_out_x - tbl_snan # ext prec shouldn't happen + short tbl_snan - tbl_snan # packed needs no help + short fsnan_out_w - tbl_snan # word integer + short fsnan_out_d - tbl_snan # dbl prec shouldn't happen + short fsnan_out_b - tbl_snan # byte integer + short tbl_snan - tbl_snan # packed needs no help + +fsnan_out_b: + mov.b FP_SRC_HI(%a6),%d0 # load upper byte of SNAN + bset &6,%d0 # set SNAN bit + cmpi.b %d1,&0x7 # is mode a data reg? + ble.b fsnan_out_b_dn # yes + mov.l EXC_EA(%a6),%a0 # pass: of default result + bsr.l _dmem_write_byte # write the default result + + tst.l %d1 # did dstore fail? + bne.l facc_out_b # yes + + bra.w fsnan_exit +fsnan_out_b_dn: + andi.w &0x0007,%d1 + bsr.l store_dreg_b # store result to regfile + bra.w fsnan_exit + +fsnan_out_w: + mov.w FP_SRC_HI(%a6),%d0 # load upper word of SNAN + bset &14,%d0 # set SNAN bit + cmpi.b %d1,&0x7 # is mode a data reg? + ble.b fsnan_out_w_dn # yes + mov.l EXC_EA(%a6),%a0 # pass: of default result + bsr.l _dmem_write_word # write the default result + + tst.l %d1 # did dstore fail? + bne.l facc_out_w # yes + + bra.w fsnan_exit +fsnan_out_w_dn: + andi.w &0x0007,%d1 + bsr.l store_dreg_w # store result to regfile + bra.w fsnan_exit + +fsnan_out_l: + mov.l FP_SRC_HI(%a6),%d0 # load upper longword of SNAN + bset &30,%d0 # set SNAN bit + cmpi.b %d1,&0x7 # is mode a data reg? + ble.b fsnan_out_l_dn # yes + mov.l EXC_EA(%a6),%a0 # pass: of default result + bsr.l _dmem_write_long # write the default result + + tst.l %d1 # did dstore fail? + bne.l facc_out_l # yes + + bra.w fsnan_exit +fsnan_out_l_dn: + andi.w &0x0007,%d1 + bsr.l store_dreg_l # store result to regfile + bra.w fsnan_exit + +fsnan_out_s: + cmpi.b %d1,&0x7 # is mode a data reg? + ble.b fsnan_out_d_dn # yes + mov.l FP_SRC_EX(%a6),%d0 # fetch SNAN sign + andi.l &0x80000000,%d0 # keep sign + ori.l &0x7fc00000,%d0 # insert new exponent,SNAN bit + mov.l FP_SRC_HI(%a6),%d1 # load mantissa + lsr.l &0x8,%d1 # shift mantissa for sgl + or.l %d1,%d0 # create sgl SNAN + mov.l EXC_EA(%a6),%a0 # pass: of default result + bsr.l _dmem_write_long # write the default result + + tst.l %d1 # did dstore fail? + bne.l facc_out_l # yes + + bra.w fsnan_exit +fsnan_out_d_dn: + mov.l FP_SRC_EX(%a6),%d0 # fetch SNAN sign + andi.l &0x80000000,%d0 # keep sign + ori.l &0x7fc00000,%d0 # insert new exponent,SNAN bit + mov.l %d1,-(%sp) + mov.l FP_SRC_HI(%a6),%d1 # load mantissa + lsr.l &0x8,%d1 # shift mantissa for sgl + or.l %d1,%d0 # create sgl SNAN + mov.l (%sp)+,%d1 + andi.w &0x0007,%d1 + bsr.l store_dreg_l # store result to regfile + bra.w fsnan_exit + +fsnan_out_d: + mov.l FP_SRC_EX(%a6),%d0 # fetch SNAN sign + andi.l &0x80000000,%d0 # keep sign + ori.l &0x7ff80000,%d0 # insert new exponent,SNAN bit + mov.l FP_SRC_HI(%a6),%d1 # load hi mantissa + mov.l %d0,FP_SCR0_EX(%a6) # store to temp space + mov.l &11,%d0 # load shift amt + lsr.l %d0,%d1 + or.l %d1,FP_SCR0_EX(%a6) # create dbl hi + mov.l FP_SRC_HI(%a6),%d1 # load hi mantissa + andi.l &0x000007ff,%d1 + ror.l %d0,%d1 + mov.l %d1,FP_SCR0_HI(%a6) # store to temp space + mov.l FP_SRC_LO(%a6),%d1 # load lo mantissa + lsr.l %d0,%d1 + or.l %d1,FP_SCR0_HI(%a6) # create dbl lo + lea FP_SCR0(%a6),%a0 # pass: ptr to operand + mov.l EXC_EA(%a6),%a1 # pass: dst addr + movq.l &0x8,%d0 # pass: size of 8 bytes + bsr.l _dmem_write # write the default result + + tst.l %d1 # did dstore fail? + bne.l facc_out_d # yes + + bra.w fsnan_exit + +# for extended precision, if the addressing mode is pre-decrement or +# post-increment, then the address register did not get updated. +# in addition, for pre-decrement, the stacked is incorrect. +fsnan_out_x: + clr.b SPCOND_FLG(%a6) # clear special case flag + + mov.w FP_SRC_EX(%a6),FP_SCR0_EX(%a6) + clr.w 2+FP_SCR0(%a6) + mov.l FP_SRC_HI(%a6),%d0 + bset &30,%d0 + mov.l %d0,FP_SCR0_HI(%a6) + mov.l FP_SRC_LO(%a6),FP_SCR0_LO(%a6) + + btst &0x5,EXC_SR(%a6) # supervisor mode exception? + bne.b fsnan_out_x_s # yes + + mov.l %usp,%a0 # fetch user stack pointer + mov.l %a0,EXC_A7(%a6) # save on stack for calc_ea() + mov.l (%a6),EXC_A6(%a6) + + bsr.l _calc_ea_fout # find the correct ea,update An + mov.l %a0,%a1 + mov.l %a0,EXC_EA(%a6) # stack correct + + mov.l EXC_A7(%a6),%a0 + mov.l %a0,%usp # restore user stack pointer + mov.l EXC_A6(%a6),(%a6) + +fsnan_out_x_save: + lea FP_SCR0(%a6),%a0 # pass: ptr to operand + movq.l &0xc,%d0 # pass: size of extended + bsr.l _dmem_write # write the default result + + tst.l %d1 # did dstore fail? + bne.l facc_out_x # yes + + bra.w fsnan_exit + +fsnan_out_x_s: + mov.l (%a6),EXC_A6(%a6) + + bsr.l _calc_ea_fout # find the correct ea,update An + mov.l %a0,%a1 + mov.l %a0,EXC_EA(%a6) # stack correct + + mov.l EXC_A6(%a6),(%a6) + + cmpi.b SPCOND_FLG(%a6),&mda7_flg # is mode -(a7)? + bne.b fsnan_out_x_save # no + +# the operation was "fmove.x SNAN,-(a7)" from supervisor mode. + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + frestore FP_SRC(%a6) + + mov.l EXC_A6(%a6),%a6 # restore frame pointer + + mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp) + mov.l LOCAL_SIZE+EXC_PC+0x2(%sp),LOCAL_SIZE+EXC_PC+0x2-0xc(%sp) + mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp) + + mov.l LOCAL_SIZE+FP_SCR0_EX(%sp),LOCAL_SIZE+EXC_SR(%sp) + mov.l LOCAL_SIZE+FP_SCR0_HI(%sp),LOCAL_SIZE+EXC_PC+0x2(%sp) + mov.l LOCAL_SIZE+FP_SCR0_LO(%sp),LOCAL_SIZE+EXC_EA(%sp) + + add.l &LOCAL_SIZE-0x8,%sp + + bra.l _real_snan + +######################################################################### +# XDEF **************************************************************** # +# _fpsp_inex(): 060FPSP entry point for FP Inexact exception. # +# # +# This handler should be the first code executed upon taking the # +# FP Inexact exception in an operating system. # +# # +# XREF **************************************************************** # +# _imem_read_long() - read instruction longword # +# fix_skewed_ops() - adjust src operand in fsave frame # +# set_tag_x() - determine optype of src/dst operands # +# store_fpreg() - store opclass 0 or 2 result to FP regfile # +# unnorm_fix() - change UNNORM operands to NORM or ZERO # +# load_fpn2() - load dst operand from FP regfile # +# smovcr() - emulate an "fmovcr" instruction # +# fout() - emulate an opclass 3 instruction # +# tbl_unsupp - add of table of emulation routines for opclass 0,2 # +# _real_inex() - "callout" to operating system inexact handler # +# # +# INPUT *************************************************************** # +# - The system stack contains the FP Inexact exception frame # +# - The fsave frame contains the source operand # +# # +# OUTPUT ************************************************************** # +# - The system stack is unchanged # +# - The fsave frame contains the adjusted src op for opclass 0,2 # +# # +# ALGORITHM *********************************************************** # +# In a system where the FP Inexact exception is enabled, the goal # +# is to get to the handler specified at _real_inex(). But, on the 060, # +# for opclass zero and two instruction taking this exception, the # +# hardware doesn't store the correct result to the destination FP # +# register as did the '040 and '881/2. This handler must emulate the # +# instruction in order to get this value and then store it to the # +# correct register before calling _real_inex(). # +# For opclass 3 instructions, the 060 doesn't store the default # +# inexact result out to memory or data register file as it should. # +# This code must emulate the move out by calling fout() before finally # +# exiting through _real_inex(). # +# # +######################################################################### + + global _fpsp_inex +_fpsp_inex: + + link.w %a6,&-LOCAL_SIZE # init stack frame + + fsave FP_SRC(%a6) # grab the "busy" frame + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack + +# the FPIAR holds the "current PC" of the faulting instruction + mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) + + mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr + addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr + bsr.l _imem_read_long # fetch the instruction words + mov.l %d0,EXC_OPWORD(%a6) + +############################################################################## + + btst &13,%d0 # is instr an fmove out? + bne.w finex_out # fmove out + + +# the hardware, for "fabs" and "fneg" w/ a long source format, puts the +# longword integer directly into the upper longword of the mantissa along +# w/ an exponent value of 0x401e. we convert this to extended precision here. + bfextu %d0{&19:&3},%d0 # fetch instr size + bne.b finex_cont # instr size is not long + cmpi.w FP_SRC_EX(%a6),&0x401e # is exponent 0x401e? + bne.b finex_cont # no + fmov.l &0x0,%fpcr + fmov.l FP_SRC_HI(%a6),%fp0 # load integer src + fmov.x %fp0,FP_SRC(%a6) # store integer as extended precision + mov.w &0xe001,0x2+FP_SRC(%a6) + +finex_cont: + lea FP_SRC(%a6),%a0 # pass: ptr to src op + bsr.l fix_skewed_ops # fix src op + +# Here, we zero the ccode and exception byte field since we're going to +# emulate the whole instruction. Notice, though, that we don't kill the +# INEX1 bit. This is because a packed op has long since been converted +# to extended before arriving here. Therefore, we need to retain the +# INEX1 bit from when the operand was first converted. + andi.l &0x00ff01ff,USER_FPSR(%a6) # zero all but accured field + + fmov.l &0x0,%fpcr # zero current control regs + fmov.l &0x0,%fpsr + + bfextu EXC_EXTWORD(%a6){&0:&6},%d1 # extract upper 6 of cmdreg + cmpi.b %d1,&0x17 # is op an fmovecr? + beq.w finex_fmovcr # yes + + lea FP_SRC(%a6),%a0 # pass: ptr to src op + bsr.l set_tag_x # tag the operand type + mov.b %d0,STAG(%a6) # maybe NORM,DENORM + +# bits four and five of the fp extension word separate the monadic and dyadic +# operations that can pass through fpsp_inex(). remember that fcmp and ftst +# will never take this exception, but fsincos will. + btst &0x5,1+EXC_CMDREG(%a6) # is operation monadic or dyadic? + beq.b finex_extract # monadic + + btst &0x4,1+EXC_CMDREG(%a6) # is operation an fsincos? + bne.b finex_extract # yes + + bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg + bsr.l load_fpn2 # load dst into FP_DST + + lea FP_DST(%a6),%a0 # pass: ptr to dst op + bsr.l set_tag_x # tag the operand type + cmpi.b %d0,&UNNORM # is operand an UNNORM? + bne.b finex_op2_done # no + bsr.l unnorm_fix # yes; convert to NORM,DENORM,or ZERO +finex_op2_done: + mov.b %d0,DTAG(%a6) # save dst optype tag + +finex_extract: + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode + + mov.b 1+EXC_CMDREG(%a6),%d1 + andi.w &0x007f,%d1 # extract extension + + lea FP_SRC(%a6),%a0 + lea FP_DST(%a6),%a1 + + mov.l (tbl_unsupp.l,%pc,%d1.w*4),%d1 # fetch routine addr + jsr (tbl_unsupp.l,%pc,%d1.l*1) + +# the operation has been emulated. the result is in fp0. +finex_save: + bfextu EXC_CMDREG(%a6){&6:&3},%d0 + bsr.l store_fpreg + +finex_exit: + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + frestore FP_SRC(%a6) + + unlk %a6 + bra.l _real_inex + +finex_fmovcr: + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd prec,mode + mov.b 1+EXC_CMDREG(%a6),%d1 + andi.l &0x0000007f,%d1 # pass rom offset + bsr.l smovcr + bra.b finex_save + +######################################################################## + +# +# the hardware does not save the default result to memory on enabled +# inexact exceptions. we do this here before passing control to +# the user inexact handler. +# +# byte, word, and long destination format operations can pass +# through here. so can double and single precision. +# although packed opclass three operations can take inexact +# exceptions, they won't pass through here since they are caught +# first by the unsupported data format exception handler. that handler +# sends them directly to _real_inex() if necessary. +# +finex_out: + + mov.b &NORM,STAG(%a6) # src is a NORM + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd prec,mode + + andi.l &0xffff00ff,USER_FPSR(%a6) # zero exception field + + lea FP_SRC(%a6),%a0 # pass ptr to src operand + + bsr.l fout # store the default result + + bra.b finex_exit + +######################################################################### +# XDEF **************************************************************** # +# _fpsp_dz(): 060FPSP entry point for FP DZ exception. # +# # +# This handler should be the first code executed upon taking # +# the FP DZ exception in an operating system. # +# # +# XREF **************************************************************** # +# _imem_read_long() - read instruction longword from memory # +# fix_skewed_ops() - adjust fsave operand # +# _real_dz() - "callout" exit point from FP DZ handler # +# # +# INPUT *************************************************************** # +# - The system stack contains the FP DZ exception stack. # +# - The fsave frame contains the source operand. # +# # +# OUTPUT ************************************************************** # +# - The system stack contains the FP DZ exception stack. # +# - The fsave frame contains the adjusted source operand. # +# # +# ALGORITHM *********************************************************** # +# In a system where the DZ exception is enabled, the goal is to # +# get to the handler specified at _real_dz(). But, on the 060, when the # +# exception is taken, the input operand in the fsave state frame may # +# be incorrect for some cases and need to be adjusted. So, this package # +# adjusts the operand using fix_skewed_ops() and then branches to # +# _real_dz(). # +# # +######################################################################### + + global _fpsp_dz +_fpsp_dz: + + link.w %a6,&-LOCAL_SIZE # init stack frame + + fsave FP_SRC(%a6) # grab the "busy" frame + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack + +# the FPIAR holds the "current PC" of the faulting instruction + mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) + + mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr + addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr + bsr.l _imem_read_long # fetch the instruction words + mov.l %d0,EXC_OPWORD(%a6) + +############################################################################## + + +# here, we simply see if the operand in the fsave frame needs to be "unskewed". +# this would be the case for opclass two operations with a source zero +# in the sgl or dbl format. + lea FP_SRC(%a6),%a0 # pass: ptr to src op + bsr.l fix_skewed_ops # fix src op + +fdz_exit: + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + frestore FP_SRC(%a6) + + unlk %a6 + bra.l _real_dz + +######################################################################### +# XDEF **************************************************************** # +# _fpsp_fline(): 060FPSP entry point for "Line F emulator" exc. # +# # +# This handler should be the first code executed upon taking the # +# "Line F Emulator" exception in an operating system. # +# # +# XREF **************************************************************** # +# _fpsp_unimp() - handle "FP Unimplemented" exceptions # +# _real_fpu_disabled() - handle "FPU disabled" exceptions # +# _real_fline() - handle "FLINE" exceptions # +# _imem_read_long() - read instruction longword # +# # +# INPUT *************************************************************** # +# - The system stack contains a "Line F Emulator" exception # +# stack frame. # +# # +# OUTPUT ************************************************************** # +# - The system stack is unchanged # +# # +# ALGORITHM *********************************************************** # +# When a "Line F Emulator" exception occurs, there are 3 possible # +# exception types, denoted by the exception stack frame format number: # +# (1) FPU unimplemented instruction (6 word stack frame) # +# (2) FPU disabled (8 word stack frame) # +# (3) Line F (4 word stack frame) # +# # +# This module determines which and forks the flow off to the # +# appropriate "callout" (for "disabled" and "Line F") or to the # +# correct emulation code (for "FPU unimplemented"). # +# This code also must check for "fmovecr" instructions w/ a # +# non-zero field. These may get flagged as "Line F" but should # +# really be flagged as "FPU Unimplemented". (This is a "feature" on # +# the '060. # +# # +######################################################################### + + global _fpsp_fline +_fpsp_fline: + +# check to see if this exception is a "FP Unimplemented Instruction" +# exception. if so, branch directly to that handler's entry point. + cmpi.w 0x6(%sp),&0x202c + beq.l _fpsp_unimp + +# check to see if the FPU is disabled. if so, jump to the OS entry +# point for that condition. + cmpi.w 0x6(%sp),&0x402c + beq.l _real_fpu_disabled + +# the exception was an "F-Line Illegal" exception. we check to see +# if the F-Line instruction is an "fmovecr" w/ a non-zero . if +# so, convert the F-Line exception stack frame to an FP Unimplemented +# Instruction exception stack frame else branch to the OS entry +# point for the F-Line exception handler. + link.w %a6,&-LOCAL_SIZE # init stack frame + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + + mov.l EXC_PC(%a6),EXC_EXTWPTR(%a6) + mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr + addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr + bsr.l _imem_read_long # fetch instruction words + + bfextu %d0{&0:&10},%d1 # is it an fmovecr? + cmpi.w %d1,&0x03c8 + bne.b fline_fline # no + + bfextu %d0{&16:&6},%d1 # is it an fmovecr? + cmpi.b %d1,&0x17 + bne.b fline_fline # no + +# it's an fmovecr w/ a non-zero that has entered through +# the F-Line Illegal exception. +# so, we need to convert the F-Line exception stack frame into an +# FP Unimplemented Instruction stack frame and jump to that entry +# point. +# +# but, if the FPU is disabled, then we need to jump to the FPU disabled +# entry point. + movc %pcr,%d0 + btst &0x1,%d0 + beq.b fline_fmovcr + + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 + + sub.l &0x8,%sp # make room for "Next PC", + mov.w 0x8(%sp),(%sp) + mov.l 0xa(%sp),0x2(%sp) # move "Current PC" + mov.w &0x402c,0x6(%sp) + mov.l 0x2(%sp),0xc(%sp) + addq.l &0x4,0x2(%sp) # set "Next PC" + + bra.l _real_fpu_disabled + +fline_fmovcr: + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 + + fmov.l 0x2(%sp),%fpiar # set current PC + addq.l &0x4,0x2(%sp) # set Next PC + + mov.l (%sp),-(%sp) + mov.l 0x8(%sp),0x4(%sp) + mov.b &0x20,0x6(%sp) + + bra.l _fpsp_unimp + +fline_fline: + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 + + bra.l _real_fline + +######################################################################### +# XDEF **************************************************************** # +# _fpsp_unimp(): 060FPSP entry point for FP "Unimplemented # +# Instruction" exception. # +# # +# This handler should be the first code executed upon taking the # +# FP Unimplemented Instruction exception in an operating system. # +# # +# XREF **************************************************************** # +# _imem_read_{word,long}() - read instruction word/longword # +# load_fop() - load src/dst ops from memory and/or FP regfile # +# store_fpreg() - store opclass 0 or 2 result to FP regfile # +# tbl_trans - addr of table of emulation routines for trnscndls # +# _real_access() - "callout" for access error exception # +# _fpsp_done() - "callout" for exit; work all done # +# _real_trace() - "callout" for Trace enabled exception # +# smovcr() - emulate "fmovecr" instruction # +# funimp_skew() - adjust fsave src ops to "incorrect" value # +# _ftrapcc() - emulate an "ftrapcc" instruction # +# _fdbcc() - emulate an "fdbcc" instruction # +# _fscc() - emulate an "fscc" instruction # +# _real_trap() - "callout" for Trap exception # +# _real_bsun() - "callout" for enabled Bsun exception # +# # +# INPUT *************************************************************** # +# - The system stack contains the "Unimplemented Instr" stk frame # +# # +# OUTPUT ************************************************************** # +# If access error: # +# - The system stack is changed to an access error stack frame # +# If Trace exception enabled: # +# - The system stack is changed to a Trace exception stack frame # +# Else: (normal case) # +# - Correct result has been stored as appropriate # +# # +# ALGORITHM *********************************************************** # +# There are two main cases of instructions that may enter here to # +# be emulated: (1) the FPgen instructions, most of which were also # +# unimplemented on the 040, and (2) "ftrapcc", "fscc", and "fdbcc". # +# For the first set, this handler calls the routine load_fop() # +# to load the source and destination (for dyadic) operands to be used # +# for instruction emulation. The correct emulation routine is then # +# chosen by decoding the instruction type and indexing into an # +# emulation subroutine index table. After emulation returns, this # +# handler checks to see if an exception should occur as a result of the # +# FP instruction emulation. If so, then an FP exception of the correct # +# type is inserted into the FPU state frame using the "frestore" # +# instruction before exiting through _fpsp_done(). In either the # +# exceptional or non-exceptional cases, we must check to see if the # +# Trace exception is enabled. If so, then we must create a Trace # +# exception frame from the current exception frame and exit through # +# _real_trace(). # +# For "fdbcc", "ftrapcc", and "fscc", the emulation subroutines # +# _fdbcc(), _ftrapcc(), and _fscc() respectively are used. All three # +# may flag that a BSUN exception should be taken. If so, then the # +# current exception stack frame is converted into a BSUN exception # +# stack frame and an exit is made through _real_bsun(). If the # +# instruction was "ftrapcc" and a Trap exception should result, a Trap # +# exception stack frame is created from the current frame and an exit # +# is made through _real_trap(). If a Trace exception is pending, then # +# a Trace exception frame is created from the current frame and a jump # +# is made to _real_trace(). Finally, if none of these conditions exist, # +# then the handler exits though the callout _fpsp_done(). # +# # +# In any of the above scenarios, if a _mem_read() or _mem_write() # +# "callout" returns a failing value, then an access error stack frame # +# is created from the current stack frame and an exit is made through # +# _real_access(). # +# # +######################################################################### + +# +# FP UNIMPLEMENTED INSTRUCTION STACK FRAME: +# +# ***************** +# * * => of fp unimp instr. +# - EA - +# * * +# ***************** +# * 0x2 * 0x02c * => frame format and vector offset(vector #11) +# ***************** +# * * +# - Next PC - => PC of instr to execute after exc handling +# * * +# ***************** +# * SR * => SR at the time the exception was taken +# ***************** +# +# Note: the !NULL bit does not get set in the fsave frame when the +# machine encounters an fp unimp exception. Therefore, it must be set +# before leaving this handler. +# + global _fpsp_unimp +_fpsp_unimp: + + link.w %a6,&-LOCAL_SIZE # init stack frame + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 + + btst &0x5,EXC_SR(%a6) # user mode exception? + bne.b funimp_s # no; supervisor mode + +# save the value of the user stack pointer onto the stack frame +funimp_u: + mov.l %usp,%a0 # fetch user stack pointer + mov.l %a0,EXC_A7(%a6) # store in stack frame + bra.b funimp_cont + +# store the value of the supervisor stack pointer BEFORE the exc occurred. +# old_sp is address just above stacked effective address. +funimp_s: + lea 4+EXC_EA(%a6),%a0 # load old a7' + mov.l %a0,EXC_A7(%a6) # store a7' + mov.l %a0,OLD_A7(%a6) # make a copy + +funimp_cont: + +# the FPIAR holds the "current PC" of the faulting instruction. + mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) + + mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr + addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr + bsr.l _imem_read_long # fetch the instruction words + mov.l %d0,EXC_OPWORD(%a6) + +############################################################################ + + fmov.l &0x0,%fpcr # clear FPCR + fmov.l &0x0,%fpsr # clear FPSR + + clr.b SPCOND_FLG(%a6) # clear "special case" flag + +# Divide the fp instructions into 8 types based on the TYPE field in +# bits 6-8 of the opword(classes 6,7 are undefined). +# (for the '060, only two types can take this exception) +# bftst %d0{&7:&3} # test TYPE + btst &22,%d0 # type 0 or 1 ? + bne.w funimp_misc # type 1 + +######################################### +# TYPE == 0: General instructions # +######################################### +funimp_gen: + + clr.b STORE_FLG(%a6) # clear "store result" flag + +# clear the ccode byte and exception status byte + andi.l &0x00ff00ff,USER_FPSR(%a6) + + bfextu %d0{&16:&6},%d1 # extract upper 6 of cmdreg + cmpi.b %d1,&0x17 # is op an fmovecr? + beq.w funimp_fmovcr # yes + +funimp_gen_op: + bsr.l _load_fop # load + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode + + mov.b 1+EXC_CMDREG(%a6),%d1 + andi.w &0x003f,%d1 # extract extension bits + lsl.w &0x3,%d1 # shift right 3 bits + or.b STAG(%a6),%d1 # insert src optag bits + + lea FP_DST(%a6),%a1 # pass dst ptr in a1 + lea FP_SRC(%a6),%a0 # pass src ptr in a0 + + mov.w (tbl_trans.w,%pc,%d1.w*2),%d1 + jsr (tbl_trans.w,%pc,%d1.w*1) # emulate + +funimp_fsave: + mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled + bne.w funimp_ena # some are enabled + +funimp_store: + bfextu EXC_CMDREG(%a6){&6:&3},%d0 # fetch Dn + bsr.l store_fpreg # store result to fp regfile + +funimp_gen_exit: + fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + +funimp_gen_exit_cmp: + cmpi.b SPCOND_FLG(%a6),&mia7_flg # was the ea mode (sp)+ ? + beq.b funimp_gen_exit_a7 # yes + + cmpi.b SPCOND_FLG(%a6),&mda7_flg # was the ea mode -(sp) ? + beq.b funimp_gen_exit_a7 # yes + +funimp_gen_exit_cont: + unlk %a6 + +funimp_gen_exit_cont2: + btst &0x7,(%sp) # is trace on? + beq.l _fpsp_done # no + +# this catches a problem with the case where an exception will be re-inserted +# into the machine. the frestore has already been executed...so, the fmov.l +# alone of the control register would trigger an unwanted exception. +# until I feel like fixing this, we'll sidestep the exception. + fsave -(%sp) + fmov.l %fpiar,0x14(%sp) # "Current PC" is in FPIAR + frestore (%sp)+ + mov.w &0x2024,0x6(%sp) # stk fmt = 0x2; voff = 0x24 + bra.l _real_trace + +funimp_gen_exit_a7: + btst &0x5,EXC_SR(%a6) # supervisor or user mode? + bne.b funimp_gen_exit_a7_s # supervisor + + mov.l %a0,-(%sp) + mov.l EXC_A7(%a6),%a0 + mov.l %a0,%usp + mov.l (%sp)+,%a0 + bra.b funimp_gen_exit_cont + +# if the instruction was executed from supervisor mode and the addressing +# mode was (a7)+, then the stack frame for the rte must be shifted "up" +# "n" bytes where "n" is the size of the src operand type. +# f.{b,w,l,s,d,x,p} +funimp_gen_exit_a7_s: + mov.l %d0,-(%sp) # save d0 + mov.l EXC_A7(%a6),%d0 # load new a7' + sub.l OLD_A7(%a6),%d0 # subtract old a7' + mov.l 0x2+EXC_PC(%a6),(0x2+EXC_PC,%a6,%d0) # shift stack frame + mov.l EXC_SR(%a6),(EXC_SR,%a6,%d0) # shift stack frame + mov.w %d0,EXC_SR(%a6) # store incr number + mov.l (%sp)+,%d0 # restore d0 + + unlk %a6 + + add.w (%sp),%sp # stack frame shifted + bra.b funimp_gen_exit_cont2 + +###################### +# fmovecr.x #ccc,fpn # +###################### +funimp_fmovcr: + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 + mov.b 1+EXC_CMDREG(%a6),%d1 + andi.l &0x0000007f,%d1 # pass rom offset in d1 + bsr.l smovcr + bra.w funimp_fsave + +######################################################################### + +# +# the user has enabled some exceptions. we figure not to see this too +# often so that's why it gets lower priority. +# +funimp_ena: + +# was an exception set that was also enabled? + and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled and set + bfffo %d0{&24:&8},%d0 # find highest priority exception + bne.b funimp_exc # at least one was set + +# no exception that was enabled was set BUT if we got an exact overflow +# and overflow wasn't enabled but inexact was (yech!) then this is +# an inexact exception; otherwise, return to normal non-exception flow. + btst &ovfl_bit,FPSR_EXCEPT(%a6) # did overflow occur? + beq.w funimp_store # no; return to normal flow + +# the overflow w/ exact result happened but was inexact set in the FPCR? +funimp_ovfl: + btst &inex2_bit,FPCR_ENABLE(%a6) # is inexact enabled? + beq.w funimp_store # no; return to normal flow + bra.b funimp_exc_ovfl # yes + +# some exception happened that was actually enabled. +# we'll insert this new exception into the FPU and then return. +funimp_exc: + subi.l &24,%d0 # fix offset to be 0-8 + cmpi.b %d0,&0x6 # is exception INEX? + bne.b funimp_exc_force # no + +# the enabled exception was inexact. so, if it occurs with an overflow +# or underflow that was disabled, then we have to force an overflow or +# underflow frame. the eventual overflow or underflow handler will see that +# it's actually an inexact and act appropriately. this is the only easy +# way to have the EXOP available for the enabled inexact handler when +# a disabled overflow or underflow has also happened. + btst &ovfl_bit,FPSR_EXCEPT(%a6) # did overflow occur? + bne.b funimp_exc_ovfl # yes + btst &unfl_bit,FPSR_EXCEPT(%a6) # did underflow occur? + bne.b funimp_exc_unfl # yes + +# force the fsave exception status bits to signal an exception of the +# appropriate type. don't forget to "skew" the source operand in case we +# "unskewed" the one the hardware initially gave us. +funimp_exc_force: + mov.l %d0,-(%sp) # save d0 + bsr.l funimp_skew # check for special case + mov.l (%sp)+,%d0 # restore d0 + mov.w (tbl_funimp_except.b,%pc,%d0.w*2),2+FP_SRC(%a6) + bra.b funimp_gen_exit2 # exit with frestore + +tbl_funimp_except: + short 0xe002, 0xe006, 0xe004, 0xe005 + short 0xe003, 0xe002, 0xe001, 0xe001 + +# insert an overflow frame +funimp_exc_ovfl: + bsr.l funimp_skew # check for special case + mov.w &0xe005,2+FP_SRC(%a6) + bra.b funimp_gen_exit2 + +# insert an underflow frame +funimp_exc_unfl: + bsr.l funimp_skew # check for special case + mov.w &0xe003,2+FP_SRC(%a6) + +# this is the general exit point for an enabled exception that will be +# restored into the machine for the instruction just emulated. +funimp_gen_exit2: + fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + frestore FP_SRC(%a6) # insert exceptional status + + bra.w funimp_gen_exit_cmp + +############################################################################ + +# +# TYPE == 1: FDB, FS, FTRAP +# +# These instructions were implemented on the '881/2 and '040 in hardware but +# are emulated in software on the '060. +# +funimp_misc: + bfextu %d0{&10:&3},%d1 # extract mode field + cmpi.b %d1,&0x1 # is it an fdb? + beq.w funimp_fdbcc # yes + cmpi.b %d1,&0x7 # is it an fs? + bne.w funimp_fscc # yes + bfextu %d0{&13:&3},%d1 + cmpi.b %d1,&0x2 # is it an fs? + blt.w funimp_fscc # yes + +######################### +# ftrap # +# ftrap.w # # +# ftrap.l # # +######################### +funimp_ftrapcc: + + bsr.l _ftrapcc # FTRAP() + + cmpi.b SPCOND_FLG(%a6),&fbsun_flg # is enabled bsun occurring? + beq.w funimp_bsun # yes + + cmpi.b SPCOND_FLG(%a6),&ftrapcc_flg # should a trap occur? + bne.w funimp_done # no + +# FP UNIMP FRAME TRAP FRAME +# ***************** ***************** +# ** ** ** Current PC ** +# ***************** ***************** +# * 0x2 * 0x02c * * 0x2 * 0x01c * +# ***************** ***************** +# ** Next PC ** ** Next PC ** +# ***************** ***************** +# * SR * * SR * +# ***************** ***************** +# (6 words) (6 words) +# +# the ftrapcc instruction should take a trap. so, here we must create a +# trap stack frame from an unimplemented fp instruction stack frame and +# jump to the user supplied entry point for the trap exception +funimp_ftrapcc_tp: + mov.l USER_FPIAR(%a6),EXC_EA(%a6) # Address = Current PC + mov.w &0x201c,EXC_VOFF(%a6) # Vector Offset = 0x01c + + fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 + bra.l _real_trap + +######################### +# fdb Dn,