1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
|
// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP
*
* (C) Copyright 2014 - 2015, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
/ {
compatible = "xlnx,zynqmp";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
enable-method = "psci";
operating-points-v2 = <&cpu_opp_table>;
reg = <0x0>;
cpu-idle-states = <&CPU_SLEEP_0>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
enable-method = "psci";
reg = <0x1>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
enable-method = "psci";
reg = <0x2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
enable-method = "psci";
reg = <0x3>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
};
idle-states {
entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x40000000>;
local-timer-stop;
entry-latency-us = <300>;
exit-latency-us = <600>;
min-residency-us = <10000>;
};
};
};
cpu_opp_table: cpu-opp-table {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <1199999988>;
opp-microvolt = <1000000>;
clock-latency-ns = <500000>;
};
opp01 {
opp-hz = /bits/ 64 <599999994>;
opp-microvolt = <1000000>;
clock-latency-ns = <500000>;
};
opp02 {
opp-hz = /bits/ 64 <399999996>;
opp-microvolt = <1000000>;
clock-latency-ns = <500000>;
};
opp03 {
opp-hz = /bits/ 64 <299999997>;
opp-microvolt = <1000000>;
clock-latency-ns = <500000>;
};
};
dcc: dcc {
compatible = "arm,dcc";
status = "disabled";
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupt-parent = <&gic>;
interrupts = <0 143 4>,
<0 144 4>,
<0 145 4>,
<0 146 4>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>,
<1 10 0xf08>;
};
amba_apu: amba-apu@0 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0 0 0xffffffff>;
gic: interrupt-controller@f9010000 {
compatible = "arm,gic-400", "arm,cortex-a15-gic";
#interrupt-cells = <3>;
reg = <0x0 0xf9010000 0x10000>,
<0x0 0xf9020000 0x20000>,
<0x0 0xf9040000 0x20000>,
<0x0 0xf9060000 0x20000>;
interrupt-controller;
interrupt-parent = <&gic>;
interrupts = <1 9 0xf04>;
};
};
amba: amba {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
can0: can@ff060000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clock-names = "can_clk", "pclk";
reg = <0x0 0xff060000 0x0 0x1000>;
interrupts = <0 23 4>;
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
can1: can@ff070000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clock-names = "can_clk", "pclk";
reg = <0x0 0xff070000 0x0 0x1000>;
interrupts = <0 24 4>;
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
cci: cci@fd6e0000 {
compatible = "arm,cci-400";
reg = <0x0 0xfd6e0000 0x0 0x9000>;
ranges = <0x0 0x0 0xfd6e0000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
pmu@9000 {
compatible = "arm,cci-400-pmu,r1";
reg = <0x9000 0x5000>;
interrupt-parent = <&gic>;
interrupts = <0 123 4>,
<0 123 4>,
<0 123 4>,
<0 123 4>,
<0 123 4>;
};
};
/* GDMA */
fpd_dma_chan1: dma@fd500000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd500000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 124 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
};
fpd_dma_chan2: dma@fd510000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd510000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 125 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
};
fpd_dma_chan3: dma@fd520000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd520000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 126 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
};
fpd_dma_chan4: dma@fd530000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd530000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 127 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
};
fpd_dma_chan5: dma@fd540000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd540000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 128 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
};
fpd_dma_chan6: dma@fd550000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd550000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 129 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
};
fpd_dma_chan7: dma@fd560000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd560000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 130 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
};
fpd_dma_chan8: dma@fd570000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd570000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 131 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
};
/* LPDDMA default allows only secured access. inorder to enable
* These dma channels, Users should ensure that these dma
* Channels are allowed for non secure access.
*/
lpd_dma_chan1: dma@ffa80000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffa80000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 77 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
};
lpd_dma_chan2: dma@ffa90000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffa90000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 78 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
};
lpd_dma_chan3: dma@ffaa0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffaa0000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 79 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
};
lpd_dma_chan4: dma@ffab0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffab0000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 80 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
};
lpd_dma_chan5: dma@ffac0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffac0000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 81 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
};
lpd_dma_chan6: dma@ffad0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffad0000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 82 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
};
lpd_dma_chan7: dma@ffae0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffae0000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 83 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
};
lpd_dma_chan8: dma@ffaf0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffaf0000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 84 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
};
gem0: ethernet@ff0b0000 {
compatible = "cdns,zynqmp-gem", "cdns,gem";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 57 4>, <0 57 4>;
reg = <0x0 0xff0b0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
};
gem1: ethernet@ff0c0000 {
compatible = "cdns,zynqmp-gem", "cdns,gem";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 59 4>, <0 59 4>;
reg = <0x0 0xff0c0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
};
gem2: ethernet@ff0d0000 {
compatible = "cdns,zynqmp-gem", "cdns,gem";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 61 4>, <0 61 4>;
reg = <0x0 0xff0d0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
};
gem3: ethernet@ff0e0000 {
compatible = "cdns,zynqmp-gem", "cdns,gem";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 63 4>, <0 63 4>;
reg = <0x0 0xff0e0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
};
gpio: gpio@ff0a0000 {
compatible = "xlnx,zynqmp-gpio-1.0";
status = "disabled";
#gpio-cells = <0x2>;
interrupt-parent = <&gic>;
interrupts = <0 16 4>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0xff0a0000 0x0 0x1000>;
};
i2c0: i2c@ff020000 {
compatible = "cdns,i2c-r1p14";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 17 4>;
reg = <0x0 0xff020000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c1: i2c@ff030000 {
compatible = "cdns,i2c-r1p14";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 18 4>;
reg = <0x0 0xff030000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
};
pcie: pcie@fd0e0000 {
compatible = "xlnx,nwl-pcie-2.11";
status = "disabled";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
msi-controller;
device_type = "pci";
interrupt-parent = <&gic>;
interrupts = <0 118 4>,
<0 117 4>,
<0 116 4>,
<0 115 4>, /* MSI_1 [63...32] */
<0 114 4>; /* MSI_0 [31...0] */
interrupt-names = "misc", "dummy", "intx",
"msi1", "msi0";
msi-parent = <&pcie>;
reg = <0x0 0xfd0e0000 0x0 0x1000>,
<0x0 0xfd480000 0x0 0x1000>,
<0x80 0x00000000 0x0 0x1000000>;
reg-names = "breg", "pcireg", "cfg";
ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
bus-range = <0x00 0xff>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
pcie_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
rtc: rtc@ffa60000 {
compatible = "xlnx,zynqmp-rtc";
status = "disabled";
reg = <0x0 0xffa60000 0x0 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 26 4>, <0 27 4>;
interrupt-names = "alarm", "sec";
calibration = <0x8000>;
};
sata: ahci@fd0c0000 {
compatible = "ceva,ahci-1v84";
status = "disabled";
reg = <0x0 0xfd0c0000 0x0 0x2000>;
interrupt-parent = <&gic>;
interrupts = <0 133 4>;
};
sdhci0: sdhci@ff160000 {
compatible = "arasan,sdhci-8.9a";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 48 4>;
reg = <0x0 0xff160000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
};
sdhci1: sdhci@ff170000 {
compatible = "arasan,sdhci-8.9a";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 49 4>;
reg = <0x0 0xff170000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
};
smmu: smmu@fd800000 {
compatible = "arm,mmu-500";
reg = <0x0 0xfd800000 0x0 0x20000>;
status = "disabled";
#global-interrupts = <1>;
interrupt-parent = <&gic>;
interrupts = <0 155 4>,
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
};
spi0: spi@ff040000 {
compatible = "cdns,spi-r1p6";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 19 4>;
reg = <0x0 0xff040000 0x0 0x1000>;
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
};
spi1: spi@ff050000 {
compatible = "cdns,spi-r1p6";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 20 4>;
reg = <0x0 0xff050000 0x0 0x1000>;
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
};
ttc0: timer@ff110000 {
compatible = "cdns,ttc";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
reg = <0x0 0xff110000 0x0 0x1000>;
timer-width = <32>;
};
ttc1: timer@ff120000 {
compatible = "cdns,ttc";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
reg = <0x0 0xff120000 0x0 0x1000>;
timer-width = <32>;
};
ttc2: timer@ff130000 {
compatible = "cdns,ttc";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
reg = <0x0 0xff130000 0x0 0x1000>;
timer-width = <32>;
};
ttc3: timer@ff140000 {
compatible = "cdns,ttc";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
reg = <0x0 0xff140000 0x0 0x1000>;
timer-width = <32>;
};
uart0: serial@ff000000 {
compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 21 4>;
reg = <0x0 0xff000000 0x0 0x1000>;
clock-names = "uart_clk", "pclk";
};
uart1: serial@ff010000 {
compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 22 4>;
reg = <0x0 0xff010000 0x0 0x1000>;
clock-names = "uart_clk", "pclk";
};
usb0: usb@fe200000 {
compatible = "snps,dwc3";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 65 4>;
reg = <0x0 0xfe200000 0x0 0x40000>;
clock-names = "clk_xin", "clk_ahb";
};
usb1: usb@fe300000 {
compatible = "snps,dwc3";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 70 4>;
reg = <0x0 0xfe300000 0x0 0x40000>;
clock-names = "clk_xin", "clk_ahb";
};
watchdog0: watchdog@fd4d0000 {
compatible = "cdns,wdt-r1p2";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 113 1>;
reg = <0x0 0xfd4d0000 0x0 0x1000>;
timeout-sec = <10>;
};
};
};
|
