From f8fe689a81f906d1b91bb3220acde2a4ecb14c5b Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Mon, 6 May 2024 05:01:46 +0200 Subject: Adding upstream version 6.0.4-dfsg. Signed-off-by: Daniel Baumann --- .../testcase/Instructions/InstructionTestGen.py | 2239 +++++++++++++ src/VBox/VMM/testcase/Instructions/Makefile.kmk | 69 + .../testcase/Instructions/env-bs2-r0-32-big.mac | 35 + .../testcase/Instructions/env-bs2-r0-64-big.mac | 35 + .../VMM/testcase/Instructions/env-bs2-r0-64.mac | 35 + .../VMM/testcase/Instructions/env-bs2-r0-big.mac | 57 + .../testcase/Instructions/env-bs2-r0-common.mac | 115 + src/VBox/VMM/testcase/Instructions/env-bs2-r0.mac | 53 + src/VBox/VMM/testcase/Instructions/env-common.mac | 346 ++ .../VMM/testcase/Instructions/env-iprt-r3-32.mac | 19 + .../VMM/testcase/Instructions/env-iprt-r3-64.mac | 19 + src/VBox/VMM/testcase/Instructions/env-iprt-r3.mac | 99 + src/VBox/VMM/testcase/Instructions/itgTableDaa.py | 1105 +++++++ src/VBox/VMM/testcase/Instructions/itgTableDas.py | 1105 +++++++ .../VMM/testcase/Instructions/tstVBInsTstR3.cpp | 120 + src/VBox/VMM/testcase/Makefile.kmk | 654 ++++ src/VBox/VMM/testcase/NemRawBench-1.cpp | 1346 ++++++++ src/VBox/VMM/testcase/dev.tar.gz | Bin 0 -> 732 bytes src/VBox/VMM/testcase/mkdsk.sh | 76 + src/VBox/VMM/testcase/tstAnimate.cpp | 950 ++++++ src/VBox/VMM/testcase/tstAsmStructs.cpp | 57 + src/VBox/VMM/testcase/tstAsmStructsAsm-lst.sed | 105 + src/VBox/VMM/testcase/tstAsmStructsAsm.asm | 41 + src/VBox/VMM/testcase/tstCFGM.cpp | 171 + src/VBox/VMM/testcase/tstCompressionBenchmark.cpp | 642 ++++ src/VBox/VMM/testcase/tstGlobalConfig.cpp | 138 + src/VBox/VMM/testcase/tstHelp.h | 169 + src/VBox/VMM/testcase/tstIEMCheckMc.cpp | 769 +++++ src/VBox/VMM/testcase/tstMMHyperHeap.cpp | 268 ++ src/VBox/VMM/testcase/tstMicro.cpp | 404 +++ src/VBox/VMM/testcase/tstMicro.h | 146 + src/VBox/VMM/testcase/tstMicro.mac | 40 + src/VBox/VMM/testcase/tstMicroRC.cpp | 258 ++ src/VBox/VMM/testcase/tstMicroRC.def | 28 + src/VBox/VMM/testcase/tstMicroRCA.asm | 558 ++++ src/VBox/VMM/testcase/tstPDMAsyncCompletion.cpp | 274 ++ .../VMM/testcase/tstPDMAsyncCompletionStress.cpp | 648 ++++ src/VBox/VMM/testcase/tstSSM-2.cpp | 81 + src/VBox/VMM/testcase/tstSSM.cpp | 950 ++++++ src/VBox/VMM/testcase/tstVMM-HM.cpp | 121 + src/VBox/VMM/testcase/tstVMM.cpp | 390 +++ src/VBox/VMM/testcase/tstVMMFork.cpp | 170 + src/VBox/VMM/testcase/tstVMMR0CallHost-1.cpp | 181 + src/VBox/VMM/testcase/tstVMREQ.cpp | 339 ++ src/VBox/VMM/testcase/tstVMStruct.h | 1520 +++++++++ src/VBox/VMM/testcase/tstVMStructDTrace.cpp | 146 + src/VBox/VMM/testcase/tstVMStructRC.cpp | 103 + src/VBox/VMM/testcase/tstVMStructSize.cpp | 568 ++++ src/VBox/VMM/testcase/tstX86-1.cpp | 270 ++ src/VBox/VMM/testcase/tstX86-1A.asm | 3443 ++++++++++++++++++++ src/VBox/VMM/testcase/tstX86-FpuSaveRestore.cpp | 116 + src/VBox/VMM/testcase/tstX86-FpuSaveRestoreA.asm | 117 + 52 files changed, 21708 insertions(+) create mode 100755 src/VBox/VMM/testcase/Instructions/InstructionTestGen.py create mode 100644 src/VBox/VMM/testcase/Instructions/Makefile.kmk create mode 100644 src/VBox/VMM/testcase/Instructions/env-bs2-r0-32-big.mac create mode 100644 src/VBox/VMM/testcase/Instructions/env-bs2-r0-64-big.mac create mode 100644 src/VBox/VMM/testcase/Instructions/env-bs2-r0-64.mac create mode 100644 src/VBox/VMM/testcase/Instructions/env-bs2-r0-big.mac create mode 100644 src/VBox/VMM/testcase/Instructions/env-bs2-r0-common.mac create mode 100644 src/VBox/VMM/testcase/Instructions/env-bs2-r0.mac create mode 100644 src/VBox/VMM/testcase/Instructions/env-common.mac create mode 100644 src/VBox/VMM/testcase/Instructions/env-iprt-r3-32.mac create mode 100644 src/VBox/VMM/testcase/Instructions/env-iprt-r3-64.mac create mode 100644 src/VBox/VMM/testcase/Instructions/env-iprt-r3.mac create mode 100644 src/VBox/VMM/testcase/Instructions/itgTableDaa.py create mode 100644 src/VBox/VMM/testcase/Instructions/itgTableDas.py create mode 100644 src/VBox/VMM/testcase/Instructions/tstVBInsTstR3.cpp create mode 100644 src/VBox/VMM/testcase/Makefile.kmk create mode 100644 src/VBox/VMM/testcase/NemRawBench-1.cpp create mode 100644 src/VBox/VMM/testcase/dev.tar.gz create mode 100755 src/VBox/VMM/testcase/mkdsk.sh create mode 100644 src/VBox/VMM/testcase/tstAnimate.cpp create mode 100644 src/VBox/VMM/testcase/tstAsmStructs.cpp create mode 100644 src/VBox/VMM/testcase/tstAsmStructsAsm-lst.sed create mode 100644 src/VBox/VMM/testcase/tstAsmStructsAsm.asm create mode 100644 src/VBox/VMM/testcase/tstCFGM.cpp create mode 100644 src/VBox/VMM/testcase/tstCompressionBenchmark.cpp create mode 100644 src/VBox/VMM/testcase/tstGlobalConfig.cpp create mode 100644 src/VBox/VMM/testcase/tstHelp.h create mode 100644 src/VBox/VMM/testcase/tstIEMCheckMc.cpp create mode 100644 src/VBox/VMM/testcase/tstMMHyperHeap.cpp create mode 100644 src/VBox/VMM/testcase/tstMicro.cpp create mode 100644 src/VBox/VMM/testcase/tstMicro.h create mode 100644 src/VBox/VMM/testcase/tstMicro.mac create mode 100644 src/VBox/VMM/testcase/tstMicroRC.cpp create mode 100644 src/VBox/VMM/testcase/tstMicroRC.def create mode 100644 src/VBox/VMM/testcase/tstMicroRCA.asm create mode 100644 src/VBox/VMM/testcase/tstPDMAsyncCompletion.cpp create mode 100644 src/VBox/VMM/testcase/tstPDMAsyncCompletionStress.cpp create mode 100644 src/VBox/VMM/testcase/tstSSM-2.cpp create mode 100644 src/VBox/VMM/testcase/tstSSM.cpp create mode 100644 src/VBox/VMM/testcase/tstVMM-HM.cpp create mode 100644 src/VBox/VMM/testcase/tstVMM.cpp create mode 100644 src/VBox/VMM/testcase/tstVMMFork.cpp create mode 100644 src/VBox/VMM/testcase/tstVMMR0CallHost-1.cpp create mode 100644 src/VBox/VMM/testcase/tstVMREQ.cpp create mode 100644 src/VBox/VMM/testcase/tstVMStruct.h create mode 100644 src/VBox/VMM/testcase/tstVMStructDTrace.cpp create mode 100644 src/VBox/VMM/testcase/tstVMStructRC.cpp create mode 100644 src/VBox/VMM/testcase/tstVMStructSize.cpp create mode 100644 src/VBox/VMM/testcase/tstX86-1.cpp create mode 100644 src/VBox/VMM/testcase/tstX86-1A.asm create mode 100644 src/VBox/VMM/testcase/tstX86-FpuSaveRestore.cpp create mode 100644 src/VBox/VMM/testcase/tstX86-FpuSaveRestoreA.asm (limited to 'src/VBox/VMM/testcase') diff --git a/src/VBox/VMM/testcase/Instructions/InstructionTestGen.py b/src/VBox/VMM/testcase/Instructions/InstructionTestGen.py new file mode 100755 index 00000000..903c86e5 --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/InstructionTestGen.py @@ -0,0 +1,2239 @@ +#!/usr/bin/env python +# -*- coding: utf-8 -*- +# $Id: InstructionTestGen.py $ + +""" +Instruction Test Generator. +""" + +from __future__ import print_function; + +__copyright__ = \ +""" +Copyright (C) 2012-2019 Oracle Corporation + +This file is part of VirtualBox Open Source Edition (OSE), as +available from http://www.virtualbox.org. This file is free software; +you can redistribute it and/or modify it under the terms of the GNU +General Public License (GPL) as published by the Free Software +Foundation, in version 2 as it comes in the "COPYING" file of the +VirtualBox OSE distribution. VirtualBox OSE is distributed in the +hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +""" +__version__ = "$Revision: 127855 $"; + + +# pylint: disable=C0103,R0913 + + +# Standard python imports. +import io; +import os; +from optparse import OptionParser +import random; +import sys; + + +## @name Exit codes +## @{ +RTEXITCODE_SUCCESS = 0; +RTEXITCODE_SYNTAX = 2; +## @} + +## @name Various C macros we're used to. +## @{ +UINT8_MAX = 0xff +UINT16_MAX = 0xffff +UINT32_MAX = 0xffffffff +UINT64_MAX = 0xffffffffffffffff +def RT_BIT_32(iBit): # pylint: disable=C0103 + """ 32-bit one bit mask. """ + return 1 << iBit; +def RT_BIT_64(iBit): # pylint: disable=C0103 + """ 64-bit one bit mask. """ + return 1 << iBit; +## @} + + +## @name ModR/M +## @{ +X86_MODRM_RM_MASK = 0x07; +X86_MODRM_REG_MASK = 0x38; +X86_MODRM_REG_SMASK = 0x07; +X86_MODRM_REG_SHIFT = 3; +X86_MODRM_MOD_MASK = 0xc0; +X86_MODRM_MOD_SMASK = 0x03; +X86_MODRM_MOD_SHIFT = 6; +## @} + +## @name SIB +## @{ +X86_SIB_BASE_MASK = 0x07; +X86_SIB_INDEX_MASK = 0x38; +X86_SIB_INDEX_SMASK = 0x07; +X86_SIB_INDEX_SHIFT = 3; +X86_SIB_SCALE_MASK = 0xc0; +X86_SIB_SCALE_SMASK = 0x03; +X86_SIB_SCALE_SHIFT = 6; +## @} + +## @name Prefixes +## @ +X86_OP_PRF_CS = 0x2e; +X86_OP_PRF_SS = 0x36; +X86_OP_PRF_DS = 0x3e; +X86_OP_PRF_ES = 0x26; +X86_OP_PRF_FS = 0x64; +X86_OP_PRF_GS = 0x65; +X86_OP_PRF_SIZE_OP = 0x66; +X86_OP_PRF_SIZE_ADDR = 0x67; +X86_OP_PRF_LOCK = 0xf0; +X86_OP_PRF_REPNZ = 0xf2; +X86_OP_PRF_REPZ = 0xf3; +X86_OP_REX_B = 0x41; +X86_OP_REX_X = 0x42; +X86_OP_REX_R = 0x44; +X86_OP_REX_W = 0x48; +## @} + + +## @name General registers +## @ +X86_GREG_xAX = 0 +X86_GREG_xCX = 1 +X86_GREG_xDX = 2 +X86_GREG_xBX = 3 +X86_GREG_xSP = 4 +X86_GREG_xBP = 5 +X86_GREG_xSI = 6 +X86_GREG_xDI = 7 +X86_GREG_x8 = 8 +X86_GREG_x9 = 9 +X86_GREG_x10 = 10 +X86_GREG_x11 = 11 +X86_GREG_x12 = 12 +X86_GREG_x13 = 13 +X86_GREG_x14 = 14 +X86_GREG_x15 = 15 +## @} + + +## @name Register names. +## @{ +g_asGRegs64NoSp = ('rax', 'rcx', 'rdx', 'rbx', None, 'rbp', 'rsi', 'rdi', 'r8', 'r9', 'r10', 'r11', 'r12', 'r13', 'r14', 'r15'); +g_asGRegs64 = ('rax', 'rcx', 'rdx', 'rbx', 'rsp', 'rbp', 'rsi', 'rdi', 'r8', 'r9', 'r10', 'r11', 'r12', 'r13', 'r14', 'r15'); +g_asGRegs32NoSp = ('eax', 'ecx', 'edx', 'ebx', None, 'ebp', 'esi', 'edi', + 'r8d', 'r9d', 'r10d', 'r11d', 'r12d', 'r13d', 'r14d', 'r15d'); +g_asGRegs32 = ('eax', 'ecx', 'edx', 'ebx', 'esp', 'ebp', 'esi', 'edi', + 'r8d', 'r9d', 'r10d', 'r11d', 'r12d', 'r13d', 'r14d', 'r15d'); +g_asGRegs16NoSp = ('ax', 'cx', 'dx', 'bx', None, 'bp', 'si', 'di', + 'r8w', 'r9w', 'r10w', 'r11w', 'r12w', 'r13w', 'r14w', 'r15w'); +g_asGRegs16 = ('ax', 'cx', 'dx', 'bx', 'sp', 'bp', 'si', 'di', + 'r8w', 'r9w', 'r10w', 'r11w', 'r12w', 'r13w', 'r14w', 'r15w'); +g_asGRegs8 = ('al', 'cl', 'dl', 'bl', 'ah', 'ch', 'dh', 'bh'); +g_asGRegs8Rex = ('al', 'cl', 'dl', 'bl', 'spl', 'bpl', 'sil', 'dil', + 'r8b', 'r9b', 'r10b', 'r11b', 'r12b', 'r13b', 'r14b', 'r15b', + 'ah', 'ch', 'dh', 'bh'); +## @} + +## @name EFLAGS/RFLAGS/EFLAGS +## @{ +X86_EFL_CF = RT_BIT_32(0); +X86_EFL_CF_BIT = 0; +X86_EFL_1 = RT_BIT_32(1); +X86_EFL_PF = RT_BIT_32(2); +X86_EFL_AF = RT_BIT_32(4); +X86_EFL_AF_BIT = 4; +X86_EFL_ZF = RT_BIT_32(6); +X86_EFL_ZF_BIT = 6; +X86_EFL_SF = RT_BIT_32(7); +X86_EFL_SF_BIT = 7; +X86_EFL_TF = RT_BIT_32(8); +X86_EFL_IF = RT_BIT_32(9); +X86_EFL_DF = RT_BIT_32(10); +X86_EFL_OF = RT_BIT_32(11); +X86_EFL_OF_BIT = 11; +X86_EFL_IOPL = (RT_BIT_32(12) | RT_BIT_32(13)); +X86_EFL_NT = RT_BIT_32(14); +X86_EFL_RF = RT_BIT_32(16); +X86_EFL_VM = RT_BIT_32(17); +X86_EFL_AC = RT_BIT_32(18); +X86_EFL_VIF = RT_BIT_32(19); +X86_EFL_VIP = RT_BIT_32(20); +X86_EFL_ID = RT_BIT_32(21); +X86_EFL_LIVE_MASK = 0x003f7fd5; +X86_EFL_RA1_MASK = RT_BIT_32(1); +X86_EFL_IOPL_SHIFT = 12; +X86_EFL_STATUS_BITS = ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF ); +## @} + +## @name Random +## @{ +g_iMyRandSeed = int((os.urandom(4)).encode('hex'), 16); +#g_iMyRandSeed = 286523426; +#g_iMyRandSeed = 1994382324; +g_oMyRand = random.Random(g_iMyRandSeed); +#g_oMyRand = random.SystemRandom(); + +def randU8(): + """ Unsigned 8-bit random number. """ + return g_oMyRand.getrandbits(8); + +def randU16(): + """ Unsigned 16-bit random number. """ + return g_oMyRand.getrandbits(16); + +def randU32(): + """ Unsigned 32-bit random number. """ + return g_oMyRand.getrandbits(32); + +def randU64(): + """ Unsigned 64-bit random number. """ + return g_oMyRand.getrandbits(64); + +def randUxx(cBits): + """ Unsigned 8-, 16-, 32-, or 64-bit random number. """ + return g_oMyRand.getrandbits(cBits); + +def randSxx(cBits): + """ Signed 8-, 16-, 32-, or 64-bit random number. """ + uVal = randUxx(cBits); + iRet = uVal & ((1 << (cBits - 1)) - 1); + if iRet != uVal: + iRet = -iRet; + return iRet; + +def randUxxList(cBits, cElements): + """ List of unsigned 8-, 16-, 32-, or 64-bit random numbers. """ + return [randUxx(cBits) for _ in range(cElements)]; +## @} + + + + +## @name Instruction Emitter Helpers +## @{ + +def calcRexPrefixForTwoModRmRegs(iReg, iRm, bOtherRexPrefixes = 0): + """ + Calculates a rex prefix if neccessary given the two registers + and optional rex size prefixes. + Returns an empty array if not necessary. + """ + bRex = bOtherRexPrefixes; + if iReg >= 8: + bRex |= X86_OP_REX_R; + if iRm >= 8: + bRex |= X86_OP_REX_B; + if bRex == 0: + return []; + return [bRex,]; + +def calcModRmForTwoRegs(iReg, iRm): + """ + Calculate the RM byte for two registers. + Returns an array with one byte in it. + """ + bRm = (0x3 << X86_MODRM_MOD_SHIFT) \ + | ((iReg << X86_MODRM_REG_SHIFT) & X86_MODRM_REG_MASK) \ + | (iRm & X86_MODRM_RM_MASK); + return [bRm,]; + +## @} + + +## @name Misc +## @{ + +def convU32ToSigned(u32): + """ Converts a 32-bit unsigned value to 32-bit signed. """ + if u32 < 0x80000000: + return u32; + return u32 - UINT32_MAX - 1; + +def rotateLeftUxx(cBits, uVal, cShift): + """ Rotate a xx-bit wide unsigned number to the left. """ + assert cShift < cBits; + + if cBits == 16: + uMask = UINT16_MAX; + elif cBits == 32: + uMask = UINT32_MAX; + elif cBits == 64: + uMask = UINT64_MAX; + else: + assert cBits == 8; + uMask = UINT8_MAX; + + uVal &= uMask; + uRet = (uVal << cShift) & uMask; + uRet |= (uVal >> (cBits - cShift)); + return uRet; + +def rotateRightUxx(cBits, uVal, cShift): + """ Rotate a xx-bit wide unsigned number to the right. """ + assert cShift < cBits; + + if cBits == 16: + uMask = UINT16_MAX; + elif cBits == 32: + uMask = UINT32_MAX; + elif cBits == 64: + uMask = UINT64_MAX; + else: + assert cBits == 8; + uMask = UINT8_MAX; + + uVal &= uMask; + uRet = (uVal >> cShift); + uRet |= (uVal << (cBits - cShift)) & uMask; + return uRet; + +def gregName(iReg, cBits, fRexByteRegs = True): + """ Gets the name of a general register by index and width. """ + if cBits == 64: + return g_asGRegs64[iReg]; + if cBits == 32: + return g_asGRegs32[iReg]; + if cBits == 16: + return g_asGRegs16[iReg]; + assert cBits == 8; + if fRexByteRegs: + return g_asGRegs8Rex[iReg]; + return g_asGRegs8[iReg]; + +## @} + + +class TargetEnv(object): + """ + Target Runtime Environment. + """ + + ## @name CPU Modes + ## @{ + ksCpuMode_Real = 'real'; + ksCpuMode_Protect = 'prot'; + ksCpuMode_Paged = 'paged'; + ksCpuMode_Long = 'long'; + ksCpuMode_V86 = 'v86'; + ## @} + + ## @name Instruction set. + ## @{ + ksInstrSet_16 = '16'; + ksInstrSet_32 = '32'; + ksInstrSet_64 = '64'; + ## @} + + def __init__(self, sName, + sInstrSet = ksInstrSet_32, + sCpuMode = ksCpuMode_Paged, + iRing = 3, + ): + self.sName = sName; + self.sInstrSet = sInstrSet; + self.sCpuMode = sCpuMode; + self.iRing = iRing; + self.asGRegs = g_asGRegs64 if self.is64Bit() else g_asGRegs32; + self.asGRegsNoSp = g_asGRegs64NoSp if self.is64Bit() else g_asGRegs32NoSp; + + def isUsingIprt(self): + """ Whether it's an IPRT environment or not. """ + return self.sName.startswith('iprt'); + + def is64Bit(self): + """ Whether it's a 64-bit environment or not. """ + return self.sInstrSet == self.ksInstrSet_64; + + def getDefOpBits(self): + """ Get the default operand size as a bit count. """ + if self.sInstrSet == self.ksInstrSet_16: + return 16; + return 32; + + def getDefOpBytes(self): + """ Get the default operand size as a byte count. """ + return self.getDefOpBits() / 8; + + def getMaxOpBits(self): + """ Get the max operand size as a bit count. """ + if self.sInstrSet == self.ksInstrSet_64: + return 64; + return 32; + + def getMaxOpBytes(self): + """ Get the max operand size as a byte count. """ + return self.getMaxOpBits() / 8; + + def getDefAddrBits(self): + """ Get the default address size as a bit count. """ + if self.sInstrSet == self.ksInstrSet_16: + return 16; + if self.sInstrSet == self.ksInstrSet_32: + return 32; + return 64; + + def getDefAddrBytes(self): + """ Get the default address size as a byte count. """ + return self.getDefAddrBits() / 8; + + def getGRegCount(self, cbEffBytes = 4): + """ Get the number of general registers. """ + if self.sInstrSet == self.ksInstrSet_64: + if cbEffBytes == 1: + return 16 + 4; + return 16; + return 8; + + def randGRegNoSp(self, cbEffBytes = 4): + """ Returns a random general register number, excluding the SP register. """ + iReg = randU16() % self.getGRegCount(cbEffBytes); + while iReg == X86_GREG_xSP: + iReg = randU16() % self.getGRegCount(cbEffBytes); + return iReg; + + def randGRegNoSpList(self, cItems, cbEffBytes = 4): + """ List of randGRegNoSp values. """ + aiRegs = []; + for _ in range(cItems): + aiRegs.append(self.randGRegNoSp(cbEffBytes)); + return aiRegs; + + def getAddrModes(self): + """ Gets a list of addressing mode (16, 32, or/and 64). """ + if self.sInstrSet == self.ksInstrSet_16: + return [16, 32]; + if self.sInstrSet == self.ksInstrSet_32: + return [32, 16]; + return [64, 32]; + + def is8BitHighGReg(self, cbEffOp, iGReg): + """ Checks if the given register is a high 8-bit general register (AH, CH, DH or BH). """ + assert cbEffOp in [1, 2, 4, 8]; + if cbEffOp == 1: + if iGReg >= 16: + return True; + if iGReg >= 4 and not self.is64Bit(): + return True; + return False; + + def gregNameBits(self, iReg, cBits): + """ Gets the name of the given register for the specified width (bits). """ + return gregName(iReg, cBits, self.is64Bit()); + + def gregNameBytes(self, iReg, cbWidth): + """ Gets the name of the given register for the specified with (in bytes). """ + return gregName(iReg, cbWidth * 8, self.is64Bit()); + + + + +## Target environments. +g_dTargetEnvs = { + 'iprt-r3-32': TargetEnv('iprt-r3-32', TargetEnv.ksInstrSet_32, TargetEnv.ksCpuMode_Protect, 3), + 'iprt-r3-64': TargetEnv('iprt-r3-64', TargetEnv.ksInstrSet_64, TargetEnv.ksCpuMode_Long, 3), + 'bs2-r0-64': TargetEnv('bs2-r0-64', TargetEnv.ksInstrSet_64, TargetEnv.ksCpuMode_Long, 0), + 'bs2-r0-64-big': TargetEnv('bs2-r0-64-big', TargetEnv.ksInstrSet_64, TargetEnv.ksCpuMode_Long, 0), + 'bs2-r0-32-big': TargetEnv('bs2-r0-32-big', TargetEnv.ksInstrSet_32, TargetEnv.ksCpuMode_Protect, 0), +}; + + +class InstrTestBase(object): + """ + Base class for testing one instruction. + """ + + def __init__(self, sName, sInstr = None): + self.sName = sName; + self.sInstr = sInstr if sInstr else sName.split()[0]; + + def isApplicable(self, oGen): + """ + Tests if the instruction test is applicable to the selected environment. + """ + _ = oGen; + return True; + + def generateTest(self, oGen, sTestFnName): + """ + Emits the test assembly code. + """ + oGen.write(';; @todo not implemented. This is for the linter: %s, %s\n' % (oGen, sTestFnName)); + return True; + + def generateInputs(self, cbEffOp, cbMaxOp, oGen, fLong = False): + """ Generate a list of inputs. """ + if fLong: + # + # Try do extremes as well as different ranges of random numbers. + # + auRet = [0, 1, ]; + if cbMaxOp >= 1: + auRet += [ UINT8_MAX / 2, UINT8_MAX / 2 + 1, UINT8_MAX ]; + if cbMaxOp >= 2: + auRet += [ UINT16_MAX / 2, UINT16_MAX / 2 + 1, UINT16_MAX ]; + if cbMaxOp >= 4: + auRet += [ UINT32_MAX / 2, UINT32_MAX / 2 + 1, UINT32_MAX ]; + if cbMaxOp >= 8: + auRet += [ UINT64_MAX / 2, UINT64_MAX / 2 + 1, UINT64_MAX ]; + + if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny: + for cBits, cValues in ( (8, 4), (16, 4), (32, 8), (64, 8) ): + if cBits < cbMaxOp * 8: + auRet += randUxxList(cBits, cValues); + cWanted = 16; + elif oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Medium: + for cBits, cValues in ( (8, 8), (16, 8), (24, 2), (32, 16), (40, 1), (48, 1), (56, 1), (64, 16) ): + if cBits < cbMaxOp * 8: + auRet += randUxxList(cBits, cValues); + cWanted = 64; + else: + for cBits, cValues in ( (8, 16), (16, 16), (24, 4), (32, 64), (40, 4), (48, 4), (56, 4), (64, 64) ): + if cBits < cbMaxOp * 8: + auRet += randUxxList(cBits, cValues); + cWanted = 168; + if len(auRet) < cWanted: + auRet += randUxxList(cbEffOp * 8, cWanted - len(auRet)); + else: + # + # Short list, just do some random numbers. + # + auRet = []; + if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny: + auRet += randUxxList(cbMaxOp, 1); + elif oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Medium: + auRet += randUxxList(cbMaxOp, 2); + else: + auRet = []; + for cBits in (8, 16, 32, 64): + if cBits < cbMaxOp * 8: + auRet += randUxxList(cBits, 1); + return auRet; + + +class InstrTest_MemOrGreg_2_Greg(InstrTestBase): + """ + Instruction reading memory or general register and writing the result to a + general register. + """ + + def __init__(self, sName, fnCalcResult, sInstr = None, acbOpVars = None): + InstrTestBase.__init__(self, sName, sInstr); + self.fnCalcResult = fnCalcResult; + self.acbOpVars = [ 1, 2, 4, 8 ] if not acbOpVars else list(acbOpVars); + self.fTestRegForm = True; + self.fTestMemForm = True; + + ## @name Test Instruction Writers + ## @{ + + def writeInstrGregGreg(self, cbEffOp, iOp1, iOp2, oGen): + """ Writes the instruction with two general registers as operands. """ + oGen.write(' %s %s, %s\n' + % ( self.sInstr, oGen.gregNameBytes(iOp1, cbEffOp), oGen.gregNameBytes(iOp2, cbEffOp),)); + return True; + + def writeInstrGregPureRM(self, cbEffOp, iOp1, cAddrBits, iOp2, iMod, offDisp, oGen): + """ Writes the instruction with two general registers as operands. """ + oGen.write(' '); + if iOp2 == 13 and iMod == 0 and cAddrBits == 64: + oGen.write('altrexb '); # Alternative encoding for rip relative addressing. + oGen.write('%s %s, [' % (self.sInstr, oGen.gregNameBytes(iOp1, cbEffOp),)); + if (iOp2 == 5 or iOp2 == 13) and iMod == 0: + oGen.write('VBINSTST_NAME(g_u%sData)' % (cbEffOp * 8,)) + if oGen.oTarget.is64Bit(): + oGen.write(' wrt rip'); + else: + if iMod == 1: + oGen.write('byte %d + ' % (offDisp,)); + elif iMod == 2: + oGen.write('dword %d + ' % (offDisp,)); + else: + assert iMod == 0; + + if cAddrBits == 64: + oGen.write(g_asGRegs64[iOp2]); + elif cAddrBits == 32: + oGen.write(g_asGRegs32[iOp2]); + elif cAddrBits == 16: + assert False; ## @todo implement 16-bit addressing. + else: + assert False, str(cAddrBits); + + oGen.write(']\n'); + return True; + + def writeInstrGregSibLabel(self, cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen): + """ Writes the instruction taking a register and a label (base only w/o reg), SIB form. """ + assert offDisp is None; assert iBaseReg in [5, 13]; assert iIndexReg == 4; assert cAddrBits != 16; + if cAddrBits == 64: + # Note! Cannot test this in 64-bit mode in any sensible way because the disp is 32-bit + # and we cannot (yet) make assumtions about where we're loaded. + ## @todo Enable testing this in environments where we can make assumptions (boot sector). + oGen.write(' %s %s, [VBINSTST_NAME(g_u%sData) xWrtRIP]\n' + % ( self.sInstr, oGen.gregNameBytes(iOp1, cbEffOp), cbEffOp * 8,)); + else: + oGen.write(' altsibx%u %s %s, [VBINSTST_NAME(g_u%sData) xWrtRIP] ; iOp1=%s cbEffOp=%s\n' + % ( iScale, self.sInstr, oGen.gregNameBytes(iOp1, cbEffOp), cbEffOp * 8, iOp1, cbEffOp)); + return True; + + def writeInstrGregSibScaledReg(self, cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen): + """ Writes the instruction taking a register and disp+scaled register (no base reg), SIB form. """ + assert iBaseReg in [5, 13]; assert iIndexReg != 4; assert cAddrBits != 16; + # Note! Using altsibxN to force scaled encoding. This is only really a + # necessity for iScale=1, but doesn't hurt for the rest. + oGen.write(' altsibx%u %s %s, [%s * %#x' + % (iScale, self.sInstr, oGen.gregNameBytes(iOp1, cbEffOp), oGen.gregNameBits(iIndexReg, cAddrBits), iScale,)); + if offDisp is not None: + oGen.write(' + %#x' % (offDisp,)); + oGen.write(']\n'); + _ = iBaseReg; + return True; + + def writeInstrGregSibBase(self, cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen): + """ Writes the instruction taking a register and base only (with reg), SIB form. """ + oGen.write(' altsibx%u %s %s, [%s' + % (iScale, self.sInstr, oGen.gregNameBytes(iOp1, cbEffOp), oGen.gregNameBits(iBaseReg, cAddrBits),)); + if offDisp is not None: + oGen.write(' + %#x' % (offDisp,)); + oGen.write(']\n'); + _ = iIndexReg; + return True; + + def writeInstrGregSibBaseAndScaledReg(self, cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen): + """ Writes tinstruction taking a register and full featured SIB form address. """ + # Note! From the looks of things, yasm will encode the following instructions the same way: + # mov eax, [rsi*1 + rbx] + # mov eax, [rbx + rsi*1] + # So, when there are two registers involved, the '*1' selects + # which is index and which is base. + oGen.write(' %s %s, [%s + %s * %u' + % ( self.sInstr, oGen.gregNameBytes(iOp1, cbEffOp), + oGen.gregNameBits(iBaseReg, cAddrBits), oGen.gregNameBits(iIndexReg, cAddrBits), iScale,)); + if offDisp is not None: + oGen.write(' + %#x' % (offDisp,)); + oGen.write(']\n'); + return True; + + ## @} + + + ## @name Memory setups + ## @{ + + def generateMemSetupReadByLabel(self, oGen, cbEffOp, uInput): + """ Sets up memory for a memory read. """ + oGen.pushConst(uInput); + oGen.write(' call VBINSTST_NAME(Common_SetupMemReadU%u)\n' % (cbEffOp*8,)); + return True; + + def generateMemSetupReadByReg(self, oGen, cAddrBits, cbEffOp, iReg1, uInput, offDisp = None): + """ Sets up memory for a memory read indirectly addressed thru one register and optional displacement. """ + oGen.pushConst(uInput); + oGen.write(' call VBINSTST_NAME(%s)\n' + % (oGen.needGRegMemSetup(cAddrBits, cbEffOp, iBaseReg = iReg1, offDisp = offDisp),)); + oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iReg1],)); + return True; + + def generateMemSetupReadByScaledReg(self, oGen, cAddrBits, cbEffOp, iIndexReg, iScale, uInput, offDisp = None): + """ Sets up memory for a memory read indirectly addressed thru one register and optional displacement. """ + oGen.pushConst(uInput); + oGen.write(' call VBINSTST_NAME(%s)\n' + % (oGen.needGRegMemSetup(cAddrBits, cbEffOp, offDisp = offDisp, iIndexReg = iIndexReg, iScale = iScale),)); + oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iIndexReg],)); + return True; + + def generateMemSetupReadByBaseAndScaledReg(self, oGen, cAddrBits, cbEffOp, iBaseReg, iIndexReg, iScale, uInput, offDisp): + """ Sets up memory for a memory read indirectly addressed thru two registers with optional displacement. """ + oGen.pushConst(uInput); + oGen.write(' call VBINSTST_NAME(%s)\n' + % (oGen.needGRegMemSetup(cAddrBits, cbEffOp, iBaseReg = iBaseReg, offDisp = offDisp, + iIndexReg = iIndexReg, iScale = iScale),)); + oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iIndexReg],)); + oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iBaseReg],)); + return True; + + def generateMemSetupPureRM(self, oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput, offDisp = None): + """ Sets up memory for a pure R/M addressed read, iOp2 being the R/M value. """ + oGen.pushConst(uInput); + assert offDisp is None or iMod != 0; + if (iOp2 != 5 and iOp2 != 13) or iMod != 0: + oGen.write(' call VBINSTST_NAME(%s)\n' + % (oGen.needGRegMemSetup(cAddrBits, cbEffOp, iOp2, offDisp),)); + else: + oGen.write(' call VBINSTST_NAME(Common_SetupMemReadU%u)\n' % (cbEffOp*8,)); + oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iOp2],)); + return True; + + ## @} + + def generateOneStdTestGregGreg(self, oGen, cbEffOp, cbMaxOp, iOp1, iOp1X, iOp2, iOp2X, uInput, uResult): + """ Generate one standard instr greg,greg test. """ + oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n'); + oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[iOp2X], uInput,)); + if iOp1X != iOp2X: + oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iOp2X],)); + self.writeInstrGregGreg(cbEffOp, iOp1, iOp2, oGen); + oGen.pushConst(uResult); + oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1X, iOp2X if iOp1X != iOp2X else None),)); + _ = cbMaxOp; + return True; + + def generateOneStdTestGregGreg8BitHighPain(self, oGen, cbEffOp, cbMaxOp, iOp1, iOp2, uInput): + """ High 8-bit registers are a real pain! """ + assert oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1) or oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2); + # Figure out the register indexes of the max op sized regs involved. + iOp1X = iOp1 & 3; + iOp2X = iOp2 & 3; + oGen.write(' ; iOp1=%u iOp1X=%u iOp2=%u iOp2X=%u\n' % (iOp1, iOp1X, iOp2, iOp2X,)); + + # Calculate unshifted result. + if iOp1X != iOp2X: + uCur = oGen.auRegValues[iOp1X]; + if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1): + uCur = rotateRightUxx(cbMaxOp * 8, uCur, 8); + else: + uCur = uInput; + if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1) != oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2): + if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1): + uCur = rotateRightUxx(cbMaxOp * 8, uCur, 8); + else: + uCur = rotateLeftUxx(cbMaxOp * 8, uCur, 8); + uResult = self.fnCalcResult(cbEffOp, uInput, uCur, oGen); + + + # Rotate the input and/or result to match their max-op-sized registers. + if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2): + uInput = rotateLeftUxx(cbMaxOp * 8, uInput, 8); + if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1): + uResult = rotateLeftUxx(cbMaxOp * 8, uResult, 8); + + # Hand it over to an overridable worker method. + return self.generateOneStdTestGregGreg(oGen, cbEffOp, cbMaxOp, iOp1, iOp1X, iOp2, iOp2X, uInput, uResult); + + + def generateOneStdTestGregMemNoSib(self, oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, iOp2, uInput, uResult): + """ Generate mode 0, 1 and 2 test for the R/M=iOp2. """ + if cAddrBits == 16: + _ = cbMaxOp; + else: + iMod = 0; # No disp, except for i=5. + oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n'); + self.generateMemSetupPureRM(oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput); + self.writeInstrGregPureRM(cbEffOp, iOp1, cAddrBits, iOp2, iMod, None, oGen); + oGen.pushConst(uResult); + oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1, iOp2),)); + + if iOp2 != 5 and iOp2 != 13: + iMod = 1; + for offDisp in oGen.getDispForMod(iMod): + oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n'); + self.generateMemSetupPureRM(oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput, offDisp); + self.writeInstrGregPureRM(cbEffOp, iOp1, cAddrBits, iOp2, iMod, offDisp, oGen); + oGen.pushConst(uResult); + oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1, iOp2),)); + + iMod = 2; + for offDisp in oGen.getDispForMod(iMod): + oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n'); + self.generateMemSetupPureRM(oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput, offDisp); + self.writeInstrGregPureRM(cbEffOp, iOp1, cAddrBits, iOp2, iMod, offDisp, oGen); + oGen.pushConst(uResult); + oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1, iOp2),)); + + return True; + + def generateOneStdTestGregMemSib(self, oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, iMod, # pylint: disable=R0913 + iBaseReg, iIndexReg, iScale, uInput, uResult): + """ Generate one SIB variations. """ + for offDisp in oGen.getDispForMod(iMod, cbEffOp): + if ((iBaseReg == 5 or iBaseReg == 13) and iMod == 0): + if iIndexReg == 4: + if cAddrBits == 64: + continue; # skipping. + oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n'); + self.generateMemSetupReadByLabel(oGen, cbEffOp, uInput); + self.writeInstrGregSibLabel(cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen); + sChecker = oGen.needGRegChecker(iOp1); + else: + oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n'); + self.generateMemSetupReadByScaledReg(oGen, cAddrBits, cbEffOp, iIndexReg, iScale, uInput, offDisp); + self.writeInstrGregSibScaledReg(cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen); + sChecker = oGen.needGRegChecker(iOp1, iIndexReg); + else: + oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n'); + if iIndexReg == 4: + self.generateMemSetupReadByReg(oGen, cAddrBits, cbEffOp, iBaseReg, uInput, offDisp); + self.writeInstrGregSibBase(cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen); + sChecker = oGen.needGRegChecker(iOp1, iBaseReg); + else: + if iIndexReg == iBaseReg and iScale == 1 and offDisp is not None and (offDisp & 1): + if offDisp < 0: offDisp += 1; + else: offDisp -= 1; + self.generateMemSetupReadByBaseAndScaledReg(oGen, cAddrBits, cbEffOp, iBaseReg, + iIndexReg, iScale, uInput, offDisp); + self.writeInstrGregSibBaseAndScaledReg(cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen); + sChecker = oGen.needGRegChecker(iOp1, iBaseReg, iIndexReg); + oGen.pushConst(uResult); + oGen.write(' call VBINSTST_NAME(%s)\n' % (sChecker,)); + _ = cbMaxOp; + return True; + + def generateStdTestGregMemSib(self, oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, auInputs): + """ Generate all SIB variations for the given iOp1 (reg) value. """ + assert cAddrBits in [32, 64]; + i = oGen.cSibBasePerRun; + while i > 0: + oGen.iSibBaseReg = (oGen.iSibBaseReg + 1) % oGen.oTarget.getGRegCount(cAddrBits / 8); + if oGen.iSibBaseReg == X86_GREG_xSP: # no RSP testing atm. + continue; + + j = oGen.getSibIndexPerRun(); + while j > 0: + oGen.iSibIndexReg = (oGen.iSibIndexReg + 1) % oGen.oTarget.getGRegCount(cAddrBits / 8); + if oGen.iSibIndexReg == iOp1 and oGen.iSibIndexReg != 4 and cAddrBits != cbMaxOp: + continue; # Don't know the high bit of the address ending up the result - skip it for now. + + for iMod in [0, 1, 2]: + if oGen.iSibBaseReg == iOp1 \ + and ((oGen.iSibBaseReg != 5 and oGen.iSibBaseReg != 13) or iMod != 0) \ + and cAddrBits != cbMaxOp: + continue; # Don't know the high bit of the address ending up the result - skip it for now. + + for _ in oGen.oSibScaleRange: + oGen.iSibScale *= 2; + if oGen.iSibScale > 8: + oGen.iSibScale = 1; + + for uInput in auInputs: + oGen.newSubTest(); + uResult = self.fnCalcResult(cbEffOp, uInput, oGen.auRegValues[iOp1], oGen); + self.generateOneStdTestGregMemSib(oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, iMod, + oGen.iSibBaseReg, oGen.iSibIndexReg, oGen.iSibScale, + uInput, uResult); + j -= 1; + i -= 1; + + return True; + + + def generateStandardTests(self, oGen): + """ Generate standard tests. """ + + # Parameters. + cbDefOp = oGen.oTarget.getDefOpBytes(); + cbMaxOp = oGen.oTarget.getMaxOpBytes(); + auShortInputs = self.generateInputs(cbDefOp, cbMaxOp, oGen); + auLongInputs = self.generateInputs(cbDefOp, cbMaxOp, oGen, fLong = True); + iLongOp1 = oGen.oTarget.randGRegNoSp(); + iLongOp2 = oGen.oTarget.randGRegNoSp(); + + # Register tests + if self.fTestRegForm: + for cbEffOp in self.acbOpVars: + if cbEffOp > cbMaxOp: + continue; + oOp2Range = range(oGen.oTarget.getGRegCount(cbEffOp)); + if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny: + oOp2Range = [iLongOp2,]; + oGen.write('; cbEffOp=%u\n' % (cbEffOp,)); + + for iOp1 in range(oGen.oTarget.getGRegCount(cbEffOp)): + if iOp1 == X86_GREG_xSP: + continue; # Cannot test xSP atm. + for iOp2 in oOp2Range: + if (iOp2 >= 16 and iOp1 in range(4, 16)) \ + or (iOp1 >= 16 and iOp2 in range(4, 16)): + continue; # Any REX encoding turns AH,CH,DH,BH regs into SPL,BPL,SIL,DIL. + if iOp2 == X86_GREG_xSP: + continue; # Cannot test xSP atm. + + oGen.write('; iOp2=%u cbEffOp=%u\n' % (iOp2, cbEffOp)); + for uInput in (auLongInputs if iOp1 == iLongOp1 and iOp2 == iLongOp2 else auShortInputs): + oGen.newSubTest(); + if not oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1) and not oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2): + uCur = oGen.auRegValues[iOp1 & 15] if iOp1 != iOp2 else uInput; + uResult = self.fnCalcResult(cbEffOp, uInput, uCur, oGen); + self.generateOneStdTestGregGreg(oGen, cbEffOp, cbMaxOp, iOp1, iOp1 & 15, iOp2, iOp2 & 15, + uInput, uResult); + else: + self.generateOneStdTestGregGreg8BitHighPain(oGen, cbEffOp, cbMaxOp, iOp1, iOp2, uInput); + + # Memory test. + if self.fTestMemForm: + for cAddrBits in oGen.oTarget.getAddrModes(): + for cbEffOp in self.acbOpVars: + if cbEffOp > cbMaxOp: + continue; + + for _ in oGen.getModRegRange(cbEffOp): + oGen.iModReg = (oGen.iModReg + 1) % oGen.oTarget.getGRegCount(cbEffOp); + if oGen.iModReg == X86_GREG_xSP: + continue; # Cannot test xSP atm. + if oGen.iModReg > 15: + continue; ## TODO AH,CH,DH,BH + + auInputs = auLongInputs if oGen.iModReg == iLongOp1 else auShortInputs; + for _ in oGen.oModRmRange: + oGen.iModRm = (oGen.iModRm + 1) % oGen.oTarget.getGRegCount(cAddrBits * 8); + if oGen.iModRm != 4 or cAddrBits == 16: + for uInput in auInputs: + oGen.newSubTest(); + if oGen.iModReg == oGen.iModRm and oGen.iModRm != 5 \ + and oGen.iModRm != 13 and cbEffOp != cbMaxOp: + continue; # Don't know the high bit of the address ending up the result - skip it for now. + uResult = self.fnCalcResult(cbEffOp, uInput, oGen.auRegValues[oGen.iModReg & 15], oGen); + self.generateOneStdTestGregMemNoSib(oGen, cAddrBits, cbEffOp, cbMaxOp, + oGen.iModReg, oGen.iModRm, uInput, uResult); + else: + # SIB - currently only short list of inputs or things may get seriously out of hand. + self.generateStdTestGregMemSib(oGen, cAddrBits, cbEffOp, cbMaxOp, oGen.iModReg, auShortInputs); + return True; + + def generateTest(self, oGen, sTestFnName): + oGen.write('VBINSTST_BEGINPROC %s\n' % (sTestFnName,)); + + self.generateStandardTests(oGen); + + oGen.write(' ret\n'); + oGen.write('VBINSTST_ENDPROC %s\n' % (sTestFnName,)); + return True; + + + +class InstrTest_Mov_Gv_Ev(InstrTest_MemOrGreg_2_Greg): + """ + Tests MOV Gv,Ev. + """ + def __init__(self): + InstrTest_MemOrGreg_2_Greg.__init__(self, 'mov Gv,Ev', self.calc_mov); + + @staticmethod + def calc_mov(cbEffOp, uInput, uCur, oGen): + """ Calculates the result of a mov instruction.""" + if cbEffOp == 8: + return uInput & UINT64_MAX; + if cbEffOp == 4: + return uInput & UINT32_MAX; + if cbEffOp == 2: + return (uCur & 0xffffffffffff0000) | (uInput & UINT16_MAX); + assert cbEffOp == 1; _ = oGen; + return (uCur & 0xffffffffffffff00) | (uInput & UINT8_MAX); + + +class InstrTest_MovSxD_Gv_Ev(InstrTest_MemOrGreg_2_Greg): + """ + Tests MOVSXD Gv,Ev. + """ + def __init__(self): + InstrTest_MemOrGreg_2_Greg.__init__(self, 'movsxd Gv,Ev', self.calc_movsxd, acbOpVars = [ 8, 4, 2, ]); + self.fTestMemForm = False; # drop this... + + def writeInstrGregGreg(self, cbEffOp, iOp1, iOp2, oGen): + """ Writes the instruction with two general registers as operands. """ + if cbEffOp == 8: + oGen.write(' movsxd %s, %s\n' + % ( oGen.gregNameBytes(iOp1, cbEffOp), oGen.gregNameBytes(iOp2, cbEffOp / 2),)); + else: + oGen.write(' oddmovsxd %s, %s\n' + % ( oGen.gregNameBytes(iOp1, cbEffOp), oGen.gregNameBytes(iOp2, cbEffOp),)); + return True; + + def isApplicable(self, oGen): + return oGen.oTarget.is64Bit(); + + @staticmethod + def calc_movsxd(cbEffOp, uInput, uCur, oGen): + """ + Calculates the result of a movxsd instruction. + Returns the result value (cbMaxOp sized). + """ + _ = oGen; + if cbEffOp == 8 and (uInput & RT_BIT_32(31)): + return (UINT32_MAX << 32) | (uInput & UINT32_MAX); + if cbEffOp == 2: + return (uCur & 0xffffffffffff0000) | (uInput & 0xffff); + return uInput & UINT32_MAX; + + +class InstrTest_DivIDiv(InstrTestBase): + """ + Tests IDIV and DIV instructions. + """ + + def __init__(self, fIsIDiv): + if not fIsIDiv: + InstrTestBase.__init__(self, 'div Gv,Ev', 'div'); + else: + InstrTestBase.__init__(self, 'idiv Gv,Ev', 'idiv'); + self.fIsIDiv = fIsIDiv; + + def generateInputEdgeCases(self, cbEffOp, fLong, fXcpt): + """ Generate edge case inputs for cbEffOp. Returns a list of pairs, dividen + divisor. """ + # Test params. + uStep = 1 << (cbEffOp * 8); + if self.fIsIDiv: + uStep /= 2; + + # edge tests + auRet = []; + + uDivisor = 1 if fLong else 3; + uDividend = uStep * uDivisor - 1; + for i in range(5 if fLong else 3): + auRet.append([uDividend + fXcpt, uDivisor]); + if self.fIsIDiv: + auRet.append([-uDividend - fXcpt, -uDivisor]); + auRet.append([-(uDividend + uDivisor + fXcpt), uDivisor]); + auRet.append([ (uDividend + uDivisor + fXcpt), -uDivisor]); + if i <= 3 and fLong: + auRet.append([uDividend - 1 + fXcpt*3, uDivisor]); + if self.fIsIDiv: + auRet.append([-(uDividend - 1 + fXcpt*3), -uDivisor]); + uDivisor += 1; + uDividend += uStep; + + uDivisor = uStep - 1; + uDividend = uStep * uDivisor - 1; + for _ in range(3 if fLong else 1): + auRet.append([uDividend + fXcpt, uDivisor]); + if self.fIsIDiv: + auRet.append([-uDividend - fXcpt, -uDivisor]); + uDivisor -= 1; + uDividend -= uStep; + + if self.fIsIDiv: + uDivisor = -uStep; + for _ in range(3 if fLong else 1): + auRet.append([uDivisor * (-uStep - 1) - (not fXcpt), uDivisor]); + uDivisor += 1 + uDivisor = uStep - 1; + for _ in range(3 if fLong else 1): + auRet.append([-(uDivisor * (uStep + 1) - (not fXcpt)), uDivisor]); + uDivisor -= 1 + + return auRet; + + def generateInputsNoXcpt(self, cbEffOp, fLong = False): + """ Generate inputs for cbEffOp. Returns a list of pairs, dividen + divisor. """ + # Test params. + uStep = 1 << (cbEffOp * 8); + if self.fIsIDiv: + uStep /= 2; + + # edge tests + auRet = self.generateInputEdgeCases(cbEffOp, fLong, False) + + # random tests. + if self.fIsIDiv: + for _ in range(6 if fLong else 2): + while True: + uDivisor = randSxx(cbEffOp * 8); + if uDivisor == 0 or uDivisor >= uStep or uDivisor < -uStep: + continue; + uDividend = randSxx(cbEffOp * 16); + uResult = uDividend / uDivisor; + if uResult >= uStep or uResult <= -uStep: # exclude difficulties + continue; + break; + auRet.append([uDividend, uDivisor]); + else: + for _ in range(6 if fLong else 2): + while True: + uDivisor = randUxx(cbEffOp * 8); + if uDivisor == 0 or uDivisor >= uStep: + continue; + uDividend = randUxx(cbEffOp * 16); + uResult = uDividend / uDivisor; + if uResult >= uStep: + continue; + break; + auRet.append([uDividend, uDivisor]); + + return auRet; + + def generateOneStdTestGreg(self, oGen, cbEffOp, iOp2, iDividend, iDivisor): + """ Generate code of one '[I]DIV rDX:rAX,' test. """ + cbMaxOp = oGen.oTarget.getMaxOpBytes(); + fEffOp = ((1 << (cbEffOp *8) ) - 1); + fMaxOp = UINT64_MAX if cbMaxOp == 8 else UINT32_MAX; assert cbMaxOp in [8, 4]; + fTopOp = fMaxOp - fEffOp; + fFullOp1 = ((1 << (cbEffOp*16)) - 1); + + uAX = iDividend & fFullOp1; # full with unsigned + uDX = uAX >> (cbEffOp*8); + uAX &= fEffOp; + uOp2Val = iDivisor & fEffOp; + + iQuotient = iDividend / iDivisor; + iReminder = iDividend % iDivisor; + if iReminder != 0 and iQuotient < 0: # python has different rounding rules for negative division. + iQuotient += 1; + iReminder -= iDivisor; + uAXResult = iQuotient & fEffOp; + uDXResult = iReminder & fEffOp; + + if cbEffOp < cbMaxOp: + uAX |= randUxx(cbMaxOp * 8) & fTopOp; + uDX |= randUxx(cbMaxOp * 8) & fTopOp; + uOp2Val |= randUxx(cbMaxOp * 8) & fTopOp; + if cbEffOp < 4: + uAXResult |= uAX & fTopOp; + uDXResult |= uDX & fTopOp; + oGen.write(' ; iDividend=%#x (%d) iDivisor=%#x (%d)\n' + ' ; iQuotient=%#x (%d) iReminder=%#x (%d)\n' + % ( iDividend & fFullOp1, iDividend, iDivisor & fEffOp, iDivisor, + iQuotient & fEffOp, iQuotient, iReminder & fEffOp, iReminder, )); + + oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n'); + oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[X86_GREG_xDX], uDX,)); + oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[X86_GREG_xAX], uAX,)); + oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[iOp2], uOp2Val,)); + + oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iOp2],)); + oGen.pushConst(uDXResult); + oGen.pushConst(uAXResult); + + oGen.write(' %-4s %s\n' % (self.sInstr, oGen.gregNameBytes(iOp2, cbEffOp),)); + oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(X86_GREG_xAX, X86_GREG_xDX, iOp2),)); + return True; + + def generateOneStdTestGreg8Bit(self, oGen, cbEffOp, iOp2, iDividend, iDivisor): + """ Generate code of one '[I]DIV AX,' test (8-bit). """ + cbMaxOp = oGen.oTarget.getMaxOpBytes(); + fMaxOp = UINT64_MAX if cbMaxOp == 8 else UINT32_MAX; assert cbMaxOp in [8, 4]; + iOp2X = (iOp2 & 3) if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2) else iOp2; + assert iOp2X != X86_GREG_xAX; + + uAX = iDividend & UINT16_MAX; # full with unsigned + uOp2Val = iDivisor & UINT8_MAX; + + iQuotient = iDividend / iDivisor; + iReminder = iDividend % iDivisor; + if iReminder != 0 and iQuotient < 0: # python has different rounding rules for negative division. + iQuotient += 1; + iReminder -= iDivisor; + uAXResult = (iQuotient & UINT8_MAX) | ((iReminder & UINT8_MAX) << 8); + + uAX |= randUxx(cbMaxOp * 8) & (fMaxOp - UINT16_MAX); + uAXResult |= uAX & (fMaxOp - UINT16_MAX); + uOp2Val |= randUxx(cbMaxOp * 8) & (fMaxOp - UINT8_MAX); + if iOp2X != iOp2: + uOp2Val = rotateLeftUxx(cbMaxOp * 8, uOp2Val, 8); + oGen.write(' ; iDividend=%#x (%d) iDivisor=%#x (%d)\n' + ' ; iQuotient=%#x (%d) iReminder=%#x (%d)\n' + % ( iDividend & UINT16_MAX, iDividend, iDivisor & UINT8_MAX, iDivisor, + iQuotient & UINT8_MAX, iQuotient, iReminder & UINT8_MAX, iReminder, )); + + oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n'); + oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[X86_GREG_xAX], uAX,)); + oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[iOp2X], uOp2Val,)); + oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iOp2X],)); + oGen.pushConst(uAXResult); + + oGen.write(' %-4s %s\n' % (self.sInstr, oGen.gregNameBytes(iOp2, cbEffOp),)); + oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(X86_GREG_xAX, iOp2X),)); + return; + + + def generateStandardTests(self, oGen): + """ Generates test that causes no exceptions. """ + + # Parameters. + iLongOp2 = oGen.oTarget.randGRegNoSp(); + + # Register tests + if True: + for cbEffOp in ( 8, 4, 2, 1 ): + if cbEffOp > oGen.oTarget.getMaxOpBytes(): + continue; + oGen.write('; cbEffOp=%u\n' % (cbEffOp,)); + oOp2Range = range(oGen.oTarget.getGRegCount(cbEffOp)); + if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny: + oOp2Range = [iLongOp2,]; + for iOp2 in oOp2Range: + if iOp2 == X86_GREG_xSP: + continue; # Cannot test xSP atm. + if iOp2 == X86_GREG_xAX or (cbEffOp > 1 and iOp2 == X86_GREG_xDX): + continue; # Will overflow or be too complicated to get right. + if cbEffOp == 1 and iOp2 == (16 if oGen.oTarget.is64Bit() else 4): + continue; # Avoid dividing by AH, same reasons as above. + + for iDividend, iDivisor in self.generateInputsNoXcpt(cbEffOp, iOp2 == iLongOp2): + oGen.newSubTest(); + if cbEffOp > 1: + self.generateOneStdTestGreg(oGen, cbEffOp, iOp2, iDividend, iDivisor); + else: + self.generateOneStdTestGreg8Bit(oGen, cbEffOp, iOp2, iDividend, iDivisor); + + ## Memory test. + #if False: + # for cAddrBits in oGen.oTarget.getAddrModes(): + # for cbEffOp in self.acbOpVars: + # if cbEffOp > cbMaxOp: + # continue; + # + # auInputs = auLongInputs if oGen.iModReg == iLongOp1 else auShortInputs; + # for _ in oGen.oModRmRange: + # oGen.iModRm = (oGen.iModRm + 1) % oGen.oTarget.getGRegCount(cAddrBits * 8); + # if oGen.iModRm != 4 or cAddrBits == 16: + # for uInput in auInputs: + # oGen.newSubTest(); + # if oGen.iModReg == oGen.iModRm and oGen.iModRm != 5 and oGen.iModRm != 13 and cbEffOp != cbMaxOp: + # continue; # Don't know the high bit of the address ending up the result - skip it for now. + # uResult = self.fnCalcResult(cbEffOp, uInput, oGen.auRegValues[oGen.iModReg & 15], oGen); + # self.generateOneStdTestGregMemNoSib(oGen, cAddrBits, cbEffOp, cbMaxOp, + # oGen.iModReg, oGen.iModRm, uInput, uResult); + # else: + # # SIB - currently only short list of inputs or things may get seriously out of hand. + # self.generateStdTestGregMemSib(oGen, cAddrBits, cbEffOp, cbMaxOp, oGen.iModReg, auShortInputs); + # + return True; + + def generateInputsXcpt(self, cbEffOp, fLong = False): + """ + Generate inputs for cbEffOp that will overflow or underflow. + Returns a list of pairs, dividen + divisor. + """ + # Test params. + uStep = 1 << (cbEffOp * 8); + if self.fIsIDiv: + uStep /= 2; + + # edge tests + auRet = self.generateInputEdgeCases(cbEffOp, fLong, True); + auRet.extend([[0, 0], [1, 0], [ uStep * uStep / 2 - 1, 0]]); + + # random tests. + if self.fIsIDiv: + for _ in range(6 if fLong else 2): + while True: + uDivisor = randSxx(cbEffOp * 8); + uDividend = randSxx(cbEffOp * 16); + if uDivisor >= uStep or uDivisor < -uStep: + continue; + if uDivisor != 0: + uResult = uDividend / uDivisor; + if (uResult <= uStep and uResult >= 0) or (uResult >= -uStep and uResult < 0): + continue; # exclude difficulties + break; + auRet.append([uDividend, uDivisor]); + else: + for _ in range(6 if fLong else 2): + while True: + uDivisor = randUxx(cbEffOp * 8); + uDividend = randUxx(cbEffOp * 16); + if uDivisor >= uStep: + continue; + if uDivisor != 0: + uResult = uDividend / uDivisor; + if uResult < uStep: + continue; + break; + auRet.append([uDividend, uDivisor]); + + return auRet; + + def generateOneDivideErrorTestGreg(self, oGen, cbEffOp, iOp2, iDividend, iDivisor): + """ Generate code of one '[I]DIV rDX:rAX,' test that causes #DE. """ + cbMaxOp = oGen.oTarget.getMaxOpBytes(); + fEffOp = ((1 << (cbEffOp *8) ) - 1); + fMaxOp = UINT64_MAX if cbMaxOp == 8 else UINT32_MAX; assert cbMaxOp in [8, 4]; + fTopOp = fMaxOp - fEffOp; + fFullOp1 = ((1 << (cbEffOp*16)) - 1); + + uAX = iDividend & fFullOp1; # full with unsigned + uDX = uAX >> (cbEffOp*8); + uAX &= fEffOp; + uOp2Val = iDivisor & fEffOp; + + if cbEffOp < cbMaxOp: + uAX |= randUxx(cbMaxOp * 8) & fTopOp; + uDX |= randUxx(cbMaxOp * 8) & fTopOp; + uOp2Val |= randUxx(cbMaxOp * 8) & fTopOp; + oGen.write(' ; iDividend=%#x (%d) iDivisor=%#x (%d)\n' + % ( iDividend & fFullOp1, iDividend, iDivisor & fEffOp, iDivisor,)); + oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n'); + oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[X86_GREG_xDX], uDX,)); + oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[X86_GREG_xAX], uAX,)); + oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[iOp2], uOp2Val,)); + oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iOp2],)); + oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[X86_GREG_xDX],)); + oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[X86_GREG_xAX],)); + oGen.write(' VBINSTST_TRAP_INSTR X86_XCPT_DE, 0, %-4s %s\n' + % (self.sInstr, oGen.gregNameBytes(iOp2, cbEffOp),)); + oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(X86_GREG_xAX, X86_GREG_xDX, iOp2),)); + return True; + + def generateOneDivideErrorTestGreg8Bit(self, oGen, cbEffOp, iOp2, iDividend, iDivisor): + """ Generate code of one '[I]DIV AX,' test that causes #DE (8-bit). """ + if not oGen.oTarget.is64Bit() and iOp2 == 4: # Avoid AH. + iOp2 = 5; + + cbMaxOp = oGen.oTarget.getMaxOpBytes(); + fMaxOp = UINT64_MAX if cbMaxOp == 8 else UINT32_MAX; assert cbMaxOp in [8, 4]; + iOp2X = (iOp2 & 3) if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2) else iOp2; + assert iOp2X != X86_GREG_xAX; + + uAX = iDividend & UINT16_MAX; # full with unsigned + uOp2Val = iDivisor & UINT8_MAX; + + uAX |= randUxx(cbMaxOp * 8) & (fMaxOp - UINT16_MAX); + uOp2Val |= randUxx(cbMaxOp * 8) & (fMaxOp - UINT8_MAX); + if iOp2X != iOp2: + uOp2Val = rotateLeftUxx(cbMaxOp * 8, uOp2Val, 8); + oGen.write(' ; iDividend=%#x (%d) iDivisor=%#x (%d)\n' + % ( iDividend & UINT16_MAX, iDividend, iDivisor & UINT8_MAX, iDivisor,)); + oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n'); + oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[X86_GREG_xAX], uAX,)); + oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[iOp2X], uOp2Val,)); + oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iOp2X],)); + oGen.write(' push sAX\n'); + oGen.write(' VBINSTST_TRAP_INSTR X86_XCPT_DE, 0, %-4s %s\n' + % (self.sInstr, oGen.gregNameBytes(iOp2, cbEffOp),)); + oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(X86_GREG_xAX, iOp2X),)); + return; + + def generateDivideErrorTests(self, oGen): + """ Generate divide error tests (raises X86_XCPT_DE). """ + oGen.write('%ifdef VBINSTST_CAN_DO_TRAPS\n'); + + # We do one register variation here, assuming the standard test has got them covered. + # Register tests + if True: + iOp2 = oGen.oTarget.randGRegNoSp(); + while iOp2 == X86_GREG_xAX or iOp2 == X86_GREG_xDX: + iOp2 = oGen.oTarget.randGRegNoSp(); + + for cbEffOp in ( 8, 4, 2, 1 ): + if cbEffOp > oGen.oTarget.getMaxOpBytes(): + continue; + oGen.write('; cbEffOp=%u iOp2=%u\n' % (cbEffOp, iOp2,)); + + for iDividend, iDivisor in self.generateInputsXcpt(cbEffOp, fLong = not oGen.isTiny()): + oGen.newSubTest(); + if cbEffOp > 1: + self.generateOneDivideErrorTestGreg(oGen, cbEffOp, iOp2, iDividend, iDivisor); + else: + self.generateOneDivideErrorTestGreg8Bit(oGen, cbEffOp, iOp2, iDividend, iDivisor); + + oGen.write('%endif ; VBINSTST_CAN_DO_TRAPS\n'); + return True; + + + def generateTest(self, oGen, sTestFnName): + oGen.write('VBINSTST_BEGINPROC %s\n' % (sTestFnName,)); + #oGen.write(' int3\n'); + + self.generateStandardTests(oGen); + self.generateDivideErrorTests(oGen); + + #oGen.write(' int3\n'); + oGen.write(' ret\n'); + oGen.write('VBINSTST_ENDPROC %s\n' % (sTestFnName,)); + return True; + + + +class InstrTest_DaaDas(InstrTestBase): + """ Tests the DAA and DAS instructions. """ + + def __init__(self, fIsDas): + InstrTestBase.__init__(self, 'das' if fIsDas else 'daa'); + self.fIsDas = fIsDas; + + def isApplicable(self, oGen): + return not oGen.oTarget.is64Bit(); + + def generateTest(self, oGen, sTestFnName): + if self.fIsDas: from itgTableDas import g_aItgDasResults as aItgResults; + else: from itgTableDaa import g_aItgDaaResults as aItgResults; + cMax = len(aItgResults); + if oGen.isTiny(): + cMax = 64; + + oGen.write('VBINSTST_BEGINPROC %s\n' % (sTestFnName,)); + oGen.write(' xor ebx, ebx\n'); + oGen.write('.das_loop:\n'); + # Save the loop variable so we can load known values. + oGen.write(' push ebx\n'); + oGen.newSubTestEx('ebx'); + + # Push the results. + oGen.write(' movzx eax, byte [.abAlResults + ebx]\n'); + oGen.write(' or eax, %#x\n' % (oGen.au32Regs[X86_GREG_xAX] & ~0xff,)); + oGen.write(' push eax\n'); + oGen.write(' movzx eax, byte [.aFlagsResults + ebx]\n'); + oGen.write(' push eax\n'); + # Calc and push the inputs. + oGen.write(' mov eax, ebx\n'); + oGen.write(' shr eax, 2\n'); + oGen.write(' and eax, 0ffh\n'); + oGen.write(' or eax, %#x\n' % (oGen.au32Regs[X86_GREG_xAX] & ~0xff,)); + oGen.write(' push eax\n'); + + oGen.write(' pushfd\n') + oGen.write(' and dword [xSP], ~(X86_EFL_CF | X86_EFL_AF)\n'); + oGen.write(' mov al, bl\n'); + oGen.write(' and al, 2\n'); + oGen.write(' shl al, X86_EFL_AF_BIT - 1\n'); + oGen.write(' or [xSP], al\n'); + oGen.write(' mov al, bl\n'); + oGen.write(' and al, X86_EFL_CF\n'); + oGen.write(' or [xSP], al\n'); + + # Load register values and do the test. + oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n'); + oGen.write(' popfd\n'); + oGen.write(' pop eax\n'); + if self.fIsDas: + oGen.write(' das\n'); + else: + oGen.write(' daa\n'); + + # Verify the results. + fFlagsToCheck = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_ZF; + oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needFlagsGRegChecker(fFlagsToCheck, X86_GREG_xAX),)); + + # Restore the loop variable and advance. + oGen.write(' pop ebx\n'); + oGen.write(' inc ebx\n'); + oGen.write(' cmp ebx, %#x\n' % (cMax,)); + oGen.write(' jb .das_loop\n'); + + oGen.write(' ret\n'); + + oGen.write('.abAlResults:\n'); + for i in range(cMax): + oGen.write(' db %#x\n' % (aItgResults[i][0],)); + + oGen.write('.aFlagsResults:\n'); + for i in range(cMax): + oGen.write(' db %#x\n' % (aItgResults[i][1],)); + + oGen.write('VBINSTST_ENDPROC %s\n' % (sTestFnName,)); + return True; + + +## +# Instruction Tests. +# +g_aoInstructionTests = [ + InstrTest_Mov_Gv_Ev(), + InstrTest_MovSxD_Gv_Ev(), + InstrTest_DivIDiv(fIsIDiv = False), + InstrTest_DivIDiv(fIsIDiv = True), + InstrTest_DaaDas(fIsDas = False), + InstrTest_DaaDas(fIsDas = True), +]; + + + + + +class InstructionTestGen(object): # pylint: disable=R0902 + """ + Instruction Test Generator. + """ + + ## @name Test size + ## @{ + ksTestSize_Large = 'large'; + ksTestSize_Medium = 'medium'; + ksTestSize_Tiny = 'tiny'; + ## @} + kasTestSizes = ( ksTestSize_Large, ksTestSize_Medium, ksTestSize_Tiny ); + + ## The prefix for the checker functions. + ksCheckerPrefix = 'Common_Check_' + + + def __init__(self, oOptions): + self.oOptions = oOptions; + self.oTarget = g_dTargetEnvs[oOptions.sTargetEnv]; + + # Calculate the number of output files. + self.cFiles = 1; + if len(g_aoInstructionTests) > self.oOptions.cInstrPerFile: + self.cFiles = len(g_aoInstructionTests) / self.oOptions.cInstrPerFile; + if self.cFiles * self.oOptions.cInstrPerFile < len(g_aoInstructionTests): + self.cFiles += 1; + + # Fix the known register values. + self.au64Regs = randUxxList(64, 16); + self.au32Regs = [(self.au64Regs[i] & UINT32_MAX) for i in range(8)]; + self.au16Regs = [(self.au64Regs[i] & UINT16_MAX) for i in range(8)]; + self.auRegValues = self.au64Regs if self.oTarget.is64Bit() else self.au32Regs; + + # Declare state variables used while generating. + self.oFile = sys.stderr; + self.iFile = -1; + self.sFile = ''; + self._dCheckFns = dict(); + self._dMemSetupFns = dict(); + self._d64BitConsts = dict(); + + # State variables used while generating test convenientely placed here (lazy bird)... + self.iModReg = 0; + self.iModRm = 0; + self.iSibBaseReg = 0; + self.iSibIndexReg = 0; + self.iSibScale = 1; + if self.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny: + self._oModRegRange = range(2); + self._oModRegRange8 = range(2); + self.oModRmRange = range(2); + self.cSibBasePerRun = 1; + self._cSibIndexPerRun = 2; + self.oSibScaleRange = range(1); + elif self.oOptions.sTestSize == InstructionTestGen.ksTestSize_Medium: + self._oModRegRange = range( 5 if self.oTarget.is64Bit() else 4); + self._oModRegRange8 = range( 6 if self.oTarget.is64Bit() else 4); + self.oModRmRange = range(5); + self.cSibBasePerRun = 5; + self._cSibIndexPerRun = 4 + self.oSibScaleRange = range(2); + else: + self._oModRegRange = range(16 if self.oTarget.is64Bit() else 8); + self._oModRegRange8 = range(20 if self.oTarget.is64Bit() else 8); + self.oModRmRange = range(16 if self.oTarget.is64Bit() else 8); + self.cSibBasePerRun = 8; + self._cSibIndexPerRun = 9; + self.oSibScaleRange = range(4); + self.iSibIndexRange = 0; + + + # + # Methods used by instruction tests. + # + + def write(self, sText): + """ Writes to the current output file. """ + return self.oFile.write(unicode(sText)); + + def writeln(self, sText): + """ Writes a line to the current output file. """ + self.write(sText); + return self.write('\n'); + + def writeInstrBytes(self, abInstr): + """ + Emits an instruction given as a sequence of bytes values. + """ + self.write(' db %#04x' % (abInstr[0],)); + for i in range(1, len(abInstr)): + self.write(', %#04x' % (abInstr[i],)); + return self.write('\n'); + + def newSubTest(self): + """ + Indicates that a new subtest has started. + """ + self.write(' mov dword [VBINSTST_NAME(g_uVBInsTstSubTestIndicator) xWrtRIP], __LINE__\n'); + return True; + + def newSubTestEx(self, sIndicator): + """ + Indicates that a new subtest has started. + """ + self.write(' mov dword [VBINSTST_NAME(g_uVBInsTstSubTestIndicator) xWrtRIP], %s\n' % (sIndicator, )); + return True; + + def needGRegChecker(self, iReg1, iReg2 = None, iReg3 = None): + """ + Records the need for a given register checker function, returning its label. + """ + if iReg2 is not None: + if iReg3 is not None: + sName = '%s_%s_%s' % (self.oTarget.asGRegs[iReg1], self.oTarget.asGRegs[iReg2], self.oTarget.asGRegs[iReg3],); + else: + sName = '%s_%s' % (self.oTarget.asGRegs[iReg1], self.oTarget.asGRegs[iReg2],); + else: + sName = '%s' % (self.oTarget.asGRegs[iReg1],); + assert iReg3 is None; + + if sName in self._dCheckFns: + self._dCheckFns[sName] += 1; + else: + self._dCheckFns[sName] = 1; + + return self.ksCheckerPrefix + sName; + + def needFlagsGRegChecker(self, fFlagsToCheck, iReg1, iReg2 = None, iReg3 = None): + """ + Records the need for a given rFLAGS + register checker function, returning its label. + """ + sWorkerName = self.needGRegChecker(iReg1, iReg2, iReg3); + + sName = 'eflags_%#x_%s' % (fFlagsToCheck, sWorkerName[len(self.ksCheckerPrefix):]); + if sName in self._dCheckFns: + self._dCheckFns[sName] += 1; + else: + self._dCheckFns[sName] = 1; + + return self.ksCheckerPrefix + sName; + + def needGRegMemSetup(self, cAddrBits, cbEffOp, iBaseReg = None, offDisp = None, iIndexReg = None, iScale = 1): + """ + Records the need for a given register checker function, returning its label. + """ + assert cAddrBits in [64, 32, 16]; + assert cbEffOp in [8, 4, 2, 1]; + assert iScale in [1, 2, 4, 8]; + + sName = '%ubit_U%u' % (cAddrBits, cbEffOp * 8,); + if iBaseReg is not None: + sName += '_%s' % (gregName(iBaseReg, cAddrBits),); + sName += '_x%u' % (iScale,); + if iIndexReg is not None: + sName += '_%s' % (gregName(iIndexReg, cAddrBits),); + if offDisp is not None: + sName += '_%#010x' % (offDisp & UINT32_MAX, ); + if sName in self._dMemSetupFns: + self._dMemSetupFns[sName] += 1; + else: + self._dMemSetupFns[sName] = 1; + return 'Common_MemSetup_' + sName; + + def need64BitConstant(self, uVal): + """ + Records the need for a 64-bit constant, returning its label. + These constants are pooled to attempt reduce the size of the whole thing. + """ + assert uVal >= 0 and uVal <= UINT64_MAX; + if uVal in self._d64BitConsts: + self._d64BitConsts[uVal] += 1; + else: + self._d64BitConsts[uVal] = 1; + return 'g_u64Const_0x%016x' % (uVal, ); + + def pushConst(self, uResult): + """ + Emits a push constant value, taking care of high values on 64-bit hosts. + """ + if self.oTarget.is64Bit() and uResult >= 0x80000000: + self.write(' push qword [%s wrt rip]\n' % (self.need64BitConstant(uResult),)); + else: + self.write(' push dword 0x%x\n' % (uResult,)); + return True; + + def getDispForMod(self, iMod, cbAlignment = 1): + """ + Get a set of address dispositions for a given addressing mode. + The alignment restriction is for SIB scaling. + """ + assert cbAlignment in [1, 2, 4, 8]; + if iMod == 0: + aoffDisp = [ None, ]; + elif iMod == 1: + aoffDisp = [ 127 & ~(cbAlignment - 1), -128 ]; + elif iMod == 2: + aoffDisp = [ 2147483647 & ~(cbAlignment - 1), -2147483648 ]; + else: assert False; + return aoffDisp; + + def getModRegRange(self, cbEffOp): + """ + The Mod R/M register range varies with the effective operand size, for + 8-bit registers we have 4 more. + """ + if cbEffOp == 1: + return self._oModRegRange8; + return self._oModRegRange; + + def getSibIndexPerRun(self): + """ + We vary the SIB index test range a little to try cover more operand + combinations and avoid repeating the same ones. + """ + self.iSibIndexRange += 1; + self.iSibIndexRange %= 3; + if self.iSibIndexRange == 0: + return self._cSibIndexPerRun - 1; + return self._cSibIndexPerRun; + + def isTiny(self): + """ Checks if we're in tiny mode.""" + return self.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny; + + def isMedium(self): + """ Checks if we're in medium mode.""" + return self.oOptions.sTestSize == InstructionTestGen.ksTestSize_Medium; + + + # + # Forwarding calls for oTarget to shorted typing and lessen the attacks + # on the right margin. + # + + def gregNameBits(self, iReg, cBitsWide): + """ Target: Get the name of a general register for the given size (in bits). """ + return self.oTarget.gregNameBits(iReg, cBitsWide); + + def gregNameBytes(self, iReg, cbWide): + """ Target: Get the name of a general register for the given size (in bytes). """ + return self.oTarget.gregNameBytes(iReg, cbWide); + + def is64Bit(self): + """ Target: Is the target 64-bit? """ + return self.oTarget.is64Bit(); + + + # + # Internal machinery. + # + + def _randInitIndexes(self): + """ + Initializes the Mod R/M and SIB state index with random numbers prior + to generating a test. + + Note! As with all other randomness and variations we do, we cannot + test all combinations for each and every instruction so we try + get coverage over time. + """ + self.iModReg = randU8(); + self.iModRm = randU8(); + self.iSibBaseReg = randU8(); + self.iSibIndexReg = randU8(); + self.iSibScale = 1 << (randU8() & 3); + self.iSibIndexRange = randU8(); + return True; + + def _calcTestFunctionName(self, oInstrTest, iInstrTest): + """ + Calc a test function name for the given instruction test. + """ + sName = 'TestInstr%03u_%s' % (iInstrTest, oInstrTest.sName); + return sName.replace(',', '_').replace(' ', '_').replace('%', '_'); + + def _generateFileHeader(self, ): + """ + Writes the file header. + Raises exception on trouble. + """ + self.write('; $Id: InstructionTestGen.py $\n' + ';; @file %s\n' + '; Autogenerate by %s %s. DO NOT EDIT\n' + ';\n' + '\n' + ';\n' + '; Headers\n' + ';\n' + '%%include "env-%s.mac"\n' + % ( os.path.basename(self.sFile), + os.path.basename(__file__), __version__[11:-1], + self.oTarget.sName, + ) ); + # Target environment specific init stuff. + + # + # Global variables. + # + self.write('\n\n' + ';\n' + '; Globals\n' + ';\n'); + self.write('VBINSTST_BEGINDATA\n' + 'VBINSTST_GLOBALNAME_EX g_pvLow16Mem4K, data hidden\n' + ' dq 0\n' + 'VBINSTST_GLOBALNAME_EX g_pvLow32Mem4K, data hidden\n' + ' dq 0\n' + 'VBINSTST_GLOBALNAME_EX g_pvMem4K, data hidden\n' + ' dq 0\n' + 'VBINSTST_GLOBALNAME_EX g_uVBInsTstSubTestIndicator, data hidden\n' + ' dd 0\n' + '%ifdef VBINSTST_CAN_DO_TRAPS\n' + 'VBINSTST_TRAP_RECS_BEGIN\n' + '%endif\n' + 'VBINSTST_BEGINCODE\n' + ); + self.write('%ifdef RT_ARCH_AMD64\n'); + for i in range(len(g_asGRegs64)): + self.write('g_u64KnownValue_%s: dq 0x%x\n' % (g_asGRegs64[i], self.au64Regs[i])); + self.write('%endif\n\n') + + # + # Common functions. + # + + # Loading common values. + self.write('\n\n' + 'VBINSTST_BEGINPROC Common_LoadKnownValues\n' + '%ifdef RT_ARCH_AMD64\n'); + for i in range(len(g_asGRegs64NoSp)): + if g_asGRegs64NoSp[i]: + self.write(' mov %s, 0x%x\n' % (g_asGRegs64NoSp[i], self.au64Regs[i],)); + self.write('%else\n'); + for i in range(8): + if g_asGRegs32NoSp[i]: + self.write(' mov %s, 0x%x\n' % (g_asGRegs32NoSp[i], self.au32Regs[i],)); + self.write('%endif\n' + ' ret\n' + 'VBINSTST_ENDPROC Common_LoadKnownValues\n' + '\n'); + + self.write('VBINSTST_BEGINPROC Common_CheckKnownValues\n' + '%ifdef RT_ARCH_AMD64\n'); + for i in range(len(g_asGRegs64NoSp)): + if g_asGRegs64NoSp[i]: + self.write(' cmp %s, [g_u64KnownValue_%s wrt rip]\n' + ' je .ok_%u\n' + ' push %u ; register number\n' + ' push %s ; actual\n' + ' push qword [g_u64KnownValue_%s wrt rip] ; expected\n' + ' call VBINSTST_NAME(Common_BadValue)\n' + '.ok_%u:\n' + % ( g_asGRegs64NoSp[i], g_asGRegs64NoSp[i], i, i, g_asGRegs64NoSp[i], g_asGRegs64NoSp[i], i,)); + self.write('%else\n'); + for i in range(8): + if g_asGRegs32NoSp[i]: + self.write(' cmp %s, 0x%x\n' + ' je .ok_%u\n' + ' push %u ; register number\n' + ' push %s ; actual\n' + ' push dword 0x%x ; expected\n' + ' call VBINSTST_NAME(Common_BadValue)\n' + '.ok_%u:\n' + % ( g_asGRegs32NoSp[i], self.au32Regs[i], i, i, g_asGRegs32NoSp[i], self.au32Regs[i], i,)); + self.write('%endif\n' + ' ret\n' + 'VBINSTST_ENDPROC Common_CheckKnownValues\n' + '\n'); + + return True; + + def _generateMemSetupFunctions(self): # pylint: disable=R0915 + """ + Generates the memory setup functions. + """ + cDefAddrBits = self.oTarget.getDefAddrBits(); + for sName in self._dMemSetupFns: + # Unpack it. + asParams = sName.split('_'); + cAddrBits = int(asParams[0][:-3]); assert asParams[0][-3:] == 'bit'; + cEffOpBits = int(asParams[1][1:]); assert asParams[1][0] == 'U'; + if cAddrBits == 64: asAddrGRegs = g_asGRegs64; + elif cAddrBits == 32: asAddrGRegs = g_asGRegs32; + else: asAddrGRegs = g_asGRegs16; + + i = 2; + iBaseReg = None; + sBaseReg = None; + if i < len(asParams) and asParams[i] in asAddrGRegs: + sBaseReg = asParams[i]; + iBaseReg = asAddrGRegs.index(sBaseReg); + i += 1 + + assert i < len(asParams); assert asParams[i][0] == 'x'; + iScale = iScale = int(asParams[i][1:]); assert iScale in [1, 2, 4, 8], '%u %s' % (iScale, sName); + i += 1; + + sIndexReg = None; + iIndexReg = None; + if i < len(asParams) and asParams[i] in asAddrGRegs: + sIndexReg = asParams[i]; + iIndexReg = asAddrGRegs.index(sIndexReg); + i += 1; + + u32Disp = None; + if i < len(asParams) and len(asParams[i]) == 10: + u32Disp = long(asParams[i], 16); + i += 1; + + assert i == len(asParams), 'i=%d len=%d len[i]=%d (%s)' % (i, len(asParams), len(asParams[i]), asParams[i],); + assert iScale == 1 or iIndexReg is not None; + + # Find a temporary register. + iTmpReg1 = X86_GREG_xCX; + while iTmpReg1 in [iBaseReg, iIndexReg]: + iTmpReg1 += 1; + + # Prologue. + self.write('\n\n' + '; cAddrBits=%s cEffOpBits=%s iBaseReg=%s u32Disp=%s iIndexReg=%s iScale=%s\n' + 'VBINSTST_BEGINPROC Common_MemSetup_%s\n' + ' MY_PUSH_FLAGS\n' + ' push %s\n' + % ( cAddrBits, cEffOpBits, iBaseReg, u32Disp, iIndexReg, iScale, + sName, self.oTarget.asGRegs[iTmpReg1], )); + + # Figure out what to use. + if cEffOpBits == 64: + sTmpReg1 = g_asGRegs64[iTmpReg1]; + sDataVar = 'VBINSTST_NAME(g_u64Data)'; + elif cEffOpBits == 32: + sTmpReg1 = g_asGRegs32[iTmpReg1]; + sDataVar = 'VBINSTST_NAME(g_u32Data)'; + elif cEffOpBits == 16: + sTmpReg1 = g_asGRegs16[iTmpReg1]; + sDataVar = 'VBINSTST_NAME(g_u16Data)'; + else: + assert cEffOpBits == 8; assert iTmpReg1 < 4; + sTmpReg1 = g_asGRegs8Rex[iTmpReg1]; + sDataVar = 'VBINSTST_NAME(g_u8Data)'; + + # Special case: reg + reg * [2,4,8] + if iBaseReg == iIndexReg and iBaseReg is not None and iScale != 1: + iTmpReg2 = X86_GREG_xBP; + while iTmpReg2 in [iBaseReg, iIndexReg, iTmpReg1]: + iTmpReg2 += 1; + sTmpReg2 = self.gregNameBits(iTmpReg2, cAddrBits); + self.write(' push sAX\n' + ' push %s\n' + ' push sDX\n' + % (self.oTarget.asGRegs[iTmpReg2],)); + if cAddrBits == 16: + self.write(' mov %s, [VBINSTST_NAME(g_pvLow16Mem4K) xWrtRIP]\n' % (sTmpReg2,)); + else: + self.write(' mov %s, [VBINSTST_NAME(g_pvLow32Mem4K) xWrtRIP]\n' % (sTmpReg2,)); + self.write(' add %s, 0x200\n' % (sTmpReg2,)); + self.write(' mov %s, %s\n' % (self.gregNameBits(X86_GREG_xAX, cAddrBits), sTmpReg2,)); + if u32Disp is not None: + self.write(' sub %s, %d\n' + % ( self.gregNameBits(X86_GREG_xAX, cAddrBits), convU32ToSigned(u32Disp), )); + self.write(' xor edx, edx\n' + '%if xCB == 2\n' + ' push 0\n' + '%endif\n'); + self.write(' push %u\n' % (iScale + 1,)); + self.write(' div %s [xSP]\n' % ('qword' if cAddrBits == 64 else 'dword',)); + self.write(' sub %s, %s\n' % (sTmpReg2, self.gregNameBits(X86_GREG_xDX, cAddrBits),)); + self.write(' pop sDX\n' + ' pop sDX\n'); # sTmpReg2 is eff address; sAX is sIndexReg value. + # Note! sTmpReg1 can be xDX and that's no problem now. + self.write(' mov %s, [xSP + sCB*3 + MY_PUSH_FLAGS_SIZE + xCB]\n' % (sTmpReg1,)); + self.write(' mov [%s], %s\n' % (sTmpReg2, sTmpReg1,)); # Value in place. + self.write(' pop %s\n' % (self.oTarget.asGRegs[iTmpReg2],)); + if iBaseReg == X86_GREG_xAX: + self.write(' pop %s\n' % (self.oTarget.asGRegs[iTmpReg1],)); + else: + self.write(' mov %s, %s\n' % (sBaseReg, self.gregNameBits(X86_GREG_xAX, cAddrBits),)); + self.write(' pop sAX\n'); + + else: + # Load the value and mem address, storing the value there. + # Note! ASSUMES that the scale and disposition works fine together. + sAddrReg = sBaseReg if sBaseReg is not None else sIndexReg; + self.write(' mov %s, [xSP + sCB + MY_PUSH_FLAGS_SIZE + xCB]\n' % (sTmpReg1,)); + if cAddrBits >= cDefAddrBits: + self.write(' mov [%s xWrtRIP], %s\n' % (sDataVar, sTmpReg1,)); + self.write(' lea %s, [%s xWrtRIP]\n' % (sAddrReg, sDataVar,)); + else: + if cAddrBits == 16: + self.write(' mov %s, [VBINSTST_NAME(g_pvLow16Mem4K) xWrtRIP]\n' % (sAddrReg,)); + else: + self.write(' mov %s, [VBINSTST_NAME(g_pvLow32Mem4K) xWrtRIP]\n' % (sAddrReg,)); + self.write(' add %s, %s\n' % (sAddrReg, (randU16() << cEffOpBits) & 0xfff, )); + self.write(' mov [%s], %s\n' % (sAddrReg, sTmpReg1, )); + + # Adjust for disposition and scaling. + if u32Disp is not None: + self.write(' sub %s, %d\n' % ( sAddrReg, convU32ToSigned(u32Disp), )); + if iIndexReg is not None: + if iBaseReg == iIndexReg: + assert iScale == 1; + assert u32Disp is None or (u32Disp & 1) == 0; + self.write(' shr %s, 1\n' % (sIndexReg,)); + elif sBaseReg is not None: + uIdxRegVal = randUxx(cAddrBits); + if cAddrBits == 64: + self.write(' mov %s, %u\n' + ' sub %s, %s\n' + ' mov %s, %u\n' + % ( sIndexReg, (uIdxRegVal * iScale) & UINT64_MAX, + sBaseReg, sIndexReg, + sIndexReg, uIdxRegVal, )); + else: + assert cAddrBits == 32; + self.write(' mov %s, %u\n' + ' sub %s, %#06x\n' + % ( sIndexReg, uIdxRegVal, sBaseReg, (uIdxRegVal * iScale) & UINT32_MAX, )); + elif iScale == 2: + assert u32Disp is None or (u32Disp & 1) == 0; + self.write(' shr %s, 1\n' % (sIndexReg,)); + elif iScale == 4: + assert u32Disp is None or (u32Disp & 3) == 0; + self.write(' shr %s, 2\n' % (sIndexReg,)); + elif iScale == 8: + assert u32Disp is None or (u32Disp & 7) == 0; + self.write(' shr %s, 3\n' % (sIndexReg,)); + else: + assert iScale == 1; + + # Set upper bits that's supposed to be unused. + if cDefAddrBits > cAddrBits or cAddrBits == 16: + if cDefAddrBits == 64: + assert cAddrBits == 32; + if iBaseReg is not None: + self.write(' mov %s, %#018x\n' + ' or %s, %s\n' + % ( g_asGRegs64[iTmpReg1], randU64() & 0xffffffff00000000, + g_asGRegs64[iBaseReg], g_asGRegs64[iTmpReg1],)); + if iIndexReg is not None and iIndexReg != iBaseReg: + self.write(' mov %s, %#018x\n' + ' or %s, %s\n' + % ( g_asGRegs64[iTmpReg1], randU64() & 0xffffffff00000000, + g_asGRegs64[iIndexReg], g_asGRegs64[iTmpReg1],)); + else: + assert cDefAddrBits == 32; assert cAddrBits == 16; assert iIndexReg is None; + if iBaseReg is not None: + self.write(' or %s, %#010x\n' + % ( g_asGRegs32[iBaseReg], randU32() & 0xffff0000, )); + + # Epilogue. + self.write(' pop %s\n' + ' MY_POP_FLAGS\n' + ' ret sCB\n' + 'VBINSTST_ENDPROC Common_MemSetup_%s\n' + % ( self.oTarget.asGRegs[iTmpReg1], sName,)); + + + def _generateFileFooter(self): + """ + Generates file footer. + """ + + # Terminate the trap records. + self.write('\n\n' + ';\n' + '; Terminate the trap records\n' + ';\n' + 'VBINSTST_BEGINDATA\n' + '%ifdef VBINSTST_CAN_DO_TRAPS\n' + 'VBINSTST_TRAP_RECS_END\n' + '%endif\n' + 'VBINSTST_BEGINCODE\n'); + + # Register checking functions. + for sName in self._dCheckFns: + asRegs = sName.split('_'); + sPushSize = 'dword'; + + # Do we check eflags first. + if asRegs[0] == 'eflags': + asRegs.pop(0); + sFlagsToCheck = asRegs.pop(0); + self.write('\n\n' + '; Check flags and then defers to the register-only checker\n' + '; To save space, the callee cleans up the stack.' + '; Ref count: %u\n' + 'VBINSTST_BEGINPROC %s%s\n' + ' MY_PUSH_FLAGS\n' + ' push sAX\n' + ' mov sAX, [xSP + sCB]\n' + ' and sAX, %s\n' + ' cmp sAX, [xSP + xCB + sCB*2]\n' + ' je .equal\n' + % ( self._dCheckFns[sName], self.ksCheckerPrefix, sName, + sFlagsToCheck,)); + self.write(' push dword 0xef ; register number\n' + ' push sAX ; actual\n' + ' mov sAX, [xSP + xCB + sCB*4]\n' + ' push sAX ; expected\n' + ' call VBINSTST_NAME(Common_BadValue)\n'); + self.write('.equal:\n' + ' mov xAX, [xSP + sCB*2]\n' # Remove the expected eflags value from the stack frame. + ' mov [xSP + sCB*2 + xCB + sCB - xCB], xAX\n' + ' pop sAX\n' + ' MY_POP_FLAGS\n' + ' lea xSP, [xSP + sCB]\n' + ' jmp VBINSTST_NAME(Common_Check_%s)\n' + 'VBINSTST_ENDPROC %s%s\n' + % ( '_'.join(asRegs), + self.ksCheckerPrefix, sName,) ); + else: + # Prologue + self.write('\n\n' + '; Checks 1 or more register values, expected values pushed on the stack.\n' + '; To save space, the callee cleans up the stack.' + '; Ref count: %u\n' + 'VBINSTST_BEGINPROC %s%s\n' + ' MY_PUSH_FLAGS\n' + % ( self._dCheckFns[sName], self.ksCheckerPrefix, sName, ) ); + + # Register checks. + for i in range(len(asRegs)): + sReg = asRegs[i]; + iReg = self.oTarget.asGRegs.index(sReg); + if i == asRegs.index(sReg): # Only check once, i.e. input = output reg. + self.write(' cmp %s, [xSP + MY_PUSH_FLAGS_SIZE + xCB + sCB * %u]\n' + ' je .equal%u\n' + ' push %s %u ; register number\n' + ' push %s ; actual\n' + ' mov %s, [xSP + sCB*2 + MY_PUSH_FLAGS_SIZE + xCB + sCB * %u]\n' + ' push %s ; expected\n' + ' call VBINSTST_NAME(Common_BadValue)\n' + '.equal%u:\n' + % ( sReg, i, i, sPushSize, iReg, sReg, sReg, i, sReg, i, ) ); + + + # Restore known register values and check the other registers. + for sReg in asRegs: + if self.oTarget.is64Bit(): + self.write(' mov %s, [g_u64KnownValue_%s wrt rip]\n' % (sReg, sReg,)); + else: + iReg = self.oTarget.asGRegs.index(sReg) + self.write(' mov %s, 0x%x\n' % (sReg, self.au32Regs[iReg],)); + self.write(' MY_POP_FLAGS\n' + ' call VBINSTST_NAME(Common_CheckKnownValues)\n' + ' ret sCB*%u\n' + 'VBINSTST_ENDPROC %s%s\n' + % (len(asRegs), self.ksCheckerPrefix, sName,)); + + # memory setup functions + self._generateMemSetupFunctions(); + + # 64-bit constants. + if len(self._d64BitConsts) > 0: + self.write('\n\n' + ';\n' + '; 64-bit constants\n' + ';\n'); + for uVal in self._d64BitConsts: + self.write('g_u64Const_0x%016x: dq 0x%016x ; Ref count: %d\n' % (uVal, uVal, self._d64BitConsts[uVal], ) ); + + return True; + + def _generateTests(self): + """ + Generate the test cases. + """ + for self.iFile in range(self.cFiles): + if self.cFiles == 1: + self.sFile = '%s.asm' % (self.oOptions.sOutputBase,) + else: + self.sFile = '%s-%u.asm' % (self.oOptions.sOutputBase, self.iFile) + self.oFile = sys.stdout; + if self.oOptions.sOutputBase != '-': + self.oFile = io.open(self.sFile, 'w', buffering = 65536, encoding = 'utf-8'); + + self._generateFileHeader(); + + # Calc the range. + iInstrTestStart = self.iFile * self.oOptions.cInstrPerFile; + iInstrTestEnd = iInstrTestStart + self.oOptions.cInstrPerFile; + if iInstrTestEnd > len(g_aoInstructionTests): + iInstrTestEnd = len(g_aoInstructionTests); + + # Generate the instruction tests. + for iInstrTest in range(iInstrTestStart, iInstrTestEnd): + oInstrTest = g_aoInstructionTests[iInstrTest]; + if oInstrTest.isApplicable(self): + self.write('\n' + '\n' + ';\n' + '; %s\n' + ';\n' + % (oInstrTest.sName,)); + self._randInitIndexes(); + oInstrTest.generateTest(self, self._calcTestFunctionName(oInstrTest, iInstrTest)); + + # Generate the main function. + self.write('\n\n' + 'VBINSTST_BEGINPROC TestInstrMain\n' + ' MY_PUSH_ALL\n' + ' sub xSP, 40h\n' + '%ifdef VBINSTST_CAN_DO_TRAPS\n' + ' VBINSTST_TRAP_RECS_INSTALL\n' + '%endif\n' + '\n'); + + for iInstrTest in range(iInstrTestStart, iInstrTestEnd): + oInstrTest = g_aoInstructionTests[iInstrTest]; + if oInstrTest.isApplicable(self): + self.write('%%ifdef ASM_CALL64_GCC\n' + ' lea rdi, [.szInstr%03u wrt rip]\n' + '%%elifdef ASM_CALL64_MSC\n' + ' lea rcx, [.szInstr%03u wrt rip]\n' + '%%else\n' + ' mov xAX, .szInstr%03u\n' + ' mov [xSP], xAX\n' + '%%endif\n' + ' VBINSTST_CALL_FN_SUB_TEST\n' + ' call VBINSTST_NAME(%s)\n' + % ( iInstrTest, iInstrTest, iInstrTest, self._calcTestFunctionName(oInstrTest, iInstrTest))); + + self.write('\n' + '%ifdef VBINSTST_CAN_DO_TRAPS\n' + ' VBINSTST_TRAP_RECS_UNINSTALL\n' + '%endif\n' + ' add xSP, 40h\n' + ' MY_POP_ALL\n' + ' ret\n\n'); + for iInstrTest in range(iInstrTestStart, iInstrTestEnd): + self.write('.szInstr%03u: db \'%s\', 0\n' % (iInstrTest, g_aoInstructionTests[iInstrTest].sName,)); + self.write('VBINSTST_ENDPROC TestInstrMain\n\n'); + + self._generateFileFooter(); + if self.oOptions.sOutputBase != '-': + self.oFile.close(); + self.oFile = None; + self.sFile = ''; + + return RTEXITCODE_SUCCESS; + + def _runMakefileMode(self): + """ + Generate a list of output files on standard output. + """ + if self.cFiles == 1: + print('%s.asm' % (self.oOptions.sOutputBase,)); + else: + print(' '.join('%s-%s.asm' % (self.oOptions.sOutputBase, i) for i in range(self.cFiles))); + return RTEXITCODE_SUCCESS; + + def run(self): + """ + Generates the tests or whatever is required. + """ + if self.oOptions.fMakefileMode: + return self._runMakefileMode(); + sys.stderr.write('InstructionTestGen.py: Seed = %s\n' % (g_iMyRandSeed,)); + return self._generateTests(); + + @staticmethod + def main(): + """ + Main function a la C/C++. Returns exit code. + """ + + # + # Parse the command line. + # + oParser = OptionParser(version = __version__[11:-1].strip()); + oParser.add_option('--makefile-mode', dest = 'fMakefileMode', action = 'store_true', default = False, + help = 'Special mode for use to output a list of output files for the benefit of ' + 'the make program (kmk).'); + oParser.add_option('--split', dest = 'cInstrPerFile', metavar = '', type = 'int', default = 9999999, + help = 'Number of instruction to test per output file.'); + oParser.add_option('--output-base', dest = 'sOutputBase', metavar = '', default = None, + help = 'The output file base name, no suffix please. Required.'); + oParser.add_option('--target', dest = 'sTargetEnv', metavar = '', + default = 'iprt-r3-32', + choices = g_dTargetEnvs.keys(), + help = 'The target environment. Choices: %s' + % (', '.join(sorted(g_dTargetEnvs.keys())),)); + oParser.add_option('--test-size', dest = 'sTestSize', default = InstructionTestGen.ksTestSize_Medium, + choices = InstructionTestGen.kasTestSizes, + help = 'Selects the test size.'); + + (oOptions, asArgs) = oParser.parse_args(); + if len(asArgs) > 0: + oParser.print_help(); + return RTEXITCODE_SYNTAX + if oOptions.sOutputBase is None: + print('syntax error: Missing required option --output-base.', file = sys.stderr); + return RTEXITCODE_SYNTAX + + # + # Instantiate the program class and run it. + # + oProgram = InstructionTestGen(oOptions); + return oProgram.run(); + + +if __name__ == '__main__': + sys.exit(InstructionTestGen.main()); + diff --git a/src/VBox/VMM/testcase/Instructions/Makefile.kmk b/src/VBox/VMM/testcase/Instructions/Makefile.kmk new file mode 100644 index 00000000..90527b77 --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/Makefile.kmk @@ -0,0 +1,69 @@ +# $Id: Makefile.kmk $ +## @file +# Sub-Makefile for the X86 and AMD64 Instruction Tests. +# + +# +# Copyright (C) 2006-2019 Oracle Corporation +# +# This file is part of VirtualBox Open Source Edition (OSE), as +# available from http://www.virtualbox.org. This file is free software; +# you can redistribute it and/or modify it under the terms of the GNU +# General Public License (GPL) as published by the Free Software +# Foundation, in version 2 as it comes in the "COPYING" file of the +# VirtualBox OSE distribution. VirtualBox OSE is distributed in the +# hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +# + +SUB_DEPTH = ../../../../.. +include $(KBUILD_PATH)/subheader.kmk + +# +# Python linting (can't live without pylint!). +# +ifdef VBOX_WITH_PYLINT +TESTING += +endif +BLDDIRS += $(PATH_TARGET)/pylint + +define def_vbox_instructions_py_check +$(eval name:=$(basename $(notdir $(py)))) + +pylint:: $(name)-py-phony.o +$(name).o: $(name)-py-phony.o +$(PATH_TARGET)/pylint/$(name).o $(name)-py-phony.o:: $(py) | $(PATH_TARGET)/pylint/ +ifdef VBOX_WITH_PYLINT + $(QUIET2)$(call MSG_L1,Subjecting $(py) to pylint...) + $(QUIET)$(REDIRECT_EXT) -E LC_ALL=C -E PYTHONPATH="$(dir $(py))" -C $(dir $(py)) \ + -- $$(VBOX_PYLINT) $$(VBOX_PYLINT_FLAGS) $$($(py)_VBOX_PYLINT_FLAGS) ./$(notdir $(py)) +endif + $(QUIET)$(APPEND) -t "$(PATH_TARGET)/pylint/$(name).o" + +TESTING += $(name)-py-phony.o +endef # def_vbox_instructions_py_check + + +$(foreach py, $(addprefix $(PATH_SUB_CURRENT)/, InstructionTestGen.py ) , $(eval $(def_vbox_instructions_py_check))) + + + +# +# Ring-3 test program based on IPRT. +# +PROGRAMS += tstVBInsTstR3 +tstVBInsTstR3_TEMPLATE = VBOXR3TSTEXE +tstVBInsTstR3_INCS = . +tstVBInsTstR3_SOURCES = \ + tstVBInsTstR3.cpp \ + $(tstVBInsTstR3_0_OUTDIR)/tstVBInsTstR3A.asm +tstVBInsTstR3_CLEAN = \ + $(tstVBInsTstR3_0_OUTDIR)/tstVBInsTstR3A.asm + +$$(tstVBInsTstR3_0_OUTDIR)/tstVBInsTstR3A.asm: $(PATH_SUB_CURRENT)/InstructionTestGen.py + $(VBOX_BLD_PYTHON) $(PATH_SUB_CURRENT)/InstructionTestGen.py \ + --target iprt-r3-$(if-expr $(intersects $(KBUILD_TARGET_ARCH), $(KBUILD_ARCHES_64)),64,32) \ + --output-base $(basename $@) + + +include $(FILE_KBUILD_SUB_FOOTER) + diff --git a/src/VBox/VMM/testcase/Instructions/env-bs2-r0-32-big.mac b/src/VBox/VMM/testcase/Instructions/env-bs2-r0-32-big.mac new file mode 100644 index 00000000..309ca880 --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/env-bs2-r0-32-big.mac @@ -0,0 +1,35 @@ +; $Id: env-bs2-r0-32-big.mac $ +;; @file +; Instruction Test Environment - Big Boot Sector Type 2, Ring-0, 64-Bit. +; + +; +; Copyright (C) 2006-2019 Oracle Corporation +; +; This file is part of VirtualBox Open Source Edition (OSE), as +; available from http://www.virtualbox.org. This file is free software; +; you can redistribute it and/or modify it under the terms of the GNU +; General Public License (GPL) as published by the Free Software +; Foundation, in version 2 as it comes in the "COPYING" file of the +; VirtualBox OSE distribution. VirtualBox OSE is distributed in the +; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +; + +%undef RT_ARCH_AMD64 +%undef RT_ARCH_X86 +%undef RT_ARCH_X86_32 +%undef RT_ARCH_X86_16 +%undef ASM_CALL64_MSC +%undef ASM_CALL64_GCC +%undef ASM_CALL64_BS2 +%undef ARCH_BITS +%undef xWrtRIP + +%define ARCH_BITS 32 +%define RT_ARCH_X86 +%define ASM_CALL32_BS2 +%define xWrtRIP +%define RTCCPTR_PRE dword + +%include "env-bs2-r0-big.mac" + diff --git a/src/VBox/VMM/testcase/Instructions/env-bs2-r0-64-big.mac b/src/VBox/VMM/testcase/Instructions/env-bs2-r0-64-big.mac new file mode 100644 index 00000000..c1346823 --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/env-bs2-r0-64-big.mac @@ -0,0 +1,35 @@ +; $Id: env-bs2-r0-64-big.mac $ +;; @file +; Instruction Test Environment - Big Boot Sector Type 2, Ring-0, 64-Bit. +; + +; +; Copyright (C) 2006-2019 Oracle Corporation +; +; This file is part of VirtualBox Open Source Edition (OSE), as +; available from http://www.virtualbox.org. This file is free software; +; you can redistribute it and/or modify it under the terms of the GNU +; General Public License (GPL) as published by the Free Software +; Foundation, in version 2 as it comes in the "COPYING" file of the +; VirtualBox OSE distribution. VirtualBox OSE is distributed in the +; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +; + +%undef RT_ARCH_AMD64 +%undef RT_ARCH_X86 +%undef RT_ARCH_X86_32 +%undef RT_ARCH_X86_16 +%undef ASM_CALL64_MSC +%undef ASM_CALL64_GCC +%undef ASM_CALL64_BS2 +%undef ARCH_BITS +%undef xWrtRIP + +%define ARCH_BITS 64 +%define RT_ARCH_AMD64 +%define ASM_CALL64_BS2 +%define xWrtRIP wrt rip +%define RTCCPTR_PRE qword + +%include "env-bs2-r0-big.mac" + diff --git a/src/VBox/VMM/testcase/Instructions/env-bs2-r0-64.mac b/src/VBox/VMM/testcase/Instructions/env-bs2-r0-64.mac new file mode 100644 index 00000000..c58792cf --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/env-bs2-r0-64.mac @@ -0,0 +1,35 @@ +; $Id: env-bs2-r0-64.mac $ +;; @file +; Instruction Test Environment - Boot Sector Type 2, Ring-0, 64-Bit. +; + +; +; Copyright (C) 2006-2019 Oracle Corporation +; +; This file is part of VirtualBox Open Source Edition (OSE), as +; available from http://www.virtualbox.org. This file is free software; +; you can redistribute it and/or modify it under the terms of the GNU +; General Public License (GPL) as published by the Free Software +; Foundation, in version 2 as it comes in the "COPYING" file of the +; VirtualBox OSE distribution. VirtualBox OSE is distributed in the +; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +; + +%undef RT_ARCH_AMD64 +%undef RT_ARCH_X86 +%undef RT_ARCH_X86_32 +%undef RT_ARCH_X86_16 +%undef ASM_CALL64_MSC +%undef ASM_CALL64_GCC +%undef ASM_CALL64_BS2 +%undef ARCH_BITS +%undef xWrtRIP + +%define ARCH_BITS 64 +%define RT_ARCH_AMD64 +%define ASM_CALL64_BS2 +%define xWrtRIP wrt rip +%define RTCCPTR_PRE qword + +%include "env-bs2-r0.mac" + diff --git a/src/VBox/VMM/testcase/Instructions/env-bs2-r0-big.mac b/src/VBox/VMM/testcase/Instructions/env-bs2-r0-big.mac new file mode 100644 index 00000000..6f503943 --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/env-bs2-r0-big.mac @@ -0,0 +1,57 @@ +; $Id: env-bs2-r0-big.mac $ +;; @file +; Instruction Test Environment - Big Boot Sector Type 2, Ring-0. +; + +; +; Copyright (C) 2006-2019 Oracle Corporation +; +; This file is part of VirtualBox Open Source Edition (OSE), as +; available from http://www.virtualbox.org. This file is free software; +; you can redistribute it and/or modify it under the terms of the GNU +; General Public License (GPL) as published by the Free Software +; Foundation, in version 2 as it comes in the "COPYING" file of the +; VirtualBox OSE distribution. VirtualBox OSE is distributed in the +; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +; + +%ifndef ___env_bs2_r0_big_mac +%define ___env_bs2_r0_big_mac + +; +; Include the BS2 API for BIG images. +; +%include "bootsector2-api.mac" + + +;; Call RTTestISub like function. +%define VBINSTST_CALL_FN_SUB_TEST call [TMPL_NM_CMN(g_pfnTestSub) xWrtRIP] + +;; Call RTTestIFailure like function with simple message. +%define VBINSTST_CALL_FN_FAILURE call [TMPL_NM_CMN(g_pfnTestFailedF) xWrtRIP] + +;; Call RTTestIFailure like function with format message + 1 arg. +%define VBINSTST_CALL_FN_FAILURE_1 call [TMPL_NM_CMN(g_pfnTestFailedF) xWrtRIP] + +;; Call RTTestIFailure like function with format message + 2 args. +%define VBINSTST_CALL_FN_FAILURE_2 call [TMPL_NM_CMN(g_pfnTestFailedF) xWrtRIP] + +;; Call RTTestIFailure like function with format message + 3 args. +%define VBINSTST_CALL_FN_FAILURE_3 call [TMPL_NM_CMN(g_pfnTestFailedF) xWrtRIP] + +;; Call RTTestIFailure like function with format message + 4 args. +%define VBINSTST_CALL_FN_FAILURE_4 call [TMPL_NM_CMN(g_pfnTestFailedF) xWrtRIP] + +;; The image base label (used by the trap macros). +%define VBINSTST_IMAGE_BASE_LABLE bs2_big_image_start + +;; Wrapper for calling TestInstallTrapRecs (used by the trap macros). +%define VBINSTST_CALL_TEST_INSTALL_TRAP_RECS call [TMPL_NM_CMN(g_pfnTestInstallTrapRecs) xWrtRIP] + +; +; Include the common bits (contains code using above macros) +; +%include "env-bs2-r0-common.mac" + +%endif + diff --git a/src/VBox/VMM/testcase/Instructions/env-bs2-r0-common.mac b/src/VBox/VMM/testcase/Instructions/env-bs2-r0-common.mac new file mode 100644 index 00000000..18b6fe24 --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/env-bs2-r0-common.mac @@ -0,0 +1,115 @@ +; $Id: env-bs2-r0-common.mac $ +;; @file +; Instruction Test Environment - Boot Sector Type 2, Ring-0. +; + +; +; Copyright (C) 2006-2019 Oracle Corporation +; +; This file is part of VirtualBox Open Source Edition (OSE), as +; available from http://www.virtualbox.org. This file is free software; +; you can redistribute it and/or modify it under the terms of the GNU +; General Public License (GPL) as published by the Free Software +; Foundation, in version 2 as it comes in the "COPYING" file of the +; VirtualBox OSE distribution. VirtualBox OSE is distributed in the +; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +; + +%ifndef ___env_bs2_r0_common_mac +%define ___env_bs2_r0_common_mac + + +;; Same as BEGINPROC in asmdefs.mac. +%macro VBINSTST_BEGINPROC 1 +VBINSTST_GLOBALNAME_EX %1, function hidden +%endm + +;; Same as ENDPROC in asmdefs.mac. +%macro VBINSTST_ENDPROC 1, +VBINSTST_GLOBALNAME_EX %1 %+ _EndProc, function hidden +%endm + +;; Same as NAME in asmdefs.mac. +%define VBINSTST_NAME(a_Name) TMPL_NM(a_Name) + +;; Same as GLOBALNAME_EX in asmdefs.mac. +%macro VBINSTST_GLOBALNAME_EX 2, +VBINSTST_NAME(%1): +%endmacro + +;; Same as BEGINCODE in asmdefs.mac. +%macro VBINSTST_BEGINCODE 0, +BEGINCODE +%endmacro + +;; Same as BEGINDATA in asmdefs.mac. +%macro VBINSTST_BEGINDATA 0, +BEGINDATA +%endmacro + + +; +; Trap related macros. +; +%define VBINSTST_CAN_DO_TRAPS 1 + +%macro VBINSTST_TRAP_INSTR 3+, + section .traprecs + istruc BS2TRAPREC + at BS2TRAPREC.offWhere, dd (%%trapinstr - VBINSTST_IMAGE_BASE_LABLE) + at BS2TRAPREC.offResumeAddend, db (%%resume - %%trapinstr) + at BS2TRAPREC.u8TrapNo, db %1 + at BS2TRAPREC.u16ErrCd, dw %2 + iend + VBINSTST_BEGINCODE + %if %1 != X86_XCPT_BP + %%trapinstr: + %3 + %else + %3 + %%trapinstr: + %endif + call VBINSTST_NAME(Common_MissingTrap_ %+ %1) + %%resume: +%endmacro + +%macro VBINSTST_TRAP_RECS_BEGIN 0, + VBINSTST_BEGINDATA + section .traprecs progbits valign=8 vfollows=.data align=8 follows=.data + dq 0ffffffffeeeeeeeeh + dq 0ddddddddcccccccch +VBINSTST_GLOBALNAME_EX g_aTrapRecs, hidden + VBINSTST_BEGINCODE +%endmacro + +%macro VBINSTST_TRAP_RECS_END 0, + section .traprecs +VBINSTST_GLOBALNAME_EX g_aTrapRecsEnd, hidden + dq 0ddddddddcccccccch + dq 0ffffffffeeeeeeeeh + VBINSTST_BEGINCODE +%endmacro + +%macro VBINSTST_TRAP_RECS_INSTALL 0, + mov sAX, VBINSTST_NAME(g_aTrapRecs) + mov edx, VBINSTST_NAME(g_aTrapRecsEnd) - VBINSTST_NAME(g_aTrapRecs) + shr edx, BS2TRAPREC_SIZE_SHIFT + mov sCX, VBINSTST_IMAGE_BASE_LABLE + VBINSTST_CALL_TEST_INSTALL_TRAP_RECS +%endmacro + +%macro VBINSTST_TRAP_RECS_UNINSTALL 0, + xor sAX, sAX + xor edx, edx + xor sCX, sCX + VBINSTST_CALL_TEST_INSTALL_TRAP_RECS +%endmacro + + +; +; Include the common bits (contains code using above macros) +; +%include "env-common.mac" + +%endif + diff --git a/src/VBox/VMM/testcase/Instructions/env-bs2-r0.mac b/src/VBox/VMM/testcase/Instructions/env-bs2-r0.mac new file mode 100644 index 00000000..1ee2ec33 --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/env-bs2-r0.mac @@ -0,0 +1,53 @@ +; $Id: env-bs2-r0.mac $ +;; @file +; Instruction Test Environment - Boot Sector Type 2, Ring-0. +; + +; +; Copyright (C) 2006-2019 Oracle Corporation +; +; This file is part of VirtualBox Open Source Edition (OSE), as +; available from http://www.virtualbox.org. This file is free software; +; you can redistribute it and/or modify it under the terms of the GNU +; General Public License (GPL) as published by the Free Software +; Foundation, in version 2 as it comes in the "COPYING" file of the +; VirtualBox OSE distribution. VirtualBox OSE is distributed in the +; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +; + +%ifndef ___env_bs2_r0_mac +%define ___env_bs2_r0_mac + + +;; Call RTTestISub like function. +%define VBINSTST_CALL_FN_SUB_TEST call TMPL_NM_CMN(TestSub) + +;; Call RTTestIFailure like function with simple message. +%define VBINSTST_CALL_FN_FAILURE call TMPL_NM_CMN(TestFailedF) + +;; Call RTTestIFailure like function with format message + 1 arg. +%define VBINSTST_CALL_FN_FAILURE_1 call TMPL_NM_CMN(TestFailedF) + +;; Call RTTestIFailure like function with format message + 2 args. +%define VBINSTST_CALL_FN_FAILURE_2 call TMPL_NM_CMN(TestFailedF) + +;; Call RTTestIFailure like function with format message + 3 args. +%define VBINSTST_CALL_FN_FAILURE_3 call TMPL_NM_CMN(TestFailedF) + +;; Call RTTestIFailure like function with format message + 4 args. +%define VBINSTST_CALL_FN_FAILURE_4 call TMPL_NM_CMN(TestFailedF) + +;; The image base label (used by the trap macros). +%define VBINSTST_IMAGE_BASE_LABLE start + +;; Wrapper for calling TestInstallTrapRecs (used by the trap macros). +%define VBINSTST_CALL_TEST_INSTALL_TRAP_RECS call TMPL_NM_CMN(TestInstallTrapRecs) + + +; +; Include the common bits (contains code using above macros) +; +%include "env-bs2-r0-common.mac" + +%endif + diff --git a/src/VBox/VMM/testcase/Instructions/env-common.mac b/src/VBox/VMM/testcase/Instructions/env-common.mac new file mode 100644 index 00000000..9afbc404 --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/env-common.mac @@ -0,0 +1,346 @@ +; $Id: env-common.mac $ +;; @file +; Instruction Test Environment - Common Bits. +; + +; +; Copyright (C) 2006-2019 Oracle Corporation +; +; This file is part of VirtualBox Open Source Edition (OSE), as +; available from http://www.virtualbox.org. This file is free software; +; you can redistribute it and/or modify it under the terms of the GNU +; General Public License (GPL) as published by the Free Software +; Foundation, in version 2 as it comes in the "COPYING" file of the +; VirtualBox OSE distribution. VirtualBox OSE is distributed in the +; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +; + +%ifndef ___env_common_mac +%define ___env_common_mac + +%include "iprt/x86.mac" + +;******************************************************************************* +;* Defined Constants And Macros * +;******************************************************************************* +%ifdef RT_ARCH_AMD64 + %define MY_PUSH_FLAGS pushfq + %define MY_POP_FLAGS popfq + %define MY_PUSH_FLAGS_SIZE 8 + + %macro MY_PUSH_ALL 0 + push rbp + mov rbp, rsp + push rax + push rbx + push rcx + push rdx + push rsi + push rdi + push r8 + push r9 + push r10 + push r11 + push r12 + push r13 + push r14 + push r15 + pushfq + %endm + %macro MY_POP_ALL 0 + popfq + pop r15 + pop r14 + pop r13 + pop r12 + pop r11 + pop r10 + pop r9 + pop r8 + pop rdi + pop rsi + pop rdx + pop rcx + pop rbx + pop rax + pop rbp + %endm + +%else + %define MY_PUSH_FLAGS pushfd + %define MY_POP_FLAGS popfd + %define MY_PUSH_FLAGS_SIZE 4 + + %macro MY_PUSH_ALL 0 + push eBP + mov xBP, xSP + push eax + push ebx + push ecx + push edx + push esi + push edi + pushfd + %endm + %macro MY_POP_ALL 0 + popfd + pop edi + pop esi + pop edx + pop ecx + pop ebx + pop eax + pop ebp + %endm +%endif + + + +;******************************************************************************* +;* Internal Functions * +;******************************************************************************* + +VBINSTST_BEGINCODE + +;; +; Report bad register value. +; +; Primary purpose is save all registers and convert from our stack-based to +; the correct calling convention for the environment. +; +; This function will clean up the stack upon return (to save space in the caller). +; +; @param uExpected +; @param uActual +; @param uRegisterNo +; +VBINSTST_BEGINPROC Common_BadValue + MY_PUSH_ALL + mov xAX, xSP ; 16-byte align the stack and reserve space for arguments and stuff. + sub xSP, 40h + and xSP, ~15 + mov [xSP + 38h], xAX + +%ifdef ASM_CALL64_GCC + mov r8d, [VBINSTST_NAME(g_uVBInsTstSubTestIndicator) wrt rip] + mov rcx, [rbp + 10h] ; expected + mov rdx, [rbp + 18h] ; actual + mov rsi, [rbp + 20h] ; reg# + lea rdi, [.szFmt wrt rip] + VBINSTST_CALL_FN_FAILURE_4 + +%elifdef ASM_CALL64_MSC + mov r10d, [VBINSTST_NAME(g_uVBInsTstSubTestIndicator) wrt rip] + mov [rsp + 20h], r10 + mov r9, [rbp + 10h] ; expected + mov r8, [rbp + 18h] ; actual + mov rdx, [rbp + 20h] ; reg# + lea rcx, [.szFmt wrt rip] + VBINSTST_CALL_FN_FAILURE_4 + +%elifdef ASM_CALL64_BS2 + mov sBX, [VBINSTST_NAME(g_uVBInsTstSubTestIndicator) xWrtRIP] + mov sCX, [xBP + xCB + xCB] ; expected + mov sAX, [xBP + xCB + xCB + sCB*1] ; actual + mov sDX, [xBP + xCB + xCB + sCB*2] ; reg# + lea sSI, [.szFmt xWrtRIP] + mov qword [xSP + xCB + 3*sCB], sBX + mov qword [xSP + xCB + 2*sCB], sCX + mov qword [xSP + xCB + 1*sCB], sAX + mov qword [xSP + xCB], sDX + mov [xSP], sSI + VBINSTST_CALL_FN_FAILURE_4 + +%else + mov sBX, [VBINSTST_NAME(g_uVBInsTstSubTestIndicator)] + mov sCX, [xBP + xCB + xCB] ; expected + mov sAX, [xBP + xCB + xCB + sCB*1] ; actual + mov sDX, [xBP + xCB + xCB + sCB*2] ; reg# + mov [xSP + xCB + 3*sCB], sBX + mov [xSP + xCB + 2*sCB], sCX + mov [xSP + xCB + 1*sCB], sAX + mov [xSP + xCB], sDX + mov [xSP], RTCCPTR_PRE .szFmt + VBINSTST_CALL_FN_FAILURE_4 +%endif + + mov xSP, [xSP + 38h] + MY_POP_ALL + ret 3*sCB +%if ARCH_BITS == 64 +.szFmt: db 'Bad register 0x%RX32 value 0x%RX64, expected 0x%RX64 (line %RU64)', 13, 0 +%else +.szFmt: db 'Bad register 0x%RX32 value 0x%RX32, expected 0x%RX32 (line %RU32)', 13, 0 +%endif +VBINSTST_ENDPROC Common_BadValue + + +%ifdef VBINSTST_CAN_DO_TRAPS + +;; +; Report a missing TRAP. +; +; Primary purpose is save all registers and convert from our stack-based to +; the correct calling convention for the environment. +; +; This function will clean up the stack upon return (to save space in the caller). +; +; @param uExpected +; +VBINSTST_BEGINPROC Common_MissingTrap + MY_PUSH_ALL + mov xAX, xSP ; 16-byte align the stack and reserve space for arguments and stuff. + sub xSP, 40h + and xSP, ~15 + mov [xSP + 38h], xAX + + %ifdef ASM_CALL64_GCC + mov rdx, [VBINSTST_NAME(g_uVBInsTstSubTestIndicator) wrt rip] + movzx rsi, byte [rbp + 10h] ; expected + lea rdi, [.szFmt wrt rip] + VBINSTST_CALL_FN_FAILURE_2 + + %elifdef ASM_CALL64_MSC + mov r8d, [VBINSTST_NAME(g_uVBInsTstSubTestIndicator) wrt rip] + movzx rdx, byte [rbp + 10h] ; expected + lea rcx, [.szFmt wrt rip] + VBINSTST_CALL_FN_FAILURE_2 + + %elifdef ASM_CALL64_BS2 + mov sBX, [VBINSTST_NAME(g_uVBInsTstSubTestIndicator) xWrtRIP] + mov sDX, [xBP + xCB + xCB] ; expected + lea sSI, [.szFmt xWrtRIP] + mov qword [xSP + xCB + 1*sCB], sBX + mov qword [xSP + xCB], sDX + mov [xSP], sSI + VBINSTST_CALL_FN_FAILURE_2 + + %else + mov sBX, [VBINSTST_NAME(g_uVBInsTstSubTestIndicator)] + mov sDX, [xBP + xCB + xCB] ; expected + mov [xSP + xCB + 1*sCB], sBX + mov [xSP + xCB], sDX + mov [xSP], RTCCPTR_PRE .szFmt + VBINSTST_CALL_FN_FAILURE_2 + %endif + + mov xSP, [xSP + 38h] + MY_POP_ALL + ret 1*sCB + %if ARCH_BITS == 64 +.szFmt: db 'Missing trap %RX8 (line %RU64)', 13, 0 + %else +.szFmt: db 'Missing trap %RX8 (line %RU32)', 13, 0 + %endif +VBINSTST_ENDPROC Common_MissingTrap + + %macro Common_MissingTrapTemplate 1 + VBINSTST_BEGINPROC Common_MissingTrap_%1 + push %1 + call VBINSTST_NAME(Common_MissingTrap) + ret + VBINSTST_ENDPROC Common_MissingTrap_%1 + %endmacro + Common_MissingTrapTemplate X86_XCPT_DE + Common_MissingTrapTemplate X86_XCPT_DB + Common_MissingTrapTemplate X86_XCPT_NMI + Common_MissingTrapTemplate X86_XCPT_BP + Common_MissingTrapTemplate X86_XCPT_OF + Common_MissingTrapTemplate X86_XCPT_BR + Common_MissingTrapTemplate X86_XCPT_UD + Common_MissingTrapTemplate X86_XCPT_NM + ;Common_MissingTrapTemplate X86_XCPT_DF + ;Common_MissingTrapTemplate X86_XCPT_CO_SEG_OVERRUN + Common_MissingTrapTemplate X86_XCPT_TS + Common_MissingTrapTemplate X86_XCPT_NP + Common_MissingTrapTemplate X86_XCPT_SS + Common_MissingTrapTemplate X86_XCPT_GP + Common_MissingTrapTemplate X86_XCPT_PF + Common_MissingTrapTemplate X86_XCPT_MF + Common_MissingTrapTemplate X86_XCPT_AC + ;Common_MissingTrapTemplate X86_XCPT_MC + Common_MissingTrapTemplate X86_XCPT_XF + +%endif ; VBINSTST_CAN_DO_TRAPS + + +; +; Global data variables used by Common_SetupMemReadUxx. +; For address calculation reasons, these must be qword aligned. +; +VBINSTST_BEGINDATA + align 64 + dd 09d8af498h, 09ab3e5f8h +VBINSTST_GLOBALNAME_EX g_u64Data, data hidden + dq 0 + dd 07d7af797h, 096b36562h +VBINSTST_GLOBALNAME_EX g_u32Data, data hidden + dd 0 + dd 012305987h +VBINSTST_GLOBALNAME_EX g_u16Data, data hidden + dw 0 + dw 05865h + dw 03863h + dw 02679h +VBINSTST_GLOBALNAME_EX g_u8Data, data hidden + db 0 + db 90h + dw 0865ah + dd 058daffe2h + +VBINSTST_BEGINCODE + +;; +; Sets up g_u8Data. +; @param uValue +VBINSTST_BEGINPROC Common_SetupMemReadU8 + push sAX + mov ax, [xSP + sCB + xCB] + mov [VBINSTST_NAME(g_u8Data) xWrtRIP], ax + pop sAX + ret sCB +VBINSTST_ENDPROC Common_SetupMemReadU8 + +;; +; Sets up g_u16Data. +; @param uValue +VBINSTST_BEGINPROC Common_SetupMemReadU16 + push sAX + mov ax, [xSP + sCB + xCB] + mov [VBINSTST_NAME(g_u16Data) xWrtRIP], ax + pop sAX + ret sCB +VBINSTST_ENDPROC Common_SetupMemReadU16 + +;; +; Sets up g_u32Data. +; @param uValue +VBINSTST_BEGINPROC Common_SetupMemReadU32 + push sAX + mov eax, [xSP + sCB + xCB] + mov [VBINSTST_NAME(g_u32Data) xWrtRIP], eax + pop sAX + ret sCB +VBINSTST_ENDPROC Common_SetupMemReadU32 + +;; +; Sets up g_u64Data. +; @param uValue +VBINSTST_BEGINPROC Common_SetupMemReadU64 + push sAX +%ifdef RT_ARCH_AMD64 + mov rax, [xSP + sCB + xCB] + mov [VBINSTST_NAME(g_u64Data) xWrtRIP], rax +%else + mov eax, [xSP + sCB + xCB] + mov [VBINSTST_NAME(g_u64Data) xWrtRIP], eax + mov eax, [xSP + sCB + xCB + 4] + mov [VBINSTST_NAME(g_u64Data) + 4 xWrtRIP], eax +%endif + pop sAX + ret sCB +VBINSTST_ENDPROC Common_SetupMemReadU64 + + +%endif + diff --git a/src/VBox/VMM/testcase/Instructions/env-iprt-r3-32.mac b/src/VBox/VMM/testcase/Instructions/env-iprt-r3-32.mac new file mode 100644 index 00000000..061d4f8b --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/env-iprt-r3-32.mac @@ -0,0 +1,19 @@ +; $Id: env-iprt-r3-32.mac $ +;; @file +; Instruction Test Environment - IPRT, Ring-3, 32-Bit. +; + +; +; Copyright (C) 2006-2019 Oracle Corporation +; +; This file is part of VirtualBox Open Source Edition (OSE), as +; available from http://www.virtualbox.org. This file is free software; +; you can redistribute it and/or modify it under the terms of the GNU +; General Public License (GPL) as published by the Free Software +; Foundation, in version 2 as it comes in the "COPYING" file of the +; VirtualBox OSE distribution. VirtualBox OSE is distributed in the +; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +; + +%include "env-iprt-r3.mac" + diff --git a/src/VBox/VMM/testcase/Instructions/env-iprt-r3-64.mac b/src/VBox/VMM/testcase/Instructions/env-iprt-r3-64.mac new file mode 100644 index 00000000..6e3ba7f6 --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/env-iprt-r3-64.mac @@ -0,0 +1,19 @@ +; $Id: env-iprt-r3-64.mac $ +;; @file +; Instruction Test Environment - IPRT, Ring-3, 64-Bit. +; + +; +; Copyright (C) 2006-2019 Oracle Corporation +; +; This file is part of VirtualBox Open Source Edition (OSE), as +; available from http://www.virtualbox.org. This file is free software; +; you can redistribute it and/or modify it under the terms of the GNU +; General Public License (GPL) as published by the Free Software +; Foundation, in version 2 as it comes in the "COPYING" file of the +; VirtualBox OSE distribution. VirtualBox OSE is distributed in the +; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +; + +%include "env-iprt-r3.mac" + diff --git a/src/VBox/VMM/testcase/Instructions/env-iprt-r3.mac b/src/VBox/VMM/testcase/Instructions/env-iprt-r3.mac new file mode 100644 index 00000000..43032580 --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/env-iprt-r3.mac @@ -0,0 +1,99 @@ +; $Id: env-iprt-r3.mac $ +;; @file +; Instruction Test Environment - IPRT, Ring-3, 32-bit and 64-bit. +; + +; +; Copyright (C) 2006-2019 Oracle Corporation +; +; This file is part of VirtualBox Open Source Edition (OSE), as +; available from http://www.virtualbox.org. This file is free software; +; you can redistribute it and/or modify it under the terms of the GNU +; General Public License (GPL) as published by the Free Software +; Foundation, in version 2 as it comes in the "COPYING" file of the +; VirtualBox OSE distribution. VirtualBox OSE is distributed in the +; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +; + +%ifndef ___env_iprt_r3_mac +%define ___env_iprt_r3_mac + +;******************************************************************************* +;* Header Files * +;******************************************************************************* +%include "iprt/asmdefs.mac" + + +;******************************************************************************* +;* Defined Constants And Macros * +;******************************************************************************* +%define sAX xAX +%define sBX xBX +%define sCX xCX +%define sDX xDX +%define sSP xSP +%define sBP xBP +%define sSI xSI +%define sDI xDI +%define sCB xCB + + +;; Same as BEGINPROC in asmdefs.mac. +%macro VBINSTST_BEGINPROC 1 +BEGINPROC %1 +%endm + +;; Same as ENDPROC in asmdefs.mac. +%macro VBINSTST_ENDPROC 1 +ENDPROC %1 +%endm + +;; Same as NAME in asmdefs.mac. +%define VBINSTST_NAME(a_Name) NAME(a_Name) + +;; Same as GLOBALNAME_EX in asmdefs.mac. +%define VBINSTST_GLOBALNAME_EX GLOBALNAME_EX + +;; Same as BEGINCODE in asmdefs.mac. +%define VBINSTST_BEGINCODE BEGINCODE + +;; Same as BEGINDATA in asmdefs.mac. +%define VBINSTST_BEGINDATA BEGINDATA + + +;; Call RTTestISub like function. +%define VBINSTST_CALL_FN_SUB_TEST call IMP2(RTTestISub) +EXTERN_IMP2 RTTestISub + +;; Call RTTestIFailure like function with simple message. +%define VBINSTST_CALL_FN_FAILURE call NAME(VBInsTstFailure) +extern NAME(VBInsTstFailure) + +;; Call RTTestIFailure like function with format message + 1 arg. +%define VBINSTST_CALL_FN_FAILURE_1 call NAME(VBInsTstFailure1) +extern NAME(VBInsTstFailure1) + +;; Call RTTestIFailure like function with format message + 2 args. +%define VBINSTST_CALL_FN_FAILURE_2 call NAME(VBInsTstFailure2) +extern NAME(VBInsTstFailure2) + +;; Call RTTestIFailure like function with format message + 3 args. +%define VBINSTST_CALL_FN_FAILURE_3 call NAME(VBInsTstFailure3) +extern NAME(VBInsTstFailure3) + +;; Call RTTestIFailure like function with format message + 4 args. +%define VBINSTST_CALL_FN_FAILURE_4 call NAME(VBInsTstFailure4) +extern NAME(VBInsTstFailure4) + + +;; Cannot do traps yet. +%undef VBINSTST_CAN_DO_TRAPS + + +; +; Include the common bits (contains code using above macros) +; +%include "env-common.mac" + +%endif + diff --git a/src/VBox/VMM/testcase/Instructions/itgTableDaa.py b/src/VBox/VMM/testcase/Instructions/itgTableDaa.py new file mode 100644 index 00000000..a54c1b41 --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/itgTableDaa.py @@ -0,0 +1,1105 @@ +# -*- coding: utf-8 -*- +# $Id: itgTableDaa.py $ + +""" +DAA (instruction) result table. +""" + + +__copyright__ = \ +""" +Copyright (C) 2012-2019 Oracle Corporation + +This file is part of VirtualBox Open Source Edition (OSE), as +available from http://www.virtualbox.org. This file is free software; +you can redistribute it and/or modify it under the terms of the GNU +General Public License (GPL) as published by the Free Software +Foundation, in version 2 as it comes in the "COPYING" file of the +VirtualBox OSE distribution. VirtualBox OSE is distributed in the +hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +""" +__version__ = "$Revision: 127855 $"; + + +## The 32-bit GCC (C99) program that produced the table below. +g_sItgCProgramDaa = \ +""" +#include + +int main() +{ + for (unsigned uInputAL = 0; uInputAL < 256; uInputAL++) + for (unsigned fAux = 0; fAux < 2; fAux++) + for (unsigned fCarry = 0; fCarry < 2; fCarry++) + { + unsigned uInputEFlags = fCarry | (fAux << 4); + unsigned uResultAL; + unsigned uResultEFlags; + __asm__ __volatile__("pushl %1\\n" + "popfl\\n" + "daa\\n" + "pushf\\n" + "pop %1\\n" + : "=a" (uResultAL), + "=r" (uResultEFlags) + : "0" (uInputAL), + "1" (uInputEFlags) + : "memory" + ); + printf(" ( 0x%02x, 0x%02x ), # AL=0x%02x, AF=%u CF=%u\\n", + uResultAL, uResultEFlags & 0xd5, uInputAL, fAux, fCarry); + /* 0xd5 = CF, PF, AF, ZF, SF */ + } + return 0; +} +"""; + + +# +# Compile and run the above program if requested to do so. +# +if __name__ == '__main__': + import sys; + if len(sys.argv) > 1 and sys.argv[1] == 'gen': + import subprocess; + oProc = subprocess.Popen(['gcc', '-x', 'c', '-std=gnu99', '-m32', '-o', './itgTableDaa', '-'], stdin = subprocess.PIPE); + oProc.communicate(g_sItgCProgramDaa); + oProc.wait(); + oProc = subprocess.Popen(['./itgTableDaa',]).wait(); + sys.exit(0); + + + +## +# The DAA results. +# +# The index / input relation is: index = (AL << 2) | (CF << 1) | AF +# +g_aItgDaaResults = \ +[ + ( 0x00, 0x44 ), # AL=0x00, AF=0 CF=0 + ( 0x60, 0x05 ), # AL=0x00, AF=0 CF=1 + ( 0x06, 0x14 ), # AL=0x00, AF=1 CF=0 + ( 0x66, 0x15 ), # AL=0x00, AF=1 CF=1 + ( 0x01, 0x00 ), # AL=0x01, AF=0 CF=0 + ( 0x61, 0x01 ), # AL=0x01, AF=0 CF=1 + ( 0x07, 0x10 ), # AL=0x01, AF=1 CF=0 + ( 0x67, 0x11 ), # AL=0x01, AF=1 CF=1 + ( 0x02, 0x00 ), # AL=0x02, AF=0 CF=0 + ( 0x62, 0x01 ), # AL=0x02, AF=0 CF=1 + ( 0x08, 0x10 ), # AL=0x02, AF=1 CF=0 + ( 0x68, 0x11 ), # AL=0x02, AF=1 CF=1 + ( 0x03, 0x04 ), # AL=0x03, AF=0 CF=0 + ( 0x63, 0x05 ), # AL=0x03, AF=0 CF=1 + ( 0x09, 0x14 ), # AL=0x03, AF=1 CF=0 + ( 0x69, 0x15 ), # AL=0x03, AF=1 CF=1 + ( 0x04, 0x00 ), # AL=0x04, AF=0 CF=0 + ( 0x64, 0x01 ), # AL=0x04, AF=0 CF=1 + ( 0x0a, 0x14 ), # AL=0x04, AF=1 CF=0 + ( 0x6a, 0x15 ), # AL=0x04, AF=1 CF=1 + ( 0x05, 0x04 ), # AL=0x05, AF=0 CF=0 + ( 0x65, 0x05 ), # AL=0x05, AF=0 CF=1 + ( 0x0b, 0x10 ), # AL=0x05, AF=1 CF=0 + ( 0x6b, 0x11 ), # AL=0x05, AF=1 CF=1 + ( 0x06, 0x04 ), # AL=0x06, AF=0 CF=0 + ( 0x66, 0x05 ), # AL=0x06, AF=0 CF=1 + ( 0x0c, 0x14 ), # AL=0x06, AF=1 CF=0 + ( 0x6c, 0x15 ), # AL=0x06, AF=1 CF=1 + ( 0x07, 0x00 ), # AL=0x07, AF=0 CF=0 + ( 0x67, 0x01 ), # AL=0x07, AF=0 CF=1 + ( 0x0d, 0x10 ), # AL=0x07, AF=1 CF=0 + ( 0x6d, 0x11 ), # AL=0x07, AF=1 CF=1 + ( 0x08, 0x00 ), # AL=0x08, AF=0 CF=0 + ( 0x68, 0x01 ), # AL=0x08, AF=0 CF=1 + ( 0x0e, 0x10 ), # AL=0x08, AF=1 CF=0 + ( 0x6e, 0x11 ), # AL=0x08, AF=1 CF=1 + ( 0x09, 0x04 ), # AL=0x09, AF=0 CF=0 + ( 0x69, 0x05 ), # AL=0x09, AF=0 CF=1 + ( 0x0f, 0x14 ), # AL=0x09, AF=1 CF=0 + ( 0x6f, 0x15 ), # AL=0x09, AF=1 CF=1 + ( 0x10, 0x10 ), # AL=0x0a, AF=0 CF=0 + ( 0x70, 0x11 ), # AL=0x0a, AF=0 CF=1 + ( 0x10, 0x10 ), # AL=0x0a, AF=1 CF=0 + ( 0x70, 0x11 ), # AL=0x0a, AF=1 CF=1 + ( 0x11, 0x14 ), # AL=0x0b, AF=0 CF=0 + ( 0x71, 0x15 ), # AL=0x0b, AF=0 CF=1 + ( 0x11, 0x14 ), # AL=0x0b, AF=1 CF=0 + ( 0x71, 0x15 ), # AL=0x0b, AF=1 CF=1 + ( 0x12, 0x14 ), # AL=0x0c, AF=0 CF=0 + ( 0x72, 0x15 ), # AL=0x0c, AF=0 CF=1 + ( 0x12, 0x14 ), # AL=0x0c, AF=1 CF=0 + ( 0x72, 0x15 ), # AL=0x0c, AF=1 CF=1 + ( 0x13, 0x10 ), # AL=0x0d, AF=0 CF=0 + ( 0x73, 0x11 ), # AL=0x0d, AF=0 CF=1 + ( 0x13, 0x10 ), # AL=0x0d, AF=1 CF=0 + ( 0x73, 0x11 ), # AL=0x0d, AF=1 CF=1 + ( 0x14, 0x14 ), # AL=0x0e, AF=0 CF=0 + ( 0x74, 0x15 ), # AL=0x0e, AF=0 CF=1 + ( 0x14, 0x14 ), # AL=0x0e, AF=1 CF=0 + ( 0x74, 0x15 ), # AL=0x0e, AF=1 CF=1 + ( 0x15, 0x10 ), # AL=0x0f, AF=0 CF=0 + ( 0x75, 0x11 ), # AL=0x0f, AF=0 CF=1 + ( 0x15, 0x10 ), # AL=0x0f, AF=1 CF=0 + ( 0x75, 0x11 ), # AL=0x0f, AF=1 CF=1 + ( 0x10, 0x00 ), # AL=0x10, AF=0 CF=0 + ( 0x70, 0x01 ), # AL=0x10, AF=0 CF=1 + ( 0x16, 0x10 ), # AL=0x10, AF=1 CF=0 + ( 0x76, 0x11 ), # AL=0x10, AF=1 CF=1 + ( 0x11, 0x04 ), # AL=0x11, AF=0 CF=0 + ( 0x71, 0x05 ), # AL=0x11, AF=0 CF=1 + ( 0x17, 0x14 ), # AL=0x11, AF=1 CF=0 + ( 0x77, 0x15 ), # AL=0x11, AF=1 CF=1 + ( 0x12, 0x04 ), # AL=0x12, AF=0 CF=0 + ( 0x72, 0x05 ), # AL=0x12, AF=0 CF=1 + ( 0x18, 0x14 ), # AL=0x12, AF=1 CF=0 + ( 0x78, 0x15 ), # AL=0x12, AF=1 CF=1 + ( 0x13, 0x00 ), # AL=0x13, AF=0 CF=0 + ( 0x73, 0x01 ), # AL=0x13, AF=0 CF=1 + ( 0x19, 0x10 ), # AL=0x13, AF=1 CF=0 + ( 0x79, 0x11 ), # AL=0x13, AF=1 CF=1 + ( 0x14, 0x04 ), # AL=0x14, AF=0 CF=0 + ( 0x74, 0x05 ), # AL=0x14, AF=0 CF=1 + ( 0x1a, 0x10 ), # AL=0x14, AF=1 CF=0 + ( 0x7a, 0x11 ), # AL=0x14, AF=1 CF=1 + ( 0x15, 0x00 ), # AL=0x15, AF=0 CF=0 + ( 0x75, 0x01 ), # AL=0x15, AF=0 CF=1 + ( 0x1b, 0x14 ), # AL=0x15, AF=1 CF=0 + ( 0x7b, 0x15 ), # AL=0x15, AF=1 CF=1 + ( 0x16, 0x00 ), # AL=0x16, AF=0 CF=0 + ( 0x76, 0x01 ), # AL=0x16, AF=0 CF=1 + ( 0x1c, 0x10 ), # AL=0x16, AF=1 CF=0 + ( 0x7c, 0x11 ), # AL=0x16, AF=1 CF=1 + ( 0x17, 0x04 ), # AL=0x17, AF=0 CF=0 + ( 0x77, 0x05 ), # AL=0x17, AF=0 CF=1 + ( 0x1d, 0x14 ), # AL=0x17, AF=1 CF=0 + ( 0x7d, 0x15 ), # AL=0x17, AF=1 CF=1 + ( 0x18, 0x04 ), # AL=0x18, AF=0 CF=0 + ( 0x78, 0x05 ), # AL=0x18, AF=0 CF=1 + ( 0x1e, 0x14 ), # AL=0x18, AF=1 CF=0 + ( 0x7e, 0x15 ), # AL=0x18, AF=1 CF=1 + ( 0x19, 0x00 ), # AL=0x19, AF=0 CF=0 + ( 0x79, 0x01 ), # AL=0x19, AF=0 CF=1 + ( 0x1f, 0x10 ), # AL=0x19, AF=1 CF=0 + ( 0x7f, 0x11 ), # AL=0x19, AF=1 CF=1 + ( 0x20, 0x10 ), # AL=0x1a, AF=0 CF=0 + ( 0x80, 0x91 ), # AL=0x1a, AF=0 CF=1 + ( 0x20, 0x10 ), # AL=0x1a, AF=1 CF=0 + ( 0x80, 0x91 ), # AL=0x1a, AF=1 CF=1 + ( 0x21, 0x14 ), # AL=0x1b, AF=0 CF=0 + ( 0x81, 0x95 ), # AL=0x1b, AF=0 CF=1 + ( 0x21, 0x14 ), # AL=0x1b, AF=1 CF=0 + ( 0x81, 0x95 ), # AL=0x1b, AF=1 CF=1 + ( 0x22, 0x14 ), # AL=0x1c, AF=0 CF=0 + ( 0x82, 0x95 ), # AL=0x1c, AF=0 CF=1 + ( 0x22, 0x14 ), # AL=0x1c, AF=1 CF=0 + ( 0x82, 0x95 ), # AL=0x1c, AF=1 CF=1 + ( 0x23, 0x10 ), # AL=0x1d, AF=0 CF=0 + ( 0x83, 0x91 ), # AL=0x1d, AF=0 CF=1 + ( 0x23, 0x10 ), # AL=0x1d, AF=1 CF=0 + ( 0x83, 0x91 ), # AL=0x1d, AF=1 CF=1 + ( 0x24, 0x14 ), # AL=0x1e, AF=0 CF=0 + ( 0x84, 0x95 ), # AL=0x1e, AF=0 CF=1 + ( 0x24, 0x14 ), # AL=0x1e, AF=1 CF=0 + ( 0x84, 0x95 ), # AL=0x1e, AF=1 CF=1 + ( 0x25, 0x10 ), # AL=0x1f, AF=0 CF=0 + ( 0x85, 0x91 ), # AL=0x1f, AF=0 CF=1 + ( 0x25, 0x10 ), # AL=0x1f, AF=1 CF=0 + ( 0x85, 0x91 ), # AL=0x1f, AF=1 CF=1 + ( 0x20, 0x00 ), # AL=0x20, AF=0 CF=0 + ( 0x80, 0x81 ), # AL=0x20, AF=0 CF=1 + ( 0x26, 0x10 ), # AL=0x20, AF=1 CF=0 + ( 0x86, 0x91 ), # AL=0x20, AF=1 CF=1 + ( 0x21, 0x04 ), # AL=0x21, AF=0 CF=0 + ( 0x81, 0x85 ), # AL=0x21, AF=0 CF=1 + ( 0x27, 0x14 ), # AL=0x21, AF=1 CF=0 + ( 0x87, 0x95 ), # AL=0x21, AF=1 CF=1 + ( 0x22, 0x04 ), # AL=0x22, AF=0 CF=0 + ( 0x82, 0x85 ), # AL=0x22, AF=0 CF=1 + ( 0x28, 0x14 ), # AL=0x22, AF=1 CF=0 + ( 0x88, 0x95 ), # AL=0x22, AF=1 CF=1 + ( 0x23, 0x00 ), # AL=0x23, AF=0 CF=0 + ( 0x83, 0x81 ), # AL=0x23, AF=0 CF=1 + ( 0x29, 0x10 ), # AL=0x23, AF=1 CF=0 + ( 0x89, 0x91 ), # AL=0x23, AF=1 CF=1 + ( 0x24, 0x04 ), # AL=0x24, AF=0 CF=0 + ( 0x84, 0x85 ), # AL=0x24, AF=0 CF=1 + ( 0x2a, 0x10 ), # AL=0x24, AF=1 CF=0 + ( 0x8a, 0x91 ), # AL=0x24, AF=1 CF=1 + ( 0x25, 0x00 ), # AL=0x25, AF=0 CF=0 + ( 0x85, 0x81 ), # AL=0x25, AF=0 CF=1 + ( 0x2b, 0x14 ), # AL=0x25, AF=1 CF=0 + ( 0x8b, 0x95 ), # AL=0x25, AF=1 CF=1 + ( 0x26, 0x00 ), # AL=0x26, AF=0 CF=0 + ( 0x86, 0x81 ), # AL=0x26, AF=0 CF=1 + ( 0x2c, 0x10 ), # AL=0x26, AF=1 CF=0 + ( 0x8c, 0x91 ), # AL=0x26, AF=1 CF=1 + ( 0x27, 0x04 ), # AL=0x27, AF=0 CF=0 + ( 0x87, 0x85 ), # AL=0x27, AF=0 CF=1 + ( 0x2d, 0x14 ), # AL=0x27, AF=1 CF=0 + ( 0x8d, 0x95 ), # AL=0x27, AF=1 CF=1 + ( 0x28, 0x04 ), # AL=0x28, AF=0 CF=0 + ( 0x88, 0x85 ), # AL=0x28, AF=0 CF=1 + ( 0x2e, 0x14 ), # AL=0x28, AF=1 CF=0 + ( 0x8e, 0x95 ), # AL=0x28, AF=1 CF=1 + ( 0x29, 0x00 ), # AL=0x29, AF=0 CF=0 + ( 0x89, 0x81 ), # AL=0x29, AF=0 CF=1 + ( 0x2f, 0x10 ), # AL=0x29, AF=1 CF=0 + ( 0x8f, 0x91 ), # AL=0x29, AF=1 CF=1 + ( 0x30, 0x14 ), # AL=0x2a, AF=0 CF=0 + ( 0x90, 0x95 ), # AL=0x2a, AF=0 CF=1 + ( 0x30, 0x14 ), # AL=0x2a, AF=1 CF=0 + ( 0x90, 0x95 ), # AL=0x2a, AF=1 CF=1 + ( 0x31, 0x10 ), # AL=0x2b, AF=0 CF=0 + ( 0x91, 0x91 ), # AL=0x2b, AF=0 CF=1 + ( 0x31, 0x10 ), # AL=0x2b, AF=1 CF=0 + ( 0x91, 0x91 ), # AL=0x2b, AF=1 CF=1 + ( 0x32, 0x10 ), # AL=0x2c, AF=0 CF=0 + ( 0x92, 0x91 ), # AL=0x2c, AF=0 CF=1 + ( 0x32, 0x10 ), # AL=0x2c, AF=1 CF=0 + ( 0x92, 0x91 ), # AL=0x2c, AF=1 CF=1 + ( 0x33, 0x14 ), # AL=0x2d, AF=0 CF=0 + ( 0x93, 0x95 ), # AL=0x2d, AF=0 CF=1 + ( 0x33, 0x14 ), # AL=0x2d, AF=1 CF=0 + ( 0x93, 0x95 ), # AL=0x2d, AF=1 CF=1 + ( 0x34, 0x10 ), # AL=0x2e, AF=0 CF=0 + ( 0x94, 0x91 ), # AL=0x2e, AF=0 CF=1 + ( 0x34, 0x10 ), # AL=0x2e, AF=1 CF=0 + ( 0x94, 0x91 ), # AL=0x2e, AF=1 CF=1 + ( 0x35, 0x14 ), # AL=0x2f, AF=0 CF=0 + ( 0x95, 0x95 ), # AL=0x2f, AF=0 CF=1 + ( 0x35, 0x14 ), # AL=0x2f, AF=1 CF=0 + ( 0x95, 0x95 ), # AL=0x2f, AF=1 CF=1 + ( 0x30, 0x04 ), # AL=0x30, AF=0 CF=0 + ( 0x90, 0x85 ), # AL=0x30, AF=0 CF=1 + ( 0x36, 0x14 ), # AL=0x30, AF=1 CF=0 + ( 0x96, 0x95 ), # AL=0x30, AF=1 CF=1 + ( 0x31, 0x00 ), # AL=0x31, AF=0 CF=0 + ( 0x91, 0x81 ), # AL=0x31, AF=0 CF=1 + ( 0x37, 0x10 ), # AL=0x31, AF=1 CF=0 + ( 0x97, 0x91 ), # AL=0x31, AF=1 CF=1 + ( 0x32, 0x00 ), # AL=0x32, AF=0 CF=0 + ( 0x92, 0x81 ), # AL=0x32, AF=0 CF=1 + ( 0x38, 0x10 ), # AL=0x32, AF=1 CF=0 + ( 0x98, 0x91 ), # AL=0x32, AF=1 CF=1 + ( 0x33, 0x04 ), # AL=0x33, AF=0 CF=0 + ( 0x93, 0x85 ), # AL=0x33, AF=0 CF=1 + ( 0x39, 0x14 ), # AL=0x33, AF=1 CF=0 + ( 0x99, 0x95 ), # AL=0x33, AF=1 CF=1 + ( 0x34, 0x00 ), # AL=0x34, AF=0 CF=0 + ( 0x94, 0x81 ), # AL=0x34, AF=0 CF=1 + ( 0x3a, 0x14 ), # AL=0x34, AF=1 CF=0 + ( 0x9a, 0x95 ), # AL=0x34, AF=1 CF=1 + ( 0x35, 0x04 ), # AL=0x35, AF=0 CF=0 + ( 0x95, 0x85 ), # AL=0x35, AF=0 CF=1 + ( 0x3b, 0x10 ), # AL=0x35, AF=1 CF=0 + ( 0x9b, 0x91 ), # AL=0x35, AF=1 CF=1 + ( 0x36, 0x04 ), # AL=0x36, AF=0 CF=0 + ( 0x96, 0x85 ), # AL=0x36, AF=0 CF=1 + ( 0x3c, 0x14 ), # AL=0x36, AF=1 CF=0 + ( 0x9c, 0x95 ), # AL=0x36, AF=1 CF=1 + ( 0x37, 0x00 ), # AL=0x37, AF=0 CF=0 + ( 0x97, 0x81 ), # AL=0x37, AF=0 CF=1 + ( 0x3d, 0x10 ), # AL=0x37, AF=1 CF=0 + ( 0x9d, 0x91 ), # AL=0x37, AF=1 CF=1 + ( 0x38, 0x00 ), # AL=0x38, AF=0 CF=0 + ( 0x98, 0x81 ), # AL=0x38, AF=0 CF=1 + ( 0x3e, 0x10 ), # AL=0x38, AF=1 CF=0 + ( 0x9e, 0x91 ), # AL=0x38, AF=1 CF=1 + ( 0x39, 0x04 ), # AL=0x39, AF=0 CF=0 + ( 0x99, 0x85 ), # AL=0x39, AF=0 CF=1 + ( 0x3f, 0x14 ), # AL=0x39, AF=1 CF=0 + ( 0x9f, 0x95 ), # AL=0x39, AF=1 CF=1 + ( 0x40, 0x10 ), # AL=0x3a, AF=0 CF=0 + ( 0xa0, 0x95 ), # AL=0x3a, AF=0 CF=1 + ( 0x40, 0x10 ), # AL=0x3a, AF=1 CF=0 + ( 0xa0, 0x95 ), # AL=0x3a, AF=1 CF=1 + ( 0x41, 0x14 ), # AL=0x3b, AF=0 CF=0 + ( 0xa1, 0x91 ), # AL=0x3b, AF=0 CF=1 + ( 0x41, 0x14 ), # AL=0x3b, AF=1 CF=0 + ( 0xa1, 0x91 ), # AL=0x3b, AF=1 CF=1 + ( 0x42, 0x14 ), # AL=0x3c, AF=0 CF=0 + ( 0xa2, 0x91 ), # AL=0x3c, AF=0 CF=1 + ( 0x42, 0x14 ), # AL=0x3c, AF=1 CF=0 + ( 0xa2, 0x91 ), # AL=0x3c, AF=1 CF=1 + ( 0x43, 0x10 ), # AL=0x3d, AF=0 CF=0 + ( 0xa3, 0x95 ), # AL=0x3d, AF=0 CF=1 + ( 0x43, 0x10 ), # AL=0x3d, AF=1 CF=0 + ( 0xa3, 0x95 ), # AL=0x3d, AF=1 CF=1 + ( 0x44, 0x14 ), # AL=0x3e, AF=0 CF=0 + ( 0xa4, 0x91 ), # AL=0x3e, AF=0 CF=1 + ( 0x44, 0x14 ), # AL=0x3e, AF=1 CF=0 + ( 0xa4, 0x91 ), # AL=0x3e, AF=1 CF=1 + ( 0x45, 0x10 ), # AL=0x3f, AF=0 CF=0 + ( 0xa5, 0x95 ), # AL=0x3f, AF=0 CF=1 + ( 0x45, 0x10 ), # AL=0x3f, AF=1 CF=0 + ( 0xa5, 0x95 ), # AL=0x3f, AF=1 CF=1 + ( 0x40, 0x00 ), # AL=0x40, AF=0 CF=0 + ( 0xa0, 0x85 ), # AL=0x40, AF=0 CF=1 + ( 0x46, 0x10 ), # AL=0x40, AF=1 CF=0 + ( 0xa6, 0x95 ), # AL=0x40, AF=1 CF=1 + ( 0x41, 0x04 ), # AL=0x41, AF=0 CF=0 + ( 0xa1, 0x81 ), # AL=0x41, AF=0 CF=1 + ( 0x47, 0x14 ), # AL=0x41, AF=1 CF=0 + ( 0xa7, 0x91 ), # AL=0x41, AF=1 CF=1 + ( 0x42, 0x04 ), # AL=0x42, AF=0 CF=0 + ( 0xa2, 0x81 ), # AL=0x42, AF=0 CF=1 + ( 0x48, 0x14 ), # AL=0x42, AF=1 CF=0 + ( 0xa8, 0x91 ), # AL=0x42, AF=1 CF=1 + ( 0x43, 0x00 ), # AL=0x43, AF=0 CF=0 + ( 0xa3, 0x85 ), # AL=0x43, AF=0 CF=1 + ( 0x49, 0x10 ), # AL=0x43, AF=1 CF=0 + ( 0xa9, 0x95 ), # AL=0x43, AF=1 CF=1 + ( 0x44, 0x04 ), # AL=0x44, AF=0 CF=0 + ( 0xa4, 0x81 ), # AL=0x44, AF=0 CF=1 + ( 0x4a, 0x10 ), # AL=0x44, AF=1 CF=0 + ( 0xaa, 0x95 ), # AL=0x44, AF=1 CF=1 + ( 0x45, 0x00 ), # AL=0x45, AF=0 CF=0 + ( 0xa5, 0x85 ), # AL=0x45, AF=0 CF=1 + ( 0x4b, 0x14 ), # AL=0x45, AF=1 CF=0 + ( 0xab, 0x91 ), # AL=0x45, AF=1 CF=1 + ( 0x46, 0x00 ), # AL=0x46, AF=0 CF=0 + ( 0xa6, 0x85 ), # AL=0x46, AF=0 CF=1 + ( 0x4c, 0x10 ), # AL=0x46, AF=1 CF=0 + ( 0xac, 0x95 ), # AL=0x46, AF=1 CF=1 + ( 0x47, 0x04 ), # AL=0x47, AF=0 CF=0 + ( 0xa7, 0x81 ), # AL=0x47, AF=0 CF=1 + ( 0x4d, 0x14 ), # AL=0x47, AF=1 CF=0 + ( 0xad, 0x91 ), # AL=0x47, AF=1 CF=1 + ( 0x48, 0x04 ), # AL=0x48, AF=0 CF=0 + ( 0xa8, 0x81 ), # AL=0x48, AF=0 CF=1 + ( 0x4e, 0x14 ), # AL=0x48, AF=1 CF=0 + ( 0xae, 0x91 ), # AL=0x48, AF=1 CF=1 + ( 0x49, 0x00 ), # AL=0x49, AF=0 CF=0 + ( 0xa9, 0x85 ), # AL=0x49, AF=0 CF=1 + ( 0x4f, 0x10 ), # AL=0x49, AF=1 CF=0 + ( 0xaf, 0x95 ), # AL=0x49, AF=1 CF=1 + ( 0x50, 0x14 ), # AL=0x4a, AF=0 CF=0 + ( 0xb0, 0x91 ), # AL=0x4a, AF=0 CF=1 + ( 0x50, 0x14 ), # AL=0x4a, AF=1 CF=0 + ( 0xb0, 0x91 ), # AL=0x4a, AF=1 CF=1 + ( 0x51, 0x10 ), # AL=0x4b, AF=0 CF=0 + ( 0xb1, 0x95 ), # AL=0x4b, AF=0 CF=1 + ( 0x51, 0x10 ), # AL=0x4b, AF=1 CF=0 + ( 0xb1, 0x95 ), # AL=0x4b, AF=1 CF=1 + ( 0x52, 0x10 ), # AL=0x4c, AF=0 CF=0 + ( 0xb2, 0x95 ), # AL=0x4c, AF=0 CF=1 + ( 0x52, 0x10 ), # AL=0x4c, AF=1 CF=0 + ( 0xb2, 0x95 ), # AL=0x4c, AF=1 CF=1 + ( 0x53, 0x14 ), # AL=0x4d, AF=0 CF=0 + ( 0xb3, 0x91 ), # AL=0x4d, AF=0 CF=1 + ( 0x53, 0x14 ), # AL=0x4d, AF=1 CF=0 + ( 0xb3, 0x91 ), # AL=0x4d, AF=1 CF=1 + ( 0x54, 0x10 ), # AL=0x4e, AF=0 CF=0 + ( 0xb4, 0x95 ), # AL=0x4e, AF=0 CF=1 + ( 0x54, 0x10 ), # AL=0x4e, AF=1 CF=0 + ( 0xb4, 0x95 ), # AL=0x4e, AF=1 CF=1 + ( 0x55, 0x14 ), # AL=0x4f, AF=0 CF=0 + ( 0xb5, 0x91 ), # AL=0x4f, AF=0 CF=1 + ( 0x55, 0x14 ), # AL=0x4f, AF=1 CF=0 + ( 0xb5, 0x91 ), # AL=0x4f, AF=1 CF=1 + ( 0x50, 0x04 ), # AL=0x50, AF=0 CF=0 + ( 0xb0, 0x81 ), # AL=0x50, AF=0 CF=1 + ( 0x56, 0x14 ), # AL=0x50, AF=1 CF=0 + ( 0xb6, 0x91 ), # AL=0x50, AF=1 CF=1 + ( 0x51, 0x00 ), # AL=0x51, AF=0 CF=0 + ( 0xb1, 0x85 ), # AL=0x51, AF=0 CF=1 + ( 0x57, 0x10 ), # AL=0x51, AF=1 CF=0 + ( 0xb7, 0x95 ), # AL=0x51, AF=1 CF=1 + ( 0x52, 0x00 ), # AL=0x52, AF=0 CF=0 + ( 0xb2, 0x85 ), # AL=0x52, AF=0 CF=1 + ( 0x58, 0x10 ), # AL=0x52, AF=1 CF=0 + ( 0xb8, 0x95 ), # AL=0x52, AF=1 CF=1 + ( 0x53, 0x04 ), # AL=0x53, AF=0 CF=0 + ( 0xb3, 0x81 ), # AL=0x53, AF=0 CF=1 + ( 0x59, 0x14 ), # AL=0x53, AF=1 CF=0 + ( 0xb9, 0x91 ), # AL=0x53, AF=1 CF=1 + ( 0x54, 0x00 ), # AL=0x54, AF=0 CF=0 + ( 0xb4, 0x85 ), # AL=0x54, AF=0 CF=1 + ( 0x5a, 0x14 ), # AL=0x54, AF=1 CF=0 + ( 0xba, 0x91 ), # AL=0x54, AF=1 CF=1 + ( 0x55, 0x04 ), # AL=0x55, AF=0 CF=0 + ( 0xb5, 0x81 ), # AL=0x55, AF=0 CF=1 + ( 0x5b, 0x10 ), # AL=0x55, AF=1 CF=0 + ( 0xbb, 0x95 ), # AL=0x55, AF=1 CF=1 + ( 0x56, 0x04 ), # AL=0x56, AF=0 CF=0 + ( 0xb6, 0x81 ), # AL=0x56, AF=0 CF=1 + ( 0x5c, 0x14 ), # AL=0x56, AF=1 CF=0 + ( 0xbc, 0x91 ), # AL=0x56, AF=1 CF=1 + ( 0x57, 0x00 ), # AL=0x57, AF=0 CF=0 + ( 0xb7, 0x85 ), # AL=0x57, AF=0 CF=1 + ( 0x5d, 0x10 ), # AL=0x57, AF=1 CF=0 + ( 0xbd, 0x95 ), # AL=0x57, AF=1 CF=1 + ( 0x58, 0x00 ), # AL=0x58, AF=0 CF=0 + ( 0xb8, 0x85 ), # AL=0x58, AF=0 CF=1 + ( 0x5e, 0x10 ), # AL=0x58, AF=1 CF=0 + ( 0xbe, 0x95 ), # AL=0x58, AF=1 CF=1 + ( 0x59, 0x04 ), # AL=0x59, AF=0 CF=0 + ( 0xb9, 0x81 ), # AL=0x59, AF=0 CF=1 + ( 0x5f, 0x14 ), # AL=0x59, AF=1 CF=0 + ( 0xbf, 0x91 ), # AL=0x59, AF=1 CF=1 + ( 0x60, 0x14 ), # AL=0x5a, AF=0 CF=0 + ( 0xc0, 0x95 ), # AL=0x5a, AF=0 CF=1 + ( 0x60, 0x14 ), # AL=0x5a, AF=1 CF=0 + ( 0xc0, 0x95 ), # AL=0x5a, AF=1 CF=1 + ( 0x61, 0x10 ), # AL=0x5b, AF=0 CF=0 + ( 0xc1, 0x91 ), # AL=0x5b, AF=0 CF=1 + ( 0x61, 0x10 ), # AL=0x5b, AF=1 CF=0 + ( 0xc1, 0x91 ), # AL=0x5b, AF=1 CF=1 + ( 0x62, 0x10 ), # AL=0x5c, AF=0 CF=0 + ( 0xc2, 0x91 ), # AL=0x5c, AF=0 CF=1 + ( 0x62, 0x10 ), # AL=0x5c, AF=1 CF=0 + ( 0xc2, 0x91 ), # AL=0x5c, AF=1 CF=1 + ( 0x63, 0x14 ), # AL=0x5d, AF=0 CF=0 + ( 0xc3, 0x95 ), # AL=0x5d, AF=0 CF=1 + ( 0x63, 0x14 ), # AL=0x5d, AF=1 CF=0 + ( 0xc3, 0x95 ), # AL=0x5d, AF=1 CF=1 + ( 0x64, 0x10 ), # AL=0x5e, AF=0 CF=0 + ( 0xc4, 0x91 ), # AL=0x5e, AF=0 CF=1 + ( 0x64, 0x10 ), # AL=0x5e, AF=1 CF=0 + ( 0xc4, 0x91 ), # AL=0x5e, AF=1 CF=1 + ( 0x65, 0x14 ), # AL=0x5f, AF=0 CF=0 + ( 0xc5, 0x95 ), # AL=0x5f, AF=0 CF=1 + ( 0x65, 0x14 ), # AL=0x5f, AF=1 CF=0 + ( 0xc5, 0x95 ), # AL=0x5f, AF=1 CF=1 + ( 0x60, 0x04 ), # AL=0x60, AF=0 CF=0 + ( 0xc0, 0x85 ), # AL=0x60, AF=0 CF=1 + ( 0x66, 0x14 ), # AL=0x60, AF=1 CF=0 + ( 0xc6, 0x95 ), # AL=0x60, AF=1 CF=1 + ( 0x61, 0x00 ), # AL=0x61, AF=0 CF=0 + ( 0xc1, 0x81 ), # AL=0x61, AF=0 CF=1 + ( 0x67, 0x10 ), # AL=0x61, AF=1 CF=0 + ( 0xc7, 0x91 ), # AL=0x61, AF=1 CF=1 + ( 0x62, 0x00 ), # AL=0x62, AF=0 CF=0 + ( 0xc2, 0x81 ), # AL=0x62, AF=0 CF=1 + ( 0x68, 0x10 ), # AL=0x62, AF=1 CF=0 + ( 0xc8, 0x91 ), # AL=0x62, AF=1 CF=1 + ( 0x63, 0x04 ), # AL=0x63, AF=0 CF=0 + ( 0xc3, 0x85 ), # AL=0x63, AF=0 CF=1 + ( 0x69, 0x14 ), # AL=0x63, AF=1 CF=0 + ( 0xc9, 0x95 ), # AL=0x63, AF=1 CF=1 + ( 0x64, 0x00 ), # AL=0x64, AF=0 CF=0 + ( 0xc4, 0x81 ), # AL=0x64, AF=0 CF=1 + ( 0x6a, 0x14 ), # AL=0x64, AF=1 CF=0 + ( 0xca, 0x95 ), # AL=0x64, AF=1 CF=1 + ( 0x65, 0x04 ), # AL=0x65, AF=0 CF=0 + ( 0xc5, 0x85 ), # AL=0x65, AF=0 CF=1 + ( 0x6b, 0x10 ), # AL=0x65, AF=1 CF=0 + ( 0xcb, 0x91 ), # AL=0x65, AF=1 CF=1 + ( 0x66, 0x04 ), # AL=0x66, AF=0 CF=0 + ( 0xc6, 0x85 ), # AL=0x66, AF=0 CF=1 + ( 0x6c, 0x14 ), # AL=0x66, AF=1 CF=0 + ( 0xcc, 0x95 ), # AL=0x66, AF=1 CF=1 + ( 0x67, 0x00 ), # AL=0x67, AF=0 CF=0 + ( 0xc7, 0x81 ), # AL=0x67, AF=0 CF=1 + ( 0x6d, 0x10 ), # AL=0x67, AF=1 CF=0 + ( 0xcd, 0x91 ), # AL=0x67, AF=1 CF=1 + ( 0x68, 0x00 ), # AL=0x68, AF=0 CF=0 + ( 0xc8, 0x81 ), # AL=0x68, AF=0 CF=1 + ( 0x6e, 0x10 ), # AL=0x68, AF=1 CF=0 + ( 0xce, 0x91 ), # AL=0x68, AF=1 CF=1 + ( 0x69, 0x04 ), # AL=0x69, AF=0 CF=0 + ( 0xc9, 0x85 ), # AL=0x69, AF=0 CF=1 + ( 0x6f, 0x14 ), # AL=0x69, AF=1 CF=0 + ( 0xcf, 0x95 ), # AL=0x69, AF=1 CF=1 + ( 0x70, 0x10 ), # AL=0x6a, AF=0 CF=0 + ( 0xd0, 0x91 ), # AL=0x6a, AF=0 CF=1 + ( 0x70, 0x10 ), # AL=0x6a, AF=1 CF=0 + ( 0xd0, 0x91 ), # AL=0x6a, AF=1 CF=1 + ( 0x71, 0x14 ), # AL=0x6b, AF=0 CF=0 + ( 0xd1, 0x95 ), # AL=0x6b, AF=0 CF=1 + ( 0x71, 0x14 ), # AL=0x6b, AF=1 CF=0 + ( 0xd1, 0x95 ), # AL=0x6b, AF=1 CF=1 + ( 0x72, 0x14 ), # AL=0x6c, AF=0 CF=0 + ( 0xd2, 0x95 ), # AL=0x6c, AF=0 CF=1 + ( 0x72, 0x14 ), # AL=0x6c, AF=1 CF=0 + ( 0xd2, 0x95 ), # AL=0x6c, AF=1 CF=1 + ( 0x73, 0x10 ), # AL=0x6d, AF=0 CF=0 + ( 0xd3, 0x91 ), # AL=0x6d, AF=0 CF=1 + ( 0x73, 0x10 ), # AL=0x6d, AF=1 CF=0 + ( 0xd3, 0x91 ), # AL=0x6d, AF=1 CF=1 + ( 0x74, 0x14 ), # AL=0x6e, AF=0 CF=0 + ( 0xd4, 0x95 ), # AL=0x6e, AF=0 CF=1 + ( 0x74, 0x14 ), # AL=0x6e, AF=1 CF=0 + ( 0xd4, 0x95 ), # AL=0x6e, AF=1 CF=1 + ( 0x75, 0x10 ), # AL=0x6f, AF=0 CF=0 + ( 0xd5, 0x91 ), # AL=0x6f, AF=0 CF=1 + ( 0x75, 0x10 ), # AL=0x6f, AF=1 CF=0 + ( 0xd5, 0x91 ), # AL=0x6f, AF=1 CF=1 + ( 0x70, 0x00 ), # AL=0x70, AF=0 CF=0 + ( 0xd0, 0x81 ), # AL=0x70, AF=0 CF=1 + ( 0x76, 0x10 ), # AL=0x70, AF=1 CF=0 + ( 0xd6, 0x91 ), # AL=0x70, AF=1 CF=1 + ( 0x71, 0x04 ), # AL=0x71, AF=0 CF=0 + ( 0xd1, 0x85 ), # AL=0x71, AF=0 CF=1 + ( 0x77, 0x14 ), # AL=0x71, AF=1 CF=0 + ( 0xd7, 0x95 ), # AL=0x71, AF=1 CF=1 + ( 0x72, 0x04 ), # AL=0x72, AF=0 CF=0 + ( 0xd2, 0x85 ), # AL=0x72, AF=0 CF=1 + ( 0x78, 0x14 ), # AL=0x72, AF=1 CF=0 + ( 0xd8, 0x95 ), # AL=0x72, AF=1 CF=1 + ( 0x73, 0x00 ), # AL=0x73, AF=0 CF=0 + ( 0xd3, 0x81 ), # AL=0x73, AF=0 CF=1 + ( 0x79, 0x10 ), # AL=0x73, AF=1 CF=0 + ( 0xd9, 0x91 ), # AL=0x73, AF=1 CF=1 + ( 0x74, 0x04 ), # AL=0x74, AF=0 CF=0 + ( 0xd4, 0x85 ), # AL=0x74, AF=0 CF=1 + ( 0x7a, 0x10 ), # AL=0x74, AF=1 CF=0 + ( 0xda, 0x91 ), # AL=0x74, AF=1 CF=1 + ( 0x75, 0x00 ), # AL=0x75, AF=0 CF=0 + ( 0xd5, 0x81 ), # AL=0x75, AF=0 CF=1 + ( 0x7b, 0x14 ), # AL=0x75, AF=1 CF=0 + ( 0xdb, 0x95 ), # AL=0x75, AF=1 CF=1 + ( 0x76, 0x00 ), # AL=0x76, AF=0 CF=0 + ( 0xd6, 0x81 ), # AL=0x76, AF=0 CF=1 + ( 0x7c, 0x10 ), # AL=0x76, AF=1 CF=0 + ( 0xdc, 0x91 ), # AL=0x76, AF=1 CF=1 + ( 0x77, 0x04 ), # AL=0x77, AF=0 CF=0 + ( 0xd7, 0x85 ), # AL=0x77, AF=0 CF=1 + ( 0x7d, 0x14 ), # AL=0x77, AF=1 CF=0 + ( 0xdd, 0x95 ), # AL=0x77, AF=1 CF=1 + ( 0x78, 0x04 ), # AL=0x78, AF=0 CF=0 + ( 0xd8, 0x85 ), # AL=0x78, AF=0 CF=1 + ( 0x7e, 0x14 ), # AL=0x78, AF=1 CF=0 + ( 0xde, 0x95 ), # AL=0x78, AF=1 CF=1 + ( 0x79, 0x00 ), # AL=0x79, AF=0 CF=0 + ( 0xd9, 0x81 ), # AL=0x79, AF=0 CF=1 + ( 0x7f, 0x10 ), # AL=0x79, AF=1 CF=0 + ( 0xdf, 0x91 ), # AL=0x79, AF=1 CF=1 + ( 0x80, 0x90 ), # AL=0x7a, AF=0 CF=0 + ( 0xe0, 0x91 ), # AL=0x7a, AF=0 CF=1 + ( 0x80, 0x90 ), # AL=0x7a, AF=1 CF=0 + ( 0xe0, 0x91 ), # AL=0x7a, AF=1 CF=1 + ( 0x81, 0x94 ), # AL=0x7b, AF=0 CF=0 + ( 0xe1, 0x95 ), # AL=0x7b, AF=0 CF=1 + ( 0x81, 0x94 ), # AL=0x7b, AF=1 CF=0 + ( 0xe1, 0x95 ), # AL=0x7b, AF=1 CF=1 + ( 0x82, 0x94 ), # AL=0x7c, AF=0 CF=0 + ( 0xe2, 0x95 ), # AL=0x7c, AF=0 CF=1 + ( 0x82, 0x94 ), # AL=0x7c, AF=1 CF=0 + ( 0xe2, 0x95 ), # AL=0x7c, AF=1 CF=1 + ( 0x83, 0x90 ), # AL=0x7d, AF=0 CF=0 + ( 0xe3, 0x91 ), # AL=0x7d, AF=0 CF=1 + ( 0x83, 0x90 ), # AL=0x7d, AF=1 CF=0 + ( 0xe3, 0x91 ), # AL=0x7d, AF=1 CF=1 + ( 0x84, 0x94 ), # AL=0x7e, AF=0 CF=0 + ( 0xe4, 0x95 ), # AL=0x7e, AF=0 CF=1 + ( 0x84, 0x94 ), # AL=0x7e, AF=1 CF=0 + ( 0xe4, 0x95 ), # AL=0x7e, AF=1 CF=1 + ( 0x85, 0x90 ), # AL=0x7f, AF=0 CF=0 + ( 0xe5, 0x91 ), # AL=0x7f, AF=0 CF=1 + ( 0x85, 0x90 ), # AL=0x7f, AF=1 CF=0 + ( 0xe5, 0x91 ), # AL=0x7f, AF=1 CF=1 + ( 0x80, 0x80 ), # AL=0x80, AF=0 CF=0 + ( 0xe0, 0x81 ), # AL=0x80, AF=0 CF=1 + ( 0x86, 0x90 ), # AL=0x80, AF=1 CF=0 + ( 0xe6, 0x91 ), # AL=0x80, AF=1 CF=1 + ( 0x81, 0x84 ), # AL=0x81, AF=0 CF=0 + ( 0xe1, 0x85 ), # AL=0x81, AF=0 CF=1 + ( 0x87, 0x94 ), # AL=0x81, AF=1 CF=0 + ( 0xe7, 0x95 ), # AL=0x81, AF=1 CF=1 + ( 0x82, 0x84 ), # AL=0x82, AF=0 CF=0 + ( 0xe2, 0x85 ), # AL=0x82, AF=0 CF=1 + ( 0x88, 0x94 ), # AL=0x82, AF=1 CF=0 + ( 0xe8, 0x95 ), # AL=0x82, AF=1 CF=1 + ( 0x83, 0x80 ), # AL=0x83, AF=0 CF=0 + ( 0xe3, 0x81 ), # AL=0x83, AF=0 CF=1 + ( 0x89, 0x90 ), # AL=0x83, AF=1 CF=0 + ( 0xe9, 0x91 ), # AL=0x83, AF=1 CF=1 + ( 0x84, 0x84 ), # AL=0x84, AF=0 CF=0 + ( 0xe4, 0x85 ), # AL=0x84, AF=0 CF=1 + ( 0x8a, 0x90 ), # AL=0x84, AF=1 CF=0 + ( 0xea, 0x91 ), # AL=0x84, AF=1 CF=1 + ( 0x85, 0x80 ), # AL=0x85, AF=0 CF=0 + ( 0xe5, 0x81 ), # AL=0x85, AF=0 CF=1 + ( 0x8b, 0x94 ), # AL=0x85, AF=1 CF=0 + ( 0xeb, 0x95 ), # AL=0x85, AF=1 CF=1 + ( 0x86, 0x80 ), # AL=0x86, AF=0 CF=0 + ( 0xe6, 0x81 ), # AL=0x86, AF=0 CF=1 + ( 0x8c, 0x90 ), # AL=0x86, AF=1 CF=0 + ( 0xec, 0x91 ), # AL=0x86, AF=1 CF=1 + ( 0x87, 0x84 ), # AL=0x87, AF=0 CF=0 + ( 0xe7, 0x85 ), # AL=0x87, AF=0 CF=1 + ( 0x8d, 0x94 ), # AL=0x87, AF=1 CF=0 + ( 0xed, 0x95 ), # AL=0x87, AF=1 CF=1 + ( 0x88, 0x84 ), # AL=0x88, AF=0 CF=0 + ( 0xe8, 0x85 ), # AL=0x88, AF=0 CF=1 + ( 0x8e, 0x94 ), # AL=0x88, AF=1 CF=0 + ( 0xee, 0x95 ), # AL=0x88, AF=1 CF=1 + ( 0x89, 0x80 ), # AL=0x89, AF=0 CF=0 + ( 0xe9, 0x81 ), # AL=0x89, AF=0 CF=1 + ( 0x8f, 0x90 ), # AL=0x89, AF=1 CF=0 + ( 0xef, 0x91 ), # AL=0x89, AF=1 CF=1 + ( 0x90, 0x94 ), # AL=0x8a, AF=0 CF=0 + ( 0xf0, 0x95 ), # AL=0x8a, AF=0 CF=1 + ( 0x90, 0x94 ), # AL=0x8a, AF=1 CF=0 + ( 0xf0, 0x95 ), # AL=0x8a, AF=1 CF=1 + ( 0x91, 0x90 ), # AL=0x8b, AF=0 CF=0 + ( 0xf1, 0x91 ), # AL=0x8b, AF=0 CF=1 + ( 0x91, 0x90 ), # AL=0x8b, AF=1 CF=0 + ( 0xf1, 0x91 ), # AL=0x8b, AF=1 CF=1 + ( 0x92, 0x90 ), # AL=0x8c, AF=0 CF=0 + ( 0xf2, 0x91 ), # AL=0x8c, AF=0 CF=1 + ( 0x92, 0x90 ), # AL=0x8c, AF=1 CF=0 + ( 0xf2, 0x91 ), # AL=0x8c, AF=1 CF=1 + ( 0x93, 0x94 ), # AL=0x8d, AF=0 CF=0 + ( 0xf3, 0x95 ), # AL=0x8d, AF=0 CF=1 + ( 0x93, 0x94 ), # AL=0x8d, AF=1 CF=0 + ( 0xf3, 0x95 ), # AL=0x8d, AF=1 CF=1 + ( 0x94, 0x90 ), # AL=0x8e, AF=0 CF=0 + ( 0xf4, 0x91 ), # AL=0x8e, AF=0 CF=1 + ( 0x94, 0x90 ), # AL=0x8e, AF=1 CF=0 + ( 0xf4, 0x91 ), # AL=0x8e, AF=1 CF=1 + ( 0x95, 0x94 ), # AL=0x8f, AF=0 CF=0 + ( 0xf5, 0x95 ), # AL=0x8f, AF=0 CF=1 + ( 0x95, 0x94 ), # AL=0x8f, AF=1 CF=0 + ( 0xf5, 0x95 ), # AL=0x8f, AF=1 CF=1 + ( 0x90, 0x84 ), # AL=0x90, AF=0 CF=0 + ( 0xf0, 0x85 ), # AL=0x90, AF=0 CF=1 + ( 0x96, 0x94 ), # AL=0x90, AF=1 CF=0 + ( 0xf6, 0x95 ), # AL=0x90, AF=1 CF=1 + ( 0x91, 0x80 ), # AL=0x91, AF=0 CF=0 + ( 0xf1, 0x81 ), # AL=0x91, AF=0 CF=1 + ( 0x97, 0x90 ), # AL=0x91, AF=1 CF=0 + ( 0xf7, 0x91 ), # AL=0x91, AF=1 CF=1 + ( 0x92, 0x80 ), # AL=0x92, AF=0 CF=0 + ( 0xf2, 0x81 ), # AL=0x92, AF=0 CF=1 + ( 0x98, 0x90 ), # AL=0x92, AF=1 CF=0 + ( 0xf8, 0x91 ), # AL=0x92, AF=1 CF=1 + ( 0x93, 0x84 ), # AL=0x93, AF=0 CF=0 + ( 0xf3, 0x85 ), # AL=0x93, AF=0 CF=1 + ( 0x99, 0x94 ), # AL=0x93, AF=1 CF=0 + ( 0xf9, 0x95 ), # AL=0x93, AF=1 CF=1 + ( 0x94, 0x80 ), # AL=0x94, AF=0 CF=0 + ( 0xf4, 0x81 ), # AL=0x94, AF=0 CF=1 + ( 0x9a, 0x94 ), # AL=0x94, AF=1 CF=0 + ( 0xfa, 0x95 ), # AL=0x94, AF=1 CF=1 + ( 0x95, 0x84 ), # AL=0x95, AF=0 CF=0 + ( 0xf5, 0x85 ), # AL=0x95, AF=0 CF=1 + ( 0x9b, 0x90 ), # AL=0x95, AF=1 CF=0 + ( 0xfb, 0x91 ), # AL=0x95, AF=1 CF=1 + ( 0x96, 0x84 ), # AL=0x96, AF=0 CF=0 + ( 0xf6, 0x85 ), # AL=0x96, AF=0 CF=1 + ( 0x9c, 0x94 ), # AL=0x96, AF=1 CF=0 + ( 0xfc, 0x95 ), # AL=0x96, AF=1 CF=1 + ( 0x97, 0x80 ), # AL=0x97, AF=0 CF=0 + ( 0xf7, 0x81 ), # AL=0x97, AF=0 CF=1 + ( 0x9d, 0x90 ), # AL=0x97, AF=1 CF=0 + ( 0xfd, 0x91 ), # AL=0x97, AF=1 CF=1 + ( 0x98, 0x80 ), # AL=0x98, AF=0 CF=0 + ( 0xf8, 0x81 ), # AL=0x98, AF=0 CF=1 + ( 0x9e, 0x90 ), # AL=0x98, AF=1 CF=0 + ( 0xfe, 0x91 ), # AL=0x98, AF=1 CF=1 + ( 0x99, 0x84 ), # AL=0x99, AF=0 CF=0 + ( 0xf9, 0x85 ), # AL=0x99, AF=0 CF=1 + ( 0x9f, 0x94 ), # AL=0x99, AF=1 CF=0 + ( 0xff, 0x95 ), # AL=0x99, AF=1 CF=1 + ( 0x00, 0x55 ), # AL=0x9a, AF=0 CF=0 + ( 0x00, 0x55 ), # AL=0x9a, AF=0 CF=1 + ( 0x00, 0x55 ), # AL=0x9a, AF=1 CF=0 + ( 0x00, 0x55 ), # AL=0x9a, AF=1 CF=1 + ( 0x01, 0x11 ), # AL=0x9b, AF=0 CF=0 + ( 0x01, 0x11 ), # AL=0x9b, AF=0 CF=1 + ( 0x01, 0x11 ), # AL=0x9b, AF=1 CF=0 + ( 0x01, 0x11 ), # AL=0x9b, AF=1 CF=1 + ( 0x02, 0x11 ), # AL=0x9c, AF=0 CF=0 + ( 0x02, 0x11 ), # AL=0x9c, AF=0 CF=1 + ( 0x02, 0x11 ), # AL=0x9c, AF=1 CF=0 + ( 0x02, 0x11 ), # AL=0x9c, AF=1 CF=1 + ( 0x03, 0x15 ), # AL=0x9d, AF=0 CF=0 + ( 0x03, 0x15 ), # AL=0x9d, AF=0 CF=1 + ( 0x03, 0x15 ), # AL=0x9d, AF=1 CF=0 + ( 0x03, 0x15 ), # AL=0x9d, AF=1 CF=1 + ( 0x04, 0x11 ), # AL=0x9e, AF=0 CF=0 + ( 0x04, 0x11 ), # AL=0x9e, AF=0 CF=1 + ( 0x04, 0x11 ), # AL=0x9e, AF=1 CF=0 + ( 0x04, 0x11 ), # AL=0x9e, AF=1 CF=1 + ( 0x05, 0x15 ), # AL=0x9f, AF=0 CF=0 + ( 0x05, 0x15 ), # AL=0x9f, AF=0 CF=1 + ( 0x05, 0x15 ), # AL=0x9f, AF=1 CF=0 + ( 0x05, 0x15 ), # AL=0x9f, AF=1 CF=1 + ( 0x00, 0x45 ), # AL=0xa0, AF=0 CF=0 + ( 0x00, 0x45 ), # AL=0xa0, AF=0 CF=1 + ( 0x06, 0x15 ), # AL=0xa0, AF=1 CF=0 + ( 0x06, 0x15 ), # AL=0xa0, AF=1 CF=1 + ( 0x01, 0x01 ), # AL=0xa1, AF=0 CF=0 + ( 0x01, 0x01 ), # AL=0xa1, AF=0 CF=1 + ( 0x07, 0x11 ), # AL=0xa1, AF=1 CF=0 + ( 0x07, 0x11 ), # AL=0xa1, AF=1 CF=1 + ( 0x02, 0x01 ), # AL=0xa2, AF=0 CF=0 + ( 0x02, 0x01 ), # AL=0xa2, AF=0 CF=1 + ( 0x08, 0x11 ), # AL=0xa2, AF=1 CF=0 + ( 0x08, 0x11 ), # AL=0xa2, AF=1 CF=1 + ( 0x03, 0x05 ), # AL=0xa3, AF=0 CF=0 + ( 0x03, 0x05 ), # AL=0xa3, AF=0 CF=1 + ( 0x09, 0x15 ), # AL=0xa3, AF=1 CF=0 + ( 0x09, 0x15 ), # AL=0xa3, AF=1 CF=1 + ( 0x04, 0x01 ), # AL=0xa4, AF=0 CF=0 + ( 0x04, 0x01 ), # AL=0xa4, AF=0 CF=1 + ( 0x0a, 0x15 ), # AL=0xa4, AF=1 CF=0 + ( 0x0a, 0x15 ), # AL=0xa4, AF=1 CF=1 + ( 0x05, 0x05 ), # AL=0xa5, AF=0 CF=0 + ( 0x05, 0x05 ), # AL=0xa5, AF=0 CF=1 + ( 0x0b, 0x11 ), # AL=0xa5, AF=1 CF=0 + ( 0x0b, 0x11 ), # AL=0xa5, AF=1 CF=1 + ( 0x06, 0x05 ), # AL=0xa6, AF=0 CF=0 + ( 0x06, 0x05 ), # AL=0xa6, AF=0 CF=1 + ( 0x0c, 0x15 ), # AL=0xa6, AF=1 CF=0 + ( 0x0c, 0x15 ), # AL=0xa6, AF=1 CF=1 + ( 0x07, 0x01 ), # AL=0xa7, AF=0 CF=0 + ( 0x07, 0x01 ), # AL=0xa7, AF=0 CF=1 + ( 0x0d, 0x11 ), # AL=0xa7, AF=1 CF=0 + ( 0x0d, 0x11 ), # AL=0xa7, AF=1 CF=1 + ( 0x08, 0x01 ), # AL=0xa8, AF=0 CF=0 + ( 0x08, 0x01 ), # AL=0xa8, AF=0 CF=1 + ( 0x0e, 0x11 ), # AL=0xa8, AF=1 CF=0 + ( 0x0e, 0x11 ), # AL=0xa8, AF=1 CF=1 + ( 0x09, 0x05 ), # AL=0xa9, AF=0 CF=0 + ( 0x09, 0x05 ), # AL=0xa9, AF=0 CF=1 + ( 0x0f, 0x15 ), # AL=0xa9, AF=1 CF=0 + ( 0x0f, 0x15 ), # AL=0xa9, AF=1 CF=1 + ( 0x10, 0x11 ), # AL=0xaa, AF=0 CF=0 + ( 0x10, 0x11 ), # AL=0xaa, AF=0 CF=1 + ( 0x10, 0x11 ), # AL=0xaa, AF=1 CF=0 + ( 0x10, 0x11 ), # AL=0xaa, AF=1 CF=1 + ( 0x11, 0x15 ), # AL=0xab, AF=0 CF=0 + ( 0x11, 0x15 ), # AL=0xab, AF=0 CF=1 + ( 0x11, 0x15 ), # AL=0xab, AF=1 CF=0 + ( 0x11, 0x15 ), # AL=0xab, AF=1 CF=1 + ( 0x12, 0x15 ), # AL=0xac, AF=0 CF=0 + ( 0x12, 0x15 ), # AL=0xac, AF=0 CF=1 + ( 0x12, 0x15 ), # AL=0xac, AF=1 CF=0 + ( 0x12, 0x15 ), # AL=0xac, AF=1 CF=1 + ( 0x13, 0x11 ), # AL=0xad, AF=0 CF=0 + ( 0x13, 0x11 ), # AL=0xad, AF=0 CF=1 + ( 0x13, 0x11 ), # AL=0xad, AF=1 CF=0 + ( 0x13, 0x11 ), # AL=0xad, AF=1 CF=1 + ( 0x14, 0x15 ), # AL=0xae, AF=0 CF=0 + ( 0x14, 0x15 ), # AL=0xae, AF=0 CF=1 + ( 0x14, 0x15 ), # AL=0xae, AF=1 CF=0 + ( 0x14, 0x15 ), # AL=0xae, AF=1 CF=1 + ( 0x15, 0x11 ), # AL=0xaf, AF=0 CF=0 + ( 0x15, 0x11 ), # AL=0xaf, AF=0 CF=1 + ( 0x15, 0x11 ), # AL=0xaf, AF=1 CF=0 + ( 0x15, 0x11 ), # AL=0xaf, AF=1 CF=1 + ( 0x10, 0x01 ), # AL=0xb0, AF=0 CF=0 + ( 0x10, 0x01 ), # AL=0xb0, AF=0 CF=1 + ( 0x16, 0x11 ), # AL=0xb0, AF=1 CF=0 + ( 0x16, 0x11 ), # AL=0xb0, AF=1 CF=1 + ( 0x11, 0x05 ), # AL=0xb1, AF=0 CF=0 + ( 0x11, 0x05 ), # AL=0xb1, AF=0 CF=1 + ( 0x17, 0x15 ), # AL=0xb1, AF=1 CF=0 + ( 0x17, 0x15 ), # AL=0xb1, AF=1 CF=1 + ( 0x12, 0x05 ), # AL=0xb2, AF=0 CF=0 + ( 0x12, 0x05 ), # AL=0xb2, AF=0 CF=1 + ( 0x18, 0x15 ), # AL=0xb2, AF=1 CF=0 + ( 0x18, 0x15 ), # AL=0xb2, AF=1 CF=1 + ( 0x13, 0x01 ), # AL=0xb3, AF=0 CF=0 + ( 0x13, 0x01 ), # AL=0xb3, AF=0 CF=1 + ( 0x19, 0x11 ), # AL=0xb3, AF=1 CF=0 + ( 0x19, 0x11 ), # AL=0xb3, AF=1 CF=1 + ( 0x14, 0x05 ), # AL=0xb4, AF=0 CF=0 + ( 0x14, 0x05 ), # AL=0xb4, AF=0 CF=1 + ( 0x1a, 0x11 ), # AL=0xb4, AF=1 CF=0 + ( 0x1a, 0x11 ), # AL=0xb4, AF=1 CF=1 + ( 0x15, 0x01 ), # AL=0xb5, AF=0 CF=0 + ( 0x15, 0x01 ), # AL=0xb5, AF=0 CF=1 + ( 0x1b, 0x15 ), # AL=0xb5, AF=1 CF=0 + ( 0x1b, 0x15 ), # AL=0xb5, AF=1 CF=1 + ( 0x16, 0x01 ), # AL=0xb6, AF=0 CF=0 + ( 0x16, 0x01 ), # AL=0xb6, AF=0 CF=1 + ( 0x1c, 0x11 ), # AL=0xb6, AF=1 CF=0 + ( 0x1c, 0x11 ), # AL=0xb6, AF=1 CF=1 + ( 0x17, 0x05 ), # AL=0xb7, AF=0 CF=0 + ( 0x17, 0x05 ), # AL=0xb7, AF=0 CF=1 + ( 0x1d, 0x15 ), # AL=0xb7, AF=1 CF=0 + ( 0x1d, 0x15 ), # AL=0xb7, AF=1 CF=1 + ( 0x18, 0x05 ), # AL=0xb8, AF=0 CF=0 + ( 0x18, 0x05 ), # AL=0xb8, AF=0 CF=1 + ( 0x1e, 0x15 ), # AL=0xb8, AF=1 CF=0 + ( 0x1e, 0x15 ), # AL=0xb8, AF=1 CF=1 + ( 0x19, 0x01 ), # AL=0xb9, AF=0 CF=0 + ( 0x19, 0x01 ), # AL=0xb9, AF=0 CF=1 + ( 0x1f, 0x11 ), # AL=0xb9, AF=1 CF=0 + ( 0x1f, 0x11 ), # AL=0xb9, AF=1 CF=1 + ( 0x20, 0x11 ), # AL=0xba, AF=0 CF=0 + ( 0x20, 0x11 ), # AL=0xba, AF=0 CF=1 + ( 0x20, 0x11 ), # AL=0xba, AF=1 CF=0 + ( 0x20, 0x11 ), # AL=0xba, AF=1 CF=1 + ( 0x21, 0x15 ), # AL=0xbb, AF=0 CF=0 + ( 0x21, 0x15 ), # AL=0xbb, AF=0 CF=1 + ( 0x21, 0x15 ), # AL=0xbb, AF=1 CF=0 + ( 0x21, 0x15 ), # AL=0xbb, AF=1 CF=1 + ( 0x22, 0x15 ), # AL=0xbc, AF=0 CF=0 + ( 0x22, 0x15 ), # AL=0xbc, AF=0 CF=1 + ( 0x22, 0x15 ), # AL=0xbc, AF=1 CF=0 + ( 0x22, 0x15 ), # AL=0xbc, AF=1 CF=1 + ( 0x23, 0x11 ), # AL=0xbd, AF=0 CF=0 + ( 0x23, 0x11 ), # AL=0xbd, AF=0 CF=1 + ( 0x23, 0x11 ), # AL=0xbd, AF=1 CF=0 + ( 0x23, 0x11 ), # AL=0xbd, AF=1 CF=1 + ( 0x24, 0x15 ), # AL=0xbe, AF=0 CF=0 + ( 0x24, 0x15 ), # AL=0xbe, AF=0 CF=1 + ( 0x24, 0x15 ), # AL=0xbe, AF=1 CF=0 + ( 0x24, 0x15 ), # AL=0xbe, AF=1 CF=1 + ( 0x25, 0x11 ), # AL=0xbf, AF=0 CF=0 + ( 0x25, 0x11 ), # AL=0xbf, AF=0 CF=1 + ( 0x25, 0x11 ), # AL=0xbf, AF=1 CF=0 + ( 0x25, 0x11 ), # AL=0xbf, AF=1 CF=1 + ( 0x20, 0x01 ), # AL=0xc0, AF=0 CF=0 + ( 0x20, 0x01 ), # AL=0xc0, AF=0 CF=1 + ( 0x26, 0x11 ), # AL=0xc0, AF=1 CF=0 + ( 0x26, 0x11 ), # AL=0xc0, AF=1 CF=1 + ( 0x21, 0x05 ), # AL=0xc1, AF=0 CF=0 + ( 0x21, 0x05 ), # AL=0xc1, AF=0 CF=1 + ( 0x27, 0x15 ), # AL=0xc1, AF=1 CF=0 + ( 0x27, 0x15 ), # AL=0xc1, AF=1 CF=1 + ( 0x22, 0x05 ), # AL=0xc2, AF=0 CF=0 + ( 0x22, 0x05 ), # AL=0xc2, AF=0 CF=1 + ( 0x28, 0x15 ), # AL=0xc2, AF=1 CF=0 + ( 0x28, 0x15 ), # AL=0xc2, AF=1 CF=1 + ( 0x23, 0x01 ), # AL=0xc3, AF=0 CF=0 + ( 0x23, 0x01 ), # AL=0xc3, AF=0 CF=1 + ( 0x29, 0x11 ), # AL=0xc3, AF=1 CF=0 + ( 0x29, 0x11 ), # AL=0xc3, AF=1 CF=1 + ( 0x24, 0x05 ), # AL=0xc4, AF=0 CF=0 + ( 0x24, 0x05 ), # AL=0xc4, AF=0 CF=1 + ( 0x2a, 0x11 ), # AL=0xc4, AF=1 CF=0 + ( 0x2a, 0x11 ), # AL=0xc4, AF=1 CF=1 + ( 0x25, 0x01 ), # AL=0xc5, AF=0 CF=0 + ( 0x25, 0x01 ), # AL=0xc5, AF=0 CF=1 + ( 0x2b, 0x15 ), # AL=0xc5, AF=1 CF=0 + ( 0x2b, 0x15 ), # AL=0xc5, AF=1 CF=1 + ( 0x26, 0x01 ), # AL=0xc6, AF=0 CF=0 + ( 0x26, 0x01 ), # AL=0xc6, AF=0 CF=1 + ( 0x2c, 0x11 ), # AL=0xc6, AF=1 CF=0 + ( 0x2c, 0x11 ), # AL=0xc6, AF=1 CF=1 + ( 0x27, 0x05 ), # AL=0xc7, AF=0 CF=0 + ( 0x27, 0x05 ), # AL=0xc7, AF=0 CF=1 + ( 0x2d, 0x15 ), # AL=0xc7, AF=1 CF=0 + ( 0x2d, 0x15 ), # AL=0xc7, AF=1 CF=1 + ( 0x28, 0x05 ), # AL=0xc8, AF=0 CF=0 + ( 0x28, 0x05 ), # AL=0xc8, AF=0 CF=1 + ( 0x2e, 0x15 ), # AL=0xc8, AF=1 CF=0 + ( 0x2e, 0x15 ), # AL=0xc8, AF=1 CF=1 + ( 0x29, 0x01 ), # AL=0xc9, AF=0 CF=0 + ( 0x29, 0x01 ), # AL=0xc9, AF=0 CF=1 + ( 0x2f, 0x11 ), # AL=0xc9, AF=1 CF=0 + ( 0x2f, 0x11 ), # AL=0xc9, AF=1 CF=1 + ( 0x30, 0x15 ), # AL=0xca, AF=0 CF=0 + ( 0x30, 0x15 ), # AL=0xca, AF=0 CF=1 + ( 0x30, 0x15 ), # AL=0xca, AF=1 CF=0 + ( 0x30, 0x15 ), # AL=0xca, AF=1 CF=1 + ( 0x31, 0x11 ), # AL=0xcb, AF=0 CF=0 + ( 0x31, 0x11 ), # AL=0xcb, AF=0 CF=1 + ( 0x31, 0x11 ), # AL=0xcb, AF=1 CF=0 + ( 0x31, 0x11 ), # AL=0xcb, AF=1 CF=1 + ( 0x32, 0x11 ), # AL=0xcc, AF=0 CF=0 + ( 0x32, 0x11 ), # AL=0xcc, AF=0 CF=1 + ( 0x32, 0x11 ), # AL=0xcc, AF=1 CF=0 + ( 0x32, 0x11 ), # AL=0xcc, AF=1 CF=1 + ( 0x33, 0x15 ), # AL=0xcd, AF=0 CF=0 + ( 0x33, 0x15 ), # AL=0xcd, AF=0 CF=1 + ( 0x33, 0x15 ), # AL=0xcd, AF=1 CF=0 + ( 0x33, 0x15 ), # AL=0xcd, AF=1 CF=1 + ( 0x34, 0x11 ), # AL=0xce, AF=0 CF=0 + ( 0x34, 0x11 ), # AL=0xce, AF=0 CF=1 + ( 0x34, 0x11 ), # AL=0xce, AF=1 CF=0 + ( 0x34, 0x11 ), # AL=0xce, AF=1 CF=1 + ( 0x35, 0x15 ), # AL=0xcf, AF=0 CF=0 + ( 0x35, 0x15 ), # AL=0xcf, AF=0 CF=1 + ( 0x35, 0x15 ), # AL=0xcf, AF=1 CF=0 + ( 0x35, 0x15 ), # AL=0xcf, AF=1 CF=1 + ( 0x30, 0x05 ), # AL=0xd0, AF=0 CF=0 + ( 0x30, 0x05 ), # AL=0xd0, AF=0 CF=1 + ( 0x36, 0x15 ), # AL=0xd0, AF=1 CF=0 + ( 0x36, 0x15 ), # AL=0xd0, AF=1 CF=1 + ( 0x31, 0x01 ), # AL=0xd1, AF=0 CF=0 + ( 0x31, 0x01 ), # AL=0xd1, AF=0 CF=1 + ( 0x37, 0x11 ), # AL=0xd1, AF=1 CF=0 + ( 0x37, 0x11 ), # AL=0xd1, AF=1 CF=1 + ( 0x32, 0x01 ), # AL=0xd2, AF=0 CF=0 + ( 0x32, 0x01 ), # AL=0xd2, AF=0 CF=1 + ( 0x38, 0x11 ), # AL=0xd2, AF=1 CF=0 + ( 0x38, 0x11 ), # AL=0xd2, AF=1 CF=1 + ( 0x33, 0x05 ), # AL=0xd3, AF=0 CF=0 + ( 0x33, 0x05 ), # AL=0xd3, AF=0 CF=1 + ( 0x39, 0x15 ), # AL=0xd3, AF=1 CF=0 + ( 0x39, 0x15 ), # AL=0xd3, AF=1 CF=1 + ( 0x34, 0x01 ), # AL=0xd4, AF=0 CF=0 + ( 0x34, 0x01 ), # AL=0xd4, AF=0 CF=1 + ( 0x3a, 0x15 ), # AL=0xd4, AF=1 CF=0 + ( 0x3a, 0x15 ), # AL=0xd4, AF=1 CF=1 + ( 0x35, 0x05 ), # AL=0xd5, AF=0 CF=0 + ( 0x35, 0x05 ), # AL=0xd5, AF=0 CF=1 + ( 0x3b, 0x11 ), # AL=0xd5, AF=1 CF=0 + ( 0x3b, 0x11 ), # AL=0xd5, AF=1 CF=1 + ( 0x36, 0x05 ), # AL=0xd6, AF=0 CF=0 + ( 0x36, 0x05 ), # AL=0xd6, AF=0 CF=1 + ( 0x3c, 0x15 ), # AL=0xd6, AF=1 CF=0 + ( 0x3c, 0x15 ), # AL=0xd6, AF=1 CF=1 + ( 0x37, 0x01 ), # AL=0xd7, AF=0 CF=0 + ( 0x37, 0x01 ), # AL=0xd7, AF=0 CF=1 + ( 0x3d, 0x11 ), # AL=0xd7, AF=1 CF=0 + ( 0x3d, 0x11 ), # AL=0xd7, AF=1 CF=1 + ( 0x38, 0x01 ), # AL=0xd8, AF=0 CF=0 + ( 0x38, 0x01 ), # AL=0xd8, AF=0 CF=1 + ( 0x3e, 0x11 ), # AL=0xd8, AF=1 CF=0 + ( 0x3e, 0x11 ), # AL=0xd8, AF=1 CF=1 + ( 0x39, 0x05 ), # AL=0xd9, AF=0 CF=0 + ( 0x39, 0x05 ), # AL=0xd9, AF=0 CF=1 + ( 0x3f, 0x15 ), # AL=0xd9, AF=1 CF=0 + ( 0x3f, 0x15 ), # AL=0xd9, AF=1 CF=1 + ( 0x40, 0x11 ), # AL=0xda, AF=0 CF=0 + ( 0x40, 0x11 ), # AL=0xda, AF=0 CF=1 + ( 0x40, 0x11 ), # AL=0xda, AF=1 CF=0 + ( 0x40, 0x11 ), # AL=0xda, AF=1 CF=1 + ( 0x41, 0x15 ), # AL=0xdb, AF=0 CF=0 + ( 0x41, 0x15 ), # AL=0xdb, AF=0 CF=1 + ( 0x41, 0x15 ), # AL=0xdb, AF=1 CF=0 + ( 0x41, 0x15 ), # AL=0xdb, AF=1 CF=1 + ( 0x42, 0x15 ), # AL=0xdc, AF=0 CF=0 + ( 0x42, 0x15 ), # AL=0xdc, AF=0 CF=1 + ( 0x42, 0x15 ), # AL=0xdc, AF=1 CF=0 + ( 0x42, 0x15 ), # AL=0xdc, AF=1 CF=1 + ( 0x43, 0x11 ), # AL=0xdd, AF=0 CF=0 + ( 0x43, 0x11 ), # AL=0xdd, AF=0 CF=1 + ( 0x43, 0x11 ), # AL=0xdd, AF=1 CF=0 + ( 0x43, 0x11 ), # AL=0xdd, AF=1 CF=1 + ( 0x44, 0x15 ), # AL=0xde, AF=0 CF=0 + ( 0x44, 0x15 ), # AL=0xde, AF=0 CF=1 + ( 0x44, 0x15 ), # AL=0xde, AF=1 CF=0 + ( 0x44, 0x15 ), # AL=0xde, AF=1 CF=1 + ( 0x45, 0x11 ), # AL=0xdf, AF=0 CF=0 + ( 0x45, 0x11 ), # AL=0xdf, AF=0 CF=1 + ( 0x45, 0x11 ), # AL=0xdf, AF=1 CF=0 + ( 0x45, 0x11 ), # AL=0xdf, AF=1 CF=1 + ( 0x40, 0x01 ), # AL=0xe0, AF=0 CF=0 + ( 0x40, 0x01 ), # AL=0xe0, AF=0 CF=1 + ( 0x46, 0x11 ), # AL=0xe0, AF=1 CF=0 + ( 0x46, 0x11 ), # AL=0xe0, AF=1 CF=1 + ( 0x41, 0x05 ), # AL=0xe1, AF=0 CF=0 + ( 0x41, 0x05 ), # AL=0xe1, AF=0 CF=1 + ( 0x47, 0x15 ), # AL=0xe1, AF=1 CF=0 + ( 0x47, 0x15 ), # AL=0xe1, AF=1 CF=1 + ( 0x42, 0x05 ), # AL=0xe2, AF=0 CF=0 + ( 0x42, 0x05 ), # AL=0xe2, AF=0 CF=1 + ( 0x48, 0x15 ), # AL=0xe2, AF=1 CF=0 + ( 0x48, 0x15 ), # AL=0xe2, AF=1 CF=1 + ( 0x43, 0x01 ), # AL=0xe3, AF=0 CF=0 + ( 0x43, 0x01 ), # AL=0xe3, AF=0 CF=1 + ( 0x49, 0x11 ), # AL=0xe3, AF=1 CF=0 + ( 0x49, 0x11 ), # AL=0xe3, AF=1 CF=1 + ( 0x44, 0x05 ), # AL=0xe4, AF=0 CF=0 + ( 0x44, 0x05 ), # AL=0xe4, AF=0 CF=1 + ( 0x4a, 0x11 ), # AL=0xe4, AF=1 CF=0 + ( 0x4a, 0x11 ), # AL=0xe4, AF=1 CF=1 + ( 0x45, 0x01 ), # AL=0xe5, AF=0 CF=0 + ( 0x45, 0x01 ), # AL=0xe5, AF=0 CF=1 + ( 0x4b, 0x15 ), # AL=0xe5, AF=1 CF=0 + ( 0x4b, 0x15 ), # AL=0xe5, AF=1 CF=1 + ( 0x46, 0x01 ), # AL=0xe6, AF=0 CF=0 + ( 0x46, 0x01 ), # AL=0xe6, AF=0 CF=1 + ( 0x4c, 0x11 ), # AL=0xe6, AF=1 CF=0 + ( 0x4c, 0x11 ), # AL=0xe6, AF=1 CF=1 + ( 0x47, 0x05 ), # AL=0xe7, AF=0 CF=0 + ( 0x47, 0x05 ), # AL=0xe7, AF=0 CF=1 + ( 0x4d, 0x15 ), # AL=0xe7, AF=1 CF=0 + ( 0x4d, 0x15 ), # AL=0xe7, AF=1 CF=1 + ( 0x48, 0x05 ), # AL=0xe8, AF=0 CF=0 + ( 0x48, 0x05 ), # AL=0xe8, AF=0 CF=1 + ( 0x4e, 0x15 ), # AL=0xe8, AF=1 CF=0 + ( 0x4e, 0x15 ), # AL=0xe8, AF=1 CF=1 + ( 0x49, 0x01 ), # AL=0xe9, AF=0 CF=0 + ( 0x49, 0x01 ), # AL=0xe9, AF=0 CF=1 + ( 0x4f, 0x11 ), # AL=0xe9, AF=1 CF=0 + ( 0x4f, 0x11 ), # AL=0xe9, AF=1 CF=1 + ( 0x50, 0x15 ), # AL=0xea, AF=0 CF=0 + ( 0x50, 0x15 ), # AL=0xea, AF=0 CF=1 + ( 0x50, 0x15 ), # AL=0xea, AF=1 CF=0 + ( 0x50, 0x15 ), # AL=0xea, AF=1 CF=1 + ( 0x51, 0x11 ), # AL=0xeb, AF=0 CF=0 + ( 0x51, 0x11 ), # AL=0xeb, AF=0 CF=1 + ( 0x51, 0x11 ), # AL=0xeb, AF=1 CF=0 + ( 0x51, 0x11 ), # AL=0xeb, AF=1 CF=1 + ( 0x52, 0x11 ), # AL=0xec, AF=0 CF=0 + ( 0x52, 0x11 ), # AL=0xec, AF=0 CF=1 + ( 0x52, 0x11 ), # AL=0xec, AF=1 CF=0 + ( 0x52, 0x11 ), # AL=0xec, AF=1 CF=1 + ( 0x53, 0x15 ), # AL=0xed, AF=0 CF=0 + ( 0x53, 0x15 ), # AL=0xed, AF=0 CF=1 + ( 0x53, 0x15 ), # AL=0xed, AF=1 CF=0 + ( 0x53, 0x15 ), # AL=0xed, AF=1 CF=1 + ( 0x54, 0x11 ), # AL=0xee, AF=0 CF=0 + ( 0x54, 0x11 ), # AL=0xee, AF=0 CF=1 + ( 0x54, 0x11 ), # AL=0xee, AF=1 CF=0 + ( 0x54, 0x11 ), # AL=0xee, AF=1 CF=1 + ( 0x55, 0x15 ), # AL=0xef, AF=0 CF=0 + ( 0x55, 0x15 ), # AL=0xef, AF=0 CF=1 + ( 0x55, 0x15 ), # AL=0xef, AF=1 CF=0 + ( 0x55, 0x15 ), # AL=0xef, AF=1 CF=1 + ( 0x50, 0x05 ), # AL=0xf0, AF=0 CF=0 + ( 0x50, 0x05 ), # AL=0xf0, AF=0 CF=1 + ( 0x56, 0x15 ), # AL=0xf0, AF=1 CF=0 + ( 0x56, 0x15 ), # AL=0xf0, AF=1 CF=1 + ( 0x51, 0x01 ), # AL=0xf1, AF=0 CF=0 + ( 0x51, 0x01 ), # AL=0xf1, AF=0 CF=1 + ( 0x57, 0x11 ), # AL=0xf1, AF=1 CF=0 + ( 0x57, 0x11 ), # AL=0xf1, AF=1 CF=1 + ( 0x52, 0x01 ), # AL=0xf2, AF=0 CF=0 + ( 0x52, 0x01 ), # AL=0xf2, AF=0 CF=1 + ( 0x58, 0x11 ), # AL=0xf2, AF=1 CF=0 + ( 0x58, 0x11 ), # AL=0xf2, AF=1 CF=1 + ( 0x53, 0x05 ), # AL=0xf3, AF=0 CF=0 + ( 0x53, 0x05 ), # AL=0xf3, AF=0 CF=1 + ( 0x59, 0x15 ), # AL=0xf3, AF=1 CF=0 + ( 0x59, 0x15 ), # AL=0xf3, AF=1 CF=1 + ( 0x54, 0x01 ), # AL=0xf4, AF=0 CF=0 + ( 0x54, 0x01 ), # AL=0xf4, AF=0 CF=1 + ( 0x5a, 0x15 ), # AL=0xf4, AF=1 CF=0 + ( 0x5a, 0x15 ), # AL=0xf4, AF=1 CF=1 + ( 0x55, 0x05 ), # AL=0xf5, AF=0 CF=0 + ( 0x55, 0x05 ), # AL=0xf5, AF=0 CF=1 + ( 0x5b, 0x11 ), # AL=0xf5, AF=1 CF=0 + ( 0x5b, 0x11 ), # AL=0xf5, AF=1 CF=1 + ( 0x56, 0x05 ), # AL=0xf6, AF=0 CF=0 + ( 0x56, 0x05 ), # AL=0xf6, AF=0 CF=1 + ( 0x5c, 0x15 ), # AL=0xf6, AF=1 CF=0 + ( 0x5c, 0x15 ), # AL=0xf6, AF=1 CF=1 + ( 0x57, 0x01 ), # AL=0xf7, AF=0 CF=0 + ( 0x57, 0x01 ), # AL=0xf7, AF=0 CF=1 + ( 0x5d, 0x11 ), # AL=0xf7, AF=1 CF=0 + ( 0x5d, 0x11 ), # AL=0xf7, AF=1 CF=1 + ( 0x58, 0x01 ), # AL=0xf8, AF=0 CF=0 + ( 0x58, 0x01 ), # AL=0xf8, AF=0 CF=1 + ( 0x5e, 0x11 ), # AL=0xf8, AF=1 CF=0 + ( 0x5e, 0x11 ), # AL=0xf8, AF=1 CF=1 + ( 0x59, 0x05 ), # AL=0xf9, AF=0 CF=0 + ( 0x59, 0x05 ), # AL=0xf9, AF=0 CF=1 + ( 0x5f, 0x15 ), # AL=0xf9, AF=1 CF=0 + ( 0x5f, 0x15 ), # AL=0xf9, AF=1 CF=1 + ( 0x60, 0x15 ), # AL=0xfa, AF=0 CF=0 + ( 0x60, 0x15 ), # AL=0xfa, AF=0 CF=1 + ( 0x60, 0x15 ), # AL=0xfa, AF=1 CF=0 + ( 0x60, 0x15 ), # AL=0xfa, AF=1 CF=1 + ( 0x61, 0x11 ), # AL=0xfb, AF=0 CF=0 + ( 0x61, 0x11 ), # AL=0xfb, AF=0 CF=1 + ( 0x61, 0x11 ), # AL=0xfb, AF=1 CF=0 + ( 0x61, 0x11 ), # AL=0xfb, AF=1 CF=1 + ( 0x62, 0x11 ), # AL=0xfc, AF=0 CF=0 + ( 0x62, 0x11 ), # AL=0xfc, AF=0 CF=1 + ( 0x62, 0x11 ), # AL=0xfc, AF=1 CF=0 + ( 0x62, 0x11 ), # AL=0xfc, AF=1 CF=1 + ( 0x63, 0x15 ), # AL=0xfd, AF=0 CF=0 + ( 0x63, 0x15 ), # AL=0xfd, AF=0 CF=1 + ( 0x63, 0x15 ), # AL=0xfd, AF=1 CF=0 + ( 0x63, 0x15 ), # AL=0xfd, AF=1 CF=1 + ( 0x64, 0x11 ), # AL=0xfe, AF=0 CF=0 + ( 0x64, 0x11 ), # AL=0xfe, AF=0 CF=1 + ( 0x64, 0x11 ), # AL=0xfe, AF=1 CF=0 + ( 0x64, 0x11 ), # AL=0xfe, AF=1 CF=1 + ( 0x65, 0x15 ), # AL=0xff, AF=0 CF=0 + ( 0x65, 0x15 ), # AL=0xff, AF=0 CF=1 + ( 0x65, 0x15 ), # AL=0xff, AF=1 CF=0 + ( 0x65, 0x15 ), # AL=0xff, AF=1 CF=1 +]; + diff --git a/src/VBox/VMM/testcase/Instructions/itgTableDas.py b/src/VBox/VMM/testcase/Instructions/itgTableDas.py new file mode 100644 index 00000000..2c2d5d95 --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/itgTableDas.py @@ -0,0 +1,1105 @@ +# -*- coding: utf-8 -*- +# $Id: itgTableDas.py $ + +""" +DAS (instruction) result table. +""" + + +__copyright__ = \ +""" +Copyright (C) 2012-2019 Oracle Corporation + +This file is part of VirtualBox Open Source Edition (OSE), as +available from http://www.virtualbox.org. This file is free software; +you can redistribute it and/or modify it under the terms of the GNU +General Public License (GPL) as published by the Free Software +Foundation, in version 2 as it comes in the "COPYING" file of the +VirtualBox OSE distribution. VirtualBox OSE is distributed in the +hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +""" +__version__ = "$Revision: 127855 $"; + + +## The 32-bit GCC (C99) program that produced the table below. +g_sItgCProgramDas = \ +""" +#include + +int main() +{ + for (unsigned uInputAL = 0; uInputAL < 256; uInputAL++) + for (unsigned fAux = 0; fAux < 2; fAux++) + for (unsigned fCarry = 0; fCarry < 2; fCarry++) + { + unsigned uInputEFlags = fCarry | (fAux << 4); + unsigned uResultAL; + unsigned uResultEFlags; + __asm__ __volatile__("pushl %1\\n" + "popfl\\n" + "das\\n" + "pushf\\n" + "pop %1\\n" + : "=a" (uResultAL), + "=r" (uResultEFlags) + : "0" (uInputAL), + "1" (uInputEFlags) + : "memory" + ); + printf(" ( 0x%02x, 0x%02x ), # AL=0x%02x, AF=%u CF=%u\\n", + uResultAL, uResultEFlags & 0xd5, uInputAL, fAux, fCarry); + /* 0xd5 = CF, PF, AF, ZF, SF */ + } + return 0; +} +"""; + + +# +# Compile and run the above program if requested to do so. +# +if __name__ == '__main__': + import sys; + if len(sys.argv) > 1 and sys.argv[1] == 'gen': + import subprocess; + oProc = subprocess.Popen(['gcc', '-x', 'c', '-std=gnu99', '-m32', '-o', './itgTableDas', '-'], stdin = subprocess.PIPE); + oProc.communicate(g_sItgCProgramDas); + oProc.wait(); + oProc = subprocess.Popen(['./itgTableDas',]).wait(); + sys.exit(0); + + + +## +# The DAS results. +# +# The index / input relation is: index = (AL << 2) | (CF << 1) | AF +# +g_aItgDasResults = \ +[ + ( 0x00, 0x44 ), # AL=0x00, AF=0 CF=0 + ( 0xa0, 0x85 ), # AL=0x00, AF=0 CF=1 + ( 0xfa, 0x95 ), # AL=0x00, AF=1 CF=0 + ( 0x9a, 0x95 ), # AL=0x00, AF=1 CF=1 + ( 0x01, 0x00 ), # AL=0x01, AF=0 CF=0 + ( 0xa1, 0x81 ), # AL=0x01, AF=0 CF=1 + ( 0xfb, 0x91 ), # AL=0x01, AF=1 CF=0 + ( 0x9b, 0x91 ), # AL=0x01, AF=1 CF=1 + ( 0x02, 0x00 ), # AL=0x02, AF=0 CF=0 + ( 0xa2, 0x81 ), # AL=0x02, AF=0 CF=1 + ( 0xfc, 0x95 ), # AL=0x02, AF=1 CF=0 + ( 0x9c, 0x95 ), # AL=0x02, AF=1 CF=1 + ( 0x03, 0x04 ), # AL=0x03, AF=0 CF=0 + ( 0xa3, 0x85 ), # AL=0x03, AF=0 CF=1 + ( 0xfd, 0x91 ), # AL=0x03, AF=1 CF=0 + ( 0x9d, 0x91 ), # AL=0x03, AF=1 CF=1 + ( 0x04, 0x00 ), # AL=0x04, AF=0 CF=0 + ( 0xa4, 0x81 ), # AL=0x04, AF=0 CF=1 + ( 0xfe, 0x91 ), # AL=0x04, AF=1 CF=0 + ( 0x9e, 0x91 ), # AL=0x04, AF=1 CF=1 + ( 0x05, 0x04 ), # AL=0x05, AF=0 CF=0 + ( 0xa5, 0x85 ), # AL=0x05, AF=0 CF=1 + ( 0xff, 0x95 ), # AL=0x05, AF=1 CF=0 + ( 0x9f, 0x95 ), # AL=0x05, AF=1 CF=1 + ( 0x06, 0x04 ), # AL=0x06, AF=0 CF=0 + ( 0xa6, 0x85 ), # AL=0x06, AF=0 CF=1 + ( 0x00, 0x54 ), # AL=0x06, AF=1 CF=0 + ( 0xa0, 0x95 ), # AL=0x06, AF=1 CF=1 + ( 0x07, 0x00 ), # AL=0x07, AF=0 CF=0 + ( 0xa7, 0x81 ), # AL=0x07, AF=0 CF=1 + ( 0x01, 0x10 ), # AL=0x07, AF=1 CF=0 + ( 0xa1, 0x91 ), # AL=0x07, AF=1 CF=1 + ( 0x08, 0x00 ), # AL=0x08, AF=0 CF=0 + ( 0xa8, 0x81 ), # AL=0x08, AF=0 CF=1 + ( 0x02, 0x10 ), # AL=0x08, AF=1 CF=0 + ( 0xa2, 0x91 ), # AL=0x08, AF=1 CF=1 + ( 0x09, 0x04 ), # AL=0x09, AF=0 CF=0 + ( 0xa9, 0x85 ), # AL=0x09, AF=0 CF=1 + ( 0x03, 0x14 ), # AL=0x09, AF=1 CF=0 + ( 0xa3, 0x95 ), # AL=0x09, AF=1 CF=1 + ( 0x04, 0x10 ), # AL=0x0a, AF=0 CF=0 + ( 0xa4, 0x91 ), # AL=0x0a, AF=0 CF=1 + ( 0x04, 0x10 ), # AL=0x0a, AF=1 CF=0 + ( 0xa4, 0x91 ), # AL=0x0a, AF=1 CF=1 + ( 0x05, 0x14 ), # AL=0x0b, AF=0 CF=0 + ( 0xa5, 0x95 ), # AL=0x0b, AF=0 CF=1 + ( 0x05, 0x14 ), # AL=0x0b, AF=1 CF=0 + ( 0xa5, 0x95 ), # AL=0x0b, AF=1 CF=1 + ( 0x06, 0x14 ), # AL=0x0c, AF=0 CF=0 + ( 0xa6, 0x95 ), # AL=0x0c, AF=0 CF=1 + ( 0x06, 0x14 ), # AL=0x0c, AF=1 CF=0 + ( 0xa6, 0x95 ), # AL=0x0c, AF=1 CF=1 + ( 0x07, 0x10 ), # AL=0x0d, AF=0 CF=0 + ( 0xa7, 0x91 ), # AL=0x0d, AF=0 CF=1 + ( 0x07, 0x10 ), # AL=0x0d, AF=1 CF=0 + ( 0xa7, 0x91 ), # AL=0x0d, AF=1 CF=1 + ( 0x08, 0x10 ), # AL=0x0e, AF=0 CF=0 + ( 0xa8, 0x91 ), # AL=0x0e, AF=0 CF=1 + ( 0x08, 0x10 ), # AL=0x0e, AF=1 CF=0 + ( 0xa8, 0x91 ), # AL=0x0e, AF=1 CF=1 + ( 0x09, 0x14 ), # AL=0x0f, AF=0 CF=0 + ( 0xa9, 0x95 ), # AL=0x0f, AF=0 CF=1 + ( 0x09, 0x14 ), # AL=0x0f, AF=1 CF=0 + ( 0xa9, 0x95 ), # AL=0x0f, AF=1 CF=1 + ( 0x10, 0x00 ), # AL=0x10, AF=0 CF=0 + ( 0xb0, 0x81 ), # AL=0x10, AF=0 CF=1 + ( 0x0a, 0x14 ), # AL=0x10, AF=1 CF=0 + ( 0xaa, 0x95 ), # AL=0x10, AF=1 CF=1 + ( 0x11, 0x04 ), # AL=0x11, AF=0 CF=0 + ( 0xb1, 0x85 ), # AL=0x11, AF=0 CF=1 + ( 0x0b, 0x10 ), # AL=0x11, AF=1 CF=0 + ( 0xab, 0x91 ), # AL=0x11, AF=1 CF=1 + ( 0x12, 0x04 ), # AL=0x12, AF=0 CF=0 + ( 0xb2, 0x85 ), # AL=0x12, AF=0 CF=1 + ( 0x0c, 0x14 ), # AL=0x12, AF=1 CF=0 + ( 0xac, 0x95 ), # AL=0x12, AF=1 CF=1 + ( 0x13, 0x00 ), # AL=0x13, AF=0 CF=0 + ( 0xb3, 0x81 ), # AL=0x13, AF=0 CF=1 + ( 0x0d, 0x10 ), # AL=0x13, AF=1 CF=0 + ( 0xad, 0x91 ), # AL=0x13, AF=1 CF=1 + ( 0x14, 0x04 ), # AL=0x14, AF=0 CF=0 + ( 0xb4, 0x85 ), # AL=0x14, AF=0 CF=1 + ( 0x0e, 0x10 ), # AL=0x14, AF=1 CF=0 + ( 0xae, 0x91 ), # AL=0x14, AF=1 CF=1 + ( 0x15, 0x00 ), # AL=0x15, AF=0 CF=0 + ( 0xb5, 0x81 ), # AL=0x15, AF=0 CF=1 + ( 0x0f, 0x14 ), # AL=0x15, AF=1 CF=0 + ( 0xaf, 0x95 ), # AL=0x15, AF=1 CF=1 + ( 0x16, 0x00 ), # AL=0x16, AF=0 CF=0 + ( 0xb6, 0x81 ), # AL=0x16, AF=0 CF=1 + ( 0x10, 0x10 ), # AL=0x16, AF=1 CF=0 + ( 0xb0, 0x91 ), # AL=0x16, AF=1 CF=1 + ( 0x17, 0x04 ), # AL=0x17, AF=0 CF=0 + ( 0xb7, 0x85 ), # AL=0x17, AF=0 CF=1 + ( 0x11, 0x14 ), # AL=0x17, AF=1 CF=0 + ( 0xb1, 0x95 ), # AL=0x17, AF=1 CF=1 + ( 0x18, 0x04 ), # AL=0x18, AF=0 CF=0 + ( 0xb8, 0x85 ), # AL=0x18, AF=0 CF=1 + ( 0x12, 0x14 ), # AL=0x18, AF=1 CF=0 + ( 0xb2, 0x95 ), # AL=0x18, AF=1 CF=1 + ( 0x19, 0x00 ), # AL=0x19, AF=0 CF=0 + ( 0xb9, 0x81 ), # AL=0x19, AF=0 CF=1 + ( 0x13, 0x10 ), # AL=0x19, AF=1 CF=0 + ( 0xb3, 0x91 ), # AL=0x19, AF=1 CF=1 + ( 0x14, 0x14 ), # AL=0x1a, AF=0 CF=0 + ( 0xb4, 0x95 ), # AL=0x1a, AF=0 CF=1 + ( 0x14, 0x14 ), # AL=0x1a, AF=1 CF=0 + ( 0xb4, 0x95 ), # AL=0x1a, AF=1 CF=1 + ( 0x15, 0x10 ), # AL=0x1b, AF=0 CF=0 + ( 0xb5, 0x91 ), # AL=0x1b, AF=0 CF=1 + ( 0x15, 0x10 ), # AL=0x1b, AF=1 CF=0 + ( 0xb5, 0x91 ), # AL=0x1b, AF=1 CF=1 + ( 0x16, 0x10 ), # AL=0x1c, AF=0 CF=0 + ( 0xb6, 0x91 ), # AL=0x1c, AF=0 CF=1 + ( 0x16, 0x10 ), # AL=0x1c, AF=1 CF=0 + ( 0xb6, 0x91 ), # AL=0x1c, AF=1 CF=1 + ( 0x17, 0x14 ), # AL=0x1d, AF=0 CF=0 + ( 0xb7, 0x95 ), # AL=0x1d, AF=0 CF=1 + ( 0x17, 0x14 ), # AL=0x1d, AF=1 CF=0 + ( 0xb7, 0x95 ), # AL=0x1d, AF=1 CF=1 + ( 0x18, 0x14 ), # AL=0x1e, AF=0 CF=0 + ( 0xb8, 0x95 ), # AL=0x1e, AF=0 CF=1 + ( 0x18, 0x14 ), # AL=0x1e, AF=1 CF=0 + ( 0xb8, 0x95 ), # AL=0x1e, AF=1 CF=1 + ( 0x19, 0x10 ), # AL=0x1f, AF=0 CF=0 + ( 0xb9, 0x91 ), # AL=0x1f, AF=0 CF=1 + ( 0x19, 0x10 ), # AL=0x1f, AF=1 CF=0 + ( 0xb9, 0x91 ), # AL=0x1f, AF=1 CF=1 + ( 0x20, 0x00 ), # AL=0x20, AF=0 CF=0 + ( 0xc0, 0x85 ), # AL=0x20, AF=0 CF=1 + ( 0x1a, 0x10 ), # AL=0x20, AF=1 CF=0 + ( 0xba, 0x91 ), # AL=0x20, AF=1 CF=1 + ( 0x21, 0x04 ), # AL=0x21, AF=0 CF=0 + ( 0xc1, 0x81 ), # AL=0x21, AF=0 CF=1 + ( 0x1b, 0x14 ), # AL=0x21, AF=1 CF=0 + ( 0xbb, 0x95 ), # AL=0x21, AF=1 CF=1 + ( 0x22, 0x04 ), # AL=0x22, AF=0 CF=0 + ( 0xc2, 0x81 ), # AL=0x22, AF=0 CF=1 + ( 0x1c, 0x10 ), # AL=0x22, AF=1 CF=0 + ( 0xbc, 0x91 ), # AL=0x22, AF=1 CF=1 + ( 0x23, 0x00 ), # AL=0x23, AF=0 CF=0 + ( 0xc3, 0x85 ), # AL=0x23, AF=0 CF=1 + ( 0x1d, 0x14 ), # AL=0x23, AF=1 CF=0 + ( 0xbd, 0x95 ), # AL=0x23, AF=1 CF=1 + ( 0x24, 0x04 ), # AL=0x24, AF=0 CF=0 + ( 0xc4, 0x81 ), # AL=0x24, AF=0 CF=1 + ( 0x1e, 0x14 ), # AL=0x24, AF=1 CF=0 + ( 0xbe, 0x95 ), # AL=0x24, AF=1 CF=1 + ( 0x25, 0x00 ), # AL=0x25, AF=0 CF=0 + ( 0xc5, 0x85 ), # AL=0x25, AF=0 CF=1 + ( 0x1f, 0x10 ), # AL=0x25, AF=1 CF=0 + ( 0xbf, 0x91 ), # AL=0x25, AF=1 CF=1 + ( 0x26, 0x00 ), # AL=0x26, AF=0 CF=0 + ( 0xc6, 0x85 ), # AL=0x26, AF=0 CF=1 + ( 0x20, 0x10 ), # AL=0x26, AF=1 CF=0 + ( 0xc0, 0x95 ), # AL=0x26, AF=1 CF=1 + ( 0x27, 0x04 ), # AL=0x27, AF=0 CF=0 + ( 0xc7, 0x81 ), # AL=0x27, AF=0 CF=1 + ( 0x21, 0x14 ), # AL=0x27, AF=1 CF=0 + ( 0xc1, 0x91 ), # AL=0x27, AF=1 CF=1 + ( 0x28, 0x04 ), # AL=0x28, AF=0 CF=0 + ( 0xc8, 0x81 ), # AL=0x28, AF=0 CF=1 + ( 0x22, 0x14 ), # AL=0x28, AF=1 CF=0 + ( 0xc2, 0x91 ), # AL=0x28, AF=1 CF=1 + ( 0x29, 0x00 ), # AL=0x29, AF=0 CF=0 + ( 0xc9, 0x85 ), # AL=0x29, AF=0 CF=1 + ( 0x23, 0x10 ), # AL=0x29, AF=1 CF=0 + ( 0xc3, 0x95 ), # AL=0x29, AF=1 CF=1 + ( 0x24, 0x14 ), # AL=0x2a, AF=0 CF=0 + ( 0xc4, 0x91 ), # AL=0x2a, AF=0 CF=1 + ( 0x24, 0x14 ), # AL=0x2a, AF=1 CF=0 + ( 0xc4, 0x91 ), # AL=0x2a, AF=1 CF=1 + ( 0x25, 0x10 ), # AL=0x2b, AF=0 CF=0 + ( 0xc5, 0x95 ), # AL=0x2b, AF=0 CF=1 + ( 0x25, 0x10 ), # AL=0x2b, AF=1 CF=0 + ( 0xc5, 0x95 ), # AL=0x2b, AF=1 CF=1 + ( 0x26, 0x10 ), # AL=0x2c, AF=0 CF=0 + ( 0xc6, 0x95 ), # AL=0x2c, AF=0 CF=1 + ( 0x26, 0x10 ), # AL=0x2c, AF=1 CF=0 + ( 0xc6, 0x95 ), # AL=0x2c, AF=1 CF=1 + ( 0x27, 0x14 ), # AL=0x2d, AF=0 CF=0 + ( 0xc7, 0x91 ), # AL=0x2d, AF=0 CF=1 + ( 0x27, 0x14 ), # AL=0x2d, AF=1 CF=0 + ( 0xc7, 0x91 ), # AL=0x2d, AF=1 CF=1 + ( 0x28, 0x14 ), # AL=0x2e, AF=0 CF=0 + ( 0xc8, 0x91 ), # AL=0x2e, AF=0 CF=1 + ( 0x28, 0x14 ), # AL=0x2e, AF=1 CF=0 + ( 0xc8, 0x91 ), # AL=0x2e, AF=1 CF=1 + ( 0x29, 0x10 ), # AL=0x2f, AF=0 CF=0 + ( 0xc9, 0x95 ), # AL=0x2f, AF=0 CF=1 + ( 0x29, 0x10 ), # AL=0x2f, AF=1 CF=0 + ( 0xc9, 0x95 ), # AL=0x2f, AF=1 CF=1 + ( 0x30, 0x04 ), # AL=0x30, AF=0 CF=0 + ( 0xd0, 0x81 ), # AL=0x30, AF=0 CF=1 + ( 0x2a, 0x10 ), # AL=0x30, AF=1 CF=0 + ( 0xca, 0x95 ), # AL=0x30, AF=1 CF=1 + ( 0x31, 0x00 ), # AL=0x31, AF=0 CF=0 + ( 0xd1, 0x85 ), # AL=0x31, AF=0 CF=1 + ( 0x2b, 0x14 ), # AL=0x31, AF=1 CF=0 + ( 0xcb, 0x91 ), # AL=0x31, AF=1 CF=1 + ( 0x32, 0x00 ), # AL=0x32, AF=0 CF=0 + ( 0xd2, 0x85 ), # AL=0x32, AF=0 CF=1 + ( 0x2c, 0x10 ), # AL=0x32, AF=1 CF=0 + ( 0xcc, 0x95 ), # AL=0x32, AF=1 CF=1 + ( 0x33, 0x04 ), # AL=0x33, AF=0 CF=0 + ( 0xd3, 0x81 ), # AL=0x33, AF=0 CF=1 + ( 0x2d, 0x14 ), # AL=0x33, AF=1 CF=0 + ( 0xcd, 0x91 ), # AL=0x33, AF=1 CF=1 + ( 0x34, 0x00 ), # AL=0x34, AF=0 CF=0 + ( 0xd4, 0x85 ), # AL=0x34, AF=0 CF=1 + ( 0x2e, 0x14 ), # AL=0x34, AF=1 CF=0 + ( 0xce, 0x91 ), # AL=0x34, AF=1 CF=1 + ( 0x35, 0x04 ), # AL=0x35, AF=0 CF=0 + ( 0xd5, 0x81 ), # AL=0x35, AF=0 CF=1 + ( 0x2f, 0x10 ), # AL=0x35, AF=1 CF=0 + ( 0xcf, 0x95 ), # AL=0x35, AF=1 CF=1 + ( 0x36, 0x04 ), # AL=0x36, AF=0 CF=0 + ( 0xd6, 0x81 ), # AL=0x36, AF=0 CF=1 + ( 0x30, 0x14 ), # AL=0x36, AF=1 CF=0 + ( 0xd0, 0x91 ), # AL=0x36, AF=1 CF=1 + ( 0x37, 0x00 ), # AL=0x37, AF=0 CF=0 + ( 0xd7, 0x85 ), # AL=0x37, AF=0 CF=1 + ( 0x31, 0x10 ), # AL=0x37, AF=1 CF=0 + ( 0xd1, 0x95 ), # AL=0x37, AF=1 CF=1 + ( 0x38, 0x00 ), # AL=0x38, AF=0 CF=0 + ( 0xd8, 0x85 ), # AL=0x38, AF=0 CF=1 + ( 0x32, 0x10 ), # AL=0x38, AF=1 CF=0 + ( 0xd2, 0x95 ), # AL=0x38, AF=1 CF=1 + ( 0x39, 0x04 ), # AL=0x39, AF=0 CF=0 + ( 0xd9, 0x81 ), # AL=0x39, AF=0 CF=1 + ( 0x33, 0x14 ), # AL=0x39, AF=1 CF=0 + ( 0xd3, 0x91 ), # AL=0x39, AF=1 CF=1 + ( 0x34, 0x10 ), # AL=0x3a, AF=0 CF=0 + ( 0xd4, 0x95 ), # AL=0x3a, AF=0 CF=1 + ( 0x34, 0x10 ), # AL=0x3a, AF=1 CF=0 + ( 0xd4, 0x95 ), # AL=0x3a, AF=1 CF=1 + ( 0x35, 0x14 ), # AL=0x3b, AF=0 CF=0 + ( 0xd5, 0x91 ), # AL=0x3b, AF=0 CF=1 + ( 0x35, 0x14 ), # AL=0x3b, AF=1 CF=0 + ( 0xd5, 0x91 ), # AL=0x3b, AF=1 CF=1 + ( 0x36, 0x14 ), # AL=0x3c, AF=0 CF=0 + ( 0xd6, 0x91 ), # AL=0x3c, AF=0 CF=1 + ( 0x36, 0x14 ), # AL=0x3c, AF=1 CF=0 + ( 0xd6, 0x91 ), # AL=0x3c, AF=1 CF=1 + ( 0x37, 0x10 ), # AL=0x3d, AF=0 CF=0 + ( 0xd7, 0x95 ), # AL=0x3d, AF=0 CF=1 + ( 0x37, 0x10 ), # AL=0x3d, AF=1 CF=0 + ( 0xd7, 0x95 ), # AL=0x3d, AF=1 CF=1 + ( 0x38, 0x10 ), # AL=0x3e, AF=0 CF=0 + ( 0xd8, 0x95 ), # AL=0x3e, AF=0 CF=1 + ( 0x38, 0x10 ), # AL=0x3e, AF=1 CF=0 + ( 0xd8, 0x95 ), # AL=0x3e, AF=1 CF=1 + ( 0x39, 0x14 ), # AL=0x3f, AF=0 CF=0 + ( 0xd9, 0x91 ), # AL=0x3f, AF=0 CF=1 + ( 0x39, 0x14 ), # AL=0x3f, AF=1 CF=0 + ( 0xd9, 0x91 ), # AL=0x3f, AF=1 CF=1 + ( 0x40, 0x00 ), # AL=0x40, AF=0 CF=0 + ( 0xe0, 0x81 ), # AL=0x40, AF=0 CF=1 + ( 0x3a, 0x14 ), # AL=0x40, AF=1 CF=0 + ( 0xda, 0x91 ), # AL=0x40, AF=1 CF=1 + ( 0x41, 0x04 ), # AL=0x41, AF=0 CF=0 + ( 0xe1, 0x85 ), # AL=0x41, AF=0 CF=1 + ( 0x3b, 0x10 ), # AL=0x41, AF=1 CF=0 + ( 0xdb, 0x95 ), # AL=0x41, AF=1 CF=1 + ( 0x42, 0x04 ), # AL=0x42, AF=0 CF=0 + ( 0xe2, 0x85 ), # AL=0x42, AF=0 CF=1 + ( 0x3c, 0x14 ), # AL=0x42, AF=1 CF=0 + ( 0xdc, 0x91 ), # AL=0x42, AF=1 CF=1 + ( 0x43, 0x00 ), # AL=0x43, AF=0 CF=0 + ( 0xe3, 0x81 ), # AL=0x43, AF=0 CF=1 + ( 0x3d, 0x10 ), # AL=0x43, AF=1 CF=0 + ( 0xdd, 0x95 ), # AL=0x43, AF=1 CF=1 + ( 0x44, 0x04 ), # AL=0x44, AF=0 CF=0 + ( 0xe4, 0x85 ), # AL=0x44, AF=0 CF=1 + ( 0x3e, 0x10 ), # AL=0x44, AF=1 CF=0 + ( 0xde, 0x95 ), # AL=0x44, AF=1 CF=1 + ( 0x45, 0x00 ), # AL=0x45, AF=0 CF=0 + ( 0xe5, 0x81 ), # AL=0x45, AF=0 CF=1 + ( 0x3f, 0x14 ), # AL=0x45, AF=1 CF=0 + ( 0xdf, 0x91 ), # AL=0x45, AF=1 CF=1 + ( 0x46, 0x00 ), # AL=0x46, AF=0 CF=0 + ( 0xe6, 0x81 ), # AL=0x46, AF=0 CF=1 + ( 0x40, 0x10 ), # AL=0x46, AF=1 CF=0 + ( 0xe0, 0x91 ), # AL=0x46, AF=1 CF=1 + ( 0x47, 0x04 ), # AL=0x47, AF=0 CF=0 + ( 0xe7, 0x85 ), # AL=0x47, AF=0 CF=1 + ( 0x41, 0x14 ), # AL=0x47, AF=1 CF=0 + ( 0xe1, 0x95 ), # AL=0x47, AF=1 CF=1 + ( 0x48, 0x04 ), # AL=0x48, AF=0 CF=0 + ( 0xe8, 0x85 ), # AL=0x48, AF=0 CF=1 + ( 0x42, 0x14 ), # AL=0x48, AF=1 CF=0 + ( 0xe2, 0x95 ), # AL=0x48, AF=1 CF=1 + ( 0x49, 0x00 ), # AL=0x49, AF=0 CF=0 + ( 0xe9, 0x81 ), # AL=0x49, AF=0 CF=1 + ( 0x43, 0x10 ), # AL=0x49, AF=1 CF=0 + ( 0xe3, 0x91 ), # AL=0x49, AF=1 CF=1 + ( 0x44, 0x14 ), # AL=0x4a, AF=0 CF=0 + ( 0xe4, 0x95 ), # AL=0x4a, AF=0 CF=1 + ( 0x44, 0x14 ), # AL=0x4a, AF=1 CF=0 + ( 0xe4, 0x95 ), # AL=0x4a, AF=1 CF=1 + ( 0x45, 0x10 ), # AL=0x4b, AF=0 CF=0 + ( 0xe5, 0x91 ), # AL=0x4b, AF=0 CF=1 + ( 0x45, 0x10 ), # AL=0x4b, AF=1 CF=0 + ( 0xe5, 0x91 ), # AL=0x4b, AF=1 CF=1 + ( 0x46, 0x10 ), # AL=0x4c, AF=0 CF=0 + ( 0xe6, 0x91 ), # AL=0x4c, AF=0 CF=1 + ( 0x46, 0x10 ), # AL=0x4c, AF=1 CF=0 + ( 0xe6, 0x91 ), # AL=0x4c, AF=1 CF=1 + ( 0x47, 0x14 ), # AL=0x4d, AF=0 CF=0 + ( 0xe7, 0x95 ), # AL=0x4d, AF=0 CF=1 + ( 0x47, 0x14 ), # AL=0x4d, AF=1 CF=0 + ( 0xe7, 0x95 ), # AL=0x4d, AF=1 CF=1 + ( 0x48, 0x14 ), # AL=0x4e, AF=0 CF=0 + ( 0xe8, 0x95 ), # AL=0x4e, AF=0 CF=1 + ( 0x48, 0x14 ), # AL=0x4e, AF=1 CF=0 + ( 0xe8, 0x95 ), # AL=0x4e, AF=1 CF=1 + ( 0x49, 0x10 ), # AL=0x4f, AF=0 CF=0 + ( 0xe9, 0x91 ), # AL=0x4f, AF=0 CF=1 + ( 0x49, 0x10 ), # AL=0x4f, AF=1 CF=0 + ( 0xe9, 0x91 ), # AL=0x4f, AF=1 CF=1 + ( 0x50, 0x04 ), # AL=0x50, AF=0 CF=0 + ( 0xf0, 0x85 ), # AL=0x50, AF=0 CF=1 + ( 0x4a, 0x10 ), # AL=0x50, AF=1 CF=0 + ( 0xea, 0x91 ), # AL=0x50, AF=1 CF=1 + ( 0x51, 0x00 ), # AL=0x51, AF=0 CF=0 + ( 0xf1, 0x81 ), # AL=0x51, AF=0 CF=1 + ( 0x4b, 0x14 ), # AL=0x51, AF=1 CF=0 + ( 0xeb, 0x95 ), # AL=0x51, AF=1 CF=1 + ( 0x52, 0x00 ), # AL=0x52, AF=0 CF=0 + ( 0xf2, 0x81 ), # AL=0x52, AF=0 CF=1 + ( 0x4c, 0x10 ), # AL=0x52, AF=1 CF=0 + ( 0xec, 0x91 ), # AL=0x52, AF=1 CF=1 + ( 0x53, 0x04 ), # AL=0x53, AF=0 CF=0 + ( 0xf3, 0x85 ), # AL=0x53, AF=0 CF=1 + ( 0x4d, 0x14 ), # AL=0x53, AF=1 CF=0 + ( 0xed, 0x95 ), # AL=0x53, AF=1 CF=1 + ( 0x54, 0x00 ), # AL=0x54, AF=0 CF=0 + ( 0xf4, 0x81 ), # AL=0x54, AF=0 CF=1 + ( 0x4e, 0x14 ), # AL=0x54, AF=1 CF=0 + ( 0xee, 0x95 ), # AL=0x54, AF=1 CF=1 + ( 0x55, 0x04 ), # AL=0x55, AF=0 CF=0 + ( 0xf5, 0x85 ), # AL=0x55, AF=0 CF=1 + ( 0x4f, 0x10 ), # AL=0x55, AF=1 CF=0 + ( 0xef, 0x91 ), # AL=0x55, AF=1 CF=1 + ( 0x56, 0x04 ), # AL=0x56, AF=0 CF=0 + ( 0xf6, 0x85 ), # AL=0x56, AF=0 CF=1 + ( 0x50, 0x14 ), # AL=0x56, AF=1 CF=0 + ( 0xf0, 0x95 ), # AL=0x56, AF=1 CF=1 + ( 0x57, 0x00 ), # AL=0x57, AF=0 CF=0 + ( 0xf7, 0x81 ), # AL=0x57, AF=0 CF=1 + ( 0x51, 0x10 ), # AL=0x57, AF=1 CF=0 + ( 0xf1, 0x91 ), # AL=0x57, AF=1 CF=1 + ( 0x58, 0x00 ), # AL=0x58, AF=0 CF=0 + ( 0xf8, 0x81 ), # AL=0x58, AF=0 CF=1 + ( 0x52, 0x10 ), # AL=0x58, AF=1 CF=0 + ( 0xf2, 0x91 ), # AL=0x58, AF=1 CF=1 + ( 0x59, 0x04 ), # AL=0x59, AF=0 CF=0 + ( 0xf9, 0x85 ), # AL=0x59, AF=0 CF=1 + ( 0x53, 0x14 ), # AL=0x59, AF=1 CF=0 + ( 0xf3, 0x95 ), # AL=0x59, AF=1 CF=1 + ( 0x54, 0x10 ), # AL=0x5a, AF=0 CF=0 + ( 0xf4, 0x91 ), # AL=0x5a, AF=0 CF=1 + ( 0x54, 0x10 ), # AL=0x5a, AF=1 CF=0 + ( 0xf4, 0x91 ), # AL=0x5a, AF=1 CF=1 + ( 0x55, 0x14 ), # AL=0x5b, AF=0 CF=0 + ( 0xf5, 0x95 ), # AL=0x5b, AF=0 CF=1 + ( 0x55, 0x14 ), # AL=0x5b, AF=1 CF=0 + ( 0xf5, 0x95 ), # AL=0x5b, AF=1 CF=1 + ( 0x56, 0x14 ), # AL=0x5c, AF=0 CF=0 + ( 0xf6, 0x95 ), # AL=0x5c, AF=0 CF=1 + ( 0x56, 0x14 ), # AL=0x5c, AF=1 CF=0 + ( 0xf6, 0x95 ), # AL=0x5c, AF=1 CF=1 + ( 0x57, 0x10 ), # AL=0x5d, AF=0 CF=0 + ( 0xf7, 0x91 ), # AL=0x5d, AF=0 CF=1 + ( 0x57, 0x10 ), # AL=0x5d, AF=1 CF=0 + ( 0xf7, 0x91 ), # AL=0x5d, AF=1 CF=1 + ( 0x58, 0x10 ), # AL=0x5e, AF=0 CF=0 + ( 0xf8, 0x91 ), # AL=0x5e, AF=0 CF=1 + ( 0x58, 0x10 ), # AL=0x5e, AF=1 CF=0 + ( 0xf8, 0x91 ), # AL=0x5e, AF=1 CF=1 + ( 0x59, 0x14 ), # AL=0x5f, AF=0 CF=0 + ( 0xf9, 0x95 ), # AL=0x5f, AF=0 CF=1 + ( 0x59, 0x14 ), # AL=0x5f, AF=1 CF=0 + ( 0xf9, 0x95 ), # AL=0x5f, AF=1 CF=1 + ( 0x60, 0x04 ), # AL=0x60, AF=0 CF=0 + ( 0x00, 0x45 ), # AL=0x60, AF=0 CF=1 + ( 0x5a, 0x14 ), # AL=0x60, AF=1 CF=0 + ( 0xfa, 0x95 ), # AL=0x60, AF=1 CF=1 + ( 0x61, 0x00 ), # AL=0x61, AF=0 CF=0 + ( 0x01, 0x01 ), # AL=0x61, AF=0 CF=1 + ( 0x5b, 0x10 ), # AL=0x61, AF=1 CF=0 + ( 0xfb, 0x91 ), # AL=0x61, AF=1 CF=1 + ( 0x62, 0x00 ), # AL=0x62, AF=0 CF=0 + ( 0x02, 0x01 ), # AL=0x62, AF=0 CF=1 + ( 0x5c, 0x14 ), # AL=0x62, AF=1 CF=0 + ( 0xfc, 0x95 ), # AL=0x62, AF=1 CF=1 + ( 0x63, 0x04 ), # AL=0x63, AF=0 CF=0 + ( 0x03, 0x05 ), # AL=0x63, AF=0 CF=1 + ( 0x5d, 0x10 ), # AL=0x63, AF=1 CF=0 + ( 0xfd, 0x91 ), # AL=0x63, AF=1 CF=1 + ( 0x64, 0x00 ), # AL=0x64, AF=0 CF=0 + ( 0x04, 0x01 ), # AL=0x64, AF=0 CF=1 + ( 0x5e, 0x10 ), # AL=0x64, AF=1 CF=0 + ( 0xfe, 0x91 ), # AL=0x64, AF=1 CF=1 + ( 0x65, 0x04 ), # AL=0x65, AF=0 CF=0 + ( 0x05, 0x05 ), # AL=0x65, AF=0 CF=1 + ( 0x5f, 0x14 ), # AL=0x65, AF=1 CF=0 + ( 0xff, 0x95 ), # AL=0x65, AF=1 CF=1 + ( 0x66, 0x04 ), # AL=0x66, AF=0 CF=0 + ( 0x06, 0x05 ), # AL=0x66, AF=0 CF=1 + ( 0x60, 0x14 ), # AL=0x66, AF=1 CF=0 + ( 0x00, 0x55 ), # AL=0x66, AF=1 CF=1 + ( 0x67, 0x00 ), # AL=0x67, AF=0 CF=0 + ( 0x07, 0x01 ), # AL=0x67, AF=0 CF=1 + ( 0x61, 0x10 ), # AL=0x67, AF=1 CF=0 + ( 0x01, 0x11 ), # AL=0x67, AF=1 CF=1 + ( 0x68, 0x00 ), # AL=0x68, AF=0 CF=0 + ( 0x08, 0x01 ), # AL=0x68, AF=0 CF=1 + ( 0x62, 0x10 ), # AL=0x68, AF=1 CF=0 + ( 0x02, 0x11 ), # AL=0x68, AF=1 CF=1 + ( 0x69, 0x04 ), # AL=0x69, AF=0 CF=0 + ( 0x09, 0x05 ), # AL=0x69, AF=0 CF=1 + ( 0x63, 0x14 ), # AL=0x69, AF=1 CF=0 + ( 0x03, 0x15 ), # AL=0x69, AF=1 CF=1 + ( 0x64, 0x10 ), # AL=0x6a, AF=0 CF=0 + ( 0x04, 0x11 ), # AL=0x6a, AF=0 CF=1 + ( 0x64, 0x10 ), # AL=0x6a, AF=1 CF=0 + ( 0x04, 0x11 ), # AL=0x6a, AF=1 CF=1 + ( 0x65, 0x14 ), # AL=0x6b, AF=0 CF=0 + ( 0x05, 0x15 ), # AL=0x6b, AF=0 CF=1 + ( 0x65, 0x14 ), # AL=0x6b, AF=1 CF=0 + ( 0x05, 0x15 ), # AL=0x6b, AF=1 CF=1 + ( 0x66, 0x14 ), # AL=0x6c, AF=0 CF=0 + ( 0x06, 0x15 ), # AL=0x6c, AF=0 CF=1 + ( 0x66, 0x14 ), # AL=0x6c, AF=1 CF=0 + ( 0x06, 0x15 ), # AL=0x6c, AF=1 CF=1 + ( 0x67, 0x10 ), # AL=0x6d, AF=0 CF=0 + ( 0x07, 0x11 ), # AL=0x6d, AF=0 CF=1 + ( 0x67, 0x10 ), # AL=0x6d, AF=1 CF=0 + ( 0x07, 0x11 ), # AL=0x6d, AF=1 CF=1 + ( 0x68, 0x10 ), # AL=0x6e, AF=0 CF=0 + ( 0x08, 0x11 ), # AL=0x6e, AF=0 CF=1 + ( 0x68, 0x10 ), # AL=0x6e, AF=1 CF=0 + ( 0x08, 0x11 ), # AL=0x6e, AF=1 CF=1 + ( 0x69, 0x14 ), # AL=0x6f, AF=0 CF=0 + ( 0x09, 0x15 ), # AL=0x6f, AF=0 CF=1 + ( 0x69, 0x14 ), # AL=0x6f, AF=1 CF=0 + ( 0x09, 0x15 ), # AL=0x6f, AF=1 CF=1 + ( 0x70, 0x00 ), # AL=0x70, AF=0 CF=0 + ( 0x10, 0x01 ), # AL=0x70, AF=0 CF=1 + ( 0x6a, 0x14 ), # AL=0x70, AF=1 CF=0 + ( 0x0a, 0x15 ), # AL=0x70, AF=1 CF=1 + ( 0x71, 0x04 ), # AL=0x71, AF=0 CF=0 + ( 0x11, 0x05 ), # AL=0x71, AF=0 CF=1 + ( 0x6b, 0x10 ), # AL=0x71, AF=1 CF=0 + ( 0x0b, 0x11 ), # AL=0x71, AF=1 CF=1 + ( 0x72, 0x04 ), # AL=0x72, AF=0 CF=0 + ( 0x12, 0x05 ), # AL=0x72, AF=0 CF=1 + ( 0x6c, 0x14 ), # AL=0x72, AF=1 CF=0 + ( 0x0c, 0x15 ), # AL=0x72, AF=1 CF=1 + ( 0x73, 0x00 ), # AL=0x73, AF=0 CF=0 + ( 0x13, 0x01 ), # AL=0x73, AF=0 CF=1 + ( 0x6d, 0x10 ), # AL=0x73, AF=1 CF=0 + ( 0x0d, 0x11 ), # AL=0x73, AF=1 CF=1 + ( 0x74, 0x04 ), # AL=0x74, AF=0 CF=0 + ( 0x14, 0x05 ), # AL=0x74, AF=0 CF=1 + ( 0x6e, 0x10 ), # AL=0x74, AF=1 CF=0 + ( 0x0e, 0x11 ), # AL=0x74, AF=1 CF=1 + ( 0x75, 0x00 ), # AL=0x75, AF=0 CF=0 + ( 0x15, 0x01 ), # AL=0x75, AF=0 CF=1 + ( 0x6f, 0x14 ), # AL=0x75, AF=1 CF=0 + ( 0x0f, 0x15 ), # AL=0x75, AF=1 CF=1 + ( 0x76, 0x00 ), # AL=0x76, AF=0 CF=0 + ( 0x16, 0x01 ), # AL=0x76, AF=0 CF=1 + ( 0x70, 0x10 ), # AL=0x76, AF=1 CF=0 + ( 0x10, 0x11 ), # AL=0x76, AF=1 CF=1 + ( 0x77, 0x04 ), # AL=0x77, AF=0 CF=0 + ( 0x17, 0x05 ), # AL=0x77, AF=0 CF=1 + ( 0x71, 0x14 ), # AL=0x77, AF=1 CF=0 + ( 0x11, 0x15 ), # AL=0x77, AF=1 CF=1 + ( 0x78, 0x04 ), # AL=0x78, AF=0 CF=0 + ( 0x18, 0x05 ), # AL=0x78, AF=0 CF=1 + ( 0x72, 0x14 ), # AL=0x78, AF=1 CF=0 + ( 0x12, 0x15 ), # AL=0x78, AF=1 CF=1 + ( 0x79, 0x00 ), # AL=0x79, AF=0 CF=0 + ( 0x19, 0x01 ), # AL=0x79, AF=0 CF=1 + ( 0x73, 0x10 ), # AL=0x79, AF=1 CF=0 + ( 0x13, 0x11 ), # AL=0x79, AF=1 CF=1 + ( 0x74, 0x14 ), # AL=0x7a, AF=0 CF=0 + ( 0x14, 0x15 ), # AL=0x7a, AF=0 CF=1 + ( 0x74, 0x14 ), # AL=0x7a, AF=1 CF=0 + ( 0x14, 0x15 ), # AL=0x7a, AF=1 CF=1 + ( 0x75, 0x10 ), # AL=0x7b, AF=0 CF=0 + ( 0x15, 0x11 ), # AL=0x7b, AF=0 CF=1 + ( 0x75, 0x10 ), # AL=0x7b, AF=1 CF=0 + ( 0x15, 0x11 ), # AL=0x7b, AF=1 CF=1 + ( 0x76, 0x10 ), # AL=0x7c, AF=0 CF=0 + ( 0x16, 0x11 ), # AL=0x7c, AF=0 CF=1 + ( 0x76, 0x10 ), # AL=0x7c, AF=1 CF=0 + ( 0x16, 0x11 ), # AL=0x7c, AF=1 CF=1 + ( 0x77, 0x14 ), # AL=0x7d, AF=0 CF=0 + ( 0x17, 0x15 ), # AL=0x7d, AF=0 CF=1 + ( 0x77, 0x14 ), # AL=0x7d, AF=1 CF=0 + ( 0x17, 0x15 ), # AL=0x7d, AF=1 CF=1 + ( 0x78, 0x14 ), # AL=0x7e, AF=0 CF=0 + ( 0x18, 0x15 ), # AL=0x7e, AF=0 CF=1 + ( 0x78, 0x14 ), # AL=0x7e, AF=1 CF=0 + ( 0x18, 0x15 ), # AL=0x7e, AF=1 CF=1 + ( 0x79, 0x10 ), # AL=0x7f, AF=0 CF=0 + ( 0x19, 0x11 ), # AL=0x7f, AF=0 CF=1 + ( 0x79, 0x10 ), # AL=0x7f, AF=1 CF=0 + ( 0x19, 0x11 ), # AL=0x7f, AF=1 CF=1 + ( 0x80, 0x80 ), # AL=0x80, AF=0 CF=0 + ( 0x20, 0x01 ), # AL=0x80, AF=0 CF=1 + ( 0x7a, 0x10 ), # AL=0x80, AF=1 CF=0 + ( 0x1a, 0x11 ), # AL=0x80, AF=1 CF=1 + ( 0x81, 0x84 ), # AL=0x81, AF=0 CF=0 + ( 0x21, 0x05 ), # AL=0x81, AF=0 CF=1 + ( 0x7b, 0x14 ), # AL=0x81, AF=1 CF=0 + ( 0x1b, 0x15 ), # AL=0x81, AF=1 CF=1 + ( 0x82, 0x84 ), # AL=0x82, AF=0 CF=0 + ( 0x22, 0x05 ), # AL=0x82, AF=0 CF=1 + ( 0x7c, 0x10 ), # AL=0x82, AF=1 CF=0 + ( 0x1c, 0x11 ), # AL=0x82, AF=1 CF=1 + ( 0x83, 0x80 ), # AL=0x83, AF=0 CF=0 + ( 0x23, 0x01 ), # AL=0x83, AF=0 CF=1 + ( 0x7d, 0x14 ), # AL=0x83, AF=1 CF=0 + ( 0x1d, 0x15 ), # AL=0x83, AF=1 CF=1 + ( 0x84, 0x84 ), # AL=0x84, AF=0 CF=0 + ( 0x24, 0x05 ), # AL=0x84, AF=0 CF=1 + ( 0x7e, 0x14 ), # AL=0x84, AF=1 CF=0 + ( 0x1e, 0x15 ), # AL=0x84, AF=1 CF=1 + ( 0x85, 0x80 ), # AL=0x85, AF=0 CF=0 + ( 0x25, 0x01 ), # AL=0x85, AF=0 CF=1 + ( 0x7f, 0x10 ), # AL=0x85, AF=1 CF=0 + ( 0x1f, 0x11 ), # AL=0x85, AF=1 CF=1 + ( 0x86, 0x80 ), # AL=0x86, AF=0 CF=0 + ( 0x26, 0x01 ), # AL=0x86, AF=0 CF=1 + ( 0x80, 0x90 ), # AL=0x86, AF=1 CF=0 + ( 0x20, 0x11 ), # AL=0x86, AF=1 CF=1 + ( 0x87, 0x84 ), # AL=0x87, AF=0 CF=0 + ( 0x27, 0x05 ), # AL=0x87, AF=0 CF=1 + ( 0x81, 0x94 ), # AL=0x87, AF=1 CF=0 + ( 0x21, 0x15 ), # AL=0x87, AF=1 CF=1 + ( 0x88, 0x84 ), # AL=0x88, AF=0 CF=0 + ( 0x28, 0x05 ), # AL=0x88, AF=0 CF=1 + ( 0x82, 0x94 ), # AL=0x88, AF=1 CF=0 + ( 0x22, 0x15 ), # AL=0x88, AF=1 CF=1 + ( 0x89, 0x80 ), # AL=0x89, AF=0 CF=0 + ( 0x29, 0x01 ), # AL=0x89, AF=0 CF=1 + ( 0x83, 0x90 ), # AL=0x89, AF=1 CF=0 + ( 0x23, 0x11 ), # AL=0x89, AF=1 CF=1 + ( 0x84, 0x94 ), # AL=0x8a, AF=0 CF=0 + ( 0x24, 0x15 ), # AL=0x8a, AF=0 CF=1 + ( 0x84, 0x94 ), # AL=0x8a, AF=1 CF=0 + ( 0x24, 0x15 ), # AL=0x8a, AF=1 CF=1 + ( 0x85, 0x90 ), # AL=0x8b, AF=0 CF=0 + ( 0x25, 0x11 ), # AL=0x8b, AF=0 CF=1 + ( 0x85, 0x90 ), # AL=0x8b, AF=1 CF=0 + ( 0x25, 0x11 ), # AL=0x8b, AF=1 CF=1 + ( 0x86, 0x90 ), # AL=0x8c, AF=0 CF=0 + ( 0x26, 0x11 ), # AL=0x8c, AF=0 CF=1 + ( 0x86, 0x90 ), # AL=0x8c, AF=1 CF=0 + ( 0x26, 0x11 ), # AL=0x8c, AF=1 CF=1 + ( 0x87, 0x94 ), # AL=0x8d, AF=0 CF=0 + ( 0x27, 0x15 ), # AL=0x8d, AF=0 CF=1 + ( 0x87, 0x94 ), # AL=0x8d, AF=1 CF=0 + ( 0x27, 0x15 ), # AL=0x8d, AF=1 CF=1 + ( 0x88, 0x94 ), # AL=0x8e, AF=0 CF=0 + ( 0x28, 0x15 ), # AL=0x8e, AF=0 CF=1 + ( 0x88, 0x94 ), # AL=0x8e, AF=1 CF=0 + ( 0x28, 0x15 ), # AL=0x8e, AF=1 CF=1 + ( 0x89, 0x90 ), # AL=0x8f, AF=0 CF=0 + ( 0x29, 0x11 ), # AL=0x8f, AF=0 CF=1 + ( 0x89, 0x90 ), # AL=0x8f, AF=1 CF=0 + ( 0x29, 0x11 ), # AL=0x8f, AF=1 CF=1 + ( 0x90, 0x84 ), # AL=0x90, AF=0 CF=0 + ( 0x30, 0x05 ), # AL=0x90, AF=0 CF=1 + ( 0x8a, 0x90 ), # AL=0x90, AF=1 CF=0 + ( 0x2a, 0x11 ), # AL=0x90, AF=1 CF=1 + ( 0x91, 0x80 ), # AL=0x91, AF=0 CF=0 + ( 0x31, 0x01 ), # AL=0x91, AF=0 CF=1 + ( 0x8b, 0x94 ), # AL=0x91, AF=1 CF=0 + ( 0x2b, 0x15 ), # AL=0x91, AF=1 CF=1 + ( 0x92, 0x80 ), # AL=0x92, AF=0 CF=0 + ( 0x32, 0x01 ), # AL=0x92, AF=0 CF=1 + ( 0x8c, 0x90 ), # AL=0x92, AF=1 CF=0 + ( 0x2c, 0x11 ), # AL=0x92, AF=1 CF=1 + ( 0x93, 0x84 ), # AL=0x93, AF=0 CF=0 + ( 0x33, 0x05 ), # AL=0x93, AF=0 CF=1 + ( 0x8d, 0x94 ), # AL=0x93, AF=1 CF=0 + ( 0x2d, 0x15 ), # AL=0x93, AF=1 CF=1 + ( 0x94, 0x80 ), # AL=0x94, AF=0 CF=0 + ( 0x34, 0x01 ), # AL=0x94, AF=0 CF=1 + ( 0x8e, 0x94 ), # AL=0x94, AF=1 CF=0 + ( 0x2e, 0x15 ), # AL=0x94, AF=1 CF=1 + ( 0x95, 0x84 ), # AL=0x95, AF=0 CF=0 + ( 0x35, 0x05 ), # AL=0x95, AF=0 CF=1 + ( 0x8f, 0x90 ), # AL=0x95, AF=1 CF=0 + ( 0x2f, 0x11 ), # AL=0x95, AF=1 CF=1 + ( 0x96, 0x84 ), # AL=0x96, AF=0 CF=0 + ( 0x36, 0x05 ), # AL=0x96, AF=0 CF=1 + ( 0x90, 0x94 ), # AL=0x96, AF=1 CF=0 + ( 0x30, 0x15 ), # AL=0x96, AF=1 CF=1 + ( 0x97, 0x80 ), # AL=0x97, AF=0 CF=0 + ( 0x37, 0x01 ), # AL=0x97, AF=0 CF=1 + ( 0x91, 0x90 ), # AL=0x97, AF=1 CF=0 + ( 0x31, 0x11 ), # AL=0x97, AF=1 CF=1 + ( 0x98, 0x80 ), # AL=0x98, AF=0 CF=0 + ( 0x38, 0x01 ), # AL=0x98, AF=0 CF=1 + ( 0x92, 0x90 ), # AL=0x98, AF=1 CF=0 + ( 0x32, 0x11 ), # AL=0x98, AF=1 CF=1 + ( 0x99, 0x84 ), # AL=0x99, AF=0 CF=0 + ( 0x39, 0x05 ), # AL=0x99, AF=0 CF=1 + ( 0x93, 0x94 ), # AL=0x99, AF=1 CF=0 + ( 0x33, 0x15 ), # AL=0x99, AF=1 CF=1 + ( 0x34, 0x11 ), # AL=0x9a, AF=0 CF=0 + ( 0x34, 0x11 ), # AL=0x9a, AF=0 CF=1 + ( 0x34, 0x11 ), # AL=0x9a, AF=1 CF=0 + ( 0x34, 0x11 ), # AL=0x9a, AF=1 CF=1 + ( 0x35, 0x15 ), # AL=0x9b, AF=0 CF=0 + ( 0x35, 0x15 ), # AL=0x9b, AF=0 CF=1 + ( 0x35, 0x15 ), # AL=0x9b, AF=1 CF=0 + ( 0x35, 0x15 ), # AL=0x9b, AF=1 CF=1 + ( 0x36, 0x15 ), # AL=0x9c, AF=0 CF=0 + ( 0x36, 0x15 ), # AL=0x9c, AF=0 CF=1 + ( 0x36, 0x15 ), # AL=0x9c, AF=1 CF=0 + ( 0x36, 0x15 ), # AL=0x9c, AF=1 CF=1 + ( 0x37, 0x11 ), # AL=0x9d, AF=0 CF=0 + ( 0x37, 0x11 ), # AL=0x9d, AF=0 CF=1 + ( 0x37, 0x11 ), # AL=0x9d, AF=1 CF=0 + ( 0x37, 0x11 ), # AL=0x9d, AF=1 CF=1 + ( 0x38, 0x11 ), # AL=0x9e, AF=0 CF=0 + ( 0x38, 0x11 ), # AL=0x9e, AF=0 CF=1 + ( 0x38, 0x11 ), # AL=0x9e, AF=1 CF=0 + ( 0x38, 0x11 ), # AL=0x9e, AF=1 CF=1 + ( 0x39, 0x15 ), # AL=0x9f, AF=0 CF=0 + ( 0x39, 0x15 ), # AL=0x9f, AF=0 CF=1 + ( 0x39, 0x15 ), # AL=0x9f, AF=1 CF=0 + ( 0x39, 0x15 ), # AL=0x9f, AF=1 CF=1 + ( 0x40, 0x01 ), # AL=0xa0, AF=0 CF=0 + ( 0x40, 0x01 ), # AL=0xa0, AF=0 CF=1 + ( 0x3a, 0x15 ), # AL=0xa0, AF=1 CF=0 + ( 0x3a, 0x15 ), # AL=0xa0, AF=1 CF=1 + ( 0x41, 0x05 ), # AL=0xa1, AF=0 CF=0 + ( 0x41, 0x05 ), # AL=0xa1, AF=0 CF=1 + ( 0x3b, 0x11 ), # AL=0xa1, AF=1 CF=0 + ( 0x3b, 0x11 ), # AL=0xa1, AF=1 CF=1 + ( 0x42, 0x05 ), # AL=0xa2, AF=0 CF=0 + ( 0x42, 0x05 ), # AL=0xa2, AF=0 CF=1 + ( 0x3c, 0x15 ), # AL=0xa2, AF=1 CF=0 + ( 0x3c, 0x15 ), # AL=0xa2, AF=1 CF=1 + ( 0x43, 0x01 ), # AL=0xa3, AF=0 CF=0 + ( 0x43, 0x01 ), # AL=0xa3, AF=0 CF=1 + ( 0x3d, 0x11 ), # AL=0xa3, AF=1 CF=0 + ( 0x3d, 0x11 ), # AL=0xa3, AF=1 CF=1 + ( 0x44, 0x05 ), # AL=0xa4, AF=0 CF=0 + ( 0x44, 0x05 ), # AL=0xa4, AF=0 CF=1 + ( 0x3e, 0x11 ), # AL=0xa4, AF=1 CF=0 + ( 0x3e, 0x11 ), # AL=0xa4, AF=1 CF=1 + ( 0x45, 0x01 ), # AL=0xa5, AF=0 CF=0 + ( 0x45, 0x01 ), # AL=0xa5, AF=0 CF=1 + ( 0x3f, 0x15 ), # AL=0xa5, AF=1 CF=0 + ( 0x3f, 0x15 ), # AL=0xa5, AF=1 CF=1 + ( 0x46, 0x01 ), # AL=0xa6, AF=0 CF=0 + ( 0x46, 0x01 ), # AL=0xa6, AF=0 CF=1 + ( 0x40, 0x11 ), # AL=0xa6, AF=1 CF=0 + ( 0x40, 0x11 ), # AL=0xa6, AF=1 CF=1 + ( 0x47, 0x05 ), # AL=0xa7, AF=0 CF=0 + ( 0x47, 0x05 ), # AL=0xa7, AF=0 CF=1 + ( 0x41, 0x15 ), # AL=0xa7, AF=1 CF=0 + ( 0x41, 0x15 ), # AL=0xa7, AF=1 CF=1 + ( 0x48, 0x05 ), # AL=0xa8, AF=0 CF=0 + ( 0x48, 0x05 ), # AL=0xa8, AF=0 CF=1 + ( 0x42, 0x15 ), # AL=0xa8, AF=1 CF=0 + ( 0x42, 0x15 ), # AL=0xa8, AF=1 CF=1 + ( 0x49, 0x01 ), # AL=0xa9, AF=0 CF=0 + ( 0x49, 0x01 ), # AL=0xa9, AF=0 CF=1 + ( 0x43, 0x11 ), # AL=0xa9, AF=1 CF=0 + ( 0x43, 0x11 ), # AL=0xa9, AF=1 CF=1 + ( 0x44, 0x15 ), # AL=0xaa, AF=0 CF=0 + ( 0x44, 0x15 ), # AL=0xaa, AF=0 CF=1 + ( 0x44, 0x15 ), # AL=0xaa, AF=1 CF=0 + ( 0x44, 0x15 ), # AL=0xaa, AF=1 CF=1 + ( 0x45, 0x11 ), # AL=0xab, AF=0 CF=0 + ( 0x45, 0x11 ), # AL=0xab, AF=0 CF=1 + ( 0x45, 0x11 ), # AL=0xab, AF=1 CF=0 + ( 0x45, 0x11 ), # AL=0xab, AF=1 CF=1 + ( 0x46, 0x11 ), # AL=0xac, AF=0 CF=0 + ( 0x46, 0x11 ), # AL=0xac, AF=0 CF=1 + ( 0x46, 0x11 ), # AL=0xac, AF=1 CF=0 + ( 0x46, 0x11 ), # AL=0xac, AF=1 CF=1 + ( 0x47, 0x15 ), # AL=0xad, AF=0 CF=0 + ( 0x47, 0x15 ), # AL=0xad, AF=0 CF=1 + ( 0x47, 0x15 ), # AL=0xad, AF=1 CF=0 + ( 0x47, 0x15 ), # AL=0xad, AF=1 CF=1 + ( 0x48, 0x15 ), # AL=0xae, AF=0 CF=0 + ( 0x48, 0x15 ), # AL=0xae, AF=0 CF=1 + ( 0x48, 0x15 ), # AL=0xae, AF=1 CF=0 + ( 0x48, 0x15 ), # AL=0xae, AF=1 CF=1 + ( 0x49, 0x11 ), # AL=0xaf, AF=0 CF=0 + ( 0x49, 0x11 ), # AL=0xaf, AF=0 CF=1 + ( 0x49, 0x11 ), # AL=0xaf, AF=1 CF=0 + ( 0x49, 0x11 ), # AL=0xaf, AF=1 CF=1 + ( 0x50, 0x05 ), # AL=0xb0, AF=0 CF=0 + ( 0x50, 0x05 ), # AL=0xb0, AF=0 CF=1 + ( 0x4a, 0x11 ), # AL=0xb0, AF=1 CF=0 + ( 0x4a, 0x11 ), # AL=0xb0, AF=1 CF=1 + ( 0x51, 0x01 ), # AL=0xb1, AF=0 CF=0 + ( 0x51, 0x01 ), # AL=0xb1, AF=0 CF=1 + ( 0x4b, 0x15 ), # AL=0xb1, AF=1 CF=0 + ( 0x4b, 0x15 ), # AL=0xb1, AF=1 CF=1 + ( 0x52, 0x01 ), # AL=0xb2, AF=0 CF=0 + ( 0x52, 0x01 ), # AL=0xb2, AF=0 CF=1 + ( 0x4c, 0x11 ), # AL=0xb2, AF=1 CF=0 + ( 0x4c, 0x11 ), # AL=0xb2, AF=1 CF=1 + ( 0x53, 0x05 ), # AL=0xb3, AF=0 CF=0 + ( 0x53, 0x05 ), # AL=0xb3, AF=0 CF=1 + ( 0x4d, 0x15 ), # AL=0xb3, AF=1 CF=0 + ( 0x4d, 0x15 ), # AL=0xb3, AF=1 CF=1 + ( 0x54, 0x01 ), # AL=0xb4, AF=0 CF=0 + ( 0x54, 0x01 ), # AL=0xb4, AF=0 CF=1 + ( 0x4e, 0x15 ), # AL=0xb4, AF=1 CF=0 + ( 0x4e, 0x15 ), # AL=0xb4, AF=1 CF=1 + ( 0x55, 0x05 ), # AL=0xb5, AF=0 CF=0 + ( 0x55, 0x05 ), # AL=0xb5, AF=0 CF=1 + ( 0x4f, 0x11 ), # AL=0xb5, AF=1 CF=0 + ( 0x4f, 0x11 ), # AL=0xb5, AF=1 CF=1 + ( 0x56, 0x05 ), # AL=0xb6, AF=0 CF=0 + ( 0x56, 0x05 ), # AL=0xb6, AF=0 CF=1 + ( 0x50, 0x15 ), # AL=0xb6, AF=1 CF=0 + ( 0x50, 0x15 ), # AL=0xb6, AF=1 CF=1 + ( 0x57, 0x01 ), # AL=0xb7, AF=0 CF=0 + ( 0x57, 0x01 ), # AL=0xb7, AF=0 CF=1 + ( 0x51, 0x11 ), # AL=0xb7, AF=1 CF=0 + ( 0x51, 0x11 ), # AL=0xb7, AF=1 CF=1 + ( 0x58, 0x01 ), # AL=0xb8, AF=0 CF=0 + ( 0x58, 0x01 ), # AL=0xb8, AF=0 CF=1 + ( 0x52, 0x11 ), # AL=0xb8, AF=1 CF=0 + ( 0x52, 0x11 ), # AL=0xb8, AF=1 CF=1 + ( 0x59, 0x05 ), # AL=0xb9, AF=0 CF=0 + ( 0x59, 0x05 ), # AL=0xb9, AF=0 CF=1 + ( 0x53, 0x15 ), # AL=0xb9, AF=1 CF=0 + ( 0x53, 0x15 ), # AL=0xb9, AF=1 CF=1 + ( 0x54, 0x11 ), # AL=0xba, AF=0 CF=0 + ( 0x54, 0x11 ), # AL=0xba, AF=0 CF=1 + ( 0x54, 0x11 ), # AL=0xba, AF=1 CF=0 + ( 0x54, 0x11 ), # AL=0xba, AF=1 CF=1 + ( 0x55, 0x15 ), # AL=0xbb, AF=0 CF=0 + ( 0x55, 0x15 ), # AL=0xbb, AF=0 CF=1 + ( 0x55, 0x15 ), # AL=0xbb, AF=1 CF=0 + ( 0x55, 0x15 ), # AL=0xbb, AF=1 CF=1 + ( 0x56, 0x15 ), # AL=0xbc, AF=0 CF=0 + ( 0x56, 0x15 ), # AL=0xbc, AF=0 CF=1 + ( 0x56, 0x15 ), # AL=0xbc, AF=1 CF=0 + ( 0x56, 0x15 ), # AL=0xbc, AF=1 CF=1 + ( 0x57, 0x11 ), # AL=0xbd, AF=0 CF=0 + ( 0x57, 0x11 ), # AL=0xbd, AF=0 CF=1 + ( 0x57, 0x11 ), # AL=0xbd, AF=1 CF=0 + ( 0x57, 0x11 ), # AL=0xbd, AF=1 CF=1 + ( 0x58, 0x11 ), # AL=0xbe, AF=0 CF=0 + ( 0x58, 0x11 ), # AL=0xbe, AF=0 CF=1 + ( 0x58, 0x11 ), # AL=0xbe, AF=1 CF=0 + ( 0x58, 0x11 ), # AL=0xbe, AF=1 CF=1 + ( 0x59, 0x15 ), # AL=0xbf, AF=0 CF=0 + ( 0x59, 0x15 ), # AL=0xbf, AF=0 CF=1 + ( 0x59, 0x15 ), # AL=0xbf, AF=1 CF=0 + ( 0x59, 0x15 ), # AL=0xbf, AF=1 CF=1 + ( 0x60, 0x05 ), # AL=0xc0, AF=0 CF=0 + ( 0x60, 0x05 ), # AL=0xc0, AF=0 CF=1 + ( 0x5a, 0x15 ), # AL=0xc0, AF=1 CF=0 + ( 0x5a, 0x15 ), # AL=0xc0, AF=1 CF=1 + ( 0x61, 0x01 ), # AL=0xc1, AF=0 CF=0 + ( 0x61, 0x01 ), # AL=0xc1, AF=0 CF=1 + ( 0x5b, 0x11 ), # AL=0xc1, AF=1 CF=0 + ( 0x5b, 0x11 ), # AL=0xc1, AF=1 CF=1 + ( 0x62, 0x01 ), # AL=0xc2, AF=0 CF=0 + ( 0x62, 0x01 ), # AL=0xc2, AF=0 CF=1 + ( 0x5c, 0x15 ), # AL=0xc2, AF=1 CF=0 + ( 0x5c, 0x15 ), # AL=0xc2, AF=1 CF=1 + ( 0x63, 0x05 ), # AL=0xc3, AF=0 CF=0 + ( 0x63, 0x05 ), # AL=0xc3, AF=0 CF=1 + ( 0x5d, 0x11 ), # AL=0xc3, AF=1 CF=0 + ( 0x5d, 0x11 ), # AL=0xc3, AF=1 CF=1 + ( 0x64, 0x01 ), # AL=0xc4, AF=0 CF=0 + ( 0x64, 0x01 ), # AL=0xc4, AF=0 CF=1 + ( 0x5e, 0x11 ), # AL=0xc4, AF=1 CF=0 + ( 0x5e, 0x11 ), # AL=0xc4, AF=1 CF=1 + ( 0x65, 0x05 ), # AL=0xc5, AF=0 CF=0 + ( 0x65, 0x05 ), # AL=0xc5, AF=0 CF=1 + ( 0x5f, 0x15 ), # AL=0xc5, AF=1 CF=0 + ( 0x5f, 0x15 ), # AL=0xc5, AF=1 CF=1 + ( 0x66, 0x05 ), # AL=0xc6, AF=0 CF=0 + ( 0x66, 0x05 ), # AL=0xc6, AF=0 CF=1 + ( 0x60, 0x15 ), # AL=0xc6, AF=1 CF=0 + ( 0x60, 0x15 ), # AL=0xc6, AF=1 CF=1 + ( 0x67, 0x01 ), # AL=0xc7, AF=0 CF=0 + ( 0x67, 0x01 ), # AL=0xc7, AF=0 CF=1 + ( 0x61, 0x11 ), # AL=0xc7, AF=1 CF=0 + ( 0x61, 0x11 ), # AL=0xc7, AF=1 CF=1 + ( 0x68, 0x01 ), # AL=0xc8, AF=0 CF=0 + ( 0x68, 0x01 ), # AL=0xc8, AF=0 CF=1 + ( 0x62, 0x11 ), # AL=0xc8, AF=1 CF=0 + ( 0x62, 0x11 ), # AL=0xc8, AF=1 CF=1 + ( 0x69, 0x05 ), # AL=0xc9, AF=0 CF=0 + ( 0x69, 0x05 ), # AL=0xc9, AF=0 CF=1 + ( 0x63, 0x15 ), # AL=0xc9, AF=1 CF=0 + ( 0x63, 0x15 ), # AL=0xc9, AF=1 CF=1 + ( 0x64, 0x11 ), # AL=0xca, AF=0 CF=0 + ( 0x64, 0x11 ), # AL=0xca, AF=0 CF=1 + ( 0x64, 0x11 ), # AL=0xca, AF=1 CF=0 + ( 0x64, 0x11 ), # AL=0xca, AF=1 CF=1 + ( 0x65, 0x15 ), # AL=0xcb, AF=0 CF=0 + ( 0x65, 0x15 ), # AL=0xcb, AF=0 CF=1 + ( 0x65, 0x15 ), # AL=0xcb, AF=1 CF=0 + ( 0x65, 0x15 ), # AL=0xcb, AF=1 CF=1 + ( 0x66, 0x15 ), # AL=0xcc, AF=0 CF=0 + ( 0x66, 0x15 ), # AL=0xcc, AF=0 CF=1 + ( 0x66, 0x15 ), # AL=0xcc, AF=1 CF=0 + ( 0x66, 0x15 ), # AL=0xcc, AF=1 CF=1 + ( 0x67, 0x11 ), # AL=0xcd, AF=0 CF=0 + ( 0x67, 0x11 ), # AL=0xcd, AF=0 CF=1 + ( 0x67, 0x11 ), # AL=0xcd, AF=1 CF=0 + ( 0x67, 0x11 ), # AL=0xcd, AF=1 CF=1 + ( 0x68, 0x11 ), # AL=0xce, AF=0 CF=0 + ( 0x68, 0x11 ), # AL=0xce, AF=0 CF=1 + ( 0x68, 0x11 ), # AL=0xce, AF=1 CF=0 + ( 0x68, 0x11 ), # AL=0xce, AF=1 CF=1 + ( 0x69, 0x15 ), # AL=0xcf, AF=0 CF=0 + ( 0x69, 0x15 ), # AL=0xcf, AF=0 CF=1 + ( 0x69, 0x15 ), # AL=0xcf, AF=1 CF=0 + ( 0x69, 0x15 ), # AL=0xcf, AF=1 CF=1 + ( 0x70, 0x01 ), # AL=0xd0, AF=0 CF=0 + ( 0x70, 0x01 ), # AL=0xd0, AF=0 CF=1 + ( 0x6a, 0x15 ), # AL=0xd0, AF=1 CF=0 + ( 0x6a, 0x15 ), # AL=0xd0, AF=1 CF=1 + ( 0x71, 0x05 ), # AL=0xd1, AF=0 CF=0 + ( 0x71, 0x05 ), # AL=0xd1, AF=0 CF=1 + ( 0x6b, 0x11 ), # AL=0xd1, AF=1 CF=0 + ( 0x6b, 0x11 ), # AL=0xd1, AF=1 CF=1 + ( 0x72, 0x05 ), # AL=0xd2, AF=0 CF=0 + ( 0x72, 0x05 ), # AL=0xd2, AF=0 CF=1 + ( 0x6c, 0x15 ), # AL=0xd2, AF=1 CF=0 + ( 0x6c, 0x15 ), # AL=0xd2, AF=1 CF=1 + ( 0x73, 0x01 ), # AL=0xd3, AF=0 CF=0 + ( 0x73, 0x01 ), # AL=0xd3, AF=0 CF=1 + ( 0x6d, 0x11 ), # AL=0xd3, AF=1 CF=0 + ( 0x6d, 0x11 ), # AL=0xd3, AF=1 CF=1 + ( 0x74, 0x05 ), # AL=0xd4, AF=0 CF=0 + ( 0x74, 0x05 ), # AL=0xd4, AF=0 CF=1 + ( 0x6e, 0x11 ), # AL=0xd4, AF=1 CF=0 + ( 0x6e, 0x11 ), # AL=0xd4, AF=1 CF=1 + ( 0x75, 0x01 ), # AL=0xd5, AF=0 CF=0 + ( 0x75, 0x01 ), # AL=0xd5, AF=0 CF=1 + ( 0x6f, 0x15 ), # AL=0xd5, AF=1 CF=0 + ( 0x6f, 0x15 ), # AL=0xd5, AF=1 CF=1 + ( 0x76, 0x01 ), # AL=0xd6, AF=0 CF=0 + ( 0x76, 0x01 ), # AL=0xd6, AF=0 CF=1 + ( 0x70, 0x11 ), # AL=0xd6, AF=1 CF=0 + ( 0x70, 0x11 ), # AL=0xd6, AF=1 CF=1 + ( 0x77, 0x05 ), # AL=0xd7, AF=0 CF=0 + ( 0x77, 0x05 ), # AL=0xd7, AF=0 CF=1 + ( 0x71, 0x15 ), # AL=0xd7, AF=1 CF=0 + ( 0x71, 0x15 ), # AL=0xd7, AF=1 CF=1 + ( 0x78, 0x05 ), # AL=0xd8, AF=0 CF=0 + ( 0x78, 0x05 ), # AL=0xd8, AF=0 CF=1 + ( 0x72, 0x15 ), # AL=0xd8, AF=1 CF=0 + ( 0x72, 0x15 ), # AL=0xd8, AF=1 CF=1 + ( 0x79, 0x01 ), # AL=0xd9, AF=0 CF=0 + ( 0x79, 0x01 ), # AL=0xd9, AF=0 CF=1 + ( 0x73, 0x11 ), # AL=0xd9, AF=1 CF=0 + ( 0x73, 0x11 ), # AL=0xd9, AF=1 CF=1 + ( 0x74, 0x15 ), # AL=0xda, AF=0 CF=0 + ( 0x74, 0x15 ), # AL=0xda, AF=0 CF=1 + ( 0x74, 0x15 ), # AL=0xda, AF=1 CF=0 + ( 0x74, 0x15 ), # AL=0xda, AF=1 CF=1 + ( 0x75, 0x11 ), # AL=0xdb, AF=0 CF=0 + ( 0x75, 0x11 ), # AL=0xdb, AF=0 CF=1 + ( 0x75, 0x11 ), # AL=0xdb, AF=1 CF=0 + ( 0x75, 0x11 ), # AL=0xdb, AF=1 CF=1 + ( 0x76, 0x11 ), # AL=0xdc, AF=0 CF=0 + ( 0x76, 0x11 ), # AL=0xdc, AF=0 CF=1 + ( 0x76, 0x11 ), # AL=0xdc, AF=1 CF=0 + ( 0x76, 0x11 ), # AL=0xdc, AF=1 CF=1 + ( 0x77, 0x15 ), # AL=0xdd, AF=0 CF=0 + ( 0x77, 0x15 ), # AL=0xdd, AF=0 CF=1 + ( 0x77, 0x15 ), # AL=0xdd, AF=1 CF=0 + ( 0x77, 0x15 ), # AL=0xdd, AF=1 CF=1 + ( 0x78, 0x15 ), # AL=0xde, AF=0 CF=0 + ( 0x78, 0x15 ), # AL=0xde, AF=0 CF=1 + ( 0x78, 0x15 ), # AL=0xde, AF=1 CF=0 + ( 0x78, 0x15 ), # AL=0xde, AF=1 CF=1 + ( 0x79, 0x11 ), # AL=0xdf, AF=0 CF=0 + ( 0x79, 0x11 ), # AL=0xdf, AF=0 CF=1 + ( 0x79, 0x11 ), # AL=0xdf, AF=1 CF=0 + ( 0x79, 0x11 ), # AL=0xdf, AF=1 CF=1 + ( 0x80, 0x81 ), # AL=0xe0, AF=0 CF=0 + ( 0x80, 0x81 ), # AL=0xe0, AF=0 CF=1 + ( 0x7a, 0x11 ), # AL=0xe0, AF=1 CF=0 + ( 0x7a, 0x11 ), # AL=0xe0, AF=1 CF=1 + ( 0x81, 0x85 ), # AL=0xe1, AF=0 CF=0 + ( 0x81, 0x85 ), # AL=0xe1, AF=0 CF=1 + ( 0x7b, 0x15 ), # AL=0xe1, AF=1 CF=0 + ( 0x7b, 0x15 ), # AL=0xe1, AF=1 CF=1 + ( 0x82, 0x85 ), # AL=0xe2, AF=0 CF=0 + ( 0x82, 0x85 ), # AL=0xe2, AF=0 CF=1 + ( 0x7c, 0x11 ), # AL=0xe2, AF=1 CF=0 + ( 0x7c, 0x11 ), # AL=0xe2, AF=1 CF=1 + ( 0x83, 0x81 ), # AL=0xe3, AF=0 CF=0 + ( 0x83, 0x81 ), # AL=0xe3, AF=0 CF=1 + ( 0x7d, 0x15 ), # AL=0xe3, AF=1 CF=0 + ( 0x7d, 0x15 ), # AL=0xe3, AF=1 CF=1 + ( 0x84, 0x85 ), # AL=0xe4, AF=0 CF=0 + ( 0x84, 0x85 ), # AL=0xe4, AF=0 CF=1 + ( 0x7e, 0x15 ), # AL=0xe4, AF=1 CF=0 + ( 0x7e, 0x15 ), # AL=0xe4, AF=1 CF=1 + ( 0x85, 0x81 ), # AL=0xe5, AF=0 CF=0 + ( 0x85, 0x81 ), # AL=0xe5, AF=0 CF=1 + ( 0x7f, 0x11 ), # AL=0xe5, AF=1 CF=0 + ( 0x7f, 0x11 ), # AL=0xe5, AF=1 CF=1 + ( 0x86, 0x81 ), # AL=0xe6, AF=0 CF=0 + ( 0x86, 0x81 ), # AL=0xe6, AF=0 CF=1 + ( 0x80, 0x91 ), # AL=0xe6, AF=1 CF=0 + ( 0x80, 0x91 ), # AL=0xe6, AF=1 CF=1 + ( 0x87, 0x85 ), # AL=0xe7, AF=0 CF=0 + ( 0x87, 0x85 ), # AL=0xe7, AF=0 CF=1 + ( 0x81, 0x95 ), # AL=0xe7, AF=1 CF=0 + ( 0x81, 0x95 ), # AL=0xe7, AF=1 CF=1 + ( 0x88, 0x85 ), # AL=0xe8, AF=0 CF=0 + ( 0x88, 0x85 ), # AL=0xe8, AF=0 CF=1 + ( 0x82, 0x95 ), # AL=0xe8, AF=1 CF=0 + ( 0x82, 0x95 ), # AL=0xe8, AF=1 CF=1 + ( 0x89, 0x81 ), # AL=0xe9, AF=0 CF=0 + ( 0x89, 0x81 ), # AL=0xe9, AF=0 CF=1 + ( 0x83, 0x91 ), # AL=0xe9, AF=1 CF=0 + ( 0x83, 0x91 ), # AL=0xe9, AF=1 CF=1 + ( 0x84, 0x95 ), # AL=0xea, AF=0 CF=0 + ( 0x84, 0x95 ), # AL=0xea, AF=0 CF=1 + ( 0x84, 0x95 ), # AL=0xea, AF=1 CF=0 + ( 0x84, 0x95 ), # AL=0xea, AF=1 CF=1 + ( 0x85, 0x91 ), # AL=0xeb, AF=0 CF=0 + ( 0x85, 0x91 ), # AL=0xeb, AF=0 CF=1 + ( 0x85, 0x91 ), # AL=0xeb, AF=1 CF=0 + ( 0x85, 0x91 ), # AL=0xeb, AF=1 CF=1 + ( 0x86, 0x91 ), # AL=0xec, AF=0 CF=0 + ( 0x86, 0x91 ), # AL=0xec, AF=0 CF=1 + ( 0x86, 0x91 ), # AL=0xec, AF=1 CF=0 + ( 0x86, 0x91 ), # AL=0xec, AF=1 CF=1 + ( 0x87, 0x95 ), # AL=0xed, AF=0 CF=0 + ( 0x87, 0x95 ), # AL=0xed, AF=0 CF=1 + ( 0x87, 0x95 ), # AL=0xed, AF=1 CF=0 + ( 0x87, 0x95 ), # AL=0xed, AF=1 CF=1 + ( 0x88, 0x95 ), # AL=0xee, AF=0 CF=0 + ( 0x88, 0x95 ), # AL=0xee, AF=0 CF=1 + ( 0x88, 0x95 ), # AL=0xee, AF=1 CF=0 + ( 0x88, 0x95 ), # AL=0xee, AF=1 CF=1 + ( 0x89, 0x91 ), # AL=0xef, AF=0 CF=0 + ( 0x89, 0x91 ), # AL=0xef, AF=0 CF=1 + ( 0x89, 0x91 ), # AL=0xef, AF=1 CF=0 + ( 0x89, 0x91 ), # AL=0xef, AF=1 CF=1 + ( 0x90, 0x85 ), # AL=0xf0, AF=0 CF=0 + ( 0x90, 0x85 ), # AL=0xf0, AF=0 CF=1 + ( 0x8a, 0x91 ), # AL=0xf0, AF=1 CF=0 + ( 0x8a, 0x91 ), # AL=0xf0, AF=1 CF=1 + ( 0x91, 0x81 ), # AL=0xf1, AF=0 CF=0 + ( 0x91, 0x81 ), # AL=0xf1, AF=0 CF=1 + ( 0x8b, 0x95 ), # AL=0xf1, AF=1 CF=0 + ( 0x8b, 0x95 ), # AL=0xf1, AF=1 CF=1 + ( 0x92, 0x81 ), # AL=0xf2, AF=0 CF=0 + ( 0x92, 0x81 ), # AL=0xf2, AF=0 CF=1 + ( 0x8c, 0x91 ), # AL=0xf2, AF=1 CF=0 + ( 0x8c, 0x91 ), # AL=0xf2, AF=1 CF=1 + ( 0x93, 0x85 ), # AL=0xf3, AF=0 CF=0 + ( 0x93, 0x85 ), # AL=0xf3, AF=0 CF=1 + ( 0x8d, 0x95 ), # AL=0xf3, AF=1 CF=0 + ( 0x8d, 0x95 ), # AL=0xf3, AF=1 CF=1 + ( 0x94, 0x81 ), # AL=0xf4, AF=0 CF=0 + ( 0x94, 0x81 ), # AL=0xf4, AF=0 CF=1 + ( 0x8e, 0x95 ), # AL=0xf4, AF=1 CF=0 + ( 0x8e, 0x95 ), # AL=0xf4, AF=1 CF=1 + ( 0x95, 0x85 ), # AL=0xf5, AF=0 CF=0 + ( 0x95, 0x85 ), # AL=0xf5, AF=0 CF=1 + ( 0x8f, 0x91 ), # AL=0xf5, AF=1 CF=0 + ( 0x8f, 0x91 ), # AL=0xf5, AF=1 CF=1 + ( 0x96, 0x85 ), # AL=0xf6, AF=0 CF=0 + ( 0x96, 0x85 ), # AL=0xf6, AF=0 CF=1 + ( 0x90, 0x95 ), # AL=0xf6, AF=1 CF=0 + ( 0x90, 0x95 ), # AL=0xf6, AF=1 CF=1 + ( 0x97, 0x81 ), # AL=0xf7, AF=0 CF=0 + ( 0x97, 0x81 ), # AL=0xf7, AF=0 CF=1 + ( 0x91, 0x91 ), # AL=0xf7, AF=1 CF=0 + ( 0x91, 0x91 ), # AL=0xf7, AF=1 CF=1 + ( 0x98, 0x81 ), # AL=0xf8, AF=0 CF=0 + ( 0x98, 0x81 ), # AL=0xf8, AF=0 CF=1 + ( 0x92, 0x91 ), # AL=0xf8, AF=1 CF=0 + ( 0x92, 0x91 ), # AL=0xf8, AF=1 CF=1 + ( 0x99, 0x85 ), # AL=0xf9, AF=0 CF=0 + ( 0x99, 0x85 ), # AL=0xf9, AF=0 CF=1 + ( 0x93, 0x95 ), # AL=0xf9, AF=1 CF=0 + ( 0x93, 0x95 ), # AL=0xf9, AF=1 CF=1 + ( 0x94, 0x91 ), # AL=0xfa, AF=0 CF=0 + ( 0x94, 0x91 ), # AL=0xfa, AF=0 CF=1 + ( 0x94, 0x91 ), # AL=0xfa, AF=1 CF=0 + ( 0x94, 0x91 ), # AL=0xfa, AF=1 CF=1 + ( 0x95, 0x95 ), # AL=0xfb, AF=0 CF=0 + ( 0x95, 0x95 ), # AL=0xfb, AF=0 CF=1 + ( 0x95, 0x95 ), # AL=0xfb, AF=1 CF=0 + ( 0x95, 0x95 ), # AL=0xfb, AF=1 CF=1 + ( 0x96, 0x95 ), # AL=0xfc, AF=0 CF=0 + ( 0x96, 0x95 ), # AL=0xfc, AF=0 CF=1 + ( 0x96, 0x95 ), # AL=0xfc, AF=1 CF=0 + ( 0x96, 0x95 ), # AL=0xfc, AF=1 CF=1 + ( 0x97, 0x91 ), # AL=0xfd, AF=0 CF=0 + ( 0x97, 0x91 ), # AL=0xfd, AF=0 CF=1 + ( 0x97, 0x91 ), # AL=0xfd, AF=1 CF=0 + ( 0x97, 0x91 ), # AL=0xfd, AF=1 CF=1 + ( 0x98, 0x91 ), # AL=0xfe, AF=0 CF=0 + ( 0x98, 0x91 ), # AL=0xfe, AF=0 CF=1 + ( 0x98, 0x91 ), # AL=0xfe, AF=1 CF=0 + ( 0x98, 0x91 ), # AL=0xfe, AF=1 CF=1 + ( 0x99, 0x95 ), # AL=0xff, AF=0 CF=0 + ( 0x99, 0x95 ), # AL=0xff, AF=0 CF=1 + ( 0x99, 0x95 ), # AL=0xff, AF=1 CF=0 + ( 0x99, 0x95 ), # AL=0xff, AF=1 CF=1 +]; + diff --git a/src/VBox/VMM/testcase/Instructions/tstVBInsTstR3.cpp b/src/VBox/VMM/testcase/Instructions/tstVBInsTstR3.cpp new file mode 100644 index 00000000..23a52092 --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/tstVBInsTstR3.cpp @@ -0,0 +1,120 @@ +/* $Id: tstVBInsTstR3.cpp $ */ +/** @file + * Instruction Test Environment - IPRT ring-3 driver. + */ + +/* + * Copyright (C) 2006-2019 Oracle Corporation + * + * This file is part of VirtualBox Open Source Edition (OSE), as + * available from http://www.virtualbox.org. This file is free software; + * you can redistribute it and/or modify it under the terms of the GNU + * General Public License (GPL) as published by the Free Software + * Foundation, in version 2 as it comes in the "COPYING" file of the + * VirtualBox OSE distribution. VirtualBox OSE is distributed in the + * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. + */ + + +/********************************************************************************************************************************* +* Header Files * +*********************************************************************************************************************************/ +#include +#include +#include + +#ifdef RT_OS_WINDOWS +# define NO_LOW_MEM +#elif defined(RT_OS_OS2) || defined(RT_OS_HAIKU) +# define NO_LOW_MEM +#else +# include +#endif + + +/********************************************************************************************************************************* +* Structures and Typedefs * +*********************************************************************************************************************************/ +#if HC_ARCH_BITS == 64 +typedef uint64_t VBINSTSTREG; +#else +typedef uint32_t VBINSTSTREG; +#endif + + +/********************************************************************************************************************************* +* Global Variables * +*********************************************************************************************************************************/ +RTTEST g_hTest; + + +RT_C_DECLS_BEGIN +extern void *g_pvLow16Mem4K; +extern void *g_pvLow32Mem4K; +DECLASM(void) TestInstrMain(void); + +DECLEXPORT(void) VBInsTstFailure(const char *pszMessage); +DECLEXPORT(void) VBInsTstFailure1(const char *pszFmt, VBINSTSTREG uArg1); +DECLEXPORT(void) VBInsTstFailure2(const char *pszFmt, VBINSTSTREG uArg1, VBINSTSTREG uArg2); +DECLEXPORT(void) VBInsTstFailure3(const char *pszFmt, VBINSTSTREG uArg1, VBINSTSTREG uArg2, VBINSTSTREG uArg3); +DECLEXPORT(void) VBInsTstFailure4(const char *pszFmt, VBINSTSTREG uArg1, VBINSTSTREG uArg2, VBINSTSTREG uArg3, VBINSTSTREG uArg4); +RT_C_DECLS_END + + +DECLEXPORT(void) VBInsTstFailure(const char *pszMessage) +{ + RTTestFailed(g_hTest, "%s", pszMessage); +} + +DECLEXPORT(void) VBInsTstFailure1(const char *pszFmt, VBINSTSTREG uArg1) +{ + RTTestFailed(g_hTest, pszFmt, uArg1); +} + + +DECLEXPORT(void) VBInsTstFailure2(const char *pszFmt, VBINSTSTREG uArg1, VBINSTSTREG uArg2) +{ + RTTestFailed(g_hTest, pszFmt, uArg1, uArg2); +} + + +DECLEXPORT(void) VBInsTstFailure3(const char *pszFmt, VBINSTSTREG uArg1, VBINSTSTREG uArg2, VBINSTSTREG uArg3) +{ + RTTestFailed(g_hTest, pszFmt, uArg1, uArg2, uArg3); +} + + +DECLEXPORT(void) VBInsTstFailure4(const char *pszFmt, VBINSTSTREG uArg1, VBINSTSTREG uArg2, VBINSTSTREG uArg3, VBINSTSTREG uArg4) +{ + RTTestFailed(g_hTest, pszFmt, uArg1, uArg2, uArg3, uArg4); +} + + + + +int main() +{ + RTEXITCODE rcExit = RTTestInitAndCreate("VBInsTstR3", &g_hTest); + if (rcExit != RTEXITCODE_SUCCESS) + return rcExit; + RTTestBanner(g_hTest); + + int rc = RTMemAllocEx(_4K, 0, RTMEMALLOCEX_FLAGS_16BIT_REACH, &g_pvLow16Mem4K); + if (RT_FAILURE(rc)) + { + RTTestPrintf(g_hTest, RTTESTLVL_ALWAYS, "Could not allocate low 16-bit memory (%Rrc)\n", rc); + g_pvLow16Mem4K = NULL; + } + + rc = RTMemAllocEx(_4K, 0, RTMEMALLOCEX_FLAGS_32BIT_REACH, &g_pvLow32Mem4K); + if (RT_FAILURE(rc)) + { + RTTestPrintf(g_hTest, RTTESTLVL_ALWAYS, "Could not allocate low 32-bit memory (%Rrc)\n", rc); + g_pvLow32Mem4K = NULL; + } + + TestInstrMain(); + + return RTTestSummaryAndDestroy(g_hTest); +} + diff --git a/src/VBox/VMM/testcase/Makefile.kmk b/src/VBox/VMM/testcase/Makefile.kmk new file mode 100644 index 00000000..6e85c85a --- /dev/null +++ b/src/VBox/VMM/testcase/Makefile.kmk @@ -0,0 +1,654 @@ +# $Id: Makefile.kmk $ +## @file +# Sub-Makefile for the VMM testcases. +# + +# +# Copyright (C) 2006-2019 Oracle Corporation +# +# This file is part of VirtualBox Open Source Edition (OSE), as +# available from http://www.virtualbox.org. This file is free software; +# you can redistribute it and/or modify it under the terms of the GNU +# General Public License (GPL) as published by the Free Software +# Foundation, in version 2 as it comes in the "COPYING" file of the +# VirtualBox OSE distribution. VirtualBox OSE is distributed in the +# hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +# + +SUB_DEPTH = ../../../.. +include $(KBUILD_PATH)/subheader.kmk + +# +# Include sub-makefiles. +# +if 0 # Not ready for general consumption yet. + include $(PATH_SUB_CURRENT)/Instructions/Makefile.kmk +endif + +# +# Target lists. +# +PROGRAMS += tstVMStructSize tstAsmStructs +ifdef VBOX_WITH_RAW_MODE + PROGRAMS += tstVMStructRC tstAsmStructsRC +endif +if !defined(VBOX_ONLY_EXTPACKS) \ + && ( defined(VBOX_WITH_DTRACE_R3) \ + || defined(VBOX_WITH_DTRACE_R0) \ + || defined(VBOX_WITH_DTRACE_RC)) +PROGRAMS += tstVMStructDTrace +INSTALLS += VMMLibDTraceStructTest +endif +ifndef VBOX_ONLY_EXTPACKS_USE_IMPLIBS + if defined(VBOX_WITH_HARDENING) && "$(KBUILD_TARGET)" == "win" +PROGRAMS += tstGlobalConfigHardened +DLL += tstGlobalConfig + else +PROGRAMS += tstGlobalConfig + endif + + ifdef VBOX_WITH_RAW_MODE + if defined(VBOX_WITH_HARDENING) && "$(KBUILD_TARGET)" == "win" +PROGRAMS += tstVMMHardened +DLLS += tstVMM + else +PROGRAMS += tstVMM tstVMM-HM + endif + ifneq ($(KBUILD_TARGET),win) +PROGRAMS += tstVMMFork + endif + endif + ifdef VBOX_WITH_TESTCASES + if defined(VBOX_WITH_HARDENING) && "$(KBUILD_TARGET)" == "win" +PROGRAMS += tstCFGMHardened tstSSMHardened tstVMREQHardened tstMMHyperHeapHardened tstAnimateHardened +DLLS += tstCFGM tstSSM tstVMREQ tstMMHyperHeap tstAnimate + else +PROGRAMS += tstCFGM tstSSM tstVMREQ tstMMHyperHeap tstAnimate + endif +PROGRAMS += \ + tstCompressionBenchmark \ + tstIEMCheckMc \ + tstVMMR0CallHost-1 \ + tstVMMR0CallHost-2 \ + tstX86-FpuSaveRestore + ifn1of ($(KBUILD_TARGET).$(KBUILD_TARGET_ARCH), solaris.x86 solaris.amd64 win.amd64 ) ## TODO: Fix the code. +PROGRAMS += tstX86-1 + endif + ifdef VBOX_WITH_RAW_MODE + if defined(VBOX_WITH_HARDENING) && "$(KBUILD_TARGET)" == "win" +PROGRAMS += tstMicroHardened +DLLS += tstMicro + else +PROGRAMS += tstMicro + endif +SYSMODS += tstMicroRC + endif + ifdef VBOX_WITH_PDM_ASYNC_COMPLETION + if defined(VBOX_WITH_HARDENING) && "$(KBUILD_TARGET)" == "win" +PROGRAMS += tstPDMAsyncCompletionHardened tstPDMAsyncCompletionStressHardened +DLLS += tstPDMAsyncCompletion tstPDMAsyncCompletionStress + else +PROGRAMS += tstPDMAsyncCompletion tstPDMAsyncCompletionStress + endif + endif + endif # VBOX_WITH_TESTCASES +endif # !VBOX_ONLY_EXTPACKS_USE_IMPLIBS + +# Where we put our temporary files (just for simplicity) +VBOX_VMM_TESTCASE_OUT_DIR := $(PATH_TARGET)/VMM +BLDDIRS += $(VBOX_VMM_TESTCASE_OUT_DIR) + +# +# We setup two 'other' targets for executing the two structure & alignment +# validation testcases. Perhaps a bit hackish, but extremely useful. +# +ifeq ($(KBUILD_TARGET),$(KBUILD_HOST)) + ifeq ($(filter-out x86.x86 amd64.amd64 x86.amd64, $(KBUILD_TARGET_ARCH).$(KBUILD_HOST_ARCH)),) +OTHERS += \ + $(VBOX_VMM_TESTCASE_OUT_DIR)/tstAsmStructs.run \ + $(VBOX_VMM_TESTCASE_OUT_DIR)/tstVMStructSize.run + endif +endif + +# The normal testing pass. +TESTING += \ + $(VBOX_VMM_TESTCASE_OUT_DIR)/tstAsmStructs.run \ + $(VBOX_VMM_TESTCASE_OUT_DIR)/tstVMStructSize.run + +OTHER_CLEAN += \ + $(VBOX_VMM_TESTCASE_OUT_DIR)/tstAsmStructs.run \ + $(VBOX_VMM_TESTCASE_OUT_DIR)/tstVMStructSize.run \ + $(VBOX_VMM_TESTCASE_OUT_DIR)/tstAsmStructsAsm.o \ + $(VBOX_VMM_TESTCASE_OUT_DIR)/tstAsmStructsAsm.o.dep \ + $(VBOX_VMM_TESTCASE_OUT_DIR)/tstAsmStructsAsm.mac \ + $(VBOX_VMM_TESTCASE_OUT_DIR)/tstAsmStructsAsm.mac.o \ + $(VBOX_VMM_TESTCASE_OUT_DIR)/tstAsmStructsAsm.mac.lst \ + $(VBOX_VMM_TESTCASE_OUT_DIR)/tstAsmStructsRC.h \ + $(VBOX_VMM_TESTCASE_OUT_DIR)/tstAsmStructsHC.h \ + $(VBOX_VMM_TESTCASE_OUT_DIR)/tstVMStructRC.h + +# +# Globals +# +VBOX_PATH_VMM_SRC = $(PATH_ROOT)/src/VBox/VMM + +# +# Targets +# +ifdef VBOX_WITH_RAW_MODE +tstVMStructRC_TEMPLATE = VBoxRcExe +tstVMStructRC_DEFS = IN_VMM_RC IN_DIS IN_RT_RC VBOX_WITH_RAW_MODE $(VMM_COMMON_DEFS) + ifdef VBOX_WITH_R0_LOGGING +tstVMStructRC_DEFS += VBOX_WITH_R0_LOGGING + endif + ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI +tstVMStructRC_DEFS += VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI + endif +tstVMStructRC_SOURCES = tstVMStructRC.cpp +tstVMStructRC_INCS = \ + $(VBOX_PATH_VMM_SRC)/include \ + $(VBOX_PATH_VMM_SRC)/PATM +endif + +tstVMStructSize_TEMPLATE= VBOXR3AUTOTST +tstVMStructSize_DEFS = IN_VMM_R3 IN_DIS $(VMM_COMMON_DEFS) +ifdef VBOX_WITH_RAW_MODE +tstVMStructSize_DEFS += VBOX_WITH_RAW_MODE +endif +tstVMStructSize_INCS = \ + $(VBOX_PATH_VMM_SRC)/include \ + $(VBOX_PATH_VMM_SRC)/PATM \ + $(VBOX_VMM_TESTCASE_OUT_DIR) +tstVMStructSize_SOURCES = tstVMStructSize.cpp +ifdef VBOX_WITH_RAW_MODE +tstVMStructSize.cpp_DEPS= $(VBOX_VMM_TESTCASE_OUT_DIR)/tstVMStructRC.h +endif +ifdef VBOX_WITH_R0_LOGGING +tstVMStructSize_DEFS += VBOX_WITH_R0_LOGGING +endif +ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI +tstVMStructSize_DEFS += VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI +endif + +tstAsmStructs_TEMPLATE = VBOXR3AUTOTST +tstAsmStructs_DEFS = IN_VMM_R3 IN_DIS $(VMM_COMMON_DEFS) +ifdef VBOX_WITH_RAW_MODE +tstAsmStructs_DEFS += VBOX_WITH_RAW_MODE +endif +ifdef VBOX_WITH_R0_LOGGING +tstAsmStructs_DEFS += VBOX_WITH_R0_LOGGING +endif +ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI +tstAsmStructs_DEFS += VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI +endif +tstAsmStructs_INCS = \ + $(VBOX_PATH_VMM_SRC)/include \ + $(VBOX_VMM_TESTCASE_OUT_DIR) +tstAsmStructs_SOURCES = tstAsmStructs.cpp +tstAsmStructs.cpp_DEPS = $(VBOX_VMM_TESTCASE_OUT_DIR)/tstAsmStructsHC.h + +ifdef VBOX_WITH_RAW_MODE +tstAsmStructsRC_TEMPLATE= VBoxRcExe +tstAsmStructsRC_DEFS = IN_VMM_RC IN_DIS IN_RT_RC VBOX_WITH_RAW_MODE $(VMM_COMMON_DEFS) + ifdef VBOX_WITH_R0_LOGGING +tstAsmStructsRC_DEFS += VBOX_WITH_R0_LOGGING + endif + ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI +tstAsmStructsRC_DEFS += VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI + endif +tstAsmStructsRC_INCS = \ + $(VBOX_PATH_VMM_SRC)/include \ + $(VBOX_VMM_TESTCASE_OUT_DIR) +tstAsmStructsRC_SOURCES = tstAsmStructs.cpp +tstAsmStructs.cpp_DEPS += $(VBOX_VMM_TESTCASE_OUT_DIR)/tstAsmStructsRC.h +endif # VBOX_WITH_RAW_MODE + + +# +# Glboal config tool. +# +if defined(VBOX_WITH_HARDENING) && "$(KBUILD_TARGET)" == "win" +tstGlobalConfigHardened_TEMPLATE = VBoxR3HardenedTstExe +tstGlobalConfigHardened_NAME = tstGlobalConfig +tstGlobalConfigHardened_DEFS = PROGRAM_NAME_STR=\"tstGlobalConfig\" +tstGlobalConfigHardened_SOURCES = ../../HostDrivers/Support/SUPR3HardenedMainTemplateTestcase.cpp +tstGlobalConfig_TEMPLATE = VBoxR3HardenedTstDll +else +tstGlobalConfig_TEMPLATE = VBOXR3TSTEXE +endif +tstGlobalConfig_SOURCES = tstGlobalConfig.cpp +tstGlobalConfig_LIBS = $(LIB_RUNTIME) + +# +# Testcase for checking the repurposing of the IEM instruction code. +# +tstIEMCheckMc_TEMPLATE = VBOXR3TSTEXE +tstIEMCheckMc_SOURCES = tstIEMCheckMc.cpp +tstIEMCheckMc_DEFS = $(VMM_COMMON_DEFS) +tstIEMCheckMc_LIBS = $(LIB_RUNTIME) +ifeq ($(KBUILD_TARGET),win) +tstIEMCheckMc_CXXFLAGS = $(VBOX_C_CXX_FLAGS_NO_UNUSED_PARAMETERS) -wd4189 # local variable is initialized but not used. +else +tstIEMCheckMc_CXXFLAGS = $(VBOX_C_CXX_FLAGS_NO_UNUSED_PARAMETERS) -Wno-unused-value -Wno-unused-variable +endif + +# +# VMM heap testcase. +# +if defined(VBOX_WITH_HARDENING) && "$(KBUILD_TARGET)" == "win" +tstMMHyperHeapHardened_TEMPLATE = VBoxR3HardenedTstExe +tstMMHyperHeapHardened_NAME = tstMMHyperHeap +tstMMHyperHeapHardened_DEFS = PROGRAM_NAME_STR=\"tstMMHyperHeap\" +tstMMHyperHeapHardened_SOURCES = ../../HostDrivers/Support/SUPR3HardenedMainTemplateTestcase.cpp +tstMMHyperHeap_TEMPLATE = VBoxR3HardenedTstDll +else +tstMMHyperHeap_TEMPLATE = VBOXR3TSTEXE +endif +tstMMHyperHeap_SOURCES = tstMMHyperHeap.cpp +tstMMHyperHeap_LIBS = $(LIB_VMM) $(LIB_REM) $(LIB_RUNTIME) + +# +# Saved state manager testcase. +# +if defined(VBOX_WITH_HARDENING) && "$(KBUILD_TARGET)" == "win" +tstSSMHardened_TEMPLATE = VBoxR3HardenedTstExe +tstSSMHardened_NAME = tstSSM +tstSSMHardened_DEFS = PROGRAM_NAME_STR=\"tstSSM\" +tstSSMHardened_SOURCES = ../../HostDrivers/Support/SUPR3HardenedMainTemplateTestcase.cpp +tstSSM_TEMPLATE = VBoxR3HardenedTstDll +else +tstSSM_TEMPLATE = VBOXR3TSTEXE +endif +tstSSM_INCS = $(VBOX_PATH_VMM_SRC)/include +tstSSM_SOURCES = tstSSM.cpp +tstSSM_LIBS = $(LIB_VMM) $(LIB_REM) $(LIB_RUNTIME) + +# +# VMM configuration manager tests. +# +if defined(VBOX_WITH_HARDENING) && "$(KBUILD_TARGET)" == "win" +tstCFGMHardened_TEMPLATE = VBoxR3HardenedTstExe +tstCFGMHardened_NAME = tstCFGM +tstCFGMHardened_DEFS = PROGRAM_NAME_STR=\"tstCFGM\" +tstCFGMHardened_SOURCES = ../../HostDrivers/Support/SUPR3HardenedMainTemplateTestcase.cpp +tstCFGM_TEMPLATE = VBoxR3HardenedTstDll +else +tstCFGM_TEMPLATE = VBOXR3TSTEXE +endif +tstCFGM_SOURCES = tstCFGM.cpp +tstCFGM_LIBS = $(LIB_VMM) $(LIB_REM) $(LIB_RUNTIME) + +# +# Comparing some compression algorithms considered for SSM usage. +# +tstCompressionBenchmark_TEMPLATE = VBOXR3TSTEXE +tstCompressionBenchmark_SOURCES = tstCompressionBenchmark.cpp + +# +# Two testcases for checking the ring-3 "long jump" code. +# +tstVMMR0CallHost-1_TEMPLATE = VBOXR3TSTEXE +tstVMMR0CallHost-1_DEFS = VMM_R0_NO_SWITCH_STACK +tstVMMR0CallHost-1_INCS = $(VBOX_PATH_VMM_SRC)/include +tstVMMR0CallHost-1_SOURCES = \ + tstVMMR0CallHost-1.cpp +tstVMMR0CallHost-1_SOURCES.amd64 = \ + $(VBOX_PATH_VMM_SRC)/VMMR0/VMMR0JmpA-amd64.asm +tstVMMR0CallHost-1_SOURCES.x86 = \ + $(VBOX_PATH_VMM_SRC)/VMMR0/VMMR0JmpA-x86.asm + +tstVMMR0CallHost-2_EXTENDS = tstVMMR0CallHost-1 +tstVMMR0CallHost-2_DEFS = VMM_R0_SWITCH_STACK + +# +# For testing the VM request queue code. +# +if defined(VBOX_WITH_HARDENING) && "$(KBUILD_TARGET)" == "win" +tstVMREQHardened_TEMPLATE = VBOXR3HARDENEDEXE +tstVMREQHardened_NAME = tstVMREQ +tstVMREQHardened_DEFS = PROGRAM_NAME_STR=\"tstVMREQ\" +tstVMREQHardened_SOURCES = ../../HostDrivers/Support/SUPR3HardenedMainTemplate.cpp +tstVMREQ_TEMPLATE = VBOXR3 +else +tstVMREQ_TEMPLATE = VBOXR3EXE +endif +tstVMREQ_SOURCES = tstVMREQ.cpp +tstVMREQ_LIBS = $(LIB_VMM) $(LIB_REM) $(LIB_RUNTIME) + +# +# Tool for reanimate things like OS/2 dumps. +# +if defined(VBOX_WITH_HARDENING) && "$(KBUILD_TARGET)" == "win" +tstAnimateHardened_TEMPLATE = VBOXR3HARDENEDEXE +tstAnimateHardened_NAME = tstAnimate +tstAnimateHardened_DEFS = PROGRAM_NAME_STR=\"tstAnimate\" +tstAnimateHardened_SOURCES = ../../HostDrivers/Support/SUPR3HardenedMainTemplate.cpp +tstAnimate_TEMPLATE = VBOXR3 +else +tstAnimate_TEMPLATE = VBOXR3EXE +endif +tstAnimate_SOURCES = tstAnimate.cpp +tstAnimate_LIBS = $(LIB_VMM) $(LIB_REM) $(LIB_RUNTIME) + +tstX86-1_TEMPLATE = VBOXR3TSTEXE +tstX86-1_SOURCES = tstX86-1.cpp tstX86-1A.asm +tstX86-1_LIBS = $(LIB_RUNTIME) +tstX86-1_LDFLAGS.linux = $(VBOX_GCC_no-pie) + +tstX86-FpuSaveRestore_TEMPLATE = VBOXR3TSTEXE +tstX86-FpuSaveRestore_SOURCES = tstX86-FpuSaveRestore.cpp tstX86-FpuSaveRestoreA.asm +tstX86-FpuSaveRestore_LIBS = $(LIB_RUNTIME) + +ifdef VBOX_WITH_RAW_MODE + + # + # Raw-mode VMM testcase. + # + if defined(VBOX_WITH_HARDENING) && "$(KBUILD_TARGET)" == "win" +tstVMMHardened_TEMPLATE = VBOXR3HARDENEDEXE +tstVMMHardened_NAME = tstVMM +tstVMMHardened_DEFS = PROGRAM_NAME_STR=\"tstVMM\" +tstVMMHardened_SOURCES = ../../HostDrivers/Support/SUPR3HardenedMainTemplate.cpp +tstVMM_TEMPLATE = VBOXR3 + else +tstVMM_TEMPLATE = VBOXR3EXE + endif +tstVMM_SOURCES = tstVMM.cpp +tstVMM_LIBS = $(LIB_VMM) $(LIB_REM) $(LIB_RUNTIME) + +# +# HM VMM testcase. +# +tstVMM-HM_TEMPLATE = VBOXR3EXE +tstVMM-HM_SOURCES = tstVMM-HM.cpp +tstVMM-HM_LIBS = $(LIB_VMM) $(LIB_REM) $(LIB_RUNTIME) + +# +# VMM host process fork test case (memory ++). +# +tstVMMFork_TEMPLATE = VBOXR3EXE +tstVMMFork_SOURCES = tstVMMFork.cpp +tstVMMFork_LIBS = $(LIB_VMM) $(LIB_REM) $(LIB_RUNTIME) + +# +# Raw-mode micro benchmark. +# + if defined(VBOX_WITH_HARDENING) && "$(KBUILD_TARGET)" == "win" +tstMicroHardened_TEMPLATE = VBOXR3HARDENEDEXE +tstMicroHardened_NAME = tstMicro +tstMicroHardened_DEFS = PROGRAM_NAME_STR=\"tstMicro\" +tstMicroHardened_SOURCES = ../../HostDrivers/Support/SUPR3HardenedMainTemplate.cpp +tstMicro_TEMPLATE = VBOXR3 + else +tstMicro_TEMPLATE = VBOXR3EXE + endif +tstMicro_SOURCES = tstMicro.cpp +tstMicro_LIBS = $(LIB_VMM) $(LIB_REM) $(LIB_RUNTIME) +tstMicro_DEFS = $(if $(VBOX_WITH_RAW_MODE),VBOX_WITH_RAW_MODE,) + +tstMicroRC_TEMPLATE = VBoxRc +tstMicroRC_SOURCES = tstMicroRC.cpp tstMicroRCA.asm +tstMicroRC_DEFS = $(if $(VBOX_WITH_RAW_MODE),VBOX_WITH_RAW_MODE,) +tstMicroRC_INCS = $(VBOX_PATH_VMM_SRC)/testcase + ifeq ($(VBOX_LDR_FMT32),pe) +tstMicroRC_LDFLAGS = -Entry:tstMicroRC + endif +tstMicroRC_SYSSUFF = .gc +tstMicroRC_LIBS = \ + $(PATH_STAGE_LIB)/DisasmRC$(VBOX_SUFF_LIB) \ + $(PATH_STAGE_LIB)/RuntimeRC$(VBOX_SUFF_LIB) + ifeq ($(filter-out pe lx,$(VBOX_LDR_FMT32)),) +tstMicroRC_LIBS += \ + $(PATH_STAGE_LIB)/VMMRCBuiltin$(VBOX_SUFF_LIB) \ + $(LIB_VMMRC) + endif +tstMicroRC_SOURCES.win = tstMicroRC.def + +endif # VBOX_WITH_RAW_MODE + + +if !defined(VBOX_ONLY_EXTPACKS_USE_IMPLIBS) +# +# Special NEM host testcase. +# + if ("$(KBUILD_TARGET_ARCH).$(KBUILD_TARGET_ARCH)" == "darwin.amd64" && (defined(VBOX_WITH_NATIVE_NEM) || "$(USERNAME)" == "bird")) \ + || ("$(KBUILD_TARGET_ARCH).$(KBUILD_TARGET_ARCH)" == "linux.amd64" && (defined(VBOX_WITH_NATIVE_NEM) || "$(USERNAME)" == "bird")) \ + || ("$(KBUILD_TARGET_ARCH).$(KBUILD_TARGET_ARCH)" == "win.amd64" && defined(VBOX_WITH_NATIVE_NEM)) +PROGRAMS += NemRawBench-1 +NemRawBench-1_TEMPLATE = VBoxR3Static +NemRawBench-1_SOURCES = NemRawBench-1.cpp +NemRawBench-1_BLD_TYPE = release +NemRawBench-1_INCS.win = \ + $(KBUILD_DEVTOOLS)/win.x86/sdk/v10.0.17134.0/include/10.0.17134.0/um \ + $(KBUILD_DEVTOOLS)/win.x86/sdk/v10.0.17134.0/include/10.0.17134.0/shared +NemRawBench-1_CXXFLAGS.darwin = \ + -F/Applications/Xcode.app/Contents/Developer/Platforms/MacOSX.platform//Developer/SDKs/MacOSX10.13.sdk/System/Library/Frameworks +#NemRawBench-1_LDFLAGS.darwin = \ +# -F/System/Library/Frameworks \ +# -framework Hypervisor +NemRawBench-1_LDFLAGS.darwin = \ + /System/Library/Frameworks/Hypervisor.framework/Hypervisor + endif +endif + + +ifdef VBOX_WITH_PDM_ASYNC_COMPLETION +# +# PDM asynchronous completation test. +# + if defined(VBOX_WITH_HARDENING) && "$(KBUILD_TARGET)" == "win" +tstPDMAsyncCompletionHardened_TEMPLATE = VBOXR3HARDENEDEXE +tstPDMAsyncCompletionHardened_NAME = tstPDMAsyncCompletion +tstPDMAsyncCompletionHardened_DEFS = PROGRAM_NAME_STR=\"tstPDMAsyncCompletion\" +tstPDMAsyncCompletionHardened_SOURCES = ../../HostDrivers/Support/SUPR3HardenedMainTemplate.cpp +tstPDMAsyncCompletion_TEMPLATE = VBOXR3 + else +tstPDMAsyncCompletion_TEMPLATE = VBOXR3EXE + endif +tstPDMAsyncCompletion_INCS = $(VBOX_PATH_VMM_SRC)/include +tstPDMAsyncCompletion_SOURCES = tstPDMAsyncCompletion.cpp +tstPDMAsyncCompletion_LIBS = $(LIB_VMM) $(LIB_REM) $(LIB_RUNTIME) + +# +# PDM asynchronous completation stress test. +# + if defined(VBOX_WITH_HARDENING) && "$(KBUILD_TARGET)" == "win" +tstPDMAsyncCompletionStressHardened_TEMPLATE = VBOXR3HARDENEDEXE +tstPDMAsyncCompletionStressHardened_NAME = tstPDMAsyncCompletionStress +tstPDMAsyncCompletionStressHardened_DEFS = PROGRAM_NAME_STR=\"tstPDMAsyncCompletionStress\" +tstPDMAsyncCompletionStressHardened_SOURCES = ../../HostDrivers/Support/SUPR3HardenedMainTemplate.cpp +tstPDMAsyncCompletionStress_TEMPLATE = VBOXR3 + else +tstPDMAsyncCompletionStress_TEMPLATE = VBOXR3EXE + endif +tstPDMAsyncCompletionStress_INCS = $(VBOX_PATH_VMM_SRC)/include +tstPDMAsyncCompletionStress_SOURCES = tstPDMAsyncCompletionStress.cpp +tstPDMAsyncCompletionStress_LIBS = $(LIB_VMM) $(LIB_REM) $(LIB_RUNTIME) +endif + +ifndef VBOX_ONLY_EXTPACKS +PROGRAMS += tstSSM-2 +tstSSM-2_TEMPLATE = VBOXR3TSTEXE +tstSSM-2_DEFS = IN_VMM_STATIC +tstSSM-2_SOURCES = tstSSM-2.cpp +tstSSM-2_LIBS = $(PATH_STAGE_LIB)/SSMStandalone$(VBOX_SUFF_LIB) +endif + +# +# Generate VM structure tests. +# +if !defined(VBOX_ONLY_EXTPACKS) \ + && ( defined(VBOX_WITH_DTRACE_R3) \ + || defined(VBOX_WITH_DTRACE_R0) \ + || defined(VBOX_WITH_DTRACE_RC)) +tstVMStructDTrace_TEMPLATE = VBOXR3AUTOTST +tstVMStructDTrace_DEFS = IN_VMM_R3 IN_DIS $(VMM_COMMON_DEFS) + ifdef VBOX_WITH_RAW_MODE +tstVMStructDTrace_DEFS += VBOX_WITH_RAW_MODE + endif +tstVMStructDTrace_INCS = \ + $(VBOX_PATH_VMM_SRC)/include \ + $(VBOX_PATH_VMM_SRC)/PATM \ + $(VBOX_VMM_TESTCASE_OUT_DIR) +tstVMStructDTrace_SOURCES = tstVMStructDTrace.cpp + ifdef VBOX_WITH_R0_LOGGING +tstVMStructDTrace_DEFS += VBOX_WITH_R0_LOGGING + endif + ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI +tstVMStructDTrace_DEFS += VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI + endif + + +VMMLibDTraceStructTest_INST = $(VBOX_INST_DTRACE_TST)$(KBUILD_TARGET_ARCH)/ +VMMLibDTraceStructTest_SOURCES = \ + $(tstVMStructDTrace_0_OUTDIR)/vbox-vm-struct-test.d + +$$(tstVMStructDTrace_0_OUTDIR)/vbox-vm-struct-test.d: \ + $$(tstVMStructDTrace_1_STAGE_TARGET) | $$(dir $$@) + $(QUIET)$(RM) -f $@ + $< > $@ + +endif + + +include $(FILE_KBUILD_SUB_FOOTER) + + +# +# Some handcrafted support targets for tstAsmStructs. +# +MY_ASA_ASM_STUFF = \ + $(addprefix -D, \ + $(DEFS) \ + $(DEFS.$(KBUILD_TYPE)) \ + $(DEFS.$(KBUILD_TARGET)) \ + IN_RING3 $(ARCH_BITS_DEFS) \ + $(DEFS.$(KBUILD_TARGET_ARCH)) \ + $(DEFS.$(KBUILD_TARGET).$(KBUILD_TARGET_ARCH)) \ + $(if $(VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI),VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI,) \ + ) \ + -f $(if $(eq $(KBUILD_TARGET),darwin),macho,elf) \ + $(foreach inc,$(INCS) $(VBOX_PATH_VMM_SRC)/testcase $(VBOX_PATH_VMM_SRC)/include $(VBOX_VMM_TESTCASE_OUT_DIR)\ + ,-I$(inc)/) + +# 1a. make a header file which makes all the structures+members globals. +$(VBOX_VMM_TESTCASE_OUT_DIR)/tstAsmStructsAsm.mac: \ + $(VBOX_PATH_VMM_SRC)/testcase/tstAsmStructsAsm.asm \ + $(VBOX_PATH_VMM_SRC)/testcase/tstAsmStructsAsm-lst.sed \ + $(DEPTH)/include/iprt/asmdefs.mac \ + $(DEPTH)/include/VBox/vmm/cpum.mac \ + $(DEPTH)/include/VBox/vmm/vm.mac \ + $(DEPTH)/include/VBox/sup.mac \ + $(DEPTH)/include/iprt/x86.mac \ + $(VBOX_PATH_VMM_SRC)/include/CPUMInternal.mac \ + $(VBOX_PATH_VMM_SRC)/include/TRPMInternal.mac \ + $(VBOX_PATH_VMM_SRC)/include/HMInternal.mac \ + $(VBOX_PATH_VMM_SRC)/include/VMMInternal.mac \ + $(VBOX_PATH_VMM_SRC)/testcase/Makefile.kmk \ + $(PATH_ROOT)/Config.kmk $(LOCALCFG) $(AUTOCFG) \ + | $$(dir $$@) + $(call MSG_GENERATE,tstVMStructSize,$@,$<) +ifndef DONT_USE_YASM + $(QUIET)$(TOOL_YASM_AS) $(MY_ASA_ASM_STUFF) -o $@.o -l $@.lst $< + $(SED) -f $(VBOX_PATH_VMM_SRC)/testcase/tstAsmStructsAsm-lst.sed --output $@ $@.lst +else + $(QUIET)$(TOOL_NASM_AS) -g $(MY_ASA_ASM_STUFF) -o $@.o -l $@.lst $< + $(VBOX_NM) $@.o | $(SED) \ + -e '/[0-9a-fA-F][0-9a-fA-F]* [^a] /d' \ + -e 's/[0-9a-fA-F][0-9a-fA-F]* a \([^ ]*\)/global \1/' \ + > $@ +endif + +# 1b. make an elf/macho object containing the offsets. +includedep $(VBOX_VMM_TESTCASE_OUT_DIR)/tstAsmStructsAsm.o.dep +$(VBOX_VMM_TESTCASE_OUT_DIR)/tstAsmStructsAsm.o: \ + $(VBOX_PATH_VMM_SRC)/testcase/tstAsmStructsAsm.asm \ + $(VBOX_VMM_TESTCASE_OUT_DIR)/tstAsmStructsAsm.mac \ + $(DEPTH)/include/iprt/asmdefs.mac \ + $(DEPTH)/include/VBox/vmm/cpum.mac \ + $(DEPTH)/include/VBox/vmm/hm_vmx.mac \ + $(DEPTH)/include/VBox/vmm/stam.mac \ + $(DEPTH)/include/VBox/vmm/trpm.mac \ + $(DEPTH)/include/VBox/vmm/vm.mac \ + $(DEPTH)/include/VBox/sup.mac \ + $(DEPTH)/include/iprt/x86.mac \ + $(VBOX_PATH_VMM_SRC)/include/CPUMInternal.mac \ + $(VBOX_PATH_VMM_SRC)/include/HMInternal.mac \ + $(VBOX_PATH_VMM_SRC)/include/VMMInternal.mac \ + $(VBOX_PATH_VMM_SRC)/include/VMMSwitcher.mac \ + $(VBOX_PATH_VMM_SRC)/testcase/Makefile.kmk \ + $$(if $$(eq $$(tstAsmStructsAsmDep_STUFF),$$(MY_ASA_ASM_STUFF)),,FORCE) \ + | $$(dir $$@) + $(call MSG_COMPILE,tstAsmStructsasm,$<,$@,AS) +ifndef DONT_USE_YASM + $(QUIET)$(TOOL_YASM_AS) $(MY_ASA_ASM_STUFF) -DDO_GLOBALS -o $@ $< +else + $(QUIET)$(TOOL_NASM_AS) $(MY_ASA_ASM_STUFF) -DDO_GLOBALS -o $@ $< +endif + %$(QUIET2)$(RM) -f -- $(VBOX_VMM_TESTCASE_OUT_DIR)/tstAsmStructsAsm.o.dep + %$(QUIET2)$(APPEND) '$(VBOX_VMM_TESTCASE_OUT_DIR)/tstAsmStructsAsm.o.dep' 'tstAsmStructsAsmDep_STUFF=$(MY_ASA_ASM_STUFF)' + +# 2. use nm and sed to transform this into the header we want. +$(VBOX_VMM_TESTCASE_OUT_DIR)/tstAsmStructsHC.h: $(VBOX_VMM_TESTCASE_OUT_DIR)/tstAsmStructsAsm.o + $(call MSG_GENERATE,tstVMStructSize,$@,$<) + $(QUIET)$(RM) -f $@ $@.dump $@.tmp + $(QUIET)$(REDIRECT) -wo $@.dump -- $(VBOX_NM) $< + $(QUIET)$(SED) \ + -e '/STAMPROFILEADV/d' \ + \ + -e '/^\(0x\)\{0,1\}00[0-9a-fA-F]* [aAnN] [^_.]*\./!d' \ + -e 's/^\(0x\)\{0,1\}\(00[0-9a-fA-F]*\) [aAnN] \([^.]*\)\.\(.*$$\)/ CHECK_OFF(\3, 0x0\2, \4);/' \ + --output $@.tmp $@.dump + $(QUIET)$(SED) \ + -e '/VM_size$$/d' \ + -e '/VMCPU_size$$/d' \ + -e '/VMMCPU_size$$/d' \ + -e '/SUPDRVTRACERUSRCTX32_size$$/d' \ + -e '/HMCPU_size$$/d' \ + \ + -e '/^\(0x\)\{0,1\}00[0-9a-fA-F]* [aAnN] [^_.]*_size$$/!d' \ + -e 's/^\(0x\)\{0,1\}\(00[0-9a-fA-F]*\) [aAnN] \([^_.]*\)_size/ CHECK_SIZE(\3, 0x0\2);/' \ + --append $@.tmp $@.dump + $(QUIET)$(MV) -f $@.tmp $@ + $(QUIET)$(RM) -f $@.dump + +ifdef VBOX_WITH_RAW_MODE +# 3. transform the HC header into a RC one by omitting some HC only structures. +$(VBOX_VMM_TESTCASE_OUT_DIR)/tstAsmStructsRC.h: $(VBOX_VMM_TESTCASE_OUT_DIR)/tstAsmStructsHC.h + $(call MSG_GENERATE,tstVMStructSize,$@,$<) + $(QUIET)$(SED) -e '/VMMSWITCHERDEF/d' --output $@ $^ +endif + +# 4. run it. +$(VBOX_VMM_TESTCASE_OUT_DIR)/tstAsmStructs.run: \ + $$(tstAsmStructs_1_STAGE_TARGET) \ + $(if-expr defined(VBOX_WITH_RAW_MODE),$$(tstAsmStructsRC_1_STAGE_TARGET),) + $(QUIET)$(RM) -f $@ + $(tstAsmStructs_1_STAGE_TARGET) +ifdef VBOX_WITH_RAW_MODE + $(tstAsmStructsRC_1_STAGE_TARGET) +endif + $(QUIET)$(APPEND) "$@" "done" + + + +# +# Run rule for tstVMStructSize. +# + +ifdef VBOX_WITH_RAW_MODE +# 1. Manually dump selected structures and members. +$(VBOX_VMM_TESTCASE_OUT_DIR)/tstVMStructRC.h: $$(tstVMStructRC_1_STAGE_TARGET) | $$(dir $$@) + $(call MSG_GENERATE,tstVMStructSize,$@) + $(QUIET)$(REDIRECT) -wo $@ -- $< +endif # VBOX_WITH_RAW_MODE + +# 2. run it. +$(VBOX_VMM_TESTCASE_OUT_DIR)/tstVMStructSize.run: $$(tstVMStructSize_1_STAGE_TARGET) | $$(dir $$@) + $(QUIET)$(RM) -f $@ + $< + $(QUIET)$(APPEND) "$@" "done" + +# alias for the two struct tests. +run-struct-tests: $(VBOX_VMM_TESTCASE_OUT_DIR)/tstAsmStructs.run $(VBOX_VMM_TESTCASE_OUT_DIR)/tstVMStructSize.run + diff --git a/src/VBox/VMM/testcase/NemRawBench-1.cpp b/src/VBox/VMM/testcase/NemRawBench-1.cpp new file mode 100644 index 00000000..8a1e085e --- /dev/null +++ b/src/VBox/VMM/testcase/NemRawBench-1.cpp @@ -0,0 +1,1346 @@ +/* $Id: NemRawBench-1.cpp $ */ +/** @file + * NEM Benchmark. + */ + +/* + * Copyright (C) 2018-2019 Oracle Corporation + * + * This file is part of VirtualBox Open Source Edition (OSE), as + * available from http://www.virtualbox.org. This file is free software; + * you can redistribute it and/or modify it under the terms of the GNU + * General Public License (GPL) as published by the Free Software + * Foundation, in version 2 as it comes in the "COPYING" file of the + * VirtualBox OSE distribution. VirtualBox OSE is distributed in the + * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. + */ + + +/********************************************************************************************************************************* +* Header Files * +*********************************************************************************************************************************/ +#ifdef RT_OS_WINDOWS +# include +# include +# if !defined(_INTPTR) && defined(_M_AMD64) /* void pedantic stdint.h warnings */ +# define _INTPTR 2 +# endif + +#elif defined(RT_OS_LINUX) +# include +# include +# include +# include +# include +# include +# include + +#elif defined(RT_OS_DARWIN) +# include +# if 1 /* header mix hack */ +# undef __OSX_AVAILABLE_STARTING +# define __OSX_AVAILABLE_STARTING(_osx, _ios) +# endif +# include +# include +# include +# include +# include +# include +# include +# include +# include +# include + +#else +# error "port me" +#endif + +#include +#include +#include +#include +#include + + +/********************************************************************************************************************************* +* Defined Constants And Macros * +*********************************************************************************************************************************/ +/** The base mapping address of the g_pbMem. */ +#define MY_MEM_BASE 0x1000 +/** No-op MMIO access address. */ +#define MY_NOP_MMIO 0x0808 +/** The RIP which the testcode starts. */ +#define MY_TEST_RIP 0x2000 + +/** The test termination port number. */ +#define MY_TERM_PORT 0x01 +/** The no-op test port number. */ +#define MY_NOP_PORT 0x7f + +#define MY_TEST_F_NOP_IO (1U<<0) +#define MY_TEST_F_CPUID (1U<<1) +#define MY_TEST_F_NOP_MMIO (1U<<2) + + + +/********************************************************************************************************************************* +* Global Variables * +*********************************************************************************************************************************/ +/** Chunk of memory mapped at address 0x1000 (MY_MEM_BASE). */ +static unsigned char *g_pbMem; +/** Amount of RAM at address 0x1000 (MY_MEM_BASE). */ +static size_t g_cbMem; +#ifdef RT_OS_WINDOWS +static WHV_PARTITION_HANDLE g_hPartition = NULL; + +/** @name APIs imported from WinHvPlatform.dll + * @{ */ +static decltype(WHvCreatePartition) *g_pfnWHvCreatePartition; +static decltype(WHvSetupPartition) *g_pfnWHvSetupPartition; +static decltype(WHvGetPartitionProperty) *g_pfnWHvGetPartitionProperty; +static decltype(WHvSetPartitionProperty) *g_pfnWHvSetPartitionProperty; +static decltype(WHvMapGpaRange) *g_pfnWHvMapGpaRange; +static decltype(WHvCreateVirtualProcessor) *g_pfnWHvCreateVirtualProcessor; +static decltype(WHvRunVirtualProcessor) *g_pfnWHvRunVirtualProcessor; +static decltype(WHvGetVirtualProcessorRegisters) *g_pfnWHvGetVirtualProcessorRegisters; +static decltype(WHvSetVirtualProcessorRegisters) *g_pfnWHvSetVirtualProcessorRegisters; +/** @} */ +static uint64_t (WINAPI *g_pfnRtlGetSystemTimePrecise)(void); + +#elif defined(RT_OS_LINUX) +/** The VM handle. */ +static int g_fdVm; +/** The VCPU handle. */ +static int g_fdVCpu; +/** The kvm_run structure for the VCpu. */ +static struct kvm_run *g_pVCpuRun; +/** The size of the g_pVCpuRun mapping. */ +static ssize_t g_cbVCpuRun; + +#elif defined(RT_OS_DARWIN) +/** The VCpu ID. */ +static hv_vcpuid_t g_idVCpu; +#endif + + +static int error(const char *pszFormat, ...) +{ + fprintf(stderr, "error: "); + va_list va; + va_start(va, pszFormat); + vfprintf(stderr, pszFormat, va); + va_end(va); + return 1; +} + + +static uint64_t getNanoTS(void) +{ +#ifdef RT_OS_WINDOWS + return g_pfnRtlGetSystemTimePrecise() * 100; + +#elif defined(RT_OS_LINUX) + struct timespec ts; + clock_gettime(CLOCK_MONOTONIC, &ts); + return (uint64_t)ts.tv_sec * UINT64_C(1000000000) + ts.tv_nsec; + +#elif defined(RT_OS_DARWIN) + static struct mach_timebase_info s_Info = { 0, 0 }; + static double s_rdFactor = 0.0; + /* Lazy init. */ + if (s_Info.denom != 0) + { /* likely */ } + else if (mach_timebase_info(&s_Info) == KERN_SUCCESS) + s_rdFactor = (double)s_Info.numer / (double)s_Info.denom; + else + { + error("mach_timebase_info(&Info) failed\n"); + exit(1); + } + if (s_Info.denom == 1 && s_Info.numer == 1) /* special case: absolute time is in nanoseconds */ + return mach_absolute_time(); + return mach_absolute_time() * s_rdFactor; +#else + struct timeval tv; + gettimeofday(&tv, NULL); + return (uint64_t)tv.tv_sec * UINT64_C(1000000000) + + (tv.tv_usec * UINT32_C(1000)); +#endif +} + + +char *formatNum(uint64_t uNum, unsigned cchWidth, char *pszDst, size_t cbDst) +{ + char szTmp[64 + 22]; +#ifdef _MSC_VER + size_t cchTmp = _snprintf(szTmp, sizeof(szTmp) - 22, "%I64u", uNum); +#else + size_t cchTmp = snprintf(szTmp, sizeof(szTmp) - 22, "%llu", (unsigned long long)uNum); +#endif + size_t cSeps = (cchTmp - 1) / 3; + size_t const cchTotal = cchTmp + cSeps; + if (cSeps) + { + szTmp[cchTotal] = '\0'; + for (size_t iSrc = cchTmp, iDst = cchTotal; cSeps > 0; cSeps--) + { + szTmp[--iDst] = szTmp[--iSrc]; + szTmp[--iDst] = szTmp[--iSrc]; + szTmp[--iDst] = szTmp[--iSrc]; + szTmp[--iDst] = ' '; + } + } + + size_t offDst = 0; + while (cchWidth-- > cchTotal && offDst < cbDst) + pszDst[offDst++] = ' '; + size_t offSrc = 0; + while (offSrc < cchTotal && offDst < cbDst) + pszDst[offDst++] = szTmp[offSrc++]; + pszDst[offDst] = '\0'; + return pszDst; +} + + +int reportResult(const char *pszInstruction, uint32_t cInstructions, uint64_t nsElapsed, uint32_t cExits) +{ + uint64_t const cInstrPerSec = nsElapsed ? (uint64_t)cInstructions * 1000000000 / nsElapsed : 0; + char szTmp1[64], szTmp2[64], szTmp3[64]; + printf("%s %7s instructions per second (%s exits in %s ns)\n", + formatNum(cInstrPerSec, 10, szTmp1, sizeof(szTmp1)), pszInstruction, + formatNum(cExits, 0, szTmp2, sizeof(szTmp2)), + formatNum(nsElapsed, 0, szTmp3, sizeof(szTmp3))); + return 0; +} + + + +#ifdef RT_OS_WINDOWS + +/* + * Windows - Hyper-V Platform API. + */ + +static int createVM(void) +{ + /* + * Resolve APIs. + */ + HMODULE hmod = LoadLibraryW(L"WinHvPlatform.dll"); + if (hmod == NULL) + return error("Error loading WinHvPlatform.dll: %u\n", GetLastError()); + static struct { const char *pszFunction; FARPROC *ppfn; } const s_aImports[] = + { +# define IMPORT_ENTRY(a_Name) { #a_Name, (FARPROC *)&g_pfn##a_Name } + IMPORT_ENTRY(WHvCreatePartition), + IMPORT_ENTRY(WHvSetupPartition), + IMPORT_ENTRY(WHvGetPartitionProperty), + IMPORT_ENTRY(WHvSetPartitionProperty), + IMPORT_ENTRY(WHvMapGpaRange), + IMPORT_ENTRY(WHvCreateVirtualProcessor), + IMPORT_ENTRY(WHvRunVirtualProcessor), + IMPORT_ENTRY(WHvGetVirtualProcessorRegisters), + IMPORT_ENTRY(WHvSetVirtualProcessorRegisters), +# undef IMPORT_ENTRY + }; + FARPROC pfn; + for (size_t i = 0; i < sizeof(s_aImports) / sizeof(s_aImports[0]); i++) + { + *s_aImports[i].ppfn = pfn = GetProcAddress(hmod, s_aImports[i].pszFunction); + if (!pfn) + return error("Error resolving WinHvPlatform.dll!%s: %u\n", s_aImports[i].pszFunction, GetLastError()); + } +# ifndef IN_SLICKEDIT +# define WHvCreatePartition g_pfnWHvCreatePartition +# define WHvSetupPartition g_pfnWHvSetupPartition +# define WHvGetPartitionProperty g_pfnWHvGetPartitionProperty +# define WHvSetPartitionProperty g_pfnWHvSetPartitionProperty +# define WHvMapGpaRange g_pfnWHvMapGpaRange +# define WHvCreateVirtualProcessor g_pfnWHvCreateVirtualProcessor +# define WHvRunVirtualProcessor g_pfnWHvRunVirtualProcessor +# define WHvGetVirtualProcessorRegisters g_pfnWHvGetVirtualProcessorRegisters +# define WHvSetVirtualProcessorRegisters g_pfnWHvSetVirtualProcessorRegisters +# endif + /* Need a precise time function. */ + *(FARPROC *)&g_pfnRtlGetSystemTimePrecise = pfn = GetProcAddress(GetModuleHandleW(L"ntdll.dll"), "RtlGetSystemTimePrecise"); + if (pfn == NULL) + return error("Error resolving ntdll.dll!RtlGetSystemTimePrecise: %u\n", GetLastError()); + + /* + * Create the partition with 1 CPU and the specfied amount of memory. + */ + WHV_PARTITION_HANDLE hPartition; + HRESULT hrc = WHvCreatePartition(&hPartition); + if (!SUCCEEDED(hrc)) + return error("WHvCreatePartition failed: %#x\n", hrc); + g_hPartition = hPartition; + + WHV_PARTITION_PROPERTY Property; + memset(&Property, 0, sizeof(Property)); + Property.ProcessorCount = 1; + hrc = WHvSetPartitionProperty(hPartition, WHvPartitionPropertyCodeProcessorCount, &Property, sizeof(Property)); + if (!SUCCEEDED(hrc)) + return error("WHvSetPartitionProperty/WHvPartitionPropertyCodeProcessorCount failed: %#x\n", hrc); + + memset(&Property, 0, sizeof(Property)); + Property.ExtendedVmExits.X64CpuidExit = 1; + Property.ExtendedVmExits.X64MsrExit = 1; + hrc = WHvSetPartitionProperty(hPartition, WHvPartitionPropertyCodeExtendedVmExits, &Property, sizeof(Property)); + if (!SUCCEEDED(hrc)) + return error("WHvSetPartitionProperty/WHvPartitionPropertyCodeExtendedVmExits failed: %#x\n", hrc); + + hrc = WHvSetupPartition(hPartition); + if (!SUCCEEDED(hrc)) + return error("WHvSetupPartition failed: %#x\n", hrc); + + hrc = WHvCreateVirtualProcessor(hPartition, 0 /*idVCpu*/, 0 /*fFlags*/); + if (!SUCCEEDED(hrc)) + return error("WHvCreateVirtualProcessor failed: %#x\n", hrc); + + g_pbMem = (unsigned char *)VirtualAlloc(NULL, g_cbMem, MEM_COMMIT, PAGE_READWRITE); + if (!g_pbMem) + return error("VirtualAlloc failed: %u\n", GetLastError()); + memset(g_pbMem, 0xcc, g_cbMem); + + hrc = WHvMapGpaRange(hPartition, g_pbMem, MY_MEM_BASE /*GCPhys*/, g_cbMem, + WHvMapGpaRangeFlagRead | WHvMapGpaRangeFlagWrite | WHvMapGpaRangeFlagExecute); + if (!SUCCEEDED(hrc)) + return error("WHvMapGpaRange failed: %#x\n", hrc); + + WHV_RUN_VP_EXIT_CONTEXT ExitInfo; + memset(&ExitInfo, 0, sizeof(ExitInfo)); + WHvRunVirtualProcessor(g_hPartition, 0 /*idCpu*/, &ExitInfo, sizeof(ExitInfo)); + + return 0; +} + + +static int runtimeError(const char *pszFormat, ...) +{ + fprintf(stderr, "runtime error: "); + va_list va; + va_start(va, pszFormat); + vfprintf(stderr, pszFormat, va); + va_end(va); + + static struct { const char *pszName; WHV_REGISTER_NAME enmName; unsigned uType; } const s_aRegs[] = + { + { "rip", WHvX64RegisterRip, 64 }, + { "cs", WHvX64RegisterCs, 1 }, + { "rflags", WHvX64RegisterRflags, 32 }, + { "rax", WHvX64RegisterRax, 64 }, + { "rcx", WHvX64RegisterRcx, 64 }, + { "rdx", WHvX64RegisterRdx, 64 }, + { "rbx", WHvX64RegisterRbx, 64 }, + { "rsp", WHvX64RegisterRsp, 64 }, + { "ss", WHvX64RegisterSs, 1 }, + { "rbp", WHvX64RegisterRbp, 64 }, + { "rsi", WHvX64RegisterRsi, 64 }, + { "rdi", WHvX64RegisterRdi, 64 }, + { "ds", WHvX64RegisterDs, 1 }, + { "es", WHvX64RegisterEs, 1 }, + { "fs", WHvX64RegisterFs, 1 }, + { "gs", WHvX64RegisterGs, 1 }, + { "cr0", WHvX64RegisterCr0, 64 }, + { "cr2", WHvX64RegisterCr2, 64 }, + { "cr3", WHvX64RegisterCr3, 64 }, + { "cr4", WHvX64RegisterCr4, 64 }, + }; + for (unsigned i = 0; i < sizeof(s_aRegs) / sizeof(s_aRegs[0]); i++) + { + WHV_REGISTER_VALUE Value; + WHV_REGISTER_NAME enmName = s_aRegs[i].enmName; + HRESULT hrc = WHvGetVirtualProcessorRegisters(g_hPartition, 0 /*idCpu*/, &enmName, 1, &Value); + if (SUCCEEDED(hrc)) + { + if (s_aRegs[i].uType == 32) + fprintf(stderr, "%8s=%08x\n", s_aRegs[i].pszName, Value.Reg32); + else if (s_aRegs[i].uType == 64) + fprintf(stderr, "%8s=%08x'%08x\n", s_aRegs[i].pszName, (unsigned)(Value.Reg64 >> 32), Value.Reg32); + else if (s_aRegs[i].uType == 1) + fprintf(stderr, "%8s=%04x base=%08x'%08x limit=%08x attr=%04x\n", s_aRegs[i].pszName, + Value.Segment.Selector, (unsigned)(Value.Segment.Base >> 32), (unsigned)Value.Segment.Base, + Value.Segment.Limit, Value.Segment.Attributes); + } + else + fprintf(stderr, "%8s=\n", s_aRegs[i].pszName, hrc); + } + + return 1; +} + + +static int runRealModeTest(unsigned cInstructions, const char *pszInstruction, unsigned fTest, + unsigned uEax, unsigned uEcx, unsigned uEdx, unsigned uEbx, + unsigned uEsp, unsigned uEbp, unsigned uEsi, unsigned uEdi) +{ + (void)fTest; + + /* + * Initialize the real mode context. + */ +# define ADD_REG64(a_enmName, a_uValue) do { \ + aenmNames[iReg] = (a_enmName); \ + aValues[iReg].Reg128.High64 = 0; \ + aValues[iReg].Reg64 = (a_uValue); \ + iReg++; \ + } while (0) +# define ADD_SEG(a_enmName, a_Base, a_Limit, a_Sel, a_fCode) \ + do { \ + aenmNames[iReg] = a_enmName; \ + aValues[iReg].Segment.Base = (a_Base); \ + aValues[iReg].Segment.Limit = (a_Limit); \ + aValues[iReg].Segment.Selector = (a_Sel); \ + aValues[iReg].Segment.Attributes = a_fCode ? 0x9b : 0x93; \ + iReg++; \ + } while (0) + WHV_REGISTER_NAME aenmNames[80]; + WHV_REGISTER_VALUE aValues[80]; + unsigned iReg = 0; + ADD_REG64(WHvX64RegisterRax, uEax); + ADD_REG64(WHvX64RegisterRcx, uEcx); + ADD_REG64(WHvX64RegisterRdx, uEdx); + ADD_REG64(WHvX64RegisterRbx, uEbx); + ADD_REG64(WHvX64RegisterRsp, uEsp); + ADD_REG64(WHvX64RegisterRbp, uEbp); + ADD_REG64(WHvX64RegisterRsi, uEsi); + ADD_REG64(WHvX64RegisterRdi, uEdi); + ADD_REG64(WHvX64RegisterRip, MY_TEST_RIP); + ADD_REG64(WHvX64RegisterRflags, 2); + ADD_SEG(WHvX64RegisterEs, 0x00000, 0xffff, 0x0000, 0); + ADD_SEG(WHvX64RegisterCs, 0x00000, 0xffff, 0x0000, 1); + ADD_SEG(WHvX64RegisterSs, 0x00000, 0xffff, 0x0000, 0); + ADD_SEG(WHvX64RegisterDs, 0x00000, 0xffff, 0x0000, 0); + ADD_SEG(WHvX64RegisterFs, 0x00000, 0xffff, 0x0000, 0); + ADD_SEG(WHvX64RegisterGs, 0x00000, 0xffff, 0x0000, 0); + ADD_REG64(WHvX64RegisterCr0, 0x10010 /*WP+ET*/); + ADD_REG64(WHvX64RegisterCr2, 0); + ADD_REG64(WHvX64RegisterCr3, 0); + ADD_REG64(WHvX64RegisterCr4, 0); + HRESULT hrc = WHvSetVirtualProcessorRegisters(g_hPartition, 0 /*idCpu*/, aenmNames, iReg, aValues); + if (!SUCCEEDED(hrc)) + return error("WHvSetVirtualProcessorRegisters failed (for %s): %#x\n", pszInstruction, hrc); +# undef ADD_REG64 +# undef ADD_SEG + + /* + * Run the test. + */ + uint32_t cExits = 0; + uint64_t const nsStart = getNanoTS(); + for (;;) + { + WHV_RUN_VP_EXIT_CONTEXT ExitInfo; + memset(&ExitInfo, 0, sizeof(ExitInfo)); + hrc = WHvRunVirtualProcessor(g_hPartition, 0 /*idCpu*/, &ExitInfo, sizeof(ExitInfo)); + if (SUCCEEDED(hrc)) + { + cExits++; + if (ExitInfo.ExitReason == WHvRunVpExitReasonX64IoPortAccess) + { + if (ExitInfo.IoPortAccess.PortNumber == MY_NOP_PORT) + { /* likely: nop instruction */ } + else if (ExitInfo.IoPortAccess.PortNumber == MY_TERM_PORT) + break; + else + return runtimeError("Unexpected I/O port access (for %s): %#x\n", pszInstruction, ExitInfo.IoPortAccess.PortNumber); + + /* Advance. */ + if (ExitInfo.VpContext.InstructionLength) + { + aenmNames[0] = WHvX64RegisterRip; + aValues[0].Reg64 = ExitInfo.VpContext.Rip + ExitInfo.VpContext.InstructionLength; + hrc = WHvSetVirtualProcessorRegisters(g_hPartition, 0 /*idCpu*/, aenmNames, 1, aValues); + if (SUCCEEDED(hrc)) + { /* likely */ } + else + return runtimeError("Error advancing RIP (for %s): %#x\n", pszInstruction, hrc); + } + else + return runtimeError("VpContext.InstructionLength is zero (for %s)\n", pszInstruction); + } + else if (ExitInfo.ExitReason == WHvRunVpExitReasonX64Cpuid) + { + /* Advance RIP and set default results. */ + if (ExitInfo.VpContext.InstructionLength) + { + aenmNames[0] = WHvX64RegisterRip; + aValues[0].Reg64 = ExitInfo.VpContext.Rip + ExitInfo.VpContext.InstructionLength; + aenmNames[1] = WHvX64RegisterRax; + aValues[1].Reg64 = ExitInfo.CpuidAccess.DefaultResultRax; + aenmNames[2] = WHvX64RegisterRcx; + aValues[2].Reg64 = ExitInfo.CpuidAccess.DefaultResultRcx; + aenmNames[3] = WHvX64RegisterRdx; + aValues[3].Reg64 = ExitInfo.CpuidAccess.DefaultResultRdx; + aenmNames[4] = WHvX64RegisterRbx; + aValues[4].Reg64 = ExitInfo.CpuidAccess.DefaultResultRbx; + hrc = WHvSetVirtualProcessorRegisters(g_hPartition, 0 /*idCpu*/, aenmNames, 5, aValues); + if (SUCCEEDED(hrc)) + { /* likely */ } + else + return runtimeError("Error advancing RIP (for %s): %#x\n", pszInstruction, hrc); + } + else + return runtimeError("VpContext.InstructionLength is zero (for %s)\n", pszInstruction); + } + else if (ExitInfo.ExitReason == WHvRunVpExitReasonMemoryAccess) + { + if (ExitInfo.MemoryAccess.Gpa == MY_NOP_MMIO) + { /* likely: nop address */ } + else + return runtimeError("Unexpected memory access (for %s): %#x\n", pszInstruction, ExitInfo.MemoryAccess.Gpa); + + /* Advance and set return register (assuming RAX and two byte instruction). */ + aenmNames[0] = WHvX64RegisterRip; + if (ExitInfo.VpContext.InstructionLength) + aValues[0].Reg64 = ExitInfo.VpContext.Rip + ExitInfo.VpContext.InstructionLength; + else + aValues[0].Reg64 = ExitInfo.VpContext.Rip + 2; + aenmNames[1] = WHvX64RegisterRax; + aValues[1].Reg64 = 42; + hrc = WHvSetVirtualProcessorRegisters(g_hPartition, 0 /*idCpu*/, aenmNames, 2, aValues); + if (SUCCEEDED(hrc)) + { /* likely */ } + else + return runtimeError("Error advancing RIP (for %s): %#x\n", pszInstruction, hrc); + } + else + return runtimeError("Unexpected exit (for %s): %#x\n", pszInstruction, ExitInfo.ExitReason); + } + else + return runtimeError("WHvRunVirtualProcessor failed (for %s): %#x\n", pszInstruction, hrc); + } + uint64_t const nsElapsed = getNanoTS() - nsStart; + return reportResult(pszInstruction, cInstructions, nsElapsed, cExits); +} + + + +#elif defined(RT_OS_LINUX) + +/* + * GNU/linux - KVM + */ + +static int createVM(void) +{ + int fd = open("/dev/kvm", O_RDWR); + if (fd < 0) + return error("Error opening /dev/kvm: %d\n", errno); + + g_fdVm = ioctl(fd, KVM_CREATE_VM, (uintptr_t)0); + if (g_fdVm < 0) + return error("KVM_CREATE_VM failed: %d\n", errno); + + /* Create the VCpu. */ + g_cbVCpuRun = ioctl(fd, KVM_GET_VCPU_MMAP_SIZE, (uintptr_t)0); + if (g_cbVCpuRun <= 0x1000 || (g_cbVCpuRun & 0xfff)) + return error("Failed to get KVM_GET_VCPU_MMAP_SIZE: %#xz errno=%d\n", g_cbVCpuRun, errno); + + g_fdVCpu = ioctl(g_fdVm, KVM_CREATE_VCPU, (uintptr_t)0); + if (g_fdVCpu < 0) + return error("KVM_CREATE_VCPU failed: %d\n", errno); + + g_pVCpuRun = (struct kvm_run *)mmap(NULL, g_cbVCpuRun, PROT_READ | PROT_WRITE, MAP_PRIVATE, g_fdVCpu, 0); + if ((void *)g_pVCpuRun == MAP_FAILED) + return error("mmap kvm_run failed: %d\n", errno); + + /* Memory. */ + g_pbMem = (unsigned char *)mmap(NULL, g_cbMem, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + if ((void *)g_pbMem == MAP_FAILED) + return error("mmap RAM failed: %d\n", errno); + + struct kvm_userspace_memory_region MemReg; + MemReg.slot = 0; + MemReg.flags = 0; + MemReg.guest_phys_addr = MY_MEM_BASE; + MemReg.memory_size = g_cbMem; + MemReg.userspace_addr = (uintptr_t)g_pbMem; + int rc = ioctl(g_fdVm, KVM_SET_USER_MEMORY_REGION, &MemReg); + if (rc != 0) + return error("KVM_SET_USER_MEMORY_REGION failed: %d (%d)\n", errno, rc); + + close(fd); + return 0; +} + + +static void printSReg(const char *pszName, struct kvm_segment const *pSReg) +{ + fprintf(stderr, " %5s=%04x base=%016llx limit=%08x type=%#x p=%d dpl=%d db=%d s=%d l=%d g=%d avl=%d un=%d\n", + pszName, pSReg->selector, pSReg->base, pSReg->limit, pSReg->type, pSReg->present, pSReg->dpl, + pSReg->db, pSReg->s, pSReg->l, pSReg->g, pSReg->avl, pSReg->unusable); +} + + +static int runtimeError(const char *pszFormat, ...) +{ + fprintf(stderr, "runtime error: "); + va_list va; + va_start(va, pszFormat); + vfprintf(stderr, pszFormat, va); + va_end(va); + + fprintf(stderr, " exit_reason=%#010x\n", g_pVCpuRun->exit_reason); + fprintf(stderr, "ready_for_interrupt_injection=%#x\n", g_pVCpuRun->ready_for_interrupt_injection); + fprintf(stderr, " if_flag=%#x\n", g_pVCpuRun->if_flag); + fprintf(stderr, " flags=%#x\n", g_pVCpuRun->flags); + fprintf(stderr, " kvm_valid_regs=%#018llx\n", g_pVCpuRun->kvm_valid_regs); + fprintf(stderr, " kvm_dirty_regs=%#018llx\n", g_pVCpuRun->kvm_dirty_regs); + + struct kvm_regs Regs; + memset(&Regs, 0, sizeof(Regs)); + struct kvm_sregs SRegs; + memset(&SRegs, 0, sizeof(SRegs)); + if ( ioctl(g_fdVCpu, KVM_GET_REGS, &Regs) != -1 + && ioctl(g_fdVCpu, KVM_GET_SREGS, &SRegs) != -1) + { + fprintf(stderr, " rip=%016llx\n", Regs.rip); + printSReg("cs", &SRegs.cs); + fprintf(stderr, " rflags=%08llx\n", Regs.rflags); + fprintf(stderr, " rax=%016llx\n", Regs.rax); + fprintf(stderr, " rbx=%016llx\n", Regs.rcx); + fprintf(stderr, " rdx=%016llx\n", Regs.rdx); + fprintf(stderr, " rcx=%016llx\n", Regs.rbx); + fprintf(stderr, " rsp=%016llx\n", Regs.rsp); + fprintf(stderr, " rbp=%016llx\n", Regs.rbp); + fprintf(stderr, " rsi=%016llx\n", Regs.rsi); + fprintf(stderr, " rdi=%016llx\n", Regs.rdi); + printSReg("ss", &SRegs.ss); + printSReg("ds", &SRegs.ds); + printSReg("es", &SRegs.es); + printSReg("fs", &SRegs.fs); + printSReg("gs", &SRegs.gs); + printSReg("tr", &SRegs.tr); + printSReg("ldtr", &SRegs.ldt); + + uint64_t const offMem = Regs.rip + SRegs.cs.base - MY_MEM_BASE; + if (offMem < g_cbMem - 10) + fprintf(stderr, " bytes at PC (%#zx): %02x %02x %02x %02x %02x %02x %02x %02x\n", (size_t)(offMem + MY_MEM_BASE), + g_pbMem[offMem ], g_pbMem[offMem + 1], g_pbMem[offMem + 2], g_pbMem[offMem + 3], + g_pbMem[offMem + 4], g_pbMem[offMem + 5], g_pbMem[offMem + 6], g_pbMem[offMem + 7]); + } + + return 1; +} + +static int runRealModeTest(unsigned cInstructions, const char *pszInstruction, unsigned fTest, + unsigned uEax, unsigned uEcx, unsigned uEdx, unsigned uEbx, + unsigned uEsp, unsigned uEbp, unsigned uEsi, unsigned uEdi) +{ + (void)fTest; + + /* + * Setup real mode context. + */ +#define SET_SEG(a_SReg, a_Base, a_Limit, a_Sel, a_fCode) \ + do { \ + a_SReg.base = (a_Base); \ + a_SReg.limit = (a_Limit); \ + a_SReg.selector = (a_Sel); \ + a_SReg.type = (a_fCode) ? 10 : 3; \ + a_SReg.present = 1; \ + a_SReg.dpl = 0; \ + a_SReg.db = 0; \ + a_SReg.s = 1; \ + a_SReg.l = 0; \ + a_SReg.g = 0; \ + a_SReg.avl = 0; \ + a_SReg.unusable = 0; \ + a_SReg.padding = 0; \ + } while (0) + struct kvm_regs Regs; + memset(&Regs, 0, sizeof(Regs)); + Regs.rax = uEax; + Regs.rcx = uEcx; + Regs.rdx = uEdx; + Regs.rbx = uEbx; + Regs.rsp = uEsp; + Regs.rbp = uEbp; + Regs.rsi = uEsi; + Regs.rdi = uEdi; + Regs.rip = MY_TEST_RIP; + Regs.rflags = 2; + int rc = ioctl(g_fdVCpu, KVM_SET_REGS, &Regs); + if (rc != 0) + return error("KVM_SET_REGS failed: %d (rc=%d)\n", errno, rc); + + struct kvm_sregs SRegs; + memset(&SRegs, 0, sizeof(SRegs)); + rc = ioctl(g_fdVCpu, KVM_GET_SREGS, &SRegs); + if (rc != 0) + return error("KVM_GET_SREGS failed: %d (rc=%d)\n", errno, rc); + SET_SEG(SRegs.es, 0x00000, 0xffff, 0x0000, 0); + SET_SEG(SRegs.cs, 0x00000, 0xffff, 0x0000, 1); + SET_SEG(SRegs.ss, 0x00000, 0xffff, 0x0000, 0); + SET_SEG(SRegs.ds, 0x00000, 0xffff, 0x0000, 0); + SET_SEG(SRegs.fs, 0x00000, 0xffff, 0x0000, 0); + SET_SEG(SRegs.gs, 0x00000, 0xffff, 0x0000, 0); + //SRegs.cr0 = 0x10010 /*WP+ET*/; + SRegs.cr2 = 0; + //SRegs.cr3 = 0; + //SRegs.cr4 = 0; + rc = ioctl(g_fdVCpu, KVM_SET_SREGS, &SRegs); + if (rc != 0) + return error("KVM_SET_SREGS failed: %d (rc=%d)\n", errno, rc); + + /* + * Run the test. + */ + uint32_t cExits = 0; + uint64_t const nsStart = getNanoTS(); + for (;;) + { + rc = ioctl(g_fdVCpu, KVM_RUN, (uintptr_t)0); + if (rc == 0) + { + cExits++; + if (g_pVCpuRun->exit_reason == KVM_EXIT_IO) + { + if (g_pVCpuRun->io.port == MY_NOP_PORT) + { /* likely: nop instruction */ } + else if (g_pVCpuRun->io.port == MY_TERM_PORT) + break; + else + return runtimeError("Unexpected I/O port access (for %s): %#x\n", pszInstruction, g_pVCpuRun->io.port); + } + else if (g_pVCpuRun->exit_reason == KVM_EXIT_MMIO) + { + if (g_pVCpuRun->mmio.phys_addr == MY_NOP_MMIO) + { /* likely: nop address */ } + else + return runtimeError("Unexpected memory access (for %s): %#llx\n", pszInstruction, g_pVCpuRun->mmio.phys_addr); + } + else + return runtimeError("Unexpected exit (for %s): %d\n", pszInstruction, g_pVCpuRun->exit_reason); + } + else + return runtimeError("KVM_RUN failed (for %s): %#x (ret %d)\n", pszInstruction, errno, rc); + } + uint64_t const nsElapsed = getNanoTS() - nsStart; + return reportResult(pszInstruction, cInstructions, nsElapsed, cExits); +} + + +#elif defined(RT_OS_DARWIN) + +/* + * Mac OS X - Hypervisor API. + */ + +static int createVM(void) +{ + /* VM and VCpu */ + hv_return_t rcHv = hv_vm_create(HV_VM_DEFAULT); + if (rcHv != HV_SUCCESS) + return error("hv_vm_create failed: %#x\n", rcHv); + + g_idVCpu = -1; + rcHv = hv_vcpu_create(&g_idVCpu, HV_VCPU_DEFAULT); + if (rcHv != HV_SUCCESS) + return error("hv_vcpu_create failed: %#x\n", rcHv); + + /* Memory. */ + g_pbMem = (unsigned char *)mmap(NULL, g_cbMem, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANON, -1, 0); + if ((void *)g_pbMem == MAP_FAILED) + return error("mmap RAM failed: %d\n", errno); + memset(g_pbMem, 0xf4, g_cbMem); + + rcHv = hv_vm_map(g_pbMem, MY_MEM_BASE, g_cbMem, HV_MEMORY_READ | HV_MEMORY_WRITE | HV_MEMORY_EXEC); + if (rcHv != HV_SUCCESS) + return error("hv_vm_map failed: %#x\n", rcHv); + + rcHv = hv_vm_protect(0x2000, 0x1000, HV_MEMORY_READ | HV_MEMORY_WRITE | HV_MEMORY_EXEC); + if (rcHv != HV_SUCCESS) + return error("hv_vm_protect failed: %#x\n", rcHv); + return 0; +} + + +static int runtimeError(const char *pszFormat, ...) +{ + fprintf(stderr, "runtime error: "); + va_list va; + va_start(va, pszFormat); + vfprintf(stderr, pszFormat, va); + va_end(va); + + static struct { const char *pszName; uint32_t uField; uint32_t uFmt : 31; uint32_t fIsReg : 1; } const s_aFields[] = + { + { "VMCS_RO_EXIT_REASON", VMCS_RO_EXIT_REASON, 64, 0 }, + { "VMCS_RO_EXIT_QUALIFIC", VMCS_RO_EXIT_QUALIFIC, 64, 0 }, + { "VMCS_RO_INSTR_ERROR", VMCS_RO_INSTR_ERROR, 64, 0 }, + { "VMCS_RO_VMEXIT_IRQ_INFO", VMCS_RO_VMEXIT_IRQ_INFO, 64, 0 }, + { "VMCS_RO_VMEXIT_IRQ_ERROR", VMCS_RO_VMEXIT_IRQ_ERROR, 64, 0 }, + { "VMCS_RO_VMEXIT_INSTR_LEN", VMCS_RO_VMEXIT_INSTR_LEN, 64, 0 }, + { "VMCS_RO_VMX_INSTR_INFO", VMCS_RO_VMX_INSTR_INFO, 64, 0 }, + { "VMCS_RO_GUEST_LIN_ADDR", VMCS_RO_GUEST_LIN_ADDR, 64, 0 }, + { "VMCS_GUEST_PHYSICAL_ADDRESS",VMCS_GUEST_PHYSICAL_ADDRESS,64, 0 }, + { "VMCS_RO_IO_RCX", VMCS_RO_IO_RCX, 64, 0 }, + { "VMCS_RO_IO_RSI", VMCS_RO_IO_RSI, 64, 0 }, + { "VMCS_RO_IO_RDI", VMCS_RO_IO_RDI, 64, 0 }, + { "VMCS_RO_IO_RIP", VMCS_RO_IO_RIP, 64, 0 }, + { "rip", HV_X86_RIP, 64, 1 }, + { "rip (vmcs)", VMCS_GUEST_RIP, 64, 0 }, + { "cs", HV_X86_CS, 16, 1 }, + { "cs (vmcs)", VMCS_GUEST_CS, 16, 0 }, + { "cs.base", VMCS_GUEST_CS_BASE, 64, 0 }, + { "cs.limit", VMCS_GUEST_CS_LIMIT, 32, 0 }, + { "cs.attr", VMCS_GUEST_CS_AR, 32, 0 }, + { "rflags", HV_X86_RFLAGS, 32, 1 }, + { "rax", HV_X86_RAX, 64, 1 }, + { "rcx", HV_X86_RCX, 64, 1 }, + { "rdx", HV_X86_RDX, 64, 1 }, + { "rbx", HV_X86_RBX, 64, 1 }, + { "rsp", HV_X86_RSP, 64, 1 }, + { "rsp (vmcs)", VMCS_GUEST_RSP, 64, 0 }, + { "ss", HV_X86_SS, 16, 1 }, + { "ss (vmcs)", VMCS_GUEST_SS, 16, 0 }, + { "ss.base", VMCS_GUEST_SS_BASE, 64, 0 }, + { "ss.limit", VMCS_GUEST_SS_LIMIT, 32, 0 }, + { "ss.attr", VMCS_GUEST_SS_AR, 32, 0 }, + { "rbp", HV_X86_RBP, 64, 1 }, + { "rsi", HV_X86_RSI, 64, 1 }, + { "rdi", HV_X86_RDI, 64, 1 }, + { "ds", HV_X86_DS, 16, 1 }, + { "ds (vmcs)", VMCS_GUEST_DS, 16, 0 }, + { "ds.base", VMCS_GUEST_DS_BASE, 64, 0 }, + { "ds.limit", VMCS_GUEST_DS_LIMIT, 32, 0 }, + { "ds.attr", VMCS_GUEST_DS_AR, 32, 0 }, + { "es", HV_X86_ES, 16, 1 }, + { "es (vmcs)", VMCS_GUEST_ES, 16, 0 }, + { "es.base", VMCS_GUEST_ES_BASE, 64, 0 }, + { "es.limit", VMCS_GUEST_ES_LIMIT, 32, 0 }, + { "es.attr", VMCS_GUEST_ES_AR, 32, 0 }, + { "fs", HV_X86_FS, 16, 1 }, + { "fs (vmcs)", VMCS_GUEST_FS, 16, 0 }, + { "fs.base", VMCS_GUEST_FS_BASE, 64, 0 }, + { "fs.limit", VMCS_GUEST_FS_LIMIT, 32, 0 }, + { "fs.attr", VMCS_GUEST_FS_AR, 32, 0 }, + { "gs", HV_X86_GS, 16, 1 }, + { "gs (vmcs)", VMCS_GUEST_GS, 16, 0 }, + { "gs.base", VMCS_GUEST_GS_BASE, 64, 0 }, + { "gs.limit", VMCS_GUEST_GS_LIMIT, 32, 0 }, + { "gs.attr", VMCS_GUEST_GS_AR, 32, 0 }, + { "cr0", HV_X86_CR0, 64, 1 }, + { "cr0 (vmcs)", VMCS_GUEST_CR0, 64, 0 }, + { "cr2", HV_X86_CR2, 64, 1 }, + { "cr3", HV_X86_CR3, 64, 1 }, + { "cr3 (vmcs)", VMCS_GUEST_CR3, 64, 0 }, + { "cr4", HV_X86_CR4, 64, 1 }, + { "cr4 (vmcs)", VMCS_GUEST_CR4, 64, 0 }, + { "idtr.base", VMCS_GUEST_IDTR_BASE, 64, 0 }, + { "idtr.limit", VMCS_GUEST_IDTR_LIMIT, 32, 0 }, + { "gdtr.base", VMCS_GUEST_GDTR_BASE, 64, 0 }, + { "gdtr.limit", VMCS_GUEST_GDTR_LIMIT, 32, 0 }, + + { "VMCS_CTRL_PIN_BASED", VMCS_CTRL_PIN_BASED, 64, 0 }, + { "VMCS_CTRL_CPU_BASED", VMCS_CTRL_CPU_BASED, 64, 0 }, + { "VMCS_CTRL_CPU_BASED2", VMCS_CTRL_CPU_BASED2, 64, 0 }, + { "VMCS_CTRL_VMENTRY_CONTROLS", VMCS_CTRL_VMENTRY_CONTROLS, 64, 0 }, + { "VMCS_CTRL_VMEXIT_CONTROLS", VMCS_CTRL_VMEXIT_CONTROLS, 64, 0 }, + { "VMCS_CTRL_EXC_BITMAP", VMCS_CTRL_EXC_BITMAP, 64, 0 }, + { "VMCS_CTRL_CR0_MASK", VMCS_CTRL_CR0_MASK, 64, 0 }, + { "VMCS_CTRL_CR0_SHADOW", VMCS_CTRL_CR0_SHADOW, 64, 0 }, + { "VMCS_CTRL_CR4_MASK", VMCS_CTRL_CR4_MASK, 64, 0 }, + { "VMCS_CTRL_CR4_SHADOW", VMCS_CTRL_CR4_SHADOW, 64, 0 }, + }; + for (unsigned i = 0; i < sizeof(s_aFields) / sizeof(s_aFields[0]); i++) + { + uint64_t uValue = UINT64_MAX; + hv_return_t rcHv; + if (s_aFields[i].fIsReg) + rcHv = hv_vcpu_read_register(g_idVCpu, (hv_x86_reg_t)s_aFields[i].uField, &uValue); + else + rcHv = hv_vmx_vcpu_read_vmcs(g_idVCpu, s_aFields[i].uField, &uValue); + if (rcHv == HV_SUCCESS) + { + if (s_aFields[i].uFmt == 16) + fprintf(stderr, "%28s=%04llx\n", s_aFields[i].pszName, uValue); + else if (s_aFields[i].uFmt == 32) + fprintf(stderr, "%28s=%08llx\n", s_aFields[i].pszName, uValue); + else + fprintf(stderr, "%28s=%08x'%08x\n", s_aFields[i].pszName, (uint32_t)(uValue >> 32), (uint32_t)uValue); + } + else + fprintf(stderr, "%28s=<%s failed %#x>\n", s_aFields[i].pszName, + s_aFields[i].fIsReg ? "hv_vcpu_read_register" : "hv_vmx_vcpu_read_vmcs", rcHv); + } + return 1; +} + + +static int runRealModeTest(unsigned cInstructions, const char *pszInstruction, unsigned fTest, + unsigned uEax, unsigned uEcx, unsigned uEdx, unsigned uEbx, + unsigned uEsp, unsigned uEbp, unsigned uEsi, unsigned uEdi) +{ + /* + * Setup real mode context. + */ +#define WRITE_REG_RET(a_enmReg, a_uValue) \ + do { \ + hv_return_t rcHvX = hv_vcpu_write_register(g_idVCpu, a_enmReg, a_uValue); \ + if (rcHvX == HV_SUCCESS) { /* likely */ } \ + else return error("hv_vcpu_write_register(%#x, %s, %#llx) -> %#x\n", g_idVCpu, #a_enmReg, (uint64_t)(a_uValue), rcHvX); \ + } while (0) +#define READ_REG_RET(a_enmReg, a_puValue) \ + do { \ + hv_return_t rcHvX = hv_vcpu_read_register(g_idVCpu, a_enmReg, a_puValue); \ + if (rcHvX == HV_SUCCESS) { /* likely */ } \ + else return error("hv_vcpu_read_register(%#x, %s,) -> %#x\n", g_idVCpu, #a_enmReg, rcHvX); \ + } while (0) +#define WRITE_VMCS_RET(a_enmField, a_uValue) \ + do { \ + hv_return_t rcHvX = hv_vmx_vcpu_write_vmcs(g_idVCpu, a_enmField, a_uValue); \ + if (rcHvX == HV_SUCCESS) { /* likely */ } \ + else return error("hv_vmx_vcpu_write_vmcs(%#x, %s, %#llx) -> %#x\n", g_idVCpu, #a_enmField, (uint64_t)(a_uValue), rcHvX); \ + } while (0) +#define READ_VMCS_RET(a_enmField, a_puValue) \ + do { \ + hv_return_t rcHvX = hv_vmx_vcpu_read_vmcs(g_idVCpu, a_enmField, a_puValue); \ + if (rcHvX == HV_SUCCESS) { /* likely */ } \ + else return error("hv_vmx_vcpu_read_vmcs(%#x, %s,) -> %#x\n", g_idVCpu, #a_enmField, rcHvX); \ + } while (0) +#define READ_CAP_RET(a_enmCap, a_puValue) \ + do { \ + hv_return_t rcHvX = hv_vmx_read_capability(a_enmCap, a_puValue); \ + if (rcHvX == HV_SUCCESS) { /* likely */ } \ + else return error("hv_vmx_read_capability(%s) -> %#x\n", #a_enmCap); \ + } while (0) +#define CAP_2_CTRL(a_uCap, a_fWanted) ( ((a_fWanted) | (uint32_t)(a_uCap)) & (uint32_t)((a_uCap) >> 32) ) +#if 1 + uint64_t uCap; + READ_CAP_RET(HV_VMX_CAP_PINBASED, &uCap); + WRITE_VMCS_RET(VMCS_CTRL_PIN_BASED, CAP_2_CTRL(uCap, PIN_BASED_INTR | PIN_BASED_NMI | PIN_BASED_VIRTUAL_NMI)); + READ_CAP_RET(HV_VMX_CAP_PROCBASED, &uCap); + WRITE_VMCS_RET(VMCS_CTRL_CPU_BASED, CAP_2_CTRL(uCap, CPU_BASED_HLT + | CPU_BASED_INVLPG + | CPU_BASED_MWAIT + | CPU_BASED_RDPMC + | CPU_BASED_RDTSC + | CPU_BASED_CR3_LOAD + | CPU_BASED_CR3_STORE + | CPU_BASED_CR8_LOAD + | CPU_BASED_CR8_STORE + | CPU_BASED_MOV_DR + | CPU_BASED_UNCOND_IO + | CPU_BASED_MONITOR + | CPU_BASED_PAUSE + )); + READ_CAP_RET(HV_VMX_CAP_PROCBASED2, &uCap); + WRITE_VMCS_RET(VMCS_CTRL_CPU_BASED2, CAP_2_CTRL(uCap, 0)); + READ_CAP_RET(HV_VMX_CAP_ENTRY, &uCap); + WRITE_VMCS_RET(VMCS_CTRL_VMENTRY_CONTROLS, CAP_2_CTRL(uCap, 0)); +#endif + WRITE_VMCS_RET(VMCS_CTRL_EXC_BITMAP, UINT32_MAX); + WRITE_VMCS_RET(VMCS_CTRL_CR0_MASK, 0x60000000); + WRITE_VMCS_RET(VMCS_CTRL_CR0_SHADOW, 0x00000000); + WRITE_VMCS_RET(VMCS_CTRL_CR4_MASK, 0x00000000); + WRITE_VMCS_RET(VMCS_CTRL_CR4_SHADOW, 0x00000000); + + WRITE_REG_RET(HV_X86_RAX, uEax); + WRITE_REG_RET(HV_X86_RCX, uEcx); + WRITE_REG_RET(HV_X86_RDX, uEdx); + WRITE_REG_RET(HV_X86_RBX, uEbx); + WRITE_REG_RET(HV_X86_RSP, uEsp); + WRITE_REG_RET(HV_X86_RBP, uEbp); + WRITE_REG_RET(HV_X86_RSI, uEsi); + WRITE_REG_RET(HV_X86_RDI, uEdi); + WRITE_REG_RET(HV_X86_RIP, MY_TEST_RIP); + WRITE_REG_RET(HV_X86_RFLAGS, 2); + WRITE_REG_RET(HV_X86_ES, 0x0000); + WRITE_VMCS_RET(VMCS_GUEST_ES_BASE, 0x0000000); + WRITE_VMCS_RET(VMCS_GUEST_ES_LIMIT, 0xffff); + WRITE_VMCS_RET(VMCS_GUEST_ES_AR, 0x93); + WRITE_REG_RET(HV_X86_CS, 0x0000); + WRITE_VMCS_RET(VMCS_GUEST_CS_BASE, 0x0000000); + WRITE_VMCS_RET(VMCS_GUEST_CS_LIMIT, 0xffff); + WRITE_VMCS_RET(VMCS_GUEST_CS_AR, 0x9b); + WRITE_REG_RET(HV_X86_SS, 0x0000); + WRITE_VMCS_RET(VMCS_GUEST_SS_BASE, 0x0000000); + WRITE_VMCS_RET(VMCS_GUEST_SS_LIMIT, 0xffff); + WRITE_VMCS_RET(VMCS_GUEST_SS_AR, 0x93); + WRITE_REG_RET(HV_X86_DS, 0x0000); + WRITE_VMCS_RET(VMCS_GUEST_DS_BASE, 0x0000000); + WRITE_VMCS_RET(VMCS_GUEST_DS_LIMIT, 0xffff); + WRITE_VMCS_RET(VMCS_GUEST_DS_AR, 0x93); + WRITE_REG_RET(HV_X86_FS, 0x0000); + WRITE_VMCS_RET(VMCS_GUEST_FS_BASE, 0x0000000); + WRITE_VMCS_RET(VMCS_GUEST_FS_LIMIT, 0xffff); + WRITE_VMCS_RET(VMCS_GUEST_FS_AR, 0x93); + WRITE_REG_RET(HV_X86_GS, 0x0000); + WRITE_VMCS_RET(VMCS_GUEST_GS_BASE, 0x0000000); + WRITE_VMCS_RET(VMCS_GUEST_GS_LIMIT, 0xffff); + WRITE_VMCS_RET(VMCS_GUEST_GS_AR, 0x93); + //WRITE_REG_RET(HV_X86_CR0, 0x10030 /*WP+NE+ET*/); + WRITE_VMCS_RET(VMCS_GUEST_CR0, 0x10030 /*WP+NE+ET*/); + //WRITE_REG_RET(HV_X86_CR2, 0); + //WRITE_REG_RET(HV_X86_CR3, 0); + WRITE_VMCS_RET(VMCS_GUEST_CR3, 0); + //WRITE_REG_RET(HV_X86_CR4, 0x2000); + WRITE_VMCS_RET(VMCS_GUEST_CR4, 0x2000); + WRITE_VMCS_RET(VMCS_GUEST_LDTR, 0x0000); + WRITE_VMCS_RET(VMCS_GUEST_LDTR_BASE, 0x00000000); + WRITE_VMCS_RET(VMCS_GUEST_LDTR_LIMIT, 0x0000); + WRITE_VMCS_RET(VMCS_GUEST_LDTR_AR, 0x10000); + WRITE_VMCS_RET(VMCS_GUEST_TR, 0x0000); + WRITE_VMCS_RET(VMCS_GUEST_TR_BASE, 0x00000000); + WRITE_VMCS_RET(VMCS_GUEST_TR_LIMIT, 0x0000); + WRITE_VMCS_RET(VMCS_GUEST_TR_AR, 0x00083); + hv_vcpu_flush(g_idVCpu); + hv_vcpu_invalidate_tlb(g_idVCpu); + + /* + * Run the test. + */ + uint32_t cExits = 0; + uint64_t const nsStart = getNanoTS(); + for (;;) + { + hv_return_t rcHv = hv_vcpu_run(g_idVCpu); + if (rcHv == HV_SUCCESS) + { + cExits++; + uint64_t uExitReason = UINT64_MAX; + READ_VMCS_RET(VMCS_RO_EXIT_REASON, &uExitReason); + if (!(uExitReason & UINT64_C(0x80000000))) + { + if (uExitReason == VMX_REASON_IO) + { + uint64_t uIoQual = UINT64_MAX; + READ_VMCS_RET(VMCS_RO_EXIT_QUALIFIC, &uIoQual); + if ((uint16_t)(uIoQual >> 16) == MY_NOP_PORT && (fTest & MY_TEST_F_NOP_IO)) + { /* likely: nop instruction */ } + else if ((uint16_t)(uIoQual >> 16) == MY_TERM_PORT) + break; + else + return runtimeError("Unexpected I/O port access (for %s): %#x\n", pszInstruction, (uint16_t)(uIoQual >> 16)); + + /* Advance RIP. */ + uint64_t cbInstr = UINT64_MAX; + READ_VMCS_RET(VMCS_RO_VMEXIT_INSTR_LEN, &cbInstr); + if (cbInstr < 1 || cbInstr > 15) + return runtimeError("Bad instr len: %#llx\n", cbInstr); + uint64_t uRip = UINT64_MAX; + READ_REG_RET(HV_X86_RIP, &uRip); + WRITE_REG_RET(HV_X86_RIP, uRip + cbInstr); + } + else if (uExitReason == VMX_REASON_CPUID && (fTest & MY_TEST_F_CPUID)) + { + /* Set registers and advance RIP. */ + WRITE_REG_RET(HV_X86_RAX, 0x42424242); + WRITE_REG_RET(HV_X86_RCX, 0x04242424); + WRITE_REG_RET(HV_X86_RDX, 0x00424242); + WRITE_REG_RET(HV_X86_RBX, 0x00024242); + + uint64_t cbInstr = UINT64_MAX; + READ_VMCS_RET(VMCS_RO_VMEXIT_INSTR_LEN, &cbInstr); + if (cbInstr < 1 || cbInstr > 15) + return runtimeError("Bad instr len: %#llx\n", cbInstr); + uint64_t uRip = UINT64_MAX; + READ_REG_RET(HV_X86_RIP, &uRip); + WRITE_REG_RET(HV_X86_RIP, uRip + cbInstr); + } + else if (uExitReason == VMX_REASON_EPT_VIOLATION) + { + uint64_t uEptQual = UINT64_MAX; + READ_VMCS_RET(VMCS_RO_EXIT_QUALIFIC, &uEptQual); + uint64_t GCPhys = UINT64_MAX; + READ_VMCS_RET(VMCS_GUEST_PHYSICAL_ADDRESS, &GCPhys); + if (GCPhys == MY_NOP_MMIO && (fTest & MY_TEST_F_NOP_MMIO)) + { /* likely */ } + else if (GCPhys == MY_TEST_RIP) + continue; /* dunno why we get this, but restarting it works */ + else + return runtimeError("Unexpected EPT viotaion at %#llx\n", GCPhys); + + /* Set RAX and advance RIP. */ + WRITE_REG_RET(HV_X86_RAX, 42); + + uint64_t cbInstr = UINT64_MAX; + READ_VMCS_RET(VMCS_RO_VMEXIT_INSTR_LEN, &cbInstr); + if (cbInstr < 1 || cbInstr > 15) + return runtimeError("Bad instr len: %#llx\n", cbInstr); + uint64_t uRip = UINT64_MAX; + READ_REG_RET(HV_X86_RIP, &uRip); + WRITE_REG_RET(HV_X86_RIP, uRip + cbInstr); + } + else if (uExitReason == VMX_REASON_IRQ) + { /* ignore */ } + else + return runtimeError("Unexpected exit reason: %#x\n", uExitReason); + } + else + return runtimeError("VM entry failure: %#x\n", uExitReason); + } + else + return runtimeError("hv_vcpu_run failed (for %s): %#x\n", pszInstruction, rcHv); + } + uint64_t const nsElapsed = getNanoTS() - nsStart; + return reportResult(pszInstruction, cInstructions, nsElapsed, cExits); +} + +#else +# error "port me" +#endif + +void dumpCode(uint8_t const *pb, uint8_t *pbEnd) +{ + printf("testing:"); + for (; pb != pbEnd; pb++) + printf(" %02x", *pb); + printf("\n"); +} + + +int ioportTest(unsigned cFactor) +{ + /* + * Produce realmode code + */ + unsigned char *pb = &g_pbMem[MY_TEST_RIP - MY_MEM_BASE]; + unsigned char * const pbStart = pb; + /* OUT DX, AL - 10 times */ + for (unsigned i = 0; i < 10; i++) + *pb++ = 0xee; + /* DEC ECX */ + *pb++ = 0x66; + *pb++ = 0x48 + 1; + /* JNZ MY_TEST_RIP */ + *pb++ = 0x75; + *pb = (signed char)(pbStart - pb - 1); + pb++; + /* OUT 1, AL - Temination port call. */ + *pb++ = 0xe6; + *pb++ = MY_TERM_PORT; + /* JMP to previous instruction */ + *pb++ = 0xeb; + *pb++ = 0xfc; + dumpCode(pbStart, pb); + + return runRealModeTest(100000 * cFactor, "OUT", MY_TEST_F_NOP_IO, + 42 /*eax*/, 10000 * cFactor /*ecx*/, MY_NOP_PORT /*edx*/, 0 /*ebx*/, + 0 /*esp*/, 0 /*ebp*/, 0 /*esi*/, 0 /*uEdi*/); +} + + +int cpuidTest(unsigned cFactor) +{ + /* + * Produce realmode code + */ + unsigned char *pb = &g_pbMem[MY_TEST_RIP - MY_MEM_BASE]; + unsigned char * const pbStart = pb; + for (unsigned i = 0; i < 10; i++) + { + /* XOR EAX,EAX */ + *pb++ = 0x66; + *pb++ = 0x33; + *pb++ = 0xc0; + + /* CPUID */ + *pb++ = 0x0f; + *pb++ = 0xa2; + } + /* DEC ESI */ + *pb++ = 0x66; + *pb++ = 0x48 + 6; + /* JNZ MY_TEST_RIP */ + *pb++ = 0x75; + *pb = (signed char)(pbStart - pb - 1); + pb++; + /* OUT 1, AL - Temination port call. */ + *pb++ = 0xe6; + *pb++ = MY_TERM_PORT; + /* JMP to previous instruction */ + *pb++ = 0xeb; + *pb++ = 0xfc; + dumpCode(pbStart, pb); + + return runRealModeTest(100000 * cFactor, "CPUID", MY_TEST_F_CPUID, + 0 /*eax*/, 0 /*ecx*/, 0 /*edx*/, 0 /*ebx*/, + 0 /*esp*/, 0 /*ebp*/, 10000 * cFactor /*esi*/, 0 /*uEdi*/); +} + + +int mmioTest(unsigned cFactor) +{ + /* + * Produce realmode code accessing MY_MMIO_NOP address assuming it's low. + */ + unsigned char *pb = &g_pbMem[MY_TEST_RIP - MY_MEM_BASE]; + unsigned char * const pbStart = pb; + for (unsigned i = 0; i < 10; i++) + { + /* MOV AL,DS:[BX] */ + *pb++ = 0x8a; + *pb++ = 0x07; + } + /* DEC ESI */ + *pb++ = 0x66; + *pb++ = 0x48 + 6; + /* JNZ MY_TEST_RIP */ + *pb++ = 0x75; + *pb = (signed char)(pbStart - pb - 1); + pb++; + /* OUT 1, AL - Temination port call. */ + *pb++ = 0xe6; + *pb++ = MY_TERM_PORT; + /* JMP to previous instruction */ + *pb++ = 0xeb; + *pb++ = 0xfc; + dumpCode(pbStart, pb); + + return runRealModeTest(100000 * cFactor, "MMIO/r1", MY_TEST_F_NOP_MMIO, + 0 /*eax*/, 0 /*ecx*/, 0 /*edx*/, MY_NOP_MMIO /*ebx*/, + 0 /*esp*/, 0 /*ebp*/, 10000 * cFactor /*esi*/, 0 /*uEdi*/); +} + + + +int main(int argc, char **argv) +{ + /* + * Do some parameter parsing. + */ +#ifdef RT_OS_WINDOWS + unsigned const cFactorDefault = 4; +#elif RT_OS_DARWIN + unsigned const cFactorDefault = 32; +#else + unsigned const cFactorDefault = 24; +#endif + unsigned cFactor = cFactorDefault; + for (int i = 1; i < argc; i++) + { + const char *pszArg = argv[i]; + if ( strcmp(pszArg, "--help") == 0 + || strcmp(pszArg, "/help") == 0 + || strcmp(pszArg, "-h") == 0 + || strcmp(pszArg, "-?") == 0 + || strcmp(pszArg, "/?") == 0) + { + printf("Does some benchmarking of the native NEM engine.\n" + "\n" + "Usage: NemRawBench-1 --factor \n" + "\n" + "Options\n" + " --factor \n" + " Iteration count factor. Default is %u.\n" + " Lower it if execution is slow, increase if quick.\n", + cFactorDefault); + return 0; + } + if (strcmp(pszArg, "--factor") == 0) + { + i++; + if (i < argc) + cFactor = atoi(argv[i]); + else + { + fprintf(stderr, "syntax error: Option %s is takes a value!\n", pszArg); + return 2; + } + } + else + { + fprintf(stderr, "syntax error: Unknown option: %s\n", pszArg); + return 2; + } + } + + /* + * Create the VM + */ + g_cbMem = 128*1024 - MY_MEM_BASE; + int rcExit = createVM(); + if (rcExit == 0) + { + printf("tstNemBench-1: Successfully created test VM...\n"); + + /* + * Do the benchmarking. + */ + ioportTest(cFactor); + cpuidTest(cFactor); + mmioTest(cFactor); + + printf("tstNemBench-1: done\n"); + } + return rcExit; +} + +/* + * Results: + * + * - Darwin/xnu 10.12.6/16.7.0; 3.1GHz Intel Core i7-7920HQ (Kaby Lake): + * 925 845 OUT instructions per second (3 200 307 exits in 3 456 301 621 ns) + * 949 278 CPUID instructions per second (3 200 222 exits in 3 370 980 173 ns) + * 871 499 MMIO/r1 instructions per second (3 200 223 exits in 3 671 834 221 ns) + * + * - Linux 4.15.0 / ubuntu 18.04.1 Desktop LiveCD; 3.1GHz Intel Core i7-7920HQ (Kaby Lake): + * 829 775 OUT instructions per second (3 200 001 exits in 3 856 466 567 ns) + * 2 212 038 CPUID instructions per second (1 exits in 1 446 629 591 ns) [1] + * 477 962 MMIO/r1 instructions per second (3 200 001 exits in 6 695 090 600 ns) + * + * - Linux 4.15.0 / ubuntu 18.04.1 Desktop LiveCD; 3.4GHz Core i5-3570 (Ivy Bridge): + * 717 216 OUT instructions per second (2 400 001 exits in 3 346 271 640 ns) + * 1 675 983 CPUID instructions per second (1 exits in 1 431 995 135 ns) [1] + * 402 621 MMIO/r1 instructions per second (2 400 001 exits in 5 960 930 854 ns) + * + * - Linux 4.18.0-1-amd64 (debian); 3.4GHz AMD Threadripper 1950X: + * 455 727 OUT instructions per second (2 400 001 exits in 5 266 300 471 ns) + * 1 745 014 CPUID instructions per second (1 exits in 1 375 346 658 ns) [1] + * 351 767 MMIO/r1 instructions per second (2 400 001 exits in 6 822 684 544 ns) + * + * - Windows 1803 updated as per 2018-10-01; 3.4GHz Core i5-3570 (Ivy Bridge): + * 67 778 OUT instructions per second (400 001 exits in 5 901 560 700 ns) + * 66 113 CPUID instructions per second (400 001 exits in 6 050 208 000 ns) + * 62 939 MMIO/r1 instructions per second (400 001 exits in 6 355 302 900 ns) + * + * - Windows 1803 updated as per 2018-09-28; 3.4GHz AMD Threadripper 1950X: + * 34 485 OUT instructions per second (400 001 exits in 11 598 918 200 ns) + * 34 043 CPUID instructions per second (400 001 exits in 11 749 753 200 ns) + * 33 124 MMIO/r1 instructions per second (400 001 exits in 12 075 617 000 ns) + * + * - Windows build 17763; 3.4GHz AMD Threadripper 1950X: + * 65 633 OUT instructions per second (400 001 exits in 6 094 409 100 ns) + * 65 245 CPUID instructions per second (400 001 exits in 6 130 720 600 ns) + * 61 642 MMIO/r1 instructions per second (400 001 exits in 6 489 013 700 ns) + * + * + * [1] CPUID causes no return to ring-3 with KVM. + * + * + * For reference we can compare with similar tests in bs2-test1 running VirtualBox: + * + * - Linux 4.18.0-1-amd64 (debian); 3.4GHz AMD Threadripper 1950X; trunk/r125404: + * real mode, 32-bit OUT : 1 338 471 ins/sec + * real mode, 32-bit OUT-to-ring-3 : 500 337 ins/sec + * real mode, CPUID : 1 566 343 ins/sec + * real mode, 32-bit write : 870 671 ins/sec + * real mode, 32-bit write-to-ring-3: 391 014 ins/sec + * + * - Darwin/xnu 10.12.6/16.7.0; 3.1GHz Intel Core i7-7920HQ (Kaby Lake); trunk/r125404: + * real mode, 32-bit OUT : 790 117 ins/sec + * real mode, 32-bit OUT-to-ring-3 : 157 205 ins/sec + * real mode, CPUID : 1 001 087 ins/sec + * real mode, 32-bit write : 651 257 ins/sec + * real mode, 32-bit write-to-ring-3: 157 773 ins/sec + * + * - Linux 4.15.0 / ubuntu 18.04.1 Desktop LiveCD; 3.1GHz Intel Core i7-7920HQ (Kaby Lake); trunk/r125450: + * real mode, 32-bit OUT : 1 229 245 ins/sec + * real mode, 32-bit OUT-to-ring-3 : 284 848 ins/sec + * real mode, CPUID : 1 429 760 ins/sec + * real mode, 32-bit write : 820 679 ins/sec + * real mode, 32-bit write-to-ring-3: 245 159 ins/sec + * + * - Windows 1803 updated as per 2018-10-01; 3.4GHz Core i5-3570 (Ivy Bridge); trunk/r15442: + * real mode, 32-bit OUT : 961 939 ins/sec + * real mode, 32-bit OUT-to-ring-3 : 189 458 ins/sec + * real mode, CPUID : 1 060 582 ins/sec + * real mode, 32-bit write : 637 967 ins/sec + * real mode, 32-bit write-to-ring-3: 148 573 ins/sec + * + */ diff --git a/src/VBox/VMM/testcase/dev.tar.gz b/src/VBox/VMM/testcase/dev.tar.gz new file mode 100644 index 00000000..95d3a358 Binary files /dev/null and b/src/VBox/VMM/testcase/dev.tar.gz differ diff --git a/src/VBox/VMM/testcase/mkdsk.sh b/src/VBox/VMM/testcase/mkdsk.sh new file mode 100755 index 00000000..f7180bbd --- /dev/null +++ b/src/VBox/VMM/testcase/mkdsk.sh @@ -0,0 +1,76 @@ +#!/bin/sh +## @file +# Obsolete? +# + +# +# Copyright (C) 2006-2019 Oracle Corporation +# +# This file is part of VirtualBox Open Source Edition (OSE), as +# available from http://www.virtualbox.org. This file is free software; +# you can redistribute it and/or modify it under the terms of the GNU +# General Public License (GPL) as published by the Free Software +# Foundation, in version 2 as it comes in the "COPYING" file of the +# VirtualBox OSE distribution. VirtualBox OSE is distributed in the +# hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +# + +if [ "x$3" == "x" ]; then + + echo "syntax error" + echo "syntax: $0 imagename [tar files]" + echo "" + echo "Simples qemu boot image is archived by only specifying an statically" + echo "linked init program and using the dev.tar.gz file to create devices." + echo "The boot linux in qemu specifying the image as -hda. Use the -kernel" + echo "option to specify a bzImage kernel image to use, and specify" + echo "-append root=/dev/hda so the kernel will mount /dev/hda and look" + echo "for /sbin/init there." + echo "" + echo "Example:" + echo " sh ./mkdsk.sh foo.img 2048 ~/VBox/Tree/out/linux/debug/bin/tstProg1 dev.tar.gz" + echo " qemu -hda foo.img -m 32 -kernel ~/qemutest/linux-test/bzImage-2.4.21 -append root=/dev/hda" + exit 1 +fi + +image=$1 +size=$2 +init=$3 + +sizebytes=`expr $size '*' 1024` +cyls=`expr 8225280 / $sizebytes` +echo $cyls + +echo "* Creating $image of $size kb...." +rm -f $image +dd if=/dev/zero of=$image count=$size bs=1024 || exit 1 + +echo "* Formatting with ext2..." +/sbin/mkfs.ext2 $image || exit 1 + +echo "* Mounting temporarily at ./tmpmnt..." +mkdir -p tmpmnt +sudo mount $image ./tmpmnt -t ext2 -o loop=/dev/loop7 || exit 1 + +# init +echo "* Copying $init to sbin/init..." +mkdir tmpmnt/sbin +sudo cp $init tmpmnt/sbin/init +sudo chmod 755 tmpmnt/sbin/init + +shift +shift +shift +while [ "x$1" != "x" ]; +do + echo "* Untarring $1 to disk..." + sudo tar -xzv -C tmpmnt -f $1 + shift +done + +echo "* Unmounting tmpmnt..." +sudo umount tmpmnt +rmdir tmpmnt +echo "* Done! (Perhaps even successfully so...)" +echo " 'root=/dev/hda' remember :-)" +exit 0 diff --git a/src/VBox/VMM/testcase/tstAnimate.cpp b/src/VBox/VMM/testcase/tstAnimate.cpp new file mode 100644 index 00000000..cb475e02 --- /dev/null +++ b/src/VBox/VMM/testcase/tstAnimate.cpp @@ -0,0 +1,950 @@ +/* $Id: tstAnimate.cpp $ */ +/** @file + * VBox Animation Testcase / Tool. + */ + +/* + * Copyright (C) 2006-2019 Oracle Corporation + * + * This file is part of VirtualBox Open Source Edition (OSE), as + * available from http://www.virtualbox.org. This file is free software; + * you can redistribute it and/or modify it under the terms of the GNU + * General Public License (GPL) as published by the Free Software + * Foundation, in version 2 as it comes in the "COPYING" file of the + * VirtualBox OSE distribution. VirtualBox OSE is distributed in the + * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. + */ + + +/********************************************************************************************************************************* +* Header Files * +*********************************************************************************************************************************/ +#include +#include +#include +#include +#include +#include +#ifdef VBOX_WITH_REM +# include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + + +/********************************************************************************************************************************* +* Global Variables * +*********************************************************************************************************************************/ +static volatile bool g_fSignaled = false; + + +static void SigInterrupt(int iSignal) +{ + NOREF(iSignal); + signal(SIGINT, SigInterrupt); + g_fSignaled = true; + RTPrintf("caught SIGINT\n"); +} + +typedef DECLCALLBACK(int) FNSETGUESTGPR(PVM, uint32_t); +typedef FNSETGUESTGPR *PFNSETGUESTGPR; +static int scriptGPReg(PVM pVM, char *pszVar, char *pszValue, void *pvUser) +{ + NOREF(pszVar); + uint32_t u32; + int rc = RTStrToUInt32Ex(pszValue, NULL, 16, &u32); + if (RT_FAILURE(rc)) + return rc; + return ((PFNSETGUESTGPR)(uintptr_t)pvUser)(pVM, u32); +} + +typedef DECLCALLBACK(int) FNSETGUESTSEL(PVM, uint16_t); +typedef FNSETGUESTSEL *PFNSETGUESTSEL; +static int scriptSelReg(PVM pVM, char *pszVar, char *pszValue, void *pvUser) +{ + NOREF(pszVar); + uint16_t u16; + int rc = RTStrToUInt16Ex(pszValue, NULL, 16, &u16); + if (RT_FAILURE(rc)) + return rc; + return ((PFNSETGUESTSEL)(uintptr_t)pvUser)(pVM, u16); +} + +typedef DECLCALLBACK(int) FNSETGUESTSYS(PVM, uint32_t); +typedef FNSETGUESTSYS *PFNSETGUESTSYS; +static int scriptSysReg(PVM pVM, char *pszVar, char *pszValue, void *pvUser) +{ + NOREF(pszVar); + uint32_t u32; + int rc = RTStrToUInt32Ex(pszValue, NULL, 16, &u32); + if (RT_FAILURE(rc)) + return rc; + return ((PFNSETGUESTSYS)(uintptr_t)pvUser)(pVM, u32); +} + + +typedef DECLCALLBACK(int) FNSETGUESTDTR(PVM, uint32_t, uint16_t); +typedef FNSETGUESTDTR *PFNSETGUESTDTR; +static int scriptDtrReg(PVM pVM, char *pszVar, char *pszValue, void *pvUser) +{ + NOREF(pszVar); + char *pszPart2 = strchr(pszValue, ':'); + if (!pszPart2) + return -1; + *pszPart2++ = '\0'; + pszPart2 = RTStrStripL(pszPart2); + pszValue = RTStrStripR(pszValue); + + uint32_t u32; + int rc = RTStrToUInt32Ex(pszValue, NULL, 16, &u32); + if (RT_FAILURE(rc)) + return rc; + + uint16_t u16; + rc = RTStrToUInt16Ex(pszPart2, NULL, 16, &u16); + if (RT_FAILURE(rc)) + return rc; + + return ((PFNSETGUESTDTR)(uintptr_t)pvUser)(pVM, u32, u16); +} + + + + +/* variables - putting in global scope to avoid MSC warning C4640. */ +static struct +{ + const char *pszVar; + int (*pfnHandler)(PVM pVM, char *pszVar, char *pszValue, void *pvUser); + PFNRT pvUser; +} g_aVars[] = +{ + { "eax", scriptGPReg, (PFNRT)CPUMSetGuestEAX }, + { "ebx", scriptGPReg, (PFNRT)CPUMSetGuestEBX }, + { "ecx", scriptGPReg, (PFNRT)CPUMSetGuestECX }, + { "edx", scriptGPReg, (PFNRT)CPUMSetGuestEDX }, + { "esp", scriptGPReg, (PFNRT)CPUMSetGuestESP }, + { "ebp", scriptGPReg, (PFNRT)CPUMSetGuestEBP }, + { "esi", scriptGPReg, (PFNRT)CPUMSetGuestESI }, + { "edi", scriptGPReg, (PFNRT)CPUMSetGuestEDI }, + { "efl", scriptGPReg, (PFNRT)CPUMSetGuestEFlags }, + { "eip", scriptGPReg, (PFNRT)CPUMSetGuestEIP }, + { "ss", scriptSelReg, (PFNRT)CPUMSetGuestSS }, + { "cs", scriptSelReg, (PFNRT)CPUMSetGuestCS }, + { "ds", scriptSelReg, (PFNRT)CPUMSetGuestDS }, + { "es", scriptSelReg, (PFNRT)CPUMSetGuestES }, + { "fs", scriptSelReg, (PFNRT)CPUMSetGuestFS }, + { "gs", scriptSelReg, (PFNRT)CPUMSetGuestGS }, + { "cr0", scriptSysReg, (PFNRT)CPUMSetGuestCR0 }, + { "cr2", scriptSysReg, (PFNRT)CPUMSetGuestCR2 }, + { "cr3", scriptSysReg, (PFNRT)CPUMSetGuestCR3 }, + { "cr4", scriptSysReg, (PFNRT)CPUMSetGuestCR4 }, + { "ldtr",scriptSelReg, (PFNRT)CPUMSetGuestLDTR }, + { "tr", scriptSelReg, (PFNRT)CPUMSetGuestTR }, + { "idtr",scriptDtrReg, (PFNRT)CPUMSetGuestIDTR }, + { "gdtr",scriptDtrReg, (PFNRT)CPUMSetGuestGDTR } +}; + + +static int scriptCommand(PVM pVM, const char *pszIn, size_t cch) +{ + NOREF(cch); + int rc = VINF_SUCCESS; + char *psz = RTStrDup(pszIn); + char *pszEqual = strchr(psz, '='); + if (pszEqual) + { + /* + * var = value + */ + *pszEqual = '\0'; + RTStrStripR(psz); + char *pszValue = RTStrStrip(pszEqual + 1); + + rc = -1; + for (unsigned i = 0; i < RT_ELEMENTS(g_aVars); i++) + { + if (!strcmp(psz, g_aVars[i].pszVar)) + { + rc = g_aVars[i].pfnHandler(pVM, psz, pszValue, (void *)(uintptr_t)g_aVars[i].pvUser); + break; + } + } + } + + RTStrFree(psz); + return rc; +} + +static DECLCALLBACK(int) scriptRun(PVM pVM, RTFILE File) +{ + RTPrintf("info: running script...\n"); + uint64_t cb; + int rc = RTFileGetSize(File, &cb); + if (RT_SUCCESS(rc)) + { + if (cb == 0) + return VINF_SUCCESS; + if (cb < _1M) + { + char *pszBuf = (char *)RTMemAllocZ(cb + 1); + if (pszBuf) + { + rc = RTFileRead(File, pszBuf, cb, NULL); + if (RT_SUCCESS(rc)) + { + pszBuf[cb] = '\0'; + + /* + * Now process what's in the buffer. + */ + char *psz = pszBuf; + while (psz && *psz) + { + /* skip blanks. */ + while (RT_C_IS_SPACE(*psz)) + psz++; + if (!*psz) + break; + + /* end of line */ + char *pszNext; + char *pszEnd = strchr(psz, '\n'); + if (!pszEnd) + pszEnd = strchr(psz, '\r'); + if (!pszEnd) + pszNext = pszEnd = strchr(psz, '\0'); + else + pszNext = pszEnd + 1; + + if (*psz != ';' && *psz != '#' && *psz != '/') + { + /* strip end */ + *pszEnd = '\0'; + while (pszEnd > psz && RT_C_IS_SPACE(pszEnd[-1])) + *--pszEnd = '\0'; + + /* process the line */ + RTPrintf("debug: executing script line '%s'\n", psz); + rc = scriptCommand(pVM, psz, pszEnd - psz); + if (RT_FAILURE(rc)) + { + RTPrintf("error: '%s' failed: %Rrc\n", psz, rc); + break; + } + } + /* else comment line */ + + /* next */ + psz = pszNext; + } + + } + else + RTPrintf("error: failed to read script file: %Rrc\n", rc); + RTMemFree(pszBuf); + } + else + { + RTPrintf("error: Out of memory. (%d bytes)\n", cb + 1); + rc = VERR_NO_MEMORY; + } + } + else + RTPrintf("error: script file is too large (0x%llx bytes)\n", cb); + } + else + RTPrintf("error: couldn't get size of script file: %Rrc\n", rc); + + return rc; +} + + +static DECLCALLBACK(int) loadMem(PVM pVM, RTFILE File, uint64_t *poff) +{ + uint64_t off = *poff; + RTPrintf("info: loading memory...\n"); + + int rc = RTFileSeek(File, off, RTFILE_SEEK_BEGIN, NULL); + if (RT_SUCCESS(rc)) + { + RTGCPHYS GCPhys = 0; + for (;;) + { + if (!(GCPhys % (PAGE_SIZE * 0x1000))) + RTPrintf("info: %RGp...\n", GCPhys); + + /* read a page from the file */ + size_t cbRead = 0; + uint8_t au8Page[PAGE_SIZE * 16]; + rc = RTFileRead(File, &au8Page, sizeof(au8Page), &cbRead); + if (RT_SUCCESS(rc) && !cbRead) + rc = RTFileRead(File, &au8Page, sizeof(au8Page), &cbRead); + if (RT_SUCCESS(rc) && !cbRead) + rc = VERR_EOF; + if (RT_FAILURE(rc) || rc == VINF_EOF) + { + if (rc == VERR_EOF) + rc = VINF_SUCCESS; + else + RTPrintf("error: Read error %Rrc while reading the raw memory file.\n", rc); + break; + } + + /* Write that page to the guest - skip known rom areas for now. */ + if (GCPhys < 0xa0000 || GCPhys >= 0x100000) /* ASSUME size of a8Page is a power of 2. */ + PGMPhysWrite(pVM, GCPhys, &au8Page, cbRead, PGMACCESSORIGIN_DEBUGGER); + GCPhys += cbRead; + } + } + else + RTPrintf("error: Failed to seek to 0x%llx in the raw memory file. rc=%Rrc\n", off, rc); + + return rc; +} + + +/** + * Creates the default configuration. + * This assumes an empty tree. + * + * @returns VBox status code. + * @param pVM Pointer to the VM. + */ +static DECLCALLBACK(int) cfgmR3CreateDefault(PUVM pUVM, PVM pVM, void *pvUser) +{ + RT_NOREF1(pUVM); + uint64_t cbMem = *(uint64_t *)pvUser; + int rc; + int rcAll = VINF_SUCCESS; + bool fIOAPIC = false; +#define UPDATERC() do { if (RT_FAILURE(rc) && RT_SUCCESS(rcAll)) rcAll = rc; } while (0) + + /* + * Create VM default values. + */ + PCFGMNODE pRoot = CFGMR3GetRoot(pVM); + rc = CFGMR3InsertString(pRoot, "Name", "Default VM"); + UPDATERC(); + rc = CFGMR3InsertInteger(pRoot, "RamSize", cbMem); + UPDATERC(); + rc = CFGMR3InsertInteger(pRoot, "TimerMillies", 10); + UPDATERC(); + rc = CFGMR3InsertInteger(pRoot, "RawR3Enabled", 0); + UPDATERC(); + /** @todo CFGM Defaults: RawR0, PATMEnabled and CASMEnabled needs attention later. */ + rc = CFGMR3InsertInteger(pRoot, "RawR0Enabled", 0); + UPDATERC(); + rc = CFGMR3InsertInteger(pRoot, "PATMEnabled", 0); + UPDATERC(); + rc = CFGMR3InsertInteger(pRoot, "CSAMEnabled", 0); + UPDATERC(); + + /* + * PDM. + */ + PCFGMNODE pPdm; + rc = CFGMR3InsertNode(pRoot, "PDM", &pPdm); + UPDATERC(); + PCFGMNODE pDevices = NULL; + rc = CFGMR3InsertNode(pPdm, "Devices", &pDevices); + UPDATERC(); + rc = CFGMR3InsertInteger(pDevices, "LoadBuiltin", 1); /* boolean */ + UPDATERC(); + PCFGMNODE pDrivers = NULL; + rc = CFGMR3InsertNode(pPdm, "Drivers", &pDrivers); + UPDATERC(); + rc = CFGMR3InsertInteger(pDrivers, "LoadBuiltin", 1); /* boolean */ + UPDATERC(); + + + /* + * Devices + */ + pDevices = NULL; + rc = CFGMR3InsertNode(pRoot, "Devices", &pDevices); + UPDATERC(); + /* device */ + PCFGMNODE pDev = NULL; + PCFGMNODE pInst = NULL; + PCFGMNODE pCfg = NULL; +#if 0 + PCFGMNODE pLunL0 = NULL; + PCFGMNODE pLunL1 = NULL; +#endif + + /* + * PC Arch. + */ + rc = CFGMR3InsertNode(pDevices, "pcarch", &pDev); + UPDATERC(); + rc = CFGMR3InsertNode(pDev, "0", &pInst); + UPDATERC(); + rc = CFGMR3InsertInteger(pInst, "Trusted", 1); /* boolean */ + UPDATERC(); + rc = CFGMR3InsertNode(pInst, "Config", &pCfg); + UPDATERC(); + + /* + * PC Bios. + */ + rc = CFGMR3InsertNode(pDevices, "pcbios", &pDev); + UPDATERC(); + rc = CFGMR3InsertNode(pDev, "0", &pInst); + UPDATERC(); + rc = CFGMR3InsertInteger(pInst, "Trusted", 1); /* boolean */ + UPDATERC(); + rc = CFGMR3InsertNode(pInst, "Config", &pCfg); + UPDATERC(); + rc = CFGMR3InsertString(pCfg, "BootDevice0", "IDE"); + UPDATERC(); + rc = CFGMR3InsertString(pCfg, "BootDevice1", "NONE"); + UPDATERC(); + rc = CFGMR3InsertString(pCfg, "BootDevice2", "NONE"); + UPDATERC(); + rc = CFGMR3InsertString(pCfg, "BootDevice3", "NONE"); + UPDATERC(); + rc = CFGMR3InsertString(pCfg, "HardDiskDevice", "piix3ide"); + UPDATERC(); + rc = CFGMR3InsertString(pCfg, "FloppyDevice", "i82078"); + rc = CFGMR3InsertInteger(pCfg, "IOAPIC", fIOAPIC); UPDATERC(); + RTUUID Uuid; + RTUuidClear(&Uuid); + rc = CFGMR3InsertBytes(pCfg, "UUID", &Uuid, sizeof(Uuid)); UPDATERC(); + /* Bios logo. */ + rc = CFGMR3InsertInteger(pCfg, "FadeIn", 0); + UPDATERC(); + rc = CFGMR3InsertInteger(pCfg, "FadeOut", 0); + UPDATERC(); + rc = CFGMR3InsertInteger(pCfg, "LogoTime", 0); + UPDATERC(); + rc = CFGMR3InsertString(pCfg, "LogoFile", ""); + UPDATERC(); + + /* + * ACPI + */ + rc = CFGMR3InsertNode(pDevices, "acpi", &pDev); UPDATERC(); + rc = CFGMR3InsertNode(pDev, "0", &pInst); UPDATERC(); + rc = CFGMR3InsertInteger(pInst, "Trusted", 1); /* boolean */ UPDATERC(); + rc = CFGMR3InsertNode(pInst, "Config", &pCfg); UPDATERC(); + rc = CFGMR3InsertInteger(pCfg, "IOAPIC", fIOAPIC); UPDATERC(); + rc = CFGMR3InsertInteger(pInst, "PCIDeviceNo", 7); UPDATERC(); + rc = CFGMR3InsertInteger(pInst, "PCIFunctionNo", 0); UPDATERC(); + + /* + * DMA + */ + rc = CFGMR3InsertNode(pDevices, "8237A", &pDev); UPDATERC(); + rc = CFGMR3InsertNode(pDev, "0", &pInst); UPDATERC(); + rc = CFGMR3InsertInteger(pInst, "Trusted", 1); /* boolean */ UPDATERC(); + + /* + * PCI bus. + */ + rc = CFGMR3InsertNode(pDevices, "pci", &pDev); /* piix3 */ + UPDATERC(); + rc = CFGMR3InsertNode(pDev, "0", &pInst); + UPDATERC(); + rc = CFGMR3InsertInteger(pInst, "Trusted", 1); /* boolean */ + UPDATERC(); + rc = CFGMR3InsertNode(pInst, "Config", &pCfg); + UPDATERC(); + rc = CFGMR3InsertInteger(pCfg, "IOAPIC", fIOAPIC); UPDATERC(); + + /* + * PS/2 keyboard & mouse + */ + rc = CFGMR3InsertNode(pDevices, "pckbd", &pDev); + UPDATERC(); + rc = CFGMR3InsertNode(pDev, "0", &pInst); + UPDATERC(); + rc = CFGMR3InsertInteger(pInst, "Trusted", 1); /* boolean */ UPDATERC(); + rc = CFGMR3InsertNode(pInst, "Config", &pCfg); + UPDATERC(); + + /* + * Floppy + */ + rc = CFGMR3InsertNode(pDevices, "i82078", &pDev); UPDATERC(); + rc = CFGMR3InsertNode(pDev, "0", &pInst); UPDATERC(); + rc = CFGMR3InsertInteger(pInst, "Trusted", 1); UPDATERC(); + rc = CFGMR3InsertNode(pInst, "Config", &pCfg); UPDATERC(); + rc = CFGMR3InsertInteger(pCfg, "IRQ", 6); UPDATERC(); + rc = CFGMR3InsertInteger(pCfg, "DMA", 2); UPDATERC(); + rc = CFGMR3InsertInteger(pCfg, "MemMapped", 0 ); UPDATERC(); + rc = CFGMR3InsertInteger(pCfg, "IOBase", 0x3f0); UPDATERC(); + + /* + * i8254 Programmable Interval Timer And Dummy Speaker + */ + rc = CFGMR3InsertNode(pDevices, "i8254", &pDev); + UPDATERC(); + rc = CFGMR3InsertNode(pDev, "0", &pInst); + UPDATERC(); + rc = CFGMR3InsertNode(pInst, "Config", &pCfg); + UPDATERC(); + + /* + * i8259 Programmable Interrupt Controller. + */ + rc = CFGMR3InsertNode(pDevices, "i8259", &pDev); + UPDATERC(); + rc = CFGMR3InsertNode(pDev, "0", &pInst); + UPDATERC(); + rc = CFGMR3InsertInteger(pInst, "Trusted", 1); /* boolean */ + UPDATERC(); + rc = CFGMR3InsertNode(pInst, "Config", &pCfg); + UPDATERC(); + + /* + * APIC. + */ + rc = CFGMR3InsertNode(pDevices, "apic", &pDev); UPDATERC(); + rc = CFGMR3InsertNode(pDev, "0", &pInst); UPDATERC(); + rc = CFGMR3InsertInteger(pInst, "Trusted", 1); /* boolean */ UPDATERC(); + rc = CFGMR3InsertNode(pInst, "Config", &pCfg); UPDATERC(); + rc = CFGMR3InsertInteger(pCfg, "IOAPIC", fIOAPIC); UPDATERC(); + + if (fIOAPIC) + { + /* + * I/O Advanced Programmable Interrupt Controller. + */ + rc = CFGMR3InsertNode(pDevices, "ioapic", &pDev); UPDATERC(); + rc = CFGMR3InsertNode(pDev, "0", &pInst); UPDATERC(); + rc = CFGMR3InsertInteger(pInst, "Trusted", 1); /* boolean */ UPDATERC(); + rc = CFGMR3InsertNode(pInst, "Config", &pCfg); UPDATERC(); + } + + + /* + * RTC MC146818. + */ + rc = CFGMR3InsertNode(pDevices, "mc146818", &pDev); UPDATERC(); + rc = CFGMR3InsertNode(pDev, "0", &pInst); UPDATERC(); + rc = CFGMR3InsertNode(pInst, "Config", &pCfg); UPDATERC(); + + /* + * VGA. + */ + rc = CFGMR3InsertNode(pDevices, "vga", &pDev); UPDATERC(); + rc = CFGMR3InsertNode(pDev, "0", &pInst); UPDATERC(); + rc = CFGMR3InsertInteger(pInst, "Trusted", 1); /* boolean */ UPDATERC(); + rc = CFGMR3InsertInteger(pInst, "PCIDeviceNo", 2); UPDATERC(); + rc = CFGMR3InsertInteger(pInst, "PCIFunctionNo", 0); UPDATERC(); + rc = CFGMR3InsertNode(pInst, "Config", &pCfg); UPDATERC(); + rc = CFGMR3InsertInteger(pCfg, "VRamSize", 8 * _1M); UPDATERC(); + rc = CFGMR3InsertInteger(pCfg, "CustomVideoModes", 0); + rc = CFGMR3InsertInteger(pCfg, "HeightReduction", 0); UPDATERC(); + //rc = CFGMR3InsertInteger(pCfg, "MonitorCount", 1); UPDATERC(); + + /* + * IDE controller. + */ + rc = CFGMR3InsertNode(pDevices, "piix3ide", &pDev); /* piix3 */ + UPDATERC(); + rc = CFGMR3InsertNode(pDev, "0", &pInst); + UPDATERC(); + rc = CFGMR3InsertInteger(pInst, "Trusted", 1); /* boolean */ + UPDATERC(); + rc = CFGMR3InsertNode(pInst, "Config", &pCfg); UPDATERC(); + rc = CFGMR3InsertInteger(pInst, "PCIDeviceNo", 1); UPDATERC(); + rc = CFGMR3InsertInteger(pInst, "PCIFunctionNo", 1); UPDATERC(); + + /* + * Network card. + */ + rc = CFGMR3InsertNode(pDevices, "pcnet", &pDev); UPDATERC(); + rc = CFGMR3InsertNode(pDev, "0", &pInst); UPDATERC(); + rc = CFGMR3InsertInteger(pInst, "Trusted", 1); /* boolean */ UPDATERC(); + rc = CFGMR3InsertInteger(pInst, "PCIDeviceNo", 3); UPDATERC(); + rc = CFGMR3InsertInteger(pInst, "PCIFunctionNo", 0); UPDATERC(); + rc = CFGMR3InsertNode(pInst, "Config", &pCfg); UPDATERC(); + rc = CFGMR3InsertInteger(pCfg, "Am79C973", 1); UPDATERC(); + RTMAC Mac; + Mac.au16[0] = 0x0080; + Mac.au16[2] = Mac.au16[1] = 0x8086; + rc = CFGMR3InsertBytes(pCfg, "MAC", &Mac, sizeof(Mac)); UPDATERC(); + + /* + * VMM Device + */ + rc = CFGMR3InsertNode(pDevices, "VMMDev", &pDev); UPDATERC(); + rc = CFGMR3InsertNode(pDev, "0", &pInst); UPDATERC(); + rc = CFGMR3InsertNode(pInst, "Config", &pCfg); UPDATERC(); + rc = CFGMR3InsertInteger(pInst, "Trusted", 1); /* boolean */ UPDATERC(); + rc = CFGMR3InsertInteger(pInst, "PCIDeviceNo", 4); UPDATERC(); + rc = CFGMR3InsertInteger(pInst, "PCIFunctionNo", 0); UPDATERC(); + + /* + * ... + */ + +#undef UPDATERC + return rcAll; +} + +static void syntax(void) +{ + RTPrintf("Syntax: tstAnimate < -r | -z > \n" + " [-o ]\n" + " [-s