blob: 1324c75b28832db6ceadaf25256cbbc484a47e1f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
|
; $Id: cidet.mac $ ;
;; @file
; CPU Instruction Decoding & Execution Tests - Assembly Header.
;
;
; Copyright (C) 2014-2019 Oracle Corporation
;
; This file is part of VirtualBox Open Source Edition (OSE), as
; available from http://www.virtualbox.org. This file is free software;
; you can redistribute it and/or modify it under the terms of the GNU
; General Public License (GPL) as published by the Free Software
; Foundation, in version 2 as it comes in the "COPYING" file of the
; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
;
; The contents of this file may alternatively be used under the terms
; of the Common Development and Distribution License Version 1.0
; (CDDL) only, as it comes in the "COPYING.CDDL" file of the
; VirtualBox OSE distribution, in which case the provisions of the
; CDDL are applicable instead of those of the GPL.
;
; You may elect to license modified versions of this file under the
; terms and conditions of either the GPL or the CDDL or both.
;
%ifndef ___cidet_mac___
%define ___cidet_mac___
struc CIDETCPUCTX
.rip resq 1
.rfl resq 1
.aGRegs resq 16
.aSRegs resw 6
%ifndef CIDET_REDUCED_CTX
.tr resw 1
.ldtr resw 1
.cr0 resq 1
%else
.au16Padding resw 2
%endif
.cr2 resq 1
%ifndef CIDET_REDUCED_CTX
.cr3 resq 1
.cr4 resq 1
.cr8 resq 1
.dr0 resq 1
.dr1 resq 1
.dr2 resq 1
.dr3 resq 1
.dr6 resq 1
.dr7 resq 1
%endif
.uErr resq 1
.uXcpt resd 1
.fIgnoredRFlags resd 1
.fTrickyStack resb 1
endstruc
%endif
|