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author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-28 09:13:47 +0000 |
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committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-28 09:13:47 +0000 |
commit | 102b0d2daa97dae68d3eed54d8fe37a9cc38a892 (patch) | |
tree | bcf648efac40ca6139842707f0eba5a4496a6dd2 /drivers/nxp/gic/ls_gicv2.c | |
parent | Initial commit. (diff) | |
download | arm-trusted-firmware-upstream/2.8.0+dfsg.tar.xz arm-trusted-firmware-upstream/2.8.0+dfsg.zip |
Adding upstream version 2.8.0+dfsg.upstream/2.8.0+dfsgupstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'drivers/nxp/gic/ls_gicv2.c')
-rw-r--r-- | drivers/nxp/gic/ls_gicv2.c | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/drivers/nxp/gic/ls_gicv2.c b/drivers/nxp/gic/ls_gicv2.c new file mode 100644 index 0000000..62bc8db --- /dev/null +++ b/drivers/nxp/gic/ls_gicv2.c @@ -0,0 +1,76 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include <gicv2.h> +#include <plat_gic.h> + + +/* + * NXP common helper to initialize the GICv3 only driver. + */ +void plat_ls_gic_driver_init(uintptr_t nxp_gicd_addr, + uintptr_t nxp_gicc_addr, + uint8_t plat_core_count, + interrupt_prop_t *ls_interrupt_props, + uint8_t ls_interrupt_prop_count, + uint32_t *target_mask_array) +{ + static struct gicv2_driver_data ls_gic_data; + + ls_gic_data.gicd_base = nxp_gicd_addr; + ls_gic_data.gicc_base = nxp_gicc_addr; + ls_gic_data.target_masks = target_mask_array; + ls_gic_data.target_masks_num = plat_core_count; + ls_gic_data.interrupt_props = ls_interrupt_props; + ls_gic_data.interrupt_props_num = ls_interrupt_prop_count; + + gicv2_driver_init(&ls_gic_data); +} + +void plat_ls_gic_init(void) +{ + gicv2_distif_init(); + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); +} + +/****************************************************************************** + * ARM common helper to enable the GICv2 CPU interface + *****************************************************************************/ +void plat_ls_gic_cpuif_enable(void) +{ + gicv2_cpuif_enable(); +} + +/****************************************************************************** + * ARM common helper to disable the GICv2 CPU interface + *****************************************************************************/ +void plat_ls_gic_cpuif_disable(void) +{ + gicv2_cpuif_disable(); +} + +/****************************************************************************** + * NXP common helper to initialize GICv2 per cpu + *****************************************************************************/ +void plat_gic_pcpu_init(void) +{ + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); +} + +/****************************************************************************** + * Stubs for Redistributor power management. Although GICv2 doesn't have + * Redistributor interface, these are provided for the sake of uniform GIC API + *****************************************************************************/ +void plat_ls_gic_redistif_on(void) +{ +} + +void plat_ls_gic_redistif_off(void) +{ +} |