diff options
author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-28 09:13:47 +0000 |
---|---|---|
committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-28 09:13:47 +0000 |
commit | 102b0d2daa97dae68d3eed54d8fe37a9cc38a892 (patch) | |
tree | bcf648efac40ca6139842707f0eba5a4496a6dd2 /drivers/nxp/pmu/pmu.c | |
parent | Initial commit. (diff) | |
download | arm-trusted-firmware-upstream.tar.xz arm-trusted-firmware-upstream.zip |
Adding upstream version 2.8.0+dfsg.upstream/2.8.0+dfsgupstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to '')
-rw-r--r-- | drivers/nxp/pmu/pmu.c | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/drivers/nxp/pmu/pmu.c b/drivers/nxp/pmu/pmu.c new file mode 100644 index 0000000..2a907c8 --- /dev/null +++ b/drivers/nxp/pmu/pmu.c @@ -0,0 +1,45 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include <arch.h> +#include <arch_helpers.h> +#include <common/debug.h> +#include <dcfg.h> +#include <lib/mmio.h> +#include <pmu.h> + +void enable_timer_base_to_cluster(uintptr_t nxp_pmu_addr) +{ + uint32_t *cltbenr = NULL; + uint32_t cltbenr_val = 0U; + + cltbenr = (uint32_t *)(nxp_pmu_addr + + CLUST_TIMER_BASE_ENBL_OFFSET); + + cltbenr_val = mmio_read_32((uintptr_t)cltbenr); + + cltbenr_val = cltbenr_val + | (1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); + + mmio_write_32((uintptr_t)cltbenr, cltbenr_val); + + VERBOSE("Enable cluster time base\n"); +} + +/* + * Enable core timebase. In certain Layerscape SoCs, the clock for each core's + * has an enable bit in the PMU Physical Core Time Base Enable + * Register (PCTBENR), which allows the watchdog to operate. + */ + +void enable_core_tb(uintptr_t nxp_pmu_addr) +{ + uint32_t *pctbenr = (uint32_t *) (nxp_pmu_addr + + CORE_TIMEBASE_ENBL_OFFSET); + + mmio_write_32((uintptr_t)pctbenr, 0xff); +} |