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author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-28 09:13:47 +0000 |
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committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-28 09:13:47 +0000 |
commit | 102b0d2daa97dae68d3eed54d8fe37a9cc38a892 (patch) | |
tree | bcf648efac40ca6139842707f0eba5a4496a6dd2 /fdts/stm32mp13-fw-config.dtsi | |
parent | Initial commit. (diff) | |
download | arm-trusted-firmware-eab28e853379ac7fd9284999ce6a23ee432c4b6d.tar.xz arm-trusted-firmware-eab28e853379ac7fd9284999ce6a23ee432c4b6d.zip |
Adding upstream version 2.8.0+dfsg.upstream/2.8.0+dfsgupstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'fdts/stm32mp13-fw-config.dtsi')
-rw-r--r-- | fdts/stm32mp13-fw-config.dtsi | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/fdts/stm32mp13-fw-config.dtsi b/fdts/stm32mp13-fw-config.dtsi new file mode 100644 index 0000000..4f3bb72 --- /dev/null +++ b/fdts/stm32mp13-fw-config.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + */ + +#include <common/tbbr/tbbr_img_def.h> +#include <dt-bindings/soc/stm32mp13-tzc400.h> + +#include <platform_def.h> + +#ifndef DDR_SIZE +#error "DDR_SIZE is not defined" +#endif + +#define DDR_NS_BASE STM32MP_DDR_BASE +#define DDR_SEC_SIZE STM32MP_DDR_S_SIZE +#define DDR_SEC_BASE (STM32MP_DDR_BASE + (DDR_SIZE - DDR_SEC_SIZE)) +#define DDR_NS_SIZE (DDR_SEC_BASE - DDR_NS_BASE) + +/dts-v1/; + +/ { + dtb-registry { + compatible = "fconf,dyn_cfg-dtb_registry"; + + hw-config { + load-address = <0x0 STM32MP_HW_CONFIG_BASE>; + max-size = <STM32MP_HW_CONFIG_MAX_SIZE>; + id = <HW_CONFIG_ID>; + }; + + nt_fw { + load-address = <0x0 STM32MP_BL33_BASE>; + max-size = <STM32MP_BL33_MAX_SIZE>; + id = <BL33_IMAGE_ID>; + }; + + tos_fw { + load-address = <0x0 DDR_SEC_BASE>; + max-size = <DDR_SEC_SIZE>; + id = <BL32_IMAGE_ID>; + }; + }; + + st-mem-firewall { + compatible = "st,mem-firewall"; + memory-ranges = < + DDR_NS_BASE DDR_NS_SIZE TZC_REGION_S_NONE TZC_REGION_NSEC_ALL_ACCESS_RDWR + DDR_SEC_BASE DDR_SEC_SIZE TZC_REGION_S_RDWR 0>; + }; +}; |