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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-28 09:13:47 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-28 09:13:47 +0000 |
| commit | 102b0d2daa97dae68d3eed54d8fe37a9cc38a892 (patch) | |
| tree | bcf648efac40ca6139842707f0eba5a4496a6dd2 /include/lib/cpus/aarch64/cortex_a510.h | |
| parent | Initial commit. (diff) | |
| download | arm-trusted-firmware-102b0d2daa97dae68d3eed54d8fe37a9cc38a892.tar.xz arm-trusted-firmware-102b0d2daa97dae68d3eed54d8fe37a9cc38a892.zip | |
Adding upstream version 2.8.0+dfsg.upstream/2.8.0+dfsgupstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to '')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a510.h | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a510.h b/include/lib/cpus/aarch64/cortex_a510.h new file mode 100644 index 0000000..6af85a8 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a510.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2022, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A510_H +#define CORTEX_A510_H + +#define CORTEX_A510_MIDR U(0x410FD460) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_A510_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT U(19) +#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE U(1) +#define CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT U(23) +#define CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT U(46) +#define CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR U(2) +#define CORTEX_A510_CPUECTLR_EL1_ATOM U(38) + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_A510_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +/******************************************************************************* + * Complex auxiliary control register specific definitions + ******************************************************************************/ +#define CORTEX_A510_CMPXACTLR_EL1 S3_0_C15_C1_3 + +/******************************************************************************* + * Auxiliary control register specific definitions + ******************************************************************************/ +#define CORTEX_A510_CPUACTLR_EL1 S3_0_C15_C1_0 +#define CORTEX_A510_CPUACTLR_EL1_BIT_17 (ULL(1) << 17) +#define CORTEX_A510_CPUACTLR_EL1_BIT_38 (ULL(1) << 38) + +#endif /* CORTEX_A510_H */
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