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author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-28 09:13:47 +0000 |
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committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-28 09:13:47 +0000 |
commit | 102b0d2daa97dae68d3eed54d8fe37a9cc38a892 (patch) | |
tree | bcf648efac40ca6139842707f0eba5a4496a6dd2 /plat/imx/imx7/warp7 | |
parent | Initial commit. (diff) | |
download | arm-trusted-firmware-102b0d2daa97dae68d3eed54d8fe37a9cc38a892.tar.xz arm-trusted-firmware-102b0d2daa97dae68d3eed54d8fe37a9cc38a892.zip |
Adding upstream version 2.8.0+dfsg.upstream/2.8.0+dfsgupstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'plat/imx/imx7/warp7')
-rw-r--r-- | plat/imx/imx7/warp7/include/platform_def.h | 218 | ||||
-rw-r--r-- | plat/imx/imx7/warp7/platform.mk | 37 | ||||
-rw-r--r-- | plat/imx/imx7/warp7/warp7_bl2_el3_setup.c | 143 |
3 files changed, 398 insertions, 0 deletions
diff --git a/plat/imx/imx7/warp7/include/platform_def.h b/plat/imx/imx7/warp7/include/platform_def.h new file mode 100644 index 0000000..683e50d --- /dev/null +++ b/plat/imx/imx7/warp7/include/platform_def.h @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include <arch.h> +#include <common/tbbr/tbbr_img_def.h> +#include <plat/common/common_def.h> + +#define PLATFORM_STACK_SIZE 0x1000 + +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(2) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER +#define PLATFORM_CLUSTER1_CORE_COUNT U(0) + +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ + PLATFORM_CLUSTER1_CORE_COUNT) + +#define WARP7_PRIMARY_CPU U(0) + +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) +#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 + +#define PLAT_MAX_RET_STATE 1 +#define PLAT_MAX_OFF_STATE 2 + +/* Local power state for power domains in Run state. */ +#define PLAT_LOCAL_STATE_RUN 0 + +/* Local power state for retention. Valid only for CPU power domains */ +#define PLAT_LOCAL_STATE_RET 1 + +/* + * Local power state for OFF/power-down. Valid for CPU and cluster power + * domains. + */ +#define PLAT_LOCAL_STATE_OFF 2 + +/* + * Macros used to parse state information from State-ID if it is using the + * recommended encoding for State-ID. + */ +#define PLAT_LOCAL_PSTATE_WIDTH 4 +#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1) + +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + * i.MX7 has a 32 byte cacheline size + * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016 pg 244 + */ +#define CACHE_WRITEBACK_SHIFT 4 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +/* + * Partition memory into secure BootROM, OCRAM_S, non-secure DRAM, secure DRAM + */ +#define BOOT_ROM_BASE 0x00000000 +#define BOOT_ROM_SIZE 0x00020000 + +#define OCRAM_S_BASE 0x00180000 +#define OCRAM_S_SIZE 0x00008000 + +/* Controller maps 2GB, board contains 512 MB. 0x80000000 - 0xa0000000 */ +#define DRAM_BASE 0x80000000 +#define DRAM_SIZE 0x20000000 +#define DRAM_LIMIT (DRAM_BASE + DRAM_SIZE) + +/* Place OPTEE at minus 32 MB from the end of memory. 0x9e000000 - 0xa0000000 */ +#define IMX7_OPTEE_SIZE 0x02000000 +#define IMX7_OPTEE_BASE (DRAM_LIMIT - IMX7_OPTEE_SIZE) +#define IMX7_OPTEE_LIMIT (IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE) + +/* Place ATF directly beneath OPTEE. 0x9df00000 - 0x9e000000 */ +#define BL2_RAM_SIZE 0x00100000 +#define BL2_RAM_BASE (IMX7_OPTEE_BASE - BL2_RAM_SIZE) +#define BL2_RAM_LIMIT (BL2_RAM_BASE + BL2_RAM_SIZE) + +/* Optional Mailbox. Only relevant on i.MX7D. 0x9deff000 - 0x9df00000*/ +#define SHARED_RAM_SIZE 0x00001000 +#define SHARED_RAM_BASE (BL2_RAM_BASE - SHARED_RAM_SIZE) +#define SHARED_RAM_LIMIT (SHARED_RAM_BASE + SHARED_RAM_SIZE) + +/* Define the absolute location of u-boot 0x87800000 - 0x87900000 */ +#define IMX7_UBOOT_SIZE 0x00100000 +#define IMX7_UBOOT_BASE (DRAM_BASE + 0x7800000) +#define IMX7_UBOOT_LIMIT (IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE) + +/* Define FIP image absolute location 0x80000000 - 0x80100000 */ +#define IMX_FIP_SIZE 0x00100000 +#define IMX_FIP_BASE (DRAM_BASE) +#define IMX_FIP_LIMIT (IMX_FIP_BASE + IMX_FIP_SIZE) + +/* Define FIP image location at 1MB offset */ +#define IMX_FIP_MMC_BASE (1024 * 1024) + +/* Define the absolute location of DTB 0x83000000 - 0x83100000 */ +#define IMX7_DTB_SIZE 0x00100000 +#define IMX7_DTB_BASE (DRAM_BASE + 0x03000000) +#define IMX7_DTB_LIMIT (IMX7_DTB_BASE + IMX7_DTB_SIZE) + +/* Define the absolute location of DTB Overlay 0x83100000 - 0x83101000 */ +#define IMX7_DTB_OVERLAY_SIZE 0x00001000 +#define IMX7_DTB_OVERLAY_BASE IMX7_DTB_LIMIT +#define IMX7_DTB_OVERLAY_LIMIT (IMX7_DTB_OVERLAY_BASE + \ + IMX7_DTB_OVERLAY_SIZE) + +/* + * BL2 specific defines. + * + * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug + * size plus a little space for growth. + */ +#define BL2_BASE BL2_RAM_BASE +#define BL2_LIMIT (BL2_RAM_BASE + BL2_RAM_SIZE) + +/* + * BL3-2/OPTEE + */ +# define BL32_BASE IMX7_OPTEE_BASE +# define BL32_LIMIT (IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE) + +/* + * BL3-3/U-BOOT + */ +#define BL33_BASE IMX7_UBOOT_BASE +#define BL33_LIMIT (IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE) + +/* + * ATF's view of memory + * + * 0xa0000000 +-----------------+ + * | DDR | BL32/OPTEE + * 0x9e000000 +-----------------+ + * | DDR | BL23 ATF + * 0x9df00000 +-----------------+ + * | DDR | Shared MBOX RAM + * 0x9de00000 +-----------------+ + * | DDR | Unallocated + * 0x87900000 +-----------------+ + * | DDR | BL33/U-BOOT + * 0x87800000 +-----------------+ + * | DDR | Unallocated + * 0x83101000 +-----------------+ + * | DDR | DTB Overlay + * 0x83100000 +-----------------+ + * | DDR | DTB + * 0x83000000 +-----------------+ + * | DDR | Unallocated + * 0x80100000 +-----------------+ + * | DDR | FIP + * 0x80000000 +-----------------+ + * | SOC I/0 | + * 0x00a00000 +-----------------+ + * | OCRAM | Not used + * 0x00900000 +-----------------+ + * | SOC I/0 | + * 0x00188000 +-----------------+ + * | OCRAM_S | Not used + * 0x00180000 +-----------------+ + * | SOC I/0 | + * 0x00020000 +-----------------+ + * | BootROM | BL1 + * 0x00000000 +-----------------+ + */ + +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) +#define MAX_MMAP_REGIONS 10 +#define MAX_XLAT_TABLES 6 +#define MAX_IO_DEVICES 2 +#define MAX_IO_HANDLES 3 +#define MAX_IO_BLOCK_DEVICES 1U + +/* UART defines */ +#if PLAT_WARP7_UART == 1 +#define PLAT_WARP7_UART_BASE MXC_UART1_BASE +#elif PLAT_WARP7_UART == 6 +#define IMX_UART_DTE +#define PLAT_WARP7_UART_BASE MXC_UART6_BASE +#else +#error "define PLAT_WARP7_UART=1 or PLAT_WARP7_UART=6" +#endif + +#define PLAT_IMX7_BOOT_UART_BASE PLAT_WARP7_UART_BASE +#define PLAT_IMX7_BOOT_UART_CLK_IN_HZ 24000000 +#define PLAT_IMX7_CONSOLE_BAUDRATE 115200 + +/* MMC defines */ +#ifndef PLAT_WARP7_SD +#define PLAT_WARP7_SD 3 +#endif + +#if PLAT_WARP7_SD == 1 +#define PLAT_WARP7_BOOT_MMC_BASE USDHC1_BASE +#endif /* PLAT_WARP7_SD == 1 */ + +#if PLAT_WARP7_SD == 2 +#define PLAT_WARP7_BOOT_MMC_BASE USDHC2_BASE +#endif /* PLAT_WARP7_SD == 2 */ + +#if PLAT_WARP7_SD == 3 +#define PLAT_WARP7_BOOT_MMC_BASE USDHC3_BASE +#endif /* PLAT_WARP7_SD == 3 */ + +/* + * System counter + */ +#define SYS_COUNTER_FREQ_IN_TICKS 8000000 /* 8 MHz */ + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/imx/imx7/warp7/platform.mk b/plat/imx/imx7/warp7/platform.mk new file mode 100644 index 0000000..ea0f001 --- /dev/null +++ b/plat/imx/imx7/warp7/platform.mk @@ -0,0 +1,37 @@ +# +# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# Include imx7 common +include plat/imx/imx7/common/imx7.mk + +# Platform +PLAT_INCLUDES += -Iplat/imx/imx7/warp7/include + +BL2_SOURCES += drivers/imx/usdhc/imx_usdhc.c \ + plat/imx/imx7/warp7/warp7_bl2_el3_setup.c + +# Build config flags +# ------------------ + +ARM_CORTEX_A7 := yes +WORKAROUND_CVE_2017_5715 := 0 + +RESET_TO_BL31 := 0 + +# Non-TF Boot ROM +BL2_AT_EL3 := 1 + +# Indicate single-core +COLD_BOOT_SINGLE_CPU := 1 + +# Have different sections for code and rodata +SEPARATE_CODE_AND_RODATA := 1 + +# Use Coherent memory +USE_COHERENT_MEM := 1 + +PLAT_WARP7_UART :=1 +$(eval $(call add_define,PLAT_WARP7_UART)) diff --git a/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c b/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c new file mode 100644 index 0000000..ec13ade --- /dev/null +++ b/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> + +#include <platform_def.h> + +#include <common/debug.h> +#include <drivers/console.h> +#include <drivers/mmc.h> +#include <lib/utils.h> + +#include <imx_caam.h> +#include <imx_clock.h> +#include <imx_io_mux.h> +#include <imx_uart.h> +#include <imx_usdhc.h> +#include <imx7_def.h> + +#define UART1_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ + CCM_TRGT_MUX_UART1_CLK_ROOT_OSC_24M) + +#define UART6_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ + CCM_TRGT_MUX_UART6_CLK_ROOT_OSC_24M) + +#define USDHC_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ + CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AHB |\ + CCM_TARGET_POST_PODF(2)) + +#define USB_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ + CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL) + +#define WARP7_UART1_TX_MUX \ + IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT0_UART1_TX_DATA + +#define WARP7_UART1_TX_FEATURES \ + (IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_3_100K_PU | \ + IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PE_EN | \ + IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_HYS_EN | \ + IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_1_X4) + +#define WARP7_UART1_RX_MUX \ + IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT0_UART1_RX_DATA + +#define WARP7_UART1_RX_FEATURES \ + (IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_3_100K_PU | \ + IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PE_EN | \ + IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_HYS_EN | \ + IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_1_X4) + +#define WARP7_UART6_TX_MUX \ + IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT1_UART6_TX_DATA + +#define WARP7_UART6_TX_FEATURES \ + (IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_3_100K_PU | \ + IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PE_EN | \ + IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_HYS_EN | \ + IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_1_X4) + +#define WARP7_UART6_RX_MUX \ + IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT1_UART6_RX_DATA + +#define WARP7_UART6_RX_FEATURES \ + (IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_3_100K_PU | \ + IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PE_EN | \ + IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_EN | \ + IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_1_X4) + +static struct mmc_device_info mmc_info; + +static void warp7_setup_pinmux(void) +{ + /* Configure UART1 TX */ + imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_OFFSET, + WARP7_UART1_TX_MUX); + imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_OFFSET, + WARP7_UART1_TX_FEATURES); + + /* Configure UART1 RX */ + imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_OFFSET, + WARP7_UART1_RX_MUX); + imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_OFFSET, + WARP7_UART1_RX_FEATURES); + + /* Configure UART6 TX */ + imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_OFFSET, + WARP7_UART6_TX_MUX); + imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_OFFSET, + WARP7_UART6_TX_FEATURES); + + /* Configure UART6 RX */ + imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_OFFSET, + WARP7_UART6_RX_MUX); + imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_OFFSET, + WARP7_UART6_RX_FEATURES); +} + +static void warp7_usdhc_setup(void) +{ + imx_usdhc_params_t params; + + zeromem(¶ms, sizeof(imx_usdhc_params_t)); + params.reg_base = PLAT_WARP7_BOOT_MMC_BASE; + params.clk_rate = 25000000; + params.bus_width = MMC_BUS_WIDTH_8; + mmc_info.mmc_dev_type = MMC_IS_EMMC; + imx_usdhc_init(¶ms, &mmc_info); +} + +static void warp7_setup_usb_clocks(void) +{ + uint32_t usb_en_bits = (uint32_t)USB_CLK_SELECT; + + imx_clock_set_usb_clk_root_bits(usb_en_bits); + imx_clock_enable_usb(CCM_CCGR_ID_USB_IPG); + imx_clock_enable_usb(CCM_CCGR_ID_USB_PHY_480MCLK); + imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG1_PHY); + imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG2_PHY); +} + +void imx7_platform_setup(u_register_t arg1, u_register_t arg2, + u_register_t arg3, u_register_t arg4) +{ + uint32_t uart1_en_bits = (uint32_t)UART1_CLK_SELECT; + uint32_t uart6_en_bits = (uint32_t)UART6_CLK_SELECT; + uint32_t usdhc_clock_sel = PLAT_WARP7_SD - 1; + + /* Initialize clocks etc */ + imx_clock_enable_uart(0, uart1_en_bits); + imx_clock_enable_uart(5, uart6_en_bits); + + imx_clock_enable_usdhc(usdhc_clock_sel, USDHC_CLK_SELECT); + + warp7_setup_usb_clocks(); + + /* Setup pin-muxes */ + warp7_setup_pinmux(); + + warp7_usdhc_setup(); +} |