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author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-28 09:13:47 +0000 |
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committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-28 09:13:47 +0000 |
commit | 102b0d2daa97dae68d3eed54d8fe37a9cc38a892 (patch) | |
tree | bcf648efac40ca6139842707f0eba5a4496a6dd2 /plat/marvell/octeontx/otx2/t91 | |
parent | Initial commit. (diff) | |
download | arm-trusted-firmware-upstream.tar.xz arm-trusted-firmware-upstream.zip |
Adding upstream version 2.8.0+dfsg.upstream/2.8.0+dfsgupstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to '')
7 files changed, 797 insertions, 0 deletions
diff --git a/plat/marvell/octeontx/otx2/t91/t9130/board/dram_port.c b/plat/marvell/octeontx/otx2/t91/t9130/board/dram_port.c new file mode 100644 index 0000000..82ce07b --- /dev/null +++ b/plat/marvell/octeontx/otx2/t91/t9130/board/dram_port.c @@ -0,0 +1,158 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#include <arch_helpers.h> +#include <common/debug.h> +#include <drivers/mentor/mi2cv.h> +#include <lib/mmio.h> + +#include <mv_ddr_if.h> +#include <mvebu_def.h> +#include <plat_marvell.h> + +#define MVEBU_CP_MPP_CTRL37_OFFS 20 +#define MVEBU_CP_MPP_CTRL38_OFFS 24 +#define MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA 0x2 +#define MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA 0x2 + +#define MVEBU_MPP_CTRL_MASK 0xf + +/* + * This struct provides the DRAM training code with + * the appropriate board DRAM configuration + */ +struct mv_ddr_iface dram_iface_ap0 = { + .ap_base = MVEBU_REGS_BASE_AP(0), + .state = MV_DDR_IFACE_NRDY, + .validation = MV_DDR_MEMORY_CHECK, + .sscg = SSCG_EN, + .id = 0, + .iface_base_addr = 0, + .tm = { + DEBUG_LEVEL_ERROR, + 0x1, /* active interfaces */ + /* cs_mask, mirror, dqs_swap, ck_swap X subphys */ + { { { {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0} }, + SPEED_BIN_DDR_2400T, /* speed_bin */ + MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */ + MV_DDR_DIE_CAP_8GBIT, /* die capacity */ + MV_DDR_FREQ_SAR, /* frequency */ + 0, 0, /* cas_l, cas_wl */ + MV_DDR_TEMP_LOW} }, /* temperature */ +#if DDR32 + MV_DDR_32BIT_ECC_PUP8_BUS_MASK, /* subphys mask */ +#else + MV_DDR_64BIT_ECC_PUP8_BUS_MASK, /* subphys mask */ +#endif + MV_DDR_CFG_SPD, /* ddr configuration data src */ + NOT_COMBINED, /* ddr twin-die combined*/ + { {0} }, /* raw spd data */ + {0}, /* timing parameters */ + { /* electrical configuration */ + { /* memory electrical configuration */ + MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ + { /* rtt_park 1cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, + /* rtt_park 2cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1 + }, + { /* rtt_wr 1cs */ + MV_DDR_RTT_WR_DYN_ODT_OFF, + /* rtt_wr 2cs */ + MV_DDR_RTT_WR_RZQ_DIV2 + }, + MV_DDR_DIC_RZQ_DIV7 /* dic */ + }, + { /* phy electrical configuration */ + MV_DDR_OHM_30, /* data_drv_p */ + MV_DDR_OHM_30, /* data_drv_n */ + MV_DDR_OHM_30, /* ctrl_drv_p */ + MV_DDR_OHM_30, /* ctrl_drv_n */ + { + MV_DDR_OHM_60, /* odt_p 1cs */ + MV_DDR_OHM_120 /* odt_p 2cs */ + }, + { + MV_DDR_OHM_60, /* odt_n 1cs */ + MV_DDR_OHM_120 /* odt_n 2cs */ + }, + }, + { /* mac electrical configuration */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ + MV_DDR_ODT_CFG_ALWAYS_ON,/* odtcfg_write */ + MV_DDR_ODT_CFG_NORMAL /* odtcfg_read */ + }, + }, + }, +}; + +/* Pointer to the first DRAM interface in the system */ +struct mv_ddr_iface *ptr_iface = &dram_iface_ap0; + +struct mv_ddr_iface *mv_ddr_iface_get(void) +{ + /* Return current ddr interface */ + return ptr_iface; +} + +struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) +{ + /* Return the board topology as defined in the board code */ + return &ptr_iface->tm; +} + +static void mpp_config(void) +{ + uintptr_t reg; + uint32_t val; + + reg = MVEBU_CP_MPP_REGS(0, 4); + /* configure CP0 MPP 37 and 38 to i2c */ + val = mmio_read_32(reg); + val &= ~((MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL37_OFFS) | + (MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL38_OFFS)); + val |= (MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA << + MVEBU_CP_MPP_CTRL37_OFFS) | + (MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA << + MVEBU_CP_MPP_CTRL38_OFFS); + mmio_write_32(reg, val); +} + +/* + * This function may modify the default DRAM parameters + * based on information received from SPD or bootloader + * configuration located on non volatile storage + */ +void plat_marvell_dram_update_topology(void) +{ + struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); + + INFO("Gathering DRAM information\n"); + + if (tm->cfg_src == MV_DDR_CFG_SPD) { + /* configure MPPs to enable i2c */ + mpp_config(); + + /* initialize i2c */ + i2c_init((void *)MVEBU_CP0_I2C_BASE); + + /* select SPD memory page 0 to access DRAM configuration */ + i2c_write(I2C_SPD_P0_ADDR, 0x0, 1, tm->spd_data.all_bytes, 0); + + /* read data from spd */ + i2c_read(I2C_SPD_ADDR, 0x0, 1, tm->spd_data.all_bytes, + sizeof(tm->spd_data.all_bytes)); + } +} diff --git a/plat/marvell/octeontx/otx2/t91/t9130/board/marvell_plat_config.c b/plat/marvell/octeontx/otx2/t91/t9130/board/marvell_plat_config.c new file mode 100644 index 0000000..fbacf54 --- /dev/null +++ b/plat/marvell/octeontx/otx2/t91/t9130/board/marvell_plat_config.c @@ -0,0 +1,192 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#include <armada_common.h> +#include <mvebu_def.h> + +/* + * If bootrom is currently at BLE there's no need to include the memory + * maps structure at this point + */ +#ifndef IMAGE_BLE + +/***************************************************************************** + * AMB Configuration + ***************************************************************************** + */ +struct addr_map_win amb_memory_map_cp0[] = { + /* CP0 SPI1 CS0 Direct Mode access */ + {0xe800, 0x2000000, AMB_SPI1_CS0_ID}, +}; + +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) +{ + switch (base) { + case MVEBU_CP_REGS_BASE(0): + *win = amb_memory_map_cp0; + *size = ARRAY_SIZE(amb_memory_map_cp0); + return 0; + case MVEBU_CP_REGS_BASE(1): + case MVEBU_CP_REGS_BASE(2): + default: + *size = 0; + *win = 0; + return 1; + } +} +#endif + +/***************************************************************************** + * IO WIN Configuration + ***************************************************************************** + */ +struct addr_map_win io_win_memory_map[] = { +#if (CP_COUNT > 1) + /* SB (MCi0) internal regs */ + {0x00000000f4000000, 0x2000000, MCI_0_TID}, +#if (CP_COUNT > 2) + /* SB (MCi1) internal regs */ + {0x00000000f6000000, 0x2000000, MCI_1_TID}, +#endif +#endif +#ifndef IMAGE_BLE + /* SB (MCi0) PCIe0-2 on CP1 */ + {0x00000000e2000000, 0x3000000, MCI_0_TID}, + /* SB (MCi1) PCIe0-2 on CP2 */ + {0x00000000e5000000, 0x3000000, MCI_1_TID}, + /* MCI 0 indirect window */ + {MVEBU_MCI_REG_BASE_REMAP(0), 0x100000, MCI_0_TID}, + /* MCI 1 indirect window */ + {MVEBU_MCI_REG_BASE_REMAP(1), 0x100000, MCI_1_TID}, +#endif +}; + +/* Global Control Register - window default target */ +uint32_t marvell_get_io_win_gcr_target(int ap_index) +{ + /* + * PIDI == iMCIP AP to SB internal MoChi connection. + * In other words CP0 + */ + return PIDI_TID; +} + +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) +{ + *win = io_win_memory_map; + if (*win == NULL) + *size = 0; + else + *size = ARRAY_SIZE(io_win_memory_map); + + return 0; +} + +#ifndef IMAGE_BLE +/***************************************************************************** + * IOB Configuration + ***************************************************************************** + */ +struct addr_map_win iob_memory_map_cp0[] = { + /* SPI1_CS0 (RUNIT) window */ + {0x00000000e8000000, 0x2000000, RUNIT_TID}, + /* PEX2_X1 window */ + {0x00000000e1000000, 0x1000000, PEX2_TID}, + /* PEX1_X1 window */ + {0x00000000e0000000, 0x1000000, PEX1_TID}, + /* PEX0_X4 window */ + {0x00000000c0000000, 0x20000000, PEX0_TID}, +}; + +struct addr_map_win iob_memory_map_cp1[] = { + + /* PEX2_X1 window */ + {0x00000000e4000000, 0x1000000, PEX2_TID}, + /* PEX1_X1 window */ + {0x00000000e3000000, 0x1000000, PEX1_TID}, + /* PEX0_X4 window */ + {0x00000000e2000000, 0x1000000, PEX0_TID}, +}; + +struct addr_map_win iob_memory_map_cp2[] = { + + /* PEX2_X1 window */ + {0x00000000e7000000, 0x1000000, PEX2_TID}, + /* PEX1_X1 window */ + {0x00000000e6000000, 0x1000000, PEX1_TID}, + /* PEX0_X4 window */ + {0x00000000e5000000, 0x1000000, PEX0_TID}, +}; + +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) +{ + switch (base) { + case MVEBU_CP_REGS_BASE(0): + *win = iob_memory_map_cp0; + *size = ARRAY_SIZE(iob_memory_map_cp0); + return 0; + case MVEBU_CP_REGS_BASE(1): + *win = iob_memory_map_cp1; + *size = ARRAY_SIZE(iob_memory_map_cp1); + return 0; + case MVEBU_CP_REGS_BASE(2): + *win = iob_memory_map_cp2; + *size = ARRAY_SIZE(iob_memory_map_cp2); + return 0; + default: + *size = 0; + *win = 0; + return 1; + } +} +#endif + +/***************************************************************************** + * CCU Configuration + ***************************************************************************** + */ +struct addr_map_win ccu_memory_map[] = { /* IO window */ +#ifdef IMAGE_BLE + {0x00000000f2000000, 0x6000000, IO_0_TID}, /* IO window */ +#else +#if LLC_SRAM + {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID}, +#endif + {0x00000000f2000000, 0xe000000, IO_0_TID}, /* IO window */ + {0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */ + {0x0000002000000000, 0x70e000000, IO_0_TID}, /* IO for CV-OS */ +#endif +}; + +uint32_t marvell_get_ccu_gcr_target(int ap) +{ + return DRAM_0_TID; +} + +int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) +{ + *win = ccu_memory_map; + *size = ARRAY_SIZE(ccu_memory_map); + + return 0; +} + +#ifdef IMAGE_BLE +/***************************************************************************** + * SKIP IMAGE Configuration + ***************************************************************************** + */ +void *plat_get_skip_image_data(void) +{ + /* No recovery button on CN-9130 board? */ + return NULL; +} +#endif diff --git a/plat/marvell/octeontx/otx2/t91/t9130/board/phy-porting-layer.h b/plat/marvell/octeontx/otx2/t91/t9130/board/phy-porting-layer.h new file mode 100644 index 0000000..6b55407 --- /dev/null +++ b/plat/marvell/octeontx/otx2/t91/t9130/board/phy-porting-layer.h @@ -0,0 +1,145 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#ifndef __PHY_PORTING_LAYER_H +#define __PHY_PORTING_LAYER_H + + +#define MAX_LANE_NR 6 +#define XFI_PARAMS static const struct xfi_params + + +XFI_PARAMS xfi_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = { + /* AP0 */ + { + /* CP 0 */ + { + { 0 }, /* Comphy0 not relevant*/ + { 0 }, /* Comphy1 not relevant*/ + { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf, + .align90 = 0x5f, + .g1_dfe_res = 0x2, .g1_amp = 0x1c, + .g1_emph = 0xe, + .g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1, + .g1_tx_emph_en = 0x1, + .g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1, + .g1_rx_selmufi = 0x0, + .g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2, + .valid = 1 }, /* Comphy2 */ + { 0 }, /* Comphy3 not relevant*/ + { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf, + .align90 = 0x5f, + .g1_dfe_res = 0x2, .g1_amp = 0x1c, + .g1_emph = 0xe, + .g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1, + .g1_tx_emph_en = 0x1, + .g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1, + .g1_rx_selmufi = 0x0, + .g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2, + .valid = 1 }, /* Comphy4 */ + { 0 }, /* Comphy5 not relevant*/ + }, +#if CP_NUM > 1 + /* CP 1 */ + { + { 0 }, /* Comphy0 not relevant*/ + { 0 }, /* Comphy1 not relevant*/ + { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf, + .align90 = 0x5f, + .g1_dfe_res = 0x2, .g1_amp = 0x1c, + .g1_emph = 0xe, + .g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1, + .g1_tx_emph_en = 0x1, + .g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1, + .g1_rx_selmufi = 0x0, + .g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2, + .valid = 1 }, /* Comphy2 */ + { 0 }, /* Comphy3 not relevant*/ + /* different from defaults */ + { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf, + .align90 = 0x5f, + .g1_dfe_res = 0x2, .g1_amp = 0xc, + .g1_emph = 0x5, + .g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1, + .g1_tx_emph_en = 0x1, + .g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1, + .g1_rx_selmufi = 0x0, + .g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2, + .valid = 1}, /* Comphy4 */ + { 0 }, /* Comphy5 not relevant*/ + }, +#if CP_NUM > 2 + /* CP 2 */ + { + { 0 }, /* Comphy0 not relevant*/ + { 0 }, /* Comphy1 not relevant*/ + { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf, + .align90 = 0x5f, + .g1_dfe_res = 0x2, .g1_amp = 0x1c, + .g1_emph = 0xe, + .g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1, + .g1_tx_emph_en = 0x1, + .g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1, + .g1_rx_selmufi = 0x0, + .g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2, + .valid = 1 }, /* Comphy2 */ + { 0 }, /* Comphy3 not relevant*/ + { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf, + .align90 = 0x5f, + .g1_dfe_res = 0x2, .g1_amp = 0x1c, + .g1_emph = 0xe, + .g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1, + .g1_tx_emph_en = 0x1, + .g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1, + .g1_rx_selmufi = 0x0, + .g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2, + .valid = 1 }, /* Comphy4 */ + { 0 }, /* Comphy5 not relevant*/ + }, +#endif +#endif + }, +}; + +#define SATA_PARAMS static const struct sata_params +SATA_PARAMS sata_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = { + [0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = { + .g1_amp = 0x8, .g2_amp = 0xa, + .g3_amp = 0x1e, + .g1_emph = 0x1, .g2_emph = 0x2, + .g3_emph = 0xe, + .g1_emph_en = 0x1, .g2_emph_en = 0x1, + .g3_emph_en = 0x1, + .g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1, + .g3_tx_amp_adj = 0x1, + .g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0, + .g3_tx_emph_en = 0x0, + .g1_tx_emph = 0x1, .g2_tx_emph = 0x1, + .g3_tx_emph = 0x1, + .g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4, + .g3_ffe_cap_sel = 0xf, + .align90 = 0x61, + .g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3, + .g3_rx_selmuff = 0x3, + .g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0, + .g3_rx_selmufi = 0x3, + .g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1, + .g3_rx_selmupf = 0x2, + .g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0, + .g3_rx_selmupi = 0x2, + .polarity_invert = COMPHY_POLARITY_NO_INVERT, + .valid = 0x1 + }, +}; + +static const struct usb_params + usb_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = { + [0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = { + .polarity_invert = COMPHY_POLARITY_NO_INVERT + }, +}; +#endif /* __PHY_PORTING_LAYER_H */ diff --git a/plat/marvell/octeontx/otx2/t91/t9130/mvebu_def.h b/plat/marvell/octeontx/otx2/t91/t9130/mvebu_def.h new file mode 100644 index 0000000..490be73 --- /dev/null +++ b/plat/marvell/octeontx/otx2/t91/t9130/mvebu_def.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#ifndef __MVEBU_DEF_H__ +#define __MVEBU_DEF_H__ + +#include <a8k_plat_def.h> + +/* + * CN-9130 has single CP0 inside the package and 2 additional one + * from MoChi interface. In case of db-9130-modular board the MCI interface + * is routed to: + * - on-board CP115 (MCI0) + * - extension board CP115 (MCI1) + */ +#define CP_COUNT CP_NUM +#define MVEBU_SOC_AP807 1 +#define I2C_SPD_ADDR 0x53 /* Access SPD data */ +#define I2C_SPD_P0_ADDR 0x36 /* Select SPD data page 0 */ + +#endif /* __MVEBU_DEF_H__ */ diff --git a/plat/marvell/octeontx/otx2/t91/t9130/platform.mk b/plat/marvell/octeontx/otx2/t91/t9130/platform.mk new file mode 100644 index 0000000..1e2716d --- /dev/null +++ b/plat/marvell/octeontx/otx2/t91/t9130/platform.mk @@ -0,0 +1,20 @@ +# +# Copyright (C) 2018 Marvell International Ltd. +# +# SPDX-License-Identifier: BSD-3-Clause +# https://spdx.org/licenses +# + +PCI_EP_SUPPORT := 0 + +CP_NUM := 1 +$(eval $(call add_define,CP_NUM)) + +DOIMAGE_SEC := tools/doimage/secure/sec_img_7K.cfg + +MARVELL_MOCHI_DRV := drivers/marvell/mochi/ap807_setup.c + +BOARD_DIR := $(shell dirname $(lastword $(MAKEFILE_LIST))) +include plat/marvell/armada/a8k/common/a8k_common.mk + +include plat/marvell/armada/common/marvell_common.mk diff --git a/plat/marvell/octeontx/otx2/t91/t9130_cex7_eval/board/marvell_plat_config.c b/plat/marvell/octeontx/otx2/t91/t9130_cex7_eval/board/marvell_plat_config.c new file mode 100644 index 0000000..5bae8eb --- /dev/null +++ b/plat/marvell/octeontx/otx2/t91/t9130_cex7_eval/board/marvell_plat_config.c @@ -0,0 +1,224 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * Copyright (C) 2021 Semihalf. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#include <armada_common.h> +#include <mvebu_def.h> + +/* + * If bootrom is currently at BLE there's no need to include the memory + * maps structure at this point + */ +#ifndef IMAGE_BLE + +/***************************************************************************** + * AMB Configuration + ***************************************************************************** + */ +struct addr_map_win amb_memory_map_cp0[] = { + /* CP0 SPI1 CS0 Direct Mode access */ + {0xef00, 0x1000000, AMB_SPI1_CS0_ID}, +}; + +struct addr_map_win amb_memory_map_cp1[] = { + /* CP1 SPI1 CS0 Direct Mode access */ + {0xe800, 0x1000000, AMB_SPI1_CS0_ID}, +}; + +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) +{ + switch (base) { + case MVEBU_CP_REGS_BASE(0): + *win = amb_memory_map_cp0; + *size = ARRAY_SIZE(amb_memory_map_cp0); + return 0; + case MVEBU_CP_REGS_BASE(1): + *win = amb_memory_map_cp1; + *size = ARRAY_SIZE(amb_memory_map_cp1); + return 0; + case MVEBU_CP_REGS_BASE(2): + default: + *size = 0; + *win = 0; + return 1; + } +} +#endif + +/***************************************************************************** + * IO WIN Configuration + ***************************************************************************** + */ +struct addr_map_win io_win_memory_map[] = { +#if (CP_COUNT > 1) + /* SB (MCi0) internal regs */ + {0x00000000f4000000, 0x2000000, MCI_0_TID}, + /* SB (MCi0) PCIe0-2 on CP1 */ + {0x00000000e2000000, 0x7000000, MCI_0_TID}, + /* + * Due to lack of sufficient number of IO windows registers, + * below CP1 PCIE configuration must be performed in the + * later firmware stages. It should replace the MCI 0 indirect + * window, which becomes no longer needed. + */ + /* {0x0000000890000000, 0x30000000, MCI_0_TID}, */ +#if (CP_COUNT > 2) + /* SB (MCi1) internal regs */ + {0x00000000f6000000, 0x2000000, MCI_1_TID}, + /* SB (MCi1) PCIe0-2 on CP2 */ + {0x00000000e9000000, 0x6000000, MCI_1_TID}, + /* + * Due to lack of sufficient number of IO windows registers, + * below CP2 PCIE configuration must be performed in the + * later firmware stages. It should replace the MCI 1 indirect + * window, which becomes no longer needed. + */ + /* {0x00000008c0000000, 0x30000000, MCI_1_TID}, */ +#endif +#endif +#ifndef IMAGE_BLE + /* MCI 0 indirect window */ + {MVEBU_MCI_REG_BASE_REMAP(0), 0x100000, MCI_0_TID}, + /* MCI 1 indirect window */ + {MVEBU_MCI_REG_BASE_REMAP(1), 0x100000, MCI_1_TID}, +#endif +}; + +/* Global Control Register - window default target */ +uint32_t marvell_get_io_win_gcr_target(int ap_index) +{ + /* + * PIDI == iMCIP AP to SB internal MoChi connection. + * In other words CP0 + */ + return PIDI_TID; +} + +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) +{ + *win = io_win_memory_map; + if (*win == NULL) + *size = 0; + else + *size = ARRAY_SIZE(io_win_memory_map); + + return 0; +} + +#ifndef IMAGE_BLE +/***************************************************************************** + * IOB Configuration + ***************************************************************************** + */ +struct addr_map_win iob_memory_map_cp0[] = { + /* SPI1_CS0 (RUNIT) window */ + {0x00000000ef000000, 0x1000000, RUNIT_TID}, + /* PEX2_X1 window */ + {0x00000000e1000000, 0x1000000, PEX2_TID}, + /* PEX1_X1 window */ + {0x00000000e0000000, 0x1000000, PEX1_TID}, + /* PEX0_X4 window */ + {0x00000000c0000000, 0x20000000, PEX0_TID}, + {0x0000000800000000, 0x90000000, PEX0_TID}, +}; + +struct addr_map_win iob_memory_map_cp1[] = { + /* SPI1_CS0 (RUNIT) window */ + {0x00000000e8000000, 0x1000000, RUNIT_TID}, + /* PEX2_X1 window */ + {0x00000000e6000000, 0x2000000, PEX2_TID}, + {0x00000008b0000000, 0x10000000, PEX2_TID}, + /* PEX1_X1 window */ + {0x00000000e4000000, 0x2000000, PEX1_TID}, + {0x00000008a0000000, 0x10000000, PEX1_TID}, + /* PEX0_X2 window */ + {0x00000000e2000000, 0x2000000, PEX0_TID}, + {0x0000000890000000, 0x10000000, PEX0_TID}, +}; + +struct addr_map_win iob_memory_map_cp2[] = { + + /* PEX2_X1 window */ + {0x00000000ed000000, 0x2000000, PEX2_TID}, + {0x00000008e0000000, 0x10000000, PEX2_TID}, + /* PEX1_X1 window */ + {0x00000000eb000000, 0x2000000, PEX1_TID}, + {0x00000008d0000000, 0x10000000, PEX1_TID}, + /* PEX0_X1 window */ + {0x00000000e9000000, 0x2000000, PEX0_TID}, + {0x00000008c0000000, 0x10000000, PEX0_TID}, +}; + +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) +{ + switch (base) { + case MVEBU_CP_REGS_BASE(0): + *win = iob_memory_map_cp0; + *size = ARRAY_SIZE(iob_memory_map_cp0); + return 0; + case MVEBU_CP_REGS_BASE(1): + *win = iob_memory_map_cp1; + *size = ARRAY_SIZE(iob_memory_map_cp1); + return 0; + case MVEBU_CP_REGS_BASE(2): + *win = iob_memory_map_cp2; + *size = ARRAY_SIZE(iob_memory_map_cp2); + return 0; + default: + *size = 0; + *win = 0; + return 1; + } +} +#endif + +/***************************************************************************** + * CCU Configuration + ***************************************************************************** + */ +struct addr_map_win ccu_memory_map[] = { /* IO window */ +#ifdef IMAGE_BLE + {0x00000000f2000000, 0x6000000, IO_0_TID}, /* IO window */ +#else +#if LLC_SRAM + {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID}, +#endif + {0x00000000f2000000, 0xe000000, IO_0_TID}, /* IO window */ + {0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */ + {0x0000000800000000, 0x100000000, IO_0_TID}, /* IO window */ + {0x0000002000000000, 0x70e000000, IO_0_TID}, /* IO for CV-OS */ +#endif +}; + +uint32_t marvell_get_ccu_gcr_target(int ap) +{ + return DRAM_0_TID; +} + +int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) +{ + *win = ccu_memory_map; + *size = ARRAY_SIZE(ccu_memory_map); + + return 0; +} + +#ifdef IMAGE_BLE +/***************************************************************************** + * SKIP IMAGE Configuration + ***************************************************************************** + */ +void *plat_get_skip_image_data(void) +{ + /* No recovery button on CN-9130 board? */ + return NULL; +} +#endif diff --git a/plat/marvell/octeontx/otx2/t91/t9130_cex7_eval/platform.mk b/plat/marvell/octeontx/otx2/t91/t9130_cex7_eval/platform.mk new file mode 100644 index 0000000..ee55455 --- /dev/null +++ b/plat/marvell/octeontx/otx2/t91/t9130_cex7_eval/platform.mk @@ -0,0 +1,33 @@ +# +# Copyright (C) 2018 Marvell International Ltd. +# Copyright (C) 2021 Semihalf. +# +# SPDX-License-Identifier: BSD-3-Clause +# https://spdx.org/licenses +# + +PCI_EP_SUPPORT := 0 + +CP_NUM := 1 +$(eval $(call add_define,CP_NUM)) + +DOIMAGE_SEC := tools/doimage/secure/sec_img_7K.cfg + +MARVELL_MOCHI_DRV := drivers/marvell/mochi/ap807_setup.c + +BOARD_DIR := $(shell dirname $(lastword $(MAKEFILE_LIST))) + +# +# CN913X CEx7 Evaluation Board shares the DRAM connectivity +# and SerDes settings with the CN913X DB - reuse relevant +# board-specific files. +# +T9130_DIR := $(BOARD_DIR)/../t9130 +PLAT_INCLUDES := -I$(T9130_DIR) \ + -I$(T9130_DIR)/board +BLE_PORTING_SOURCES := $(T9130_DIR)/board/dram_port.c \ + $(BOARD_DIR)/board/marvell_plat_config.c + +include plat/marvell/armada/a8k/common/a8k_common.mk + +include plat/marvell/armada/common/marvell_common.mk |