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authorDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-28 09:13:47 +0000
committerDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-28 09:13:47 +0000
commit102b0d2daa97dae68d3eed54d8fe37a9cc38a892 (patch)
treebcf648efac40ca6139842707f0eba5a4496a6dd2 /plat/mediatek/mt8183
parentInitial commit. (diff)
downloadarm-trusted-firmware-102b0d2daa97dae68d3eed54d8fe37a9cc38a892.tar.xz
arm-trusted-firmware-102b0d2daa97dae68d3eed54d8fe37a9cc38a892.zip
Adding upstream version 2.8.0+dfsg.upstream/2.8.0+dfsgupstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'plat/mediatek/mt8183')
-rw-r--r--plat/mediatek/mt8183/aarch64/plat_helpers.S34
-rw-r--r--plat/mediatek/mt8183/aarch64/platform_common.c84
-rw-r--r--plat/mediatek/mt8183/bl31_plat_setup.c181
-rw-r--r--plat/mediatek/mt8183/drivers/devapc/devapc.c231
-rw-r--r--plat/mediatek/mt8183/drivers/devapc/devapc.h499
-rw-r--r--plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.c147
-rw-r--r--plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.h106
-rw-r--r--plat/mediatek/mt8183/drivers/gpio/mtgpio.c439
-rw-r--r--plat/mediatek/mt8183/drivers/gpio/mtgpio.h154
-rw-r--r--plat/mediatek/mt8183/drivers/gpio/mtgpio_cfg.h208
-rw-r--r--plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.c259
-rw-r--r--plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.h34
-rw-r--r--plat/mediatek/mt8183/drivers/mcsi/mcsi.c211
-rw-r--r--plat/mediatek/mt8183/drivers/mcsi/mcsi.h116
-rw-r--r--plat/mediatek/mt8183/drivers/pmic/pmic.c42
-rw-r--r--plat/mediatek/mt8183/drivers/pmic/pmic.h30
-rw-r--r--plat/mediatek/mt8183/drivers/pmic/pmic_wrap_init.h94
-rw-r--r--plat/mediatek/mt8183/drivers/rtc/rtc.c133
-rw-r--r--plat/mediatek/mt8183/drivers/rtc/rtc.h147
-rw-r--r--plat/mediatek/mt8183/drivers/spm/spm.c363
-rw-r--r--plat/mediatek/mt8183/drivers/spm/spm.h2552
-rw-r--r--plat/mediatek/mt8183/drivers/spm/spm_pmic_wrap.c170
-rw-r--r--plat/mediatek/mt8183/drivers/spm/spm_pmic_wrap.h50
-rw-r--r--plat/mediatek/mt8183/drivers/spm/spm_suspend.c255
-rw-r--r--plat/mediatek/mt8183/drivers/spm/spm_suspend.h13
-rw-r--r--plat/mediatek/mt8183/drivers/spmc/mtspmc.c366
-rw-r--r--plat/mediatek/mt8183/drivers/spmc/mtspmc.h42
-rw-r--r--plat/mediatek/mt8183/drivers/spmc/mtspmc_private.h233
-rw-r--r--plat/mediatek/mt8183/drivers/sspm/sspm.c159
-rw-r--r--plat/mediatek/mt8183/drivers/sspm/sspm.h32
-rw-r--r--plat/mediatek/mt8183/drivers/timer/mt_timer.c29
-rw-r--r--plat/mediatek/mt8183/drivers/timer/mt_timer.h20
-rw-r--r--plat/mediatek/mt8183/include/mcucfg.h568
-rw-r--r--plat/mediatek/mt8183/include/mt_gic_v3.h34
-rw-r--r--plat/mediatek/mt8183/include/plat_dcm.h53
-rw-r--r--plat/mediatek/mt8183/include/plat_debug.h34
-rw-r--r--plat/mediatek/mt8183/include/plat_macros.S78
-rw-r--r--plat/mediatek/mt8183/include/plat_private.h28
-rw-r--r--plat/mediatek/mt8183/include/platform_def.h321
-rw-r--r--plat/mediatek/mt8183/include/power_tracer.h20
-rw-r--r--plat/mediatek/mt8183/include/scu.h13
-rw-r--r--plat/mediatek/mt8183/include/sspm_reg.h41
-rw-r--r--plat/mediatek/mt8183/plat_dcm.c112
-rw-r--r--plat/mediatek/mt8183/plat_debug.c58
-rw-r--r--plat/mediatek/mt8183/plat_mt_gic.c160
-rw-r--r--plat/mediatek/mt8183/plat_pm.c589
-rw-r--r--plat/mediatek/mt8183/plat_topology.c59
-rw-r--r--plat/mediatek/mt8183/platform.mk90
-rw-r--r--plat/mediatek/mt8183/scu.c56
49 files changed, 9747 insertions, 0 deletions
diff --git a/plat/mediatek/mt8183/aarch64/plat_helpers.S b/plat/mediatek/mt8183/aarch64/plat_helpers.S
new file mode 100644
index 0000000..5c39633
--- /dev/null
+++ b/plat/mediatek/mt8183/aarch64/plat_helpers.S
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <platform_def.h>
+
+ .globl plat_is_my_cpu_primary
+ .globl plat_my_core_pos
+
+func plat_is_my_cpu_primary
+ mrs x0, mpidr_el1
+ and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
+ cmp x0, #PLAT_PRIMARY_CPU
+ cset x0, eq
+ ret
+endfunc plat_is_my_cpu_primary
+
+ /* -----------------------------------------------------
+ * unsigned int plat_my_core_pos(void);
+ *
+ * result: CorePos = CoreId + (ClusterId << 2)
+ * -----------------------------------------------------
+ */
+func plat_my_core_pos
+ mrs x0, mpidr_el1
+ and x1, x0, #MPIDR_CPU_MASK
+ and x0, x0, #MPIDR_CLUSTER_MASK
+ add x0, x1, x0, LSR #6
+ ret
+endfunc plat_my_core_pos
diff --git a/plat/mediatek/mt8183/aarch64/platform_common.c b/plat/mediatek/mt8183/aarch64/platform_common.c
new file mode 100644
index 0000000..31d1339
--- /dev/null
+++ b/plat/mediatek/mt8183/aarch64/platform_common.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <mcsi/mcsi.h>
+#include <platform_def.h>
+#include <lib/utils.h>
+#include <lib/xlat_tables/xlat_tables.h>
+
+static const int cci_map[] = {
+ PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX,
+ PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX
+};
+
+/* Table of regions to map using the MMU. */
+const mmap_region_t plat_mmap[] = {
+ /* for TF text, RO, RW */
+ MAP_REGION_FLAT(TZRAM_BASE, TZRAM_SIZE,
+ MT_MEMORY | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(MTK_DEV_RNG2_BASE, MTK_DEV_RNG2_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE),
+ { 0 }
+};
+
+/*******************************************************************************
+ * Macro generating the code for the function setting up the pagetables as per
+ * the platform memory map & initialize the mmu, for the given exception level
+ ******************************************************************************/
+void plat_configure_mmu_el3(uintptr_t total_base,
+ uintptr_t total_size,
+ uintptr_t ro_start,
+ uintptr_t ro_limit,
+ uintptr_t coh_start,
+ uintptr_t coh_limit)
+{
+ mmap_add_region(total_base, total_base, total_size,
+ MT_MEMORY | MT_RW | MT_SECURE);
+ mmap_add_region(ro_start, ro_start, ro_limit - ro_start,
+ MT_MEMORY | MT_RO | MT_SECURE);
+ mmap_add_region(coh_start, coh_start, coh_limit - coh_start,
+ MT_DEVICE | MT_RW | MT_SECURE);
+ mmap_add(plat_mmap);
+ init_xlat_tables();
+ enable_mmu_el3(0);
+}
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+ return SYS_COUNTER_FREQ_IN_TICKS;
+}
+
+void plat_mtk_cci_init(void)
+{
+ /* Initialize CCI driver */
+ mcsi_init(PLAT_MT_CCI_BASE, ARRAY_SIZE(cci_map));
+}
+
+void plat_mtk_cci_enable(void)
+{
+ /* Enable CCI coherency for this cluster.
+ * No need for locks as no other cpu is active at the moment.
+ */
+ cci_enable_cluster_coherency(read_mpidr());
+}
+
+void plat_mtk_cci_disable(void)
+{
+ cci_disable_cluster_coherency(read_mpidr());
+}
+
+void plat_mtk_cci_init_sf(void)
+{
+ /* Init mcsi snoop filter. */
+ cci_init_sf();
+}
diff --git a/plat/mediatek/mt8183/bl31_plat_setup.c b/plat/mediatek/mt8183/bl31_plat_setup.c
new file mode 100644
index 0000000..7dac8a4
--- /dev/null
+++ b/plat/mediatek/mt8183/bl31_plat_setup.c
@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <arch_helpers.h>
+#include <common/bl_common.h>
+#include <common/desc_image_load.h>
+#include <devapc.h>
+#include <emi_mpu.h>
+#include <plat/common/common_def.h>
+#include <drivers/console.h>
+#include <common/debug.h>
+#include <drivers/generic_delay_timer.h>
+#include <mcucfg.h>
+#include <mt_gic_v3.h>
+#include <mt_timer.h>
+#include <lib/coreboot.h>
+#include <lib/mmio.h>
+#include <mtk_mcdi.h>
+#include <mtk_plat_common.h>
+#include <mtspmc.h>
+#include <plat_debug.h>
+#include <plat_params.h>
+#include <plat_private.h>
+#include <platform_def.h>
+#include <scu.h>
+#include <spm.h>
+#include <drivers/ti/uart/uart_16550.h>
+
+static entry_point_info_t bl32_ep_info;
+static entry_point_info_t bl33_ep_info;
+
+static void platform_setup_cpu(void)
+{
+ mmio_write_32((uintptr_t)&mt8183_mcucfg->mp0_rw_rsvd0, 0x00000001);
+
+ /* Mcusys dcm control */
+ /* Enable pll plldiv dcm */
+ mmio_setbits_32((uintptr_t)&mt8183_mcucfg->bus_pll_divider_cfg,
+ BUS_PLLDIV_DCM);
+ mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_pll_divider_cfg,
+ MP0_PLLDIV_DCM);
+ mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp2_pll_divider_cfg,
+ MP2_PLLDIV_DCM);
+ /* Enable mscib dcm */
+ mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en,
+ MCSIB_CACTIVE_SEL_MASK, MCSIB_CACTIVE_SEL);
+ mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en,
+ MCSIB_DCM_MASK, MCSIB_DCM);
+ /* Enable adb400 dcm */
+ mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->cci_adb400_dcm_config,
+ CCI_ADB400_DCM_MASK, CCI_ADB400_DCM);
+ /* Enable bus clock dcm */
+ mmio_setbits_32((uintptr_t)&mt8183_mcucfg->cci_clk_ctrl,
+ MCU_BUS_DCM);
+ /* Enable bus fabric dcm */
+ mmio_clrsetbits_32(
+ (uintptr_t)&mt8183_mcucfg->mcusys_bus_fabric_dcm_ctrl,
+ MCUSYS_BUS_FABRIC_DCM_MASK,
+ MCUSYS_BUS_FABRIC_DCM);
+ /* Enable l2c sram dcm */
+ mmio_setbits_32((uintptr_t)&mt8183_mcucfg->l2c_sram_ctrl,
+ L2C_SRAM_DCM);
+ /* Enable busmp0 sync dcm */
+ mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_config,
+ SYNC_DCM_MASK, SYNC_DCM);
+ /* Enable cntvalue dcm */
+ mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mcu_misc_dcm_ctrl,
+ CNTVALUEB_DCM);
+ /* Enable dcm cluster stall */
+ mmio_clrsetbits_32(
+ (uintptr_t)&mt8183_mcucfg->sync_dcm_cluster_config,
+ MCUSYS_MAX_ACCESS_LATENCY_MASK,
+ MCUSYS_MAX_ACCESS_LATENCY);
+ mmio_setbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_cluster_config,
+ MCU0_SYNC_DCM_STALL_WR_EN);
+ /* Enable rgu dcm */
+ mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_rgu_dcm_config,
+ CPUSYS_RGU_DCM_CINFIG);
+}
+
+/*******************************************************************************
+ * Return a pointer to the 'entry_point_info' structure of the next image for
+ * the security state specified. BL33 corresponds to the non-secure image type
+ * while BL32 corresponds to the secure image type. A NULL pointer is returned
+ * if the image does not exist.
+ ******************************************************************************/
+entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
+{
+ entry_point_info_t *next_image_info;
+
+ next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
+ assert(next_image_info->h.type == PARAM_EP);
+
+ /* None of the images on this platform can have 0x0 as the entrypoint */
+ if (next_image_info->pc)
+ return next_image_info;
+ else
+ return NULL;
+}
+
+/*******************************************************************************
+ * Perform any BL31 early platform setup. Here is an opportunity to copy
+ * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
+ * are lost (potentially). This needs to be done before the MMU is initialized
+ * so that the memory layout can be used while creating page tables.
+ * BL2 has flushed this information to memory, so we are guaranteed to pick up
+ * good data.
+ ******************************************************************************/
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
+{
+ static console_t console;
+
+ params_early_setup(arg1);
+
+#if COREBOOT
+ if (coreboot_serial.type)
+ console_16550_register(coreboot_serial.baseaddr,
+ coreboot_serial.input_hertz,
+ coreboot_serial.baud,
+ &console);
+#else
+ console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console);
+#endif
+
+ NOTICE("MT8183 bl31_setup\n");
+
+ bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info);
+}
+
+
+/*******************************************************************************
+ * Perform any BL31 platform setup code
+ ******************************************************************************/
+void bl31_platform_setup(void)
+{
+ devapc_init();
+
+ emi_mpu_init();
+
+ platform_setup_cpu();
+ generic_delay_timer_init();
+
+ /* Initialize the GIC driver, CPU and distributor interfaces */
+ mt_gic_driver_init();
+ mt_gic_init();
+
+ mt_systimer_init();
+
+ /* Init mcsi SF */
+ plat_mtk_cci_init_sf();
+
+#if SPMC_MODE == 1
+ spmc_init();
+#endif
+ spm_boot_init();
+ mcdi_init();
+}
+
+/*******************************************************************************
+ * Perform the very early platform specific architectural setup here. At the
+ * moment this is only intializes the mmu in a quick and dirty way.
+ ******************************************************************************/
+void bl31_plat_arch_setup(void)
+{
+ plat_mtk_cci_init();
+ plat_mtk_cci_enable();
+
+ enable_scu(read_mpidr());
+
+ plat_configure_mmu_el3(BL_CODE_BASE,
+ BL_COHERENT_RAM_END - BL_CODE_BASE,
+ BL_CODE_BASE,
+ BL_CODE_END,
+ BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END);
+}
diff --git a/plat/mediatek/mt8183/drivers/devapc/devapc.c b/plat/mediatek/mt8183/drivers/devapc/devapc.c
new file mode 100644
index 0000000..9d76aa5
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/devapc/devapc.c
@@ -0,0 +1,231 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <devapc.h>
+#include <drivers/console.h>
+#include <lib/mmio.h>
+
+static void set_master_transaction(uint32_t master_index,
+ enum TRANSACTION transaction_type)
+{
+ uintptr_t base;
+ uint32_t master_register_index;
+ uint32_t master_set_index;
+ uint32_t set_bit;
+
+ master_register_index = master_index / (MOD_NO_IN_1_DEVAPC * 2);
+ master_set_index = master_index % (MOD_NO_IN_1_DEVAPC * 2);
+
+ base = DEVAPC_INFRA_MAS_SEC_0 + master_register_index * 4;
+
+ set_bit = 0x1 << master_set_index;
+ if (transaction_type == SECURE_TRANSACTION)
+ mmio_setbits_32(base, set_bit);
+ else
+ mmio_clrbits_32(base, set_bit);
+}
+
+static void set_master_domain(uint32_t master_index, enum MASK_DOM domain)
+{
+ uintptr_t base;
+ uint32_t domain_reg;
+ uint32_t domain_index;
+ uint32_t clr_bit;
+ uint32_t set_bit;
+
+ domain_reg = master_index / MASTER_MOD_NO_IN_1_DEVAPC;
+ domain_index = master_index % MASTER_MOD_NO_IN_1_DEVAPC;
+ clr_bit = 0xF << (4 * domain_index);
+ set_bit = domain << (4 * domain_index);
+
+ base = DEVAPC_INFRA_MAS_DOM_0 + domain_reg * 4;
+ mmio_clrsetbits_32(base, clr_bit, set_bit);
+}
+
+static void set_master_domain_remap_infra(enum MASK_DOM domain_emi_view,
+ enum MASK_DOM domain_infra_view)
+{
+ uintptr_t base;
+ uint32_t clr_bit;
+ uint32_t set_bit;
+
+ if (domain_emi_view < DOMAIN_10) {
+ base = DEVAPC_INFRA_DOM_RMP_0;
+ clr_bit = 0x7 << (domain_emi_view * 3);
+ set_bit = domain_infra_view << (domain_emi_view * 3);
+ mmio_clrsetbits_32(base, clr_bit, set_bit);
+ } else if (domain_emi_view > DOMAIN_10) {
+ base = DEVAPC_INFRA_DOM_RMP_1;
+ domain_emi_view = domain_emi_view - DOMAIN_11;
+ clr_bit = 0x7 << (domain_emi_view * 3 + 1);
+ set_bit = domain_infra_view << (domain_emi_view * 3 + 1);
+ mmio_clrsetbits_32(base, clr_bit, set_bit);
+ } else {
+ base = DEVAPC_INFRA_DOM_RMP_0;
+ clr_bit = 0x3 << (domain_emi_view * 3);
+ set_bit = domain_infra_view << (domain_emi_view * 3);
+ mmio_clrsetbits_32(base, clr_bit, set_bit);
+
+ base = DEVAPC_INFRA_DOM_RMP_1;
+ set_bit = (domain_infra_view & 0x4) >> 2;
+ mmio_clrsetbits_32(base, 0x1, set_bit);
+ }
+}
+
+static void set_master_domain_remap_mm(enum MASK_DOM domain_emi_view,
+ enum MASK_DOM domain_mm_view)
+{
+ uintptr_t base;
+ uint32_t clr_bit;
+ uint32_t set_bit;
+
+ base = DEVAPC_MM_DOM_RMP_0;
+ clr_bit = 0x3 << (domain_emi_view * 2);
+ set_bit = domain_mm_view << (domain_emi_view * 2);
+
+ mmio_clrsetbits_32(base, clr_bit, set_bit);
+}
+
+static void set_module_apc(enum DAPC_SLAVE_TYPE slave_type, uint32_t module,
+ enum MASK_DOM domain_num,
+ enum APC_ATTR permission_control)
+{
+ uintptr_t base;
+ uint32_t apc_index;
+ uint32_t apc_set_index;
+ uint32_t clr_bit;
+ uint32_t set_bit;
+
+ apc_index = module / MOD_NO_IN_1_DEVAPC;
+ apc_set_index = module % MOD_NO_IN_1_DEVAPC;
+ clr_bit = 0x3 << (apc_set_index * 2);
+ set_bit = permission_control << (apc_set_index * 2);
+
+ if (slave_type == DAPC_INFRA_SLAVE && module <= SLAVE_INFRA_MAX_INDEX)
+ base = DEVAPC_INFRA_D0_APC_0 + domain_num * 0x100 +
+ apc_index * 4;
+ else if (slave_type == DAPC_MM_SLAVE && module <= SLAVE_MM_MAX_INDEX)
+ base = DEVAPC_MM_D0_APC_0 + domain_num * 0x100 + apc_index * 4;
+ else
+ return;
+
+ mmio_clrsetbits_32(base, clr_bit, set_bit);
+}
+
+static void set_default_master_transaction(void)
+{
+ set_master_transaction(MASTER_SSPM, SECURE_TRANSACTION);
+}
+
+static void set_default_master_domain(void)
+{
+ set_master_domain(MASTER_SCP, DOMAIN_1);
+ set_master_domain_remap_infra(DOMAIN_1, DOMAIN_1);
+ set_master_domain_remap_mm(DOMAIN_1, DOMAIN_1);
+
+ set_master_domain(MASTER_SPM, DOMAIN_2);
+ set_master_domain_remap_infra(DOMAIN_2, DOMAIN_2);
+ set_master_domain_remap_mm(DOMAIN_2, DOMAIN_2);
+
+ set_master_domain(MASTER_SSPM, DOMAIN_2);
+ set_master_domain_remap_infra(DOMAIN_2, DOMAIN_2);
+ set_master_domain_remap_mm(DOMAIN_2, DOMAIN_2);
+}
+
+static void set_default_slave_permission(void)
+{
+ uint32_t module_index;
+ uint32_t infra_size;
+ uint32_t mm_size;
+
+ infra_size = sizeof(D_APC_INFRA_Devices) / sizeof(struct DEVICE_INFO);
+ mm_size = sizeof(D_APC_MM_Devices) / sizeof(struct DEVICE_INFO);
+
+ for (module_index = 0; module_index < infra_size; module_index++) {
+ if (D_APC_INFRA_Devices[module_index].d0_permission > 0) {
+ set_module_apc(DAPC_INFRA_SLAVE, module_index, DOMAIN_0,
+ D_APC_INFRA_Devices[module_index].d0_permission);
+ }
+ if (D_APC_INFRA_Devices[module_index].d1_permission > 0) {
+ set_module_apc(DAPC_INFRA_SLAVE, module_index, DOMAIN_1,
+ D_APC_INFRA_Devices[module_index].d1_permission);
+ }
+ if (D_APC_INFRA_Devices[module_index].d2_permission > 0) {
+ set_module_apc(DAPC_INFRA_SLAVE, module_index, DOMAIN_2,
+ D_APC_INFRA_Devices[module_index].d2_permission);
+ }
+ }
+
+ for (module_index = 0; module_index < mm_size; module_index++) {
+ if (D_APC_MM_Devices[module_index].d0_permission > 0) {
+ set_module_apc(DAPC_MM_SLAVE, module_index, DOMAIN_0,
+ D_APC_MM_Devices[module_index].d0_permission);
+ }
+ if (D_APC_MM_Devices[module_index].d1_permission > 0) {
+ set_module_apc(DAPC_MM_SLAVE, module_index, DOMAIN_1,
+ D_APC_MM_Devices[module_index].d1_permission);
+ }
+ if (D_APC_MM_Devices[module_index].d2_permission > 0) {
+ set_module_apc(DAPC_MM_SLAVE, module_index, DOMAIN_2,
+ D_APC_MM_Devices[module_index].d2_permission);
+ }
+ }
+}
+
+static void dump_devapc(void)
+{
+ int i;
+
+ INFO("[DEVAPC] dump DEVAPC registers:\n");
+
+ for (i = 0; i < 13; i++) {
+ INFO("[DEVAPC] (INFRA)D0_APC_%d = 0x%x, "
+ "(INFRA)D1_APC_%d = 0x%x, "
+ "(INFRA)D2_APC_%d = 0x%x\n",
+ i, mmio_read_32(DEVAPC_INFRA_D0_APC_0 + i * 4),
+ i, mmio_read_32(DEVAPC_INFRA_D0_APC_0 + 0x100 + i * 4),
+ i, mmio_read_32(DEVAPC_INFRA_D0_APC_0 + 0x200 + i * 4));
+ }
+
+ for (i = 0; i < 9; i++) {
+ INFO("[DEVAPC] (MM)D0_APC_%d = 0x%x, "
+ "(MM)D1_APC_%d = 0x%x, "
+ "(MM)D2_APC_%d = 0x%x\n",
+ i, mmio_read_32(DEVAPC_MM_D0_APC_0 + i * 4),
+ i, mmio_read_32(DEVAPC_MM_D0_APC_0 + 0x100 + i * 4),
+ i, mmio_read_32(DEVAPC_MM_D0_APC_0 + 0x200 + i * 4));
+ }
+
+ for (i = 0; i < 4; i++) {
+ INFO("[DEVAPC] MAS_DOM_%d = 0x%x\n", i,
+ mmio_read_32(DEVAPC_INFRA_MAS_DOM_0 + i * 4));
+ }
+
+ INFO("[DEVAPC] MAS_SEC_0 = 0x%x\n",
+ mmio_read_32(DEVAPC_INFRA_MAS_SEC_0));
+
+ INFO("[DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x%x, "
+ "(INFRA)MAS_DOMAIN_REMAP_1 = 0x%x\n",
+ mmio_read_32(DEVAPC_INFRA_DOM_RMP_0),
+ mmio_read_32(DEVAPC_INFRA_DOM_RMP_1));
+
+ INFO("[DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x%x\n",
+ mmio_read_32(DEVAPC_MM_DOM_RMP_0));
+}
+
+void devapc_init(void)
+{
+ mmio_write_32(DEVAPC_INFRA_APC_CON, 0x80000001);
+ mmio_write_32(DEVAPC_MM_APC_CON, 0x80000001);
+ mmio_write_32(DEVAPC_MD_APC_CON, 0x80000001);
+
+ set_default_master_transaction();
+ set_default_master_domain();
+ set_default_slave_permission();
+ dump_devapc();
+}
+
diff --git a/plat/mediatek/mt8183/drivers/devapc/devapc.h b/plat/mediatek/mt8183/drivers/devapc/devapc.h
new file mode 100644
index 0000000..042a8ff
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/devapc/devapc.h
@@ -0,0 +1,499 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DEVAPC_H
+#define DEVAPC_H
+
+#include <stdint.h>
+
+#define DEVAPC_AO_INFRA_BASE 0x1000E000
+#define DEVAPC_AO_MM_BASE 0x1001C000
+#define DEVAPC_AO_MD_BASE 0x10019000
+
+#define DEVAPC_INFRA_D0_APC_0 (DEVAPC_AO_INFRA_BASE + 0x0000)
+#define DEVAPC_INFRA_MAS_DOM_0 (DEVAPC_AO_INFRA_BASE + 0x0A00)
+#define DEVAPC_INFRA_MAS_SEC_0 (DEVAPC_AO_INFRA_BASE + 0x0B00)
+#define DEVAPC_INFRA_DOM_RMP_0 (DEVAPC_AO_INFRA_BASE + 0x0D00)
+#define DEVAPC_INFRA_DOM_RMP_1 (DEVAPC_AO_INFRA_BASE + 0x0D04)
+#define DEVAPC_INFRA_APC_CON (DEVAPC_AO_INFRA_BASE + 0x0F00)
+
+#define DEVAPC_MD_APC_CON (DEVAPC_AO_MD_BASE + 0x0F00)
+
+#define DEVAPC_MM_D0_APC_0 (DEVAPC_AO_MM_BASE + 0x0000)
+#define DEVAPC_MM_DOM_RMP_0 (DEVAPC_AO_MM_BASE + 0x0D00)
+#define DEVAPC_MM_APC_CON (DEVAPC_AO_MM_BASE + 0x0F00)
+
+#define MOD_NO_IN_1_DEVAPC 16
+#define MASTER_MOD_NO_IN_1_DEVAPC 8
+#define SLAVE_INFRA_MAX_INDEX 195
+#define SLAVE_MM_MAX_INDEX 140
+
+enum {
+ MASTER_SCP = 0,
+ MASTER_SPM = 10,
+ MASTER_SSPM = 27
+};
+
+enum MASK_DOM {
+ DOMAIN_0 = 0,
+ DOMAIN_1,
+ DOMAIN_2,
+ DOMAIN_3,
+ DOMAIN_4,
+ DOMAIN_5,
+ DOMAIN_6,
+ DOMAIN_7,
+ DOMAIN_8,
+ DOMAIN_9,
+ DOMAIN_10,
+ DOMAIN_11
+};
+
+enum TRANSACTION {
+ NON_SECURE_TRANSACTION = 0,
+ SECURE_TRANSACTION
+};
+
+enum DAPC_SLAVE_TYPE {
+ DAPC_INFRA_SLAVE = 0,
+ DAPC_MM_SLAVE
+};
+
+enum APC_ATTR {
+ NO_SEC = 0,
+ S_RW_ONLY,
+ S_RW_NS_R,
+ FORBID,
+};
+
+struct DEVICE_INFO {
+ uint8_t d0_permission;
+ uint8_t d1_permission;
+ uint8_t d2_permission;
+};
+
+#define PERMISSION(DEV_NAME, ATTR1, ATTR2, ATTR3) \
+{(uint8_t)ATTR1, (uint8_t)ATTR2, (uint8_t)ATTR3}
+
+static const struct DEVICE_INFO D_APC_INFRA_Devices[] = {
+/* module, domain0, domain1, domain2 */
+
+/* 0 */
+PERMISSION("INFRA_AO_TOPCKGEN", NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("INFRA_AO_INFRASYS_CONFIG_REGS", NO_SEC, FORBID, NO_SEC),
+PERMISSION("IO_CFG", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_PERICFG", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_EFUSE_AO_DEBUG", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_GPIO", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_SLEEP_CONTROLLER", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_TOPRGU", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_APXGPT", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_RESERVE", NO_SEC, FORBID, NO_SEC),
+
+/* 10 */
+PERMISSION("INFRA_AO_SEJ", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_AP_CIRQ_EINT", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_APMIXEDSYS", NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("INFRA_AO_PMIC_WRAP", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_DEVICE_APC_AO_INFRA_PERI", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_SLEEP_CONTROLLER_MD", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_KEYPAD", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_TOP_MISC", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_DVFS_CTRL_PROC", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_MBIST_AO_REG", NO_SEC, FORBID, NO_SEC),
+
+/* 20 */
+PERMISSION("INFRA_AO_CLDMA_AO_AP", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_DEVICE_MPU", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_AES_TOP_0", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_SYS_TIMER", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_MDEM_TEMP_SHARE", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_DEVICE_APC_AO_MD", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_SECURITY_AO", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_TOPCKGEN_REG", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_DEVICE_APC_AO_MM", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_RESERVE", NO_SEC, FORBID, NO_SEC),
+
+/* 30 */
+PERMISSION("INFRASYS_RESERVE", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_RESERVE", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_RESERVE", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_SYS_CIRQ", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_MM_IOMMU", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_EFUSE_PDN_DEBUG", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_DEVICE_APC", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_DBG_TRACKER", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_CCIF0_AP", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_CCIF0_MD", NO_SEC, FORBID, NO_SEC),
+
+/* 40 */
+PERMISSION("INFRASYS_CCIF1_AP", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_CCIF1_MD", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_MBIST", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_INFRA_PDN_REGISTER", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_TRNG", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_DX_CC", NO_SEC, FORBID, NO_SEC),
+PERMISSION("MD_CCIF_MD1", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_CQ_DMA", NO_SEC, FORBID, NO_SEC),
+PERMISSION("MD_CCIF_MD2", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_SRAMROM", NO_SEC, FORBID, NO_SEC),
+
+/* 50 */
+PERMISSION("ANA_MIPI_DSI0", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_RESERVE", NO_SEC, FORBID, NO_SEC),
+PERMISSION("ANA_MIPI_CSI0", NO_SEC, FORBID, NO_SEC),
+PERMISSION("ANA_MIPI_CSI1", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_EMI", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_RESERVE", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_CLDMA_PDN", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CLDMA_PDN_MD_MISC", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_MD", NO_SEC, FORBID, NO_SEC),
+PERMISSION("BPI_BSI_SLV0", NO_SEC, FORBID, NO_SEC),
+
+/* 60 */
+PERMISSION("BPI_BSI_SLV1", NO_SEC, FORBID, NO_SEC),
+PERMISSION("BPI_BSI_SLV2", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_EMI_MPU", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_DVFS_PROC", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_DRAMC_CH0_TOP0", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_DRAMC_CH0_TOP1", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_DRAMC_CH0_TOP2", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_DRAMC_CH0_TOP3", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_DRAMC_CH0_TOP4", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_DRAMC_CH1_TOP0", NO_SEC, FORBID, NO_SEC),
+
+/* 70 */
+PERMISSION("INFRASYS_DRAMC_CH1_TOP1", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_DRAMC_CH1_TOP2", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_DRAMC_CH1_TOP3", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_DRAMC_CH1_TOP4", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_GCE", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_CCIF2_AP", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_CCIF2_MD", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_CCIF3_AP", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_CCIF3_MD", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_PWRMCU Partition 1", S_RW_NS_R, FORBID, NO_SEC),
+
+/* 80 */
+PERMISSION("INFRA_AO_PWRMCU Partition 2", S_RW_NS_R, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_PWRMCU Partition 3", S_RW_NS_R, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_PWRMCU Partition 4", S_RW_NS_R, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_PWRMCU Partition 5", S_RW_NS_R, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_PWRMCU Partition 6", S_RW_NS_R, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_PWRMCU Partition 7", S_RW_NS_R, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_PWRMCU Partition 8", S_RW_NS_R, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_SCP", NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("INFRA_AO_MCUCFG", NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_DBUGSYS", NO_SEC, FORBID, NO_SEC),
+
+/* 90 */
+PERMISSION("PERISYS_APDMA", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_AUXADC", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_UART0", NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("PERISYS_UART1", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_UART2", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_I2C6", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_PWM", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_I2C0", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_I2C1", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_I2C2", NO_SEC, FORBID, NO_SEC),
+
+/* 100 */
+PERMISSION("PERISYS_SPI0", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_PTP", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_BTIF", NO_SEC, FORBID, NO_SEC),
+PERMISSION("RESERVE", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_DISP_PWM", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_I2C3", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_SPI1", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_I2C4", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_SPI2", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_SPI3", NO_SEC, FORBID, NO_SEC),
+
+/* 110 */
+PERMISSION("PERISYS_I2C1_IMM", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_I2C2_IMM", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_I2C5", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_I2C5_IMM", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_SPI4", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_SPI5", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_I2C7", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_I2C8", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_USB", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_USB_2_0_SUB", NO_SEC, FORBID, NO_SEC),
+
+/* 120 */
+PERMISSION("PERISYS_AUDIO", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_MSDC0", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_MSDC1", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_MSDC2", NO_SEC, FORBID, NO_SEC),
+PERMISSION("RESERVE", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_UFS", NO_SEC, FORBID, NO_SEC),
+PERMISSION("RESERVE", NO_SEC, FORBID, NO_SEC),
+PERMISSION("RESERVE", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_RESERVE", NO_SEC, FORBID, NO_SEC),
+PERMISSION("EAST_RESERVE_0", NO_SEC, FORBID, NO_SEC),
+
+/* 130 */
+PERMISSION("EAST_RESERVE_1", NO_SEC, FORBID, NO_SEC),
+PERMISSION("EAST_RESERVE_2", NO_SEC, FORBID, NO_SEC),
+PERMISSION("EAST_RESERVE_3", NO_SEC, FORBID, NO_SEC),
+PERMISSION("EAST_RESERVE_4", NO_SEC, FORBID, NO_SEC),
+PERMISSION("EAST_IO_CFG_RT", NO_SEC, FORBID, NO_SEC),
+PERMISSION("EAST_RESERVE_6", NO_SEC, FORBID, NO_SEC),
+PERMISSION("EAST_RESERVE_7", NO_SEC, FORBID, NO_SEC),
+PERMISSION("EAST_CSI0_TOP_AO", NO_SEC, FORBID, NO_SEC),
+PERMISSION("RESERVE", NO_SEC, FORBID, NO_SEC),
+PERMISSION("EAST_RESERVE_A", NO_SEC, FORBID, NO_SEC),
+
+/* 140 */
+PERMISSION("EAST_RESERVE_B", NO_SEC, FORBID, NO_SEC),
+PERMISSION("EAST_RESERVE_C", NO_SEC, FORBID, NO_SEC),
+PERMISSION("EAST_RESERVE_D", NO_SEC, FORBID, NO_SEC),
+PERMISSION("EAST_RESERVE_E", NO_SEC, FORBID, NO_SEC),
+PERMISSION("EAST_RESERVE_F", NO_SEC, FORBID, NO_SEC),
+PERMISSION("SOUTH_RESERVE_0", NO_SEC, FORBID, NO_SEC),
+PERMISSION("SOUTH_RESERVE_1", NO_SEC, FORBID, NO_SEC),
+PERMISSION("SOUTH_IO_CFG_RM", NO_SEC, FORBID, NO_SEC),
+PERMISSION("SOUTH_IO_CFG_RB", NO_SEC, FORBID, NO_SEC),
+PERMISSION("SOUTH_EFUSE", NO_SEC, FORBID, NO_SEC),
+
+/* 150 */
+PERMISSION("SOUTH_RESERVE_5", NO_SEC, FORBID, NO_SEC),
+PERMISSION("SOUTH_RESERVE_6", NO_SEC, FORBID, NO_SEC),
+PERMISSION("SOUTH_RESERVE_7", NO_SEC, FORBID, NO_SEC),
+PERMISSION("SOUTH_RESERVE_8", NO_SEC, FORBID, NO_SEC),
+PERMISSION("SOUTH_RESERVE_9", NO_SEC, FORBID, NO_SEC),
+PERMISSION("SOUTH_RESERVE_A", NO_SEC, FORBID, NO_SEC),
+PERMISSION("SOUTH_RESERVE_B", NO_SEC, FORBID, NO_SEC),
+PERMISSION("SOUTH_RESERVE_C", NO_SEC, FORBID, NO_SEC),
+PERMISSION("SOUTH_RESERVE_D", NO_SEC, FORBID, NO_SEC),
+PERMISSION("SOUTH_RESERVE_E", NO_SEC, FORBID, NO_SEC),
+
+/* 160 */
+PERMISSION("SOUTH_RESERVE_F", NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_RESERVE_0", NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_MSDC1_PAD_MACRO", NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_RESERVE_2", NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_RESERVE_3", NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_RESERVE_4", NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_MIPI_TX_CONFIG", NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_RESERVE_6", NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_IO_CFG_LB", NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_IO_CFG_LM", NO_SEC, FORBID, NO_SEC),
+
+/* 170 */
+PERMISSION("WEST_IO_CFG_BL", NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_RESERVE_A", NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_RESERVE_B", NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_RESERVE_C", NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_RESERVE_D", NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_RESERVE_E", NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_RESERVE_F", NO_SEC, FORBID, NO_SEC),
+PERMISSION("NORTH_RESERVE_0", NO_SEC, FORBID, NO_SEC),
+PERMISSION("EFUSE_TOP", NO_SEC, FORBID, NO_SEC),
+PERMISSION("NORTH_IO_CFG_LT", NO_SEC, FORBID, NO_SEC),
+
+/* 180 */
+PERMISSION("NORTH_IO_CFG_TL", NO_SEC, FORBID, NO_SEC),
+PERMISSION("NORTH_USB20 PHY", NO_SEC, FORBID, NO_SEC),
+PERMISSION("NORTH_MSDC0 PAD MACRO", NO_SEC, FORBID, NO_SEC),
+PERMISSION("NORTH_RESERVE_6", NO_SEC, FORBID, NO_SEC),
+PERMISSION("NORTH_RESERVE_7", NO_SEC, FORBID, NO_SEC),
+PERMISSION("NORTH_RESERVE_8", NO_SEC, FORBID, NO_SEC),
+PERMISSION("NORTH_RESERVE_9", NO_SEC, FORBID, NO_SEC),
+PERMISSION("NORTH_UFS_MPHY", NO_SEC, FORBID, NO_SEC),
+PERMISSION("NORTH_RESERVE_B", NO_SEC, FORBID, NO_SEC),
+PERMISSION("NORTH_RESERVE_C", NO_SEC, FORBID, NO_SEC),
+
+/* 190 */
+PERMISSION("NORTH_RESERVE_D", NO_SEC, FORBID, NO_SEC),
+PERMISSION("NORTH_RESERVE_E", NO_SEC, FORBID, NO_SEC),
+PERMISSION("NORTH_RESERVE_F", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_CONN", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_MD_VIOLATION", NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_RESERVE", NO_SEC, FORBID, NO_SEC)
+};
+
+static const struct DEVICE_INFO D_APC_MM_Devices[] = {
+/* module, domain0, domain1, domain2 */
+
+/* 0 */
+PERMISSION("G3D_CONFIG", NO_SEC, FORBID, NO_SEC),
+PERMISSION("MFG VAD", NO_SEC, FORBID, NO_SEC),
+PERMISSION("SC0 VAD", NO_SEC, FORBID, NO_SEC),
+PERMISSION("MFG_OTHERS", NO_SEC, FORBID, NO_SEC),
+PERMISSION("MMSYS_CONFIG", NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("MDP_RDMA0", NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("MDP_RDMA1", NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("MDP_RSZ0", NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("MDP_RSZ1", NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("MDP_WROT0", NO_SEC, NO_SEC, NO_SEC),
+
+/* 10 */
+PERMISSION("MDP_WDMA", NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("MDP_TDSHP", NO_SEC, FORBID, NO_SEC),
+PERMISSION("DISP_OVL0", NO_SEC, FORBID, NO_SEC),
+PERMISSION("DISP_OVL0_2L", NO_SEC, FORBID, NO_SEC),
+PERMISSION("DISP_OVL1_2L", NO_SEC, FORBID, NO_SEC),
+PERMISSION("DISP_RDMA0", NO_SEC, FORBID, NO_SEC),
+PERMISSION("DISP_RDMA1", NO_SEC, FORBID, NO_SEC),
+PERMISSION("DISP_WDMA0", NO_SEC, FORBID, NO_SEC),
+PERMISSION("DISP_COLOR0", NO_SEC, FORBID, NO_SEC),
+PERMISSION("DISP_CCORR0", NO_SEC, FORBID, NO_SEC),
+
+/* 20 */
+PERMISSION("DISP_AAL0", NO_SEC, FORBID, NO_SEC),
+PERMISSION("DISP_GAMMA0", NO_SEC, FORBID, NO_SEC),
+PERMISSION("DISP_DITHER0", NO_SEC, FORBID, NO_SEC),
+PERMISSION("DSI_SPLIT", NO_SEC, FORBID, NO_SEC),
+PERMISSION("DSI0", NO_SEC, FORBID, NO_SEC),
+PERMISSION("DPI", NO_SEC, FORBID, NO_SEC),
+PERMISSION("MM_MUTEX", NO_SEC, FORBID, NO_SEC),
+PERMISSION("SMI_LARB0", NO_SEC, FORBID, NO_SEC),
+PERMISSION("SMI_LARB1", NO_SEC, FORBID, NO_SEC),
+PERMISSION("SMI_COMMON", NO_SEC, FORBID, NO_SEC),
+
+/* 30 */
+PERMISSION("DISP_RSZ", NO_SEC, FORBID, NO_SEC),
+PERMISSION("MDP_AAL", NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("MDP_CCORR", NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("DBI", NO_SEC, FORBID, NO_SEC),
+PERMISSION("MMSYS_OTHERS", NO_SEC, FORBID, NO_SEC),
+PERMISSION("IMGSYS_CONFIG", NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("IMGSYS_SMI_LARB1", NO_SEC, FORBID, NO_SEC),
+PERMISSION("IMGSYS_DISP_A0", NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("IMGSYS_DISP_A1", NO_SEC, FORBID, NO_SEC),
+PERMISSION("IMGSYS_DISP_A2", NO_SEC, FORBID, NO_SEC),
+
+/* 40 */
+PERMISSION("IMGSYS_DISP_A3", NO_SEC, FORBID, NO_SEC),
+PERMISSION("IMGSYS_DISP_A4", NO_SEC, FORBID, NO_SEC),
+PERMISSION("IMGSYS_DISP_A5", NO_SEC, FORBID, NO_SEC),
+PERMISSION("IMGSYS_DPE", NO_SEC, FORBID, NO_SEC),
+PERMISSION("IMGSYS_RSC", NO_SEC, FORBID, NO_SEC),
+PERMISSION("IMGSYS_WPEA", NO_SEC, FORBID, NO_SEC),
+PERMISSION("IMGSYS_FDVT", NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("IMGSYS_OWE", NO_SEC, FORBID, NO_SEC),
+PERMISSION("IMGSYS_WPEB", NO_SEC, FORBID, NO_SEC),
+PERMISSION("IMGSYS_MFB", NO_SEC, FORBID, NO_SEC),
+
+/* 50 */
+PERMISSION("IMGSYS_SMI_LARB2", NO_SEC, FORBID, NO_SEC),
+PERMISSION("IMGSYS_OTHERS", NO_SEC, FORBID, NO_SEC),
+PERMISSION("VENCSYS_GLOBAL_CON", NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("VENCSYSSYS_SMI_LARB4", NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("VENCSYS_VENC", NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("VENCSYS_JPGENC", NO_SEC, FORBID, NO_SEC),
+PERMISSION("VENCSYS_MBIST_CTRL", NO_SEC, FORBID, NO_SEC),
+PERMISSION("VENCSYS_OTHERS", NO_SEC, FORBID, NO_SEC),
+PERMISSION("VDECSYS_GLOBAL_CON", NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("VDECSYS_SMI_LARB1", NO_SEC, FORBID, NO_SEC),
+
+/* 60 */
+PERMISSION("VDECSYS_FULL_TOP", NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("VDECSYS_OTHERS", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAMSYS_TOP", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_LARB6", NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("CAMSYS_LARB3", NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("CAMSYS_CAM_TOP", NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("CAMSYS_CAM_A", NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("CAMSYS_CAM_A", NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("CAMSYS_CAM_B", NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("CAMSYS_CAM_B", NO_SEC, NO_SEC, NO_SEC),
+
+/* 70 */
+PERMISSION("CAMSYS_CAM_C", NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("CAMSYS_CAM_C", NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("CAMSYS_CAM_TOP_SET", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_A_SET", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_A_SET", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_B_SET", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_B_SET", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_C_SET", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_C_SET", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_TOP_INNER", NO_SEC, FORBID, NO_SEC),
+
+/* 80 */
+PERMISSION("CAMSYS_CAM_A_INNER", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_A_INNER", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_B_INNER", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_B_INNER", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_C_INNER", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_C_INNER", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_A_EXT", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_B_EXT", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_C_EXT", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_TOP_CLR", NO_SEC, FORBID, NO_SEC),
+
+/* 90 */
+PERMISSION("CAMSYS_CAM_A_CLR", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_A_CLR", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_B_CLR", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_B_CLR", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_C_CLR", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_C_CLR", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_A_EXT", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_B_EXT", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_C_EXT", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_RESERVE", NO_SEC, FORBID, NO_SEC),
+
+/* 100 */
+PERMISSION("CAMSYS_SENINF_A", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_SENINF_B", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_SENINF_C", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_SENINF_D", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_SENINF_E", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_SENINF_F", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_SENINF_G", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_SENINF_H", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAMSV_A", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAMSV_B", NO_SEC, FORBID, NO_SEC),
+
+/* 110 */
+PERMISSION("CAMSYS_CAMSV_C", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAMSV_D", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_MD32 DMEM_12", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_RESEVE", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CCU_CTL", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CCU_H2T_A", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CCU_T2H_A", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_RESERVE", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_RESERVE", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CCU_DMA", NO_SEC, FORBID, NO_SEC),
+
+/* 120 */
+PERMISSION("CAMSYS_TSF", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_MD32_PMEM_24", NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_OTHERS", NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_CFG", NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_ADL_CTRL", NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_COREA_DMEM_0_128KB", NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_COREA_DMEM_128_256KB", NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_COREA_IMEM_256KB", NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_COREA_CONTROL", NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_COREA_DEBUG", NO_SEC, FORBID, NO_SEC),
+
+/* 130 */
+PERMISSION("VPUSYS_COREB_DMEM_0_128KB", NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_COREB_DMEM_128_256KB", NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_COREB_IMEM_256KB", NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_COREB_CONTROL", NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_COREB_DEBUG", NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_COREC_DMEM_0_128KB", NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_COREC_DMEM_128_256KB", NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_COREC_IMEM_256KB", NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_COREC_CONTROL", NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_COREC_DEBUG", NO_SEC, FORBID, NO_SEC),
+
+/* 140 */
+PERMISSION("VPUSYS_OTHERS", NO_SEC, FORBID, NO_SEC)
+};
+
+void devapc_init(void);
+
+#endif /* DEVAPC_H */
+
diff --git a/plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.c b/plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.c
new file mode 100644
index 0000000..56d2ce2
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <emi_mpu.h>
+
+int is_4GB(void)
+{
+ return 0; /* 8183 doesn't use 4GB */
+}
+
+/*
+ * emi_mpu_set_region_protection: protect a region.
+ * @start: start address of the region
+ * @end: end address of the region
+ * @region: EMI MPU region id
+ * @access_permission: EMI MPU access permission
+ * Return 0 for success, otherwise negative status code.
+ */
+int emi_mpu_set_region_protection(
+ unsigned long start, unsigned long end,
+ int region,
+ unsigned int access_permission)
+{
+ int ret = 0;
+
+ if (end <= start) {
+ ERROR("[EMI][MTEE][MPU] Invalid address!.\n");
+ return -1;
+ }
+
+ if (is_4GB()) {
+ /* 4GB mode: emi_addr = phy_addr & 0xffff */
+ start = EMI_PHY_OFFSET & 0xffff;
+ end = EMI_PHY_OFFSET & 0xffff;
+ } else {
+ /* non-4GB mode: emi_addr = phy_addr - MEM_OFFSET */
+ start = start - EMI_PHY_OFFSET;
+ end = end - EMI_PHY_OFFSET;
+ }
+
+ /*Address 64KB alignment*/
+ start = start >> 16;
+ end = end >> 16;
+
+ switch (region) {
+ case 0:
+ mmio_write_32(EMI_MPU_APC0, 0);
+ mmio_write_32(EMI_MPU_SA0, start);
+ mmio_write_32(EMI_MPU_EA0, end);
+ mmio_write_32(EMI_MPU_APC0, access_permission);
+ break;
+
+ case 1:
+ mmio_write_32(EMI_MPU_APC1, 0);
+ mmio_write_32(EMI_MPU_SA1, start);
+ mmio_write_32(EMI_MPU_EA1, end);
+ mmio_write_32(EMI_MPU_APC1, access_permission);
+ break;
+
+ case 2:
+ mmio_write_32(EMI_MPU_APC2, 0);
+ mmio_write_32(EMI_MPU_SA2, start);
+ mmio_write_32(EMI_MPU_EA2, end);
+ mmio_write_32(EMI_MPU_APC2, access_permission);
+ break;
+
+ case 3:
+ mmio_write_32(EMI_MPU_APC3, 0);
+ mmio_write_32(EMI_MPU_SA3, start);
+ mmio_write_32(EMI_MPU_EA3, end);
+ mmio_write_32(EMI_MPU_APC3, access_permission);
+ break;
+
+ case 4:
+ mmio_write_32(EMI_MPU_APC4, 0);
+ mmio_write_32(EMI_MPU_SA4, start);
+ mmio_write_32(EMI_MPU_EA4, end);
+ mmio_write_32(EMI_MPU_APC4, access_permission);
+ break;
+
+ case 5:
+ mmio_write_32(EMI_MPU_APC5, 0);
+ mmio_write_32(EMI_MPU_SA5, start);
+ mmio_write_32(EMI_MPU_EA5, end);
+ mmio_write_32(EMI_MPU_APC5, access_permission);
+ break;
+
+ case 6:
+ mmio_write_32(EMI_MPU_APC6, 0);
+ mmio_write_32(EMI_MPU_SA6, start);
+ mmio_write_32(EMI_MPU_EA6, end);
+ mmio_write_32(EMI_MPU_APC6, access_permission);
+ break;
+
+ case 7:
+ mmio_write_32(EMI_MPU_APC7, 0);
+ mmio_write_32(EMI_MPU_SA7, start);
+ mmio_write_32(EMI_MPU_EA7, end);
+ mmio_write_32(EMI_MPU_APC7, access_permission);
+ break;
+
+ default:
+ ret = -1;
+ break;
+ }
+
+ return ret;
+}
+
+void dump_emi_mpu_regions(void)
+{
+ unsigned int apc, sa, ea;
+ unsigned int apc_addr = EMI_MPU_APC0;
+ unsigned int sa_addr = EMI_MPU_SA0;
+ unsigned int ea_addr = EMI_MPU_EA0;
+ int i;
+
+ for (i = 0; i < 8; ++i) {
+ apc = mmio_read_32(apc_addr + i * 4);
+ sa = mmio_read_32(sa_addr + i * 4);
+ ea = mmio_read_32(ea_addr + i * 4);
+ WARN("region %d:\n", i);
+ WARN("\tapc:0x%x, sa:0x%x, ea:0x%x\n", apc, sa, ea);
+ }
+}
+
+void emi_mpu_init(void)
+{
+ /* Set permission */
+ emi_mpu_set_region_protection(0x40000000UL, 0x4FFFFFFFUL, 0,
+ (FORBIDDEN << 3 | FORBIDDEN << 6));
+ emi_mpu_set_region_protection(0x50000000UL, 0x528FFFFFUL, 1,
+ (FORBIDDEN << 6));
+ emi_mpu_set_region_protection(0x52900000UL, 0x5FFFFFFFUL, 2,
+ (FORBIDDEN << 3 | FORBIDDEN << 6));
+ emi_mpu_set_region_protection(0x60000000UL, 0xFFFFFFFFUL, 3,
+ (FORBIDDEN << 3 | FORBIDDEN << 6));
+ emi_mpu_set_region_protection(0x100000000UL, 0x23FFFFFFFUL, 4,
+ (FORBIDDEN << 3 | FORBIDDEN << 6));
+ dump_emi_mpu_regions();
+}
+
diff --git a/plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.h b/plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.h
new file mode 100644
index 0000000..b67ea56
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __EMI_MPU_H
+#define __EMI_MPU_H
+
+#include <platform_def.h>
+
+#define EMI_MPUP (EMI_BASE + 0x01D8)
+#define EMI_MPUQ (EMI_BASE + 0x01E0)
+#define EMI_MPUR (EMI_BASE + 0x01E8)
+#define EMI_MPUS (EMI_BASE + 0x01F0)
+#define EMI_MPUT (EMI_BASE + 0x01F8)
+#define EMI_MPUY (EMI_BASE + 0x0220)
+#define EMI_MPU_CTRL (EMI_MPU_BASE + 0x0000)
+#define EMI_MPUD0_ST (EMI_BASE + 0x0160)
+#define EMI_MPUD1_ST (EMI_BASE + 0x0164)
+#define EMI_MPUD2_ST (EMI_BASE + 0x0168)
+#define EMI_MPUD3_ST (EMI_BASE + 0x016C)
+#define EMI_MPUD0_ST2 (EMI_BASE + 0x0200)
+#define EMI_MPUD1_ST2 (EMI_BASE + 0x0204)
+#define EMI_MPUD2_ST2 (EMI_BASE + 0x0208)
+#define EMI_MPUD3_ST2 (EMI_BASE + 0x020C)
+
+#define EMI_PHY_OFFSET (0x40000000UL)
+#define EIGHT_DOMAIN
+
+#define NO_PROTECTION (0)
+#define SEC_RW (1)
+#define SEC_RW_NSEC_R (2)
+#define SEC_RW_NSEC_W (3)
+#define SEC_R_NSEC_R (4)
+#define FORBIDDEN (5)
+#define SEC_R_NSEC_RW (6)
+
+#define SECURE_OS_MPU_REGION_ID (0)
+#define ATF_MPU_REGION_ID (1)
+
+#ifdef EIGHT_DOMAIN
+#define SET_ACCESS_PERMISSON(d7, d6, d5, d4, d3, d2, d1, d0) \
+ (((d7) << 21) | ((d6) << 18) | ((d5) << 15) | ((d4) << 12) \
+ | ((d3) << 9) | ((d2) << 6) | ((d1) << 3) | (d0))
+#else
+#define SET_ACCESS_PERMISSON(d3, d2, d1, d0) \
+ (((d3) << 9) | ((d2) << 6) | ((d1) << 3) | (d0))
+#endif
+
+//#define EMI_MPU_BASE (0x1020E000U)
+
+#define EMI_MPU_SA0 (EMI_MPU_BASE + 0x100)
+#define EMI_MPU_SA1 (EMI_MPU_BASE + 0x104)
+#define EMI_MPU_SA2 (EMI_MPU_BASE + 0x108)
+#define EMI_MPU_SA3 (EMI_MPU_BASE + 0x10C)
+#define EMI_MPU_SA4 (EMI_MPU_BASE + 0x110)
+#define EMI_MPU_SA5 (EMI_MPU_BASE + 0x114)
+#define EMI_MPU_SA6 (EMI_MPU_BASE + 0x118)
+#define EMI_MPU_SA7 (EMI_MPU_BASE + 0x11C)
+
+#define EMI_MPU_EA0 (EMI_MPU_BASE + 0x200)
+#define EMI_MPU_EA1 (EMI_MPU_BASE + 0x204)
+#define EMI_MPU_EA2 (EMI_MPU_BASE + 0x208)
+#define EMI_MPU_EA3 (EMI_MPU_BASE + 0x20C)
+#define EMI_MPU_EA4 (EMI_MPU_BASE + 0x210)
+#define EMI_MPU_EA5 (EMI_MPU_BASE + 0x214)
+#define EMI_MPU_EA6 (EMI_MPU_BASE + 0x218)
+#define EMI_MPU_EA7 (EMI_MPU_BASE + 0x21C)
+
+#define EMI_MPU_APC0 (EMI_MPU_BASE + 0x300)
+#define EMI_MPU_APC1 (EMI_MPU_BASE + 0x304)
+#define EMI_MPU_APC2 (EMI_MPU_BASE + 0x308)
+#define EMI_MPU_APC3 (EMI_MPU_BASE + 0x30C)
+#define EMI_MPU_APC4 (EMI_MPU_BASE + 0x310)
+#define EMI_MPU_APC5 (EMI_MPU_BASE + 0x314)
+#define EMI_MPU_APC6 (EMI_MPU_BASE + 0x318)
+#define EMI_MPU_APC7 (EMI_MPU_BASE + 0x31C)
+
+#define EMI_MPU_CTRL_D0 (EMI_MPU_BASE + 0x800)
+#define EMI_MPU_CTRL_D1 (EMI_MPU_BASE + 0x804)
+#define EMI_MPU_CTRL_D2 (EMI_MPU_BASE + 0x808)
+#define EMI_MPU_CTRL_D3 (EMI_MPU_BASE + 0x80C)
+#define EMI_MPU_CTRL_D4 (EMI_MPU_BASE + 0x810)
+#define EMI_MPU_CTRL_D5 (EMI_MPU_BASE + 0x814)
+#define EMI_MPU_CTRL_D6 (EMI_MPU_BASE + 0x818)
+#define EMI_MPU_CTRL_D7 (EMI_MPU_BASE + 0x81C)
+
+#define EMI_MPU_MASK_D0 (EMI_MPU_BASE + 0x900)
+#define EMI_MPU_MASK_D1 (EMI_MPU_BASE + 0x904)
+#define EMI_MPU_MASK_D2 (EMI_MPU_BASE + 0x908)
+#define EMI_MPU_MASK_D3 (EMI_MPU_BASE + 0x90C)
+#define EMI_MPU_MASK_D4 (EMI_MPU_BASE + 0x910)
+#define EMI_MPU_MASK_D5 (EMI_MPU_BASE + 0x914)
+#define EMI_MPU_MASK_D6 (EMI_MPU_BASE + 0x918)
+#define EMI_MPU_MASK_D7 (EMI_MPU_BASE + 0x91C)
+
+int emi_mpu_set_region_protection(
+ unsigned long start, unsigned long end,
+ int region,
+ unsigned int access_permission);
+
+void dump_emi_mpu_regions(void);
+void emi_mpu_init(void);
+
+#endif /* __EMI_MPU_H */
diff --git a/plat/mediatek/mt8183/drivers/gpio/mtgpio.c b/plat/mediatek/mt8183/drivers/gpio/mtgpio.c
new file mode 100644
index 0000000..61aaeef
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/gpio/mtgpio.c
@@ -0,0 +1,439 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <gpio/mtgpio.h>
+#include <gpio/mtgpio_cfg.h>
+#include <drivers/gpio.h>
+#include <mcucfg.h>
+#include <lib/mmio.h>
+#include <platform_def.h>
+#include <spm.h>
+#include <stdbool.h>
+
+/******************************************************************************
+ *Macro Definition
+ ******************************************************************************/
+#define GPIO_MODE_BITS 4
+#define MAX_GPIO_MODE_PER_REG 8
+#define MAX_GPIO_REG_BITS 32
+#define DIR_BASE (GPIO_BASE + 0x000)
+#define DOUT_BASE (GPIO_BASE + 0x100)
+#define DIN_BASE (GPIO_BASE + 0x200)
+#define MODE_BASE (GPIO_BASE + 0x300)
+#define SET 0x4
+#define CLR 0x8
+#define PULLEN_ADDR_OFFSET 0x060
+#define PULLSEL_ADDR_OFFSET 0x080
+
+void mt_set_gpio_dir_chip(uint32_t pin, int dir)
+{
+ uint32_t pos, bit;
+
+ assert(pin < MAX_GPIO_PIN);
+ assert(dir < GPIO_DIR_MAX);
+
+ pos = pin / MAX_GPIO_REG_BITS;
+ bit = pin % MAX_GPIO_REG_BITS;
+
+ if (dir == GPIO_DIR_IN)
+ mmio_write_32(DIR_BASE + 0x10 * pos + CLR, 1U << bit);
+ else
+ mmio_write_32(DIR_BASE + 0x10 * pos + SET, 1U << bit);
+}
+
+int mt_get_gpio_dir_chip(uint32_t pin)
+{
+ uint32_t pos, bit;
+ uint32_t reg;
+
+ assert(pin < MAX_GPIO_PIN);
+
+ pos = pin / MAX_GPIO_REG_BITS;
+ bit = pin % MAX_GPIO_REG_BITS;
+
+ reg = mmio_read_32(DIR_BASE + 0x10 * pos);
+ return (((reg & (1U << bit)) != 0) ? GPIO_DIR_OUT : GPIO_DIR_IN);
+}
+
+void mt_set_gpio_out_chip(uint32_t pin, int output)
+{
+ uint32_t pos, bit;
+
+ assert(pin < MAX_GPIO_PIN);
+ assert(output < GPIO_OUT_MAX);
+
+ pos = pin / MAX_GPIO_REG_BITS;
+ bit = pin % MAX_GPIO_REG_BITS;
+
+ if (output == GPIO_OUT_ZERO)
+ mmio_write_32(DOUT_BASE + 0x10 * pos + CLR, 1U << bit);
+ else
+ mmio_write_32(DOUT_BASE + 0x10 * pos + SET, 1U << bit);
+}
+
+int mt_get_gpio_out_chip(uint32_t pin)
+{
+ uint32_t pos, bit;
+ uint32_t reg;
+
+ assert(pin < MAX_GPIO_PIN);
+
+ pos = pin / MAX_GPIO_REG_BITS;
+ bit = pin % MAX_GPIO_REG_BITS;
+
+ reg = mmio_read_32(DOUT_BASE + 0x10 * pos);
+ return (((reg & (1U << bit)) != 0) ? 1 : 0);
+}
+
+int mt_get_gpio_in_chip(uint32_t pin)
+{
+ uint32_t pos, bit;
+ uint32_t reg;
+
+ assert(pin < MAX_GPIO_PIN);
+
+ pos = pin / MAX_GPIO_REG_BITS;
+ bit = pin % MAX_GPIO_REG_BITS;
+
+ reg = mmio_read_32(DIN_BASE + 0x10 * pos);
+ return (((reg & (1U << bit)) != 0) ? 1 : 0);
+}
+
+void mt_set_gpio_mode_chip(uint32_t pin, int mode)
+{
+ uint32_t pos, bit;
+ uint32_t data;
+ uint32_t mask;
+
+ assert(pin < MAX_GPIO_PIN);
+ assert(mode < GPIO_MODE_MAX);
+
+ mask = (1U << GPIO_MODE_BITS) - 1;
+
+ mode = mode & mask;
+ pos = pin / MAX_GPIO_MODE_PER_REG;
+ bit = (pin % MAX_GPIO_MODE_PER_REG) * GPIO_MODE_BITS;
+
+ data = mmio_read_32(MODE_BASE + 0x10 * pos);
+ data &= (~(mask << bit));
+ data |= (mode << bit);
+ mmio_write_32(MODE_BASE + 0x10 * pos, data);
+}
+
+int mt_get_gpio_mode_chip(uint32_t pin)
+{
+ uint32_t pos, bit;
+ uint32_t data;
+ uint32_t mask;
+
+ assert(pin < MAX_GPIO_PIN);
+
+ mask = (1U << GPIO_MODE_BITS) - 1;
+
+ pos = pin / MAX_GPIO_MODE_PER_REG;
+ bit = (pin % MAX_GPIO_MODE_PER_REG) * GPIO_MODE_BITS;
+
+ data = mmio_read_32(MODE_BASE + 0x10 * pos);
+ return (data >> bit) & mask;
+}
+
+int32_t gpio_get_pull_iocfg(uint32_t pin)
+{
+ switch (pin) {
+ case 0 ... 10:
+ return IOCFG_5_BASE;
+ case 11 ... 12:
+ return IOCFG_0_BASE;
+ case 13 ... 28:
+ return IOCFG_1_BASE;
+ case 43 ... 49:
+ return IOCFG_2_BASE;
+ case 50 ... 60:
+ return IOCFG_3_BASE;
+ case 61 ... 88:
+ return IOCFG_4_BASE;
+ case 89 ... 90:
+ return IOCFG_5_BASE;
+ case 95 ... 106:
+ return IOCFG_5_BASE;
+ case 107 ... 121:
+ return IOCFG_6_BASE;
+ case 134 ... 160:
+ return IOCFG_0_BASE;
+ case 161 ... 166:
+ return IOCFG_1_BASE;
+ case 167 ... 176:
+ return IOCFG_3_BASE;
+ case 177 ... 179:
+ return IOCFG_5_BASE;
+ default:
+ return -1;
+ }
+}
+
+int32_t gpio_get_pupd_iocfg(uint32_t pin)
+{
+ const int32_t offset = 0x0c0;
+
+ switch (pin) {
+ case 29 ... 34:
+ return IOCFG_1_BASE + offset;
+ case 35 ... 42:
+ return IOCFG_2_BASE + offset;
+ case 91 ... 94:
+ return IOCFG_5_BASE + offset;
+ case 122 ... 133:
+ return IOCFG_7_BASE + offset;
+ default:
+ return -1;
+ }
+}
+
+int gpio_get_pupd_offset(uint32_t pin)
+{
+ switch (pin) {
+ case 29 ... 34:
+ return (pin - 29) * 4 % 32;
+ case 35 ... 42:
+ return (pin - 35) * 4 % 32;
+ case 91 ... 94:
+ return (pin - 91) * 4 % 32;
+ case 122 ... 129:
+ return (pin - 122) * 4 % 32;
+ case 130 ... 133:
+ return (pin - 130) * 4 % 32;
+ default:
+ return -1;
+ }
+}
+
+void mt_set_gpio_pull_enable_chip(uint32_t pin, int en)
+{
+ int pullen_addr = gpio_get_pull_iocfg(pin) + PULLEN_ADDR_OFFSET;
+ int pupd_addr = gpio_get_pupd_iocfg(pin);
+ int pupd_offset = gpio_get_pupd_offset(pin);
+
+ assert(pin < MAX_GPIO_PIN);
+
+ assert(!((PULL_offset[pin].offset == (int8_t)-1) &&
+ (pupd_offset == (int8_t)-1)));
+
+ if (en == GPIO_PULL_DISABLE) {
+ if (PULL_offset[pin].offset == (int8_t)-1)
+ mmio_clrbits_32(pupd_addr, 3U << pupd_offset);
+ else
+ mmio_clrbits_32(pullen_addr,
+ 1U << PULL_offset[pin].offset);
+ } else if (en == GPIO_PULL_ENABLE) {
+ if (PULL_offset[pin].offset == (int8_t)-1) {
+ /* For PUPD+R0+R1 Type, mt_set_gpio_pull_enable
+ * does not know
+ * which one between PU and PD shall be enabled.
+ * Use R0 to guarantee at one resistor is set when lk
+ * apply default setting
+ */
+ mmio_setbits_32(pupd_addr, 1U << pupd_offset);
+ mmio_clrbits_32(pupd_addr, 1U << (pupd_offset + 1));
+ } else {
+ /* For PULLEN + PULLSEL Type */
+ mmio_setbits_32(pullen_addr,
+ 1U << PULL_offset[pin].offset);
+ }
+ } else if (en == GPIO_PULL_ENABLE_R0) {
+ assert(!(pupd_offset == (int8_t)-1));
+ mmio_setbits_32(pupd_addr, 1U << pupd_offset);
+ mmio_clrbits_32(pupd_addr, 1U << (pupd_offset + 1));
+ } else if (en == GPIO_PULL_ENABLE_R1) {
+ assert(!(pupd_offset == (int8_t)-1));
+
+ mmio_clrbits_32(pupd_addr, 1U << pupd_offset);
+ mmio_setbits_32(pupd_addr, 1U << (pupd_offset + 1));
+ } else if (en == GPIO_PULL_ENABLE_R0R1) {
+ assert(!(pupd_offset == (int8_t)-1));
+ mmio_setbits_32(pupd_addr, 3U << pupd_offset);
+ }
+}
+
+int mt_get_gpio_pull_enable_chip(uint32_t pin)
+{
+ uint32_t reg;
+
+ int pullen_addr = gpio_get_pull_iocfg(pin) + PULLEN_ADDR_OFFSET;
+ int pupd_addr = gpio_get_pupd_iocfg(pin);
+ int pupd_offset = gpio_get_pupd_offset(pin);
+
+ assert(pin < MAX_GPIO_PIN);
+
+ assert(!((PULL_offset[pin].offset == (int8_t)-1) &&
+ (pupd_offset == (int8_t)-1)));
+
+ if (PULL_offset[pin].offset == (int8_t)-1) {
+ reg = mmio_read_32(pupd_addr);
+ return ((reg & (3U << pupd_offset)) ? 1 : 0);
+ } else if (pupd_offset == (int8_t)-1) {
+ reg = mmio_read_32(pullen_addr);
+ return ((reg & (1U << PULL_offset[pin].offset)) ? 1 : 0);
+ }
+
+ return -ERINVAL;
+}
+
+void mt_set_gpio_pull_select_chip(uint32_t pin, int sel)
+{
+ int pullsel_addr = gpio_get_pull_iocfg(pin) + PULLSEL_ADDR_OFFSET;
+ int pupd_addr = gpio_get_pupd_iocfg(pin);
+ int pupd_offset = gpio_get_pupd_offset(pin);
+
+ assert(pin < MAX_GPIO_PIN);
+
+ assert(!((PULL_offset[pin].offset == (int8_t) -1) &&
+ (pupd_offset == (int8_t)-1)));
+
+ if (sel == GPIO_PULL_NONE) {
+ /* Regard No PULL as PULL disable + pull down */
+ mt_set_gpio_pull_enable_chip(pin, GPIO_PULL_DISABLE);
+ if (PULL_offset[pin].offset == (int8_t)-1)
+ mmio_setbits_32(pupd_addr, 1U << (pupd_offset + 2));
+ else
+ mmio_clrbits_32(pullsel_addr,
+ 1U << PULL_offset[pin].offset);
+ } else if (sel == GPIO_PULL_UP) {
+ mt_set_gpio_pull_enable_chip(pin, GPIO_PULL_ENABLE);
+ if (PULL_offset[pin].offset == (int8_t)-1)
+ mmio_clrbits_32(pupd_addr, 1U << (pupd_offset + 2));
+ else
+ mmio_setbits_32(pullsel_addr,
+ 1U << PULL_offset[pin].offset);
+ } else if (sel == GPIO_PULL_DOWN) {
+ mt_set_gpio_pull_enable_chip(pin, GPIO_PULL_ENABLE);
+ if (PULL_offset[pin].offset == -1)
+ mmio_setbits_32(pupd_addr, 1U << (pupd_offset + 2));
+ else
+ mmio_clrbits_32(pullsel_addr,
+ 1U << PULL_offset[pin].offset);
+ }
+}
+
+/* get pull-up or pull-down, regardless of resistor value */
+int mt_get_gpio_pull_select_chip(uint32_t pin)
+{
+ uint32_t reg;
+
+ int pullen_addr = gpio_get_pull_iocfg(pin) + PULLEN_ADDR_OFFSET;
+ int pullsel_addr = gpio_get_pull_iocfg(pin) + PULLSEL_ADDR_OFFSET;
+ int pupd_addr = gpio_get_pupd_iocfg(pin);
+ int pupd_offset = gpio_get_pupd_offset(pin);
+
+ assert(pin < MAX_GPIO_PIN);
+
+ assert(!((PULL_offset[pin].offset == (int8_t)-1) &&
+ (pupd_offset == (int8_t)-1)));
+
+ if (PULL_offset[pin].offset == (int8_t)-1) {
+ reg = mmio_read_32(pupd_addr);
+ if (reg & (3U << pupd_offset)) {
+ reg = mmio_read_32(pupd_addr);
+ /* Reg value: 0 for PU, 1 for PD -->
+ * reverse return value */
+ return ((reg & (1U << (pupd_offset + 2))) ?
+ GPIO_PULL_DOWN : GPIO_PULL_UP);
+ } else {
+ return GPIO_PULL_NONE;
+ }
+ } else if (pupd_offset == (int8_t)-1) {
+ reg = mmio_read_32(pullen_addr);
+ if ((reg & (1U << PULL_offset[pin].offset))) {
+ reg = mmio_read_32(pullsel_addr);
+ return ((reg & (1U << PULL_offset[pin].offset)) ?
+ GPIO_PULL_UP : GPIO_PULL_DOWN);
+ } else {
+ return GPIO_PULL_NONE;
+ }
+ }
+
+ return -ERINVAL;
+}
+
+void mt_set_gpio_dir(int gpio, int direction)
+{
+ mt_set_gpio_dir_chip((uint32_t)gpio, direction);
+}
+
+int mt_get_gpio_dir(int gpio)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ return mt_get_gpio_dir_chip(pin);
+}
+
+void mt_set_gpio_pull(int gpio, int pull)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ mt_set_gpio_pull_select_chip(pin, pull);
+}
+
+int mt_get_gpio_pull(int gpio)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ return mt_get_gpio_pull_select_chip(pin);
+}
+
+void mt_set_gpio_out(int gpio, int value)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ mt_set_gpio_out_chip(pin, value);
+}
+
+int mt_get_gpio_out(int gpio)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ return mt_get_gpio_out_chip(pin);
+}
+
+int mt_get_gpio_in(int gpio)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ return mt_get_gpio_in_chip(pin);
+}
+
+void mt_set_gpio_mode(int gpio, int mode)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ mt_set_gpio_mode_chip(pin, mode);
+}
+
+int mt_get_gpio_mode(int gpio)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ return mt_get_gpio_mode_chip(pin);
+}
+
+const gpio_ops_t mtgpio_ops = {
+ .get_direction = mt_get_gpio_dir,
+ .set_direction = mt_set_gpio_dir,
+ .get_value = mt_get_gpio_in,
+ .set_value = mt_set_gpio_out,
+ .set_pull = mt_set_gpio_pull,
+ .get_pull = mt_get_gpio_pull,
+};
diff --git a/plat/mediatek/mt8183/drivers/gpio/mtgpio.h b/plat/mediatek/mt8183/drivers/gpio/mtgpio.h
new file mode 100644
index 0000000..9461c54
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/gpio/mtgpio.h
@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_GPIO_H
+#define MT_GPIO_H
+
+#include <stdint.h>
+#include <plat/common/common_def.h>
+
+/* Error Code No. */
+#define RSUCCESS 0
+#define ERACCESS 1
+#define ERINVAL 2
+#define ERWRAPPER 3
+#define MAX_GPIO_PIN MT_GPIO_BASE_MAX
+
+/* Enumeration for GPIO pin */
+typedef enum GPIO_PIN {
+ GPIO_UNSUPPORTED = -1,
+
+ GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7,
+ GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, GPIO14, GPIO15,
+ GPIO16, GPIO17, GPIO18, GPIO19, GPIO20, GPIO21, GPIO22, GPIO23,
+ GPIO24, GPIO25, GPIO26, GPIO27, GPIO28, GPIO29, GPIO30, GPIO31,
+ GPIO32, GPIO33, GPIO34, GPIO35, GPIO36, GPIO37, GPIO38, GPIO39,
+ GPIO40, GPIO41, GPIO42, GPIO43, GPIO44, GPIO45, GPIO46, GPIO47,
+ GPIO48, GPIO49, GPIO50, GPIO51, GPIO52, GPIO53, GPIO54, GPIO55,
+ GPIO56, GPIO57, GPIO58, GPIO59, GPIO60, GPIO61, GPIO62, GPIO63,
+ GPIO64, GPIO65, GPIO66, GPIO67, GPIO68, GPIO69, GPIO70, GPIO71,
+ GPIO72, GPIO73, GPIO74, GPIO75, GPIO76, GPIO77, GPIO78, GPIO79,
+ GPIO80, GPIO81, GPIO82, GPIO83, GPIO84, GPIO85, GPIO86, GPIO87,
+ GPIO88, GPIO89, GPIO90, GPIO91, GPIO92, GPIO93, GPIO94, GPIO95,
+ GPIO96, GPIO97, GPIO98, GPIO99, GPIO100, GPIO101, GPIO102, GPIO103,
+ GPIO104, GPIO105, GPIO106, GPIO107, GPIO108, GPIO109, GPIO110, GPIO111,
+ GPIO112, GPIO113, GPIO114, GPIO115, GPIO116, GPIO117, GPIO118, GPIO119,
+ GPIO120, GPIO121, GPIO122, GPIO123, GPIO124, GPIO125, GPIO126, GPIO127,
+ GPIO128, GPIO129, GPIO130, GPIO131, GPIO132, GPIO133, GPIO134, GPIO135,
+ GPIO136, GPIO137, GPIO138, GPIO139, GPIO140, GPIO141, GPIO142, GPIO143,
+ GPIO144, GPIO145, GPIO146, GPIO147, GPIO148, GPIO149, GPIO150, GPIO151,
+ GPIO152, GPIO153, GPIO154, GPIO155, GPIO156, GPIO157, GPIO158, GPIO159,
+ GPIO160, GPIO161, GPIO162, GPIO163, GPIO164, GPIO165, GPIO166, GPIO167,
+ GPIO168, GPIO169, GPIO170, GPIO171, GPIO172, GPIO173, GPIO174, GPIO175,
+ GPIO176, GPIO177, GPIO178, GPIO179,
+ MT_GPIO_BASE_MAX
+} GPIO_PIN;
+
+/* GPIO MODE CONTROL VALUE*/
+typedef enum {
+ GPIO_MODE_UNSUPPORTED = -1,
+ GPIO_MODE_GPIO = 0,
+ GPIO_MODE_00 = 0,
+ GPIO_MODE_01,
+ GPIO_MODE_02,
+ GPIO_MODE_03,
+ GPIO_MODE_04,
+ GPIO_MODE_05,
+ GPIO_MODE_06,
+ GPIO_MODE_07,
+
+ GPIO_MODE_MAX,
+ GPIO_MODE_DEFAULT = GPIO_MODE_00,
+} GPIO_MODE;
+
+/* GPIO DIRECTION */
+typedef enum {
+ GPIO_DIR_UNSUPPORTED = -1,
+ GPIO_DIR_OUT = 0,
+ GPIO_DIR_IN = 1,
+ GPIO_DIR_MAX,
+ GPIO_DIR_DEFAULT = GPIO_DIR_IN,
+} GPIO_DIR;
+
+/* GPIO PULL ENABLE*/
+typedef enum {
+ GPIO_PULL_EN_UNSUPPORTED = -1,
+ GPIO_PULL_DISABLE = 0,
+ GPIO_PULL_ENABLE = 1,
+ GPIO_PULL_ENABLE_R0 = 2,
+ GPIO_PULL_ENABLE_R1 = 3,
+ GPIO_PULL_ENABLE_R0R1 = 4,
+
+ GPIO_PULL_EN_MAX,
+ GPIO_PULL_EN_DEFAULT = GPIO_PULL_ENABLE,
+} GPIO_PULL_EN;
+
+/* GPIO PULL-UP/PULL-DOWN*/
+typedef enum {
+ GPIO_PULL_UNSUPPORTED = -1,
+ GPIO_PULL_NONE = 0,
+ GPIO_PULL_UP = 1,
+ GPIO_PULL_DOWN = 2,
+ GPIO_PULL_MAX,
+ GPIO_PULL_DEFAULT = GPIO_PULL_DOWN
+} GPIO_PULL;
+
+/* GPIO OUTPUT */
+typedef enum {
+ GPIO_OUT_UNSUPPORTED = -1,
+ GPIO_OUT_ZERO = 0,
+ GPIO_OUT_ONE = 1,
+
+ GPIO_OUT_MAX,
+ GPIO_OUT_DEFAULT = GPIO_OUT_ZERO,
+ GPIO_DATA_OUT_DEFAULT = GPIO_OUT_ZERO, /*compatible with DCT*/
+} GPIO_OUT;
+
+/* GPIO INPUT */
+typedef enum {
+ GPIO_IN_UNSUPPORTED = -1,
+ GPIO_IN_ZERO = 0,
+ GPIO_IN_ONE = 1,
+
+ GPIO_IN_MAX,
+} GPIO_IN;
+
+typedef struct {
+ uint32_t val;
+ uint32_t set;
+ uint32_t rst;
+ uint32_t _align1;
+} VAL_REGS;
+
+typedef struct {
+ VAL_REGS dir[6]; /*0x0000 ~ 0x005F: 96 bytes */
+ uint8_t rsv00[160]; /*0x0060 ~ 0x00FF: 160 bytes */
+ VAL_REGS dout[6]; /*0x0100 ~ 0x015F: 96 bytes */
+ uint8_t rsv01[160]; /*0x0160 ~ 0x01FF: 160 bytes */
+ VAL_REGS din[6]; /*0x0200 ~ 0x025F: 96 bytes */
+ uint8_t rsv02[160]; /*0x0260 ~ 0x02FF: 160 bytes */
+ VAL_REGS mode[23]; /*0x0300 ~ 0x046F: 368 bytes */
+} GPIO_REGS;
+
+/* GPIO Driver interface */
+/*direction*/
+void mt_set_gpio_dir(int gpio, int direction);
+int mt_get_gpio_dir(int gpio);
+
+/*pull select*/
+void mt_set_gpio_pull(int gpio, int pull);
+int mt_get_gpio_pull(int gpio);
+
+/*input/output*/
+void mt_set_gpio_out(int gpio, int value);
+int mt_get_gpio_out(int gpio);
+int mt_get_gpio_in(int gpio);
+
+/*mode control*/
+void mt_set_gpio_mode(int gpio, int mode);
+int mt_get_gpio_mode(int gpio);
+
+#endif /* MT_GPIO_H */
diff --git a/plat/mediatek/mt8183/drivers/gpio/mtgpio_cfg.h b/plat/mediatek/mt8183/drivers/gpio/mtgpio_cfg.h
new file mode 100644
index 0000000..4e1fd2b
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/gpio/mtgpio_cfg.h
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_GPIO_CFG_H
+#define MT_GPIO_CFG_H
+
+#include <stdint.h>
+#include <plat/common/common_def.h>
+
+#define IOCFG_0_BASE 0x11F20000
+#define IOCFG_1_BASE 0x11E80000
+#define IOCFG_2_BASE 0x11E70000
+#define IOCFG_3_BASE 0x11E90000
+#define IOCFG_4_BASE 0x11D30000
+#define IOCFG_5_BASE 0x11D20000
+#define IOCFG_6_BASE 0x11C50000
+#define IOCFG_7_BASE 0x11F30000
+
+typedef struct {
+ int8_t offset;
+} PIN_offset;
+
+PIN_offset PULL_offset[] = {
+ /* 0 */ {6},
+ /* 1 */ {7},
+ /* 2 */ {8},
+ /* 3 */ {9},
+ /* 4 */ {11},
+ /* 5 */ {12},
+ /* 6 */ {13},
+ /* 7 */ {14},
+ /* 8 */ {0},
+ /* 9 */ {26},
+ /* 10 */ {27},
+ /* 11 */ {10},
+ /* 12 */ {17},
+ /* 13 */ {6},
+ /* 14 */ {7},
+ /* 15 */ {8},
+ /* 16 */ {9},
+ /* 17 */ {10},
+ /* 18 */ {11},
+ /* 19 */ {12},
+ /* 20 */ {13},
+ /* 21 */ {14},
+ /* 22 */ {15},
+ /* 23 */ {16},
+ /* 24 */ {17},
+ /* 25 */ {18},
+ /* 26 */ {19},
+ /* 27 */ {20},
+ /* 28 */ {21},
+ /* 29 */ {-1},
+ /* 30 */ {-1},
+ /* 31 */ {-1},
+ /* 32 */ {-1},
+ /* 33 */ {-1},
+ /* 34 */ {-1},
+ /* 35 */ {-1},
+ /* 36 */ {-1},
+ /* 37 */ {-1},
+ /* 38 */ {-1},
+ /* 39 */ {-1},
+ /* 40 */ {-1},
+ /* 41 */ {-1},
+ /* 42 */ {-1},
+ /* 43 */ {8},
+ /* 44 */ {9},
+ /* 45 */ {10},
+ /* 46 */ {11},
+ /* 47 */ {12},
+ /* 48 */ {13},
+ /* 49 */ {14},
+ /* 50 */ {0},
+ /* 51 */ {1},
+ /* 52 */ {2},
+ /* 53 */ {3},
+ /* 54 */ {4},
+ /* 55 */ {5},
+ /* 56 */ {6},
+ /* 57 */ {7},
+ /* 58 */ {8},
+ /* 59 */ {9},
+ /* 60 */ {10},
+ /* 61 */ {0},
+ /* 62 */ {1},
+ /* 63 */ {2},
+ /* 64 */ {3},
+ /* 65 */ {4},
+ /* 66 */ {5},
+ /* 67 */ {6},
+ /* 68 */ {7},
+ /* 69 */ {8},
+ /* 70 */ {9},
+ /* 71 */ {10},
+ /* 72 */ {11},
+ /* 73 */ {12},
+ /* 74 */ {13},
+ /* 75 */ {14},
+ /* 76 */ {15},
+ /* 77 */ {16},
+ /* 78 */ {17},
+ /* 79 */ {18},
+ /* 80 */ {19},
+ /* 81 */ {20},
+ /* 82 */ {21},
+ /* 83 */ {22},
+ /* 84 */ {23},
+ /* 85 */ {24},
+ /* 86 */ {25},
+ /* 87 */ {26},
+ /* 88 */ {27},
+ /* 89 */ {24},
+ /* 90 */ {1},
+ /* 91 */ {-1},
+ /* 92 */ {-1},
+ /* 93 */ {-1},
+ /* 94 */ {-1},
+ /* 95 */ {15},
+ /* 96 */ {17},
+ /* 97 */ {18},
+ /* 98 */ {19},
+ /* 99 */ {20},
+ /* 100 */ {21},
+ /* 101 */ {22},
+ /* 102 */ {23},
+ /* 103 */ {28},
+ /* 104 */ {29},
+ /* 105 */ {30},
+ /* 106 */ {31},
+ /* 107 */ {0},
+ /* 108 */ {1},
+ /* 109 */ {2},
+ /* 110 */ {3},
+ /* 111 */ {4},
+ /* 112 */ {5},
+ /* 113 */ {6},
+ /* 114 */ {7},
+ /* 115 */ {8},
+ /* 116 */ {9},
+ /* 117 */ {10},
+ /* 118 */ {11},
+ /* 119 */ {12},
+ /* 120 */ {13},
+ /* 121 */ {14},
+ /* 122 */ {-1},
+ /* 123 */ {-1},
+ /* 124 */ {-1},
+ /* 125 */ {-1},
+ /* 126 */ {-1},
+ /* 127 */ {-1},
+ /* 128 */ {-1},
+ /* 129 */ {-1},
+ /* 130 */ {-1},
+ /* 131 */ {-1},
+ /* 132 */ {-1},
+ /* 133 */ {-1},
+ /* 134 */ {0},
+ /* 135 */ {1},
+ /* 136 */ {2},
+ /* 137 */ {3},
+ /* 138 */ {4},
+ /* 139 */ {5},
+ /* 140 */ {6},
+ /* 141 */ {7},
+ /* 142 */ {8},
+ /* 143 */ {9},
+ /* 144 */ {11},
+ /* 145 */ {12},
+ /* 146 */ {13},
+ /* 147 */ {14},
+ /* 148 */ {15},
+ /* 149 */ {16},
+ /* 150 */ {18},
+ /* 151 */ {19},
+ /* 152 */ {20},
+ /* 153 */ {21},
+ /* 154 */ {22},
+ /* 155 */ {23},
+ /* 156 */ {24},
+ /* 157 */ {25},
+ /* 158 */ {26},
+ /* 159 */ {27},
+ /* 160 */ {28},
+ /* 161 */ {0},
+ /* 162 */ {1},
+ /* 163 */ {2},
+ /* 164 */ {3},
+ /* 165 */ {4},
+ /* 166 */ {5},
+ /* 167 */ {11},
+ /* 168 */ {12},
+ /* 169 */ {13},
+ /* 170 */ {14},
+ /* 171 */ {15},
+ /* 172 */ {16},
+ /* 173 */ {17},
+ /* 174 */ {18},
+ /* 175 */ {19},
+ /* 176 */ {20},
+ /* 177 */ {10},
+ /* 178 */ {16},
+ /* 179 */ {25}
+};
+#endif /* MT_GPIO_CFG_H */
diff --git a/plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.c b/plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.c
new file mode 100644
index 0000000..29eebcb
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.c
@@ -0,0 +1,259 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <sspm_reg.h>
+#include <mtk_mcdi.h>
+
+static inline uint32_t mcdi_mbox_read(uint32_t id)
+{
+ return mmio_read_32(SSPM_MBOX_3_BASE + (id << 2));
+}
+
+static inline void mcdi_mbox_write(uint32_t id, uint32_t val)
+{
+ mmio_write_32(SSPM_MBOX_3_BASE + (id << 2), val);
+}
+
+void sspm_set_bootaddr(uint32_t bootaddr)
+{
+ mcdi_mbox_write(MCDI_MBOX_BOOTADDR, bootaddr);
+}
+
+void sspm_cluster_pwr_off_notify(uint32_t cluster)
+{
+ mcdi_mbox_write(MCDI_MBOX_CLUSTER_0_ATF_ACTION_DONE + cluster, 1);
+}
+
+void sspm_cluster_pwr_on_notify(uint32_t cluster)
+{
+ mcdi_mbox_write(MCDI_MBOX_CLUSTER_0_ATF_ACTION_DONE + cluster, 0);
+}
+
+void sspm_standbywfi_irq_enable(uint32_t cpu_idx)
+{
+ mmio_write_32(SSPM_CFGREG_ACAO_INT_SET, STANDBYWFI_EN(cpu_idx));
+}
+
+uint32_t mcdi_avail_cpu_mask_read(void)
+{
+ return mcdi_mbox_read(MCDI_MBOX_AVAIL_CPU_MASK);
+}
+
+uint32_t mcdi_avail_cpu_mask_write(uint32_t mask)
+{
+ mcdi_mbox_write(MCDI_MBOX_AVAIL_CPU_MASK, mask);
+
+ return mask;
+}
+
+uint32_t mcdi_avail_cpu_mask_set(uint32_t mask)
+{
+ uint32_t m;
+
+ m = mcdi_mbox_read(MCDI_MBOX_AVAIL_CPU_MASK);
+ m |= mask;
+ mcdi_mbox_write(MCDI_MBOX_AVAIL_CPU_MASK, m);
+
+ return m;
+}
+
+uint32_t mcdi_avail_cpu_mask_clr(uint32_t mask)
+{
+ uint32_t m;
+
+ m = mcdi_mbox_read(MCDI_MBOX_AVAIL_CPU_MASK);
+ m &= ~mask;
+ mcdi_mbox_write(MCDI_MBOX_AVAIL_CPU_MASK, m);
+
+ return m;
+}
+
+uint32_t mcdi_cpu_cluster_pwr_stat_read(void)
+{
+ return mcdi_mbox_read(MCDI_MBOX_CPU_CLUSTER_PWR_STAT);
+}
+
+#define PAUSE_BIT 1
+#define CLUSTER_OFF_OFS 20
+#define CPU_OFF_OFS 24
+#define CLUSTER_ON_OFS 4
+#define CPU_ON_OFS 8
+
+static uint32_t target_mask(int cluster, int cpu_idx, bool on)
+{
+ uint32_t t = 0;
+
+ if (on) {
+ if (cluster >= 0)
+ t |= BIT(cluster + CLUSTER_ON_OFS);
+
+ if (cpu_idx >= 0)
+ t |= BIT(cpu_idx + CPU_ON_OFS);
+ } else {
+ if (cluster >= 0)
+ t |= BIT(cluster + CLUSTER_OFF_OFS);
+
+ if (cpu_idx >= 0)
+ t |= BIT(cpu_idx + CPU_OFF_OFS);
+ }
+
+ return t;
+}
+
+void mcdi_pause_clr(int cluster, int cpu_idx, bool on)
+{
+ uint32_t tgt = target_mask(cluster, cpu_idx, on);
+ uint32_t m = mcdi_mbox_read(MCDI_MBOX_PAUSE_ACTION);
+
+ m &= ~tgt;
+ mcdi_mbox_write(MCDI_MBOX_PAUSE_ACTION, m);
+}
+
+void mcdi_pause_set(int cluster, int cpu_idx, bool on)
+{
+ uint32_t tgt = target_mask(cluster, cpu_idx, on);
+ uint32_t m = mcdi_mbox_read(MCDI_MBOX_PAUSE_ACTION);
+ uint32_t tgtn = target_mask(-1, cpu_idx, !on);
+
+ /* request on and off at the same time to ensure it can be paused */
+ m |= tgt | tgtn;
+ mcdi_mbox_write(MCDI_MBOX_PAUSE_ACTION, m);
+
+ /* wait pause_ack */
+ while (!mcdi_mbox_read(MCDI_MBOX_PAUSE_ACK))
+ ;
+
+ /* clear non-requested operation */
+ m &= ~tgtn;
+ mcdi_mbox_write(MCDI_MBOX_PAUSE_ACTION, m);
+}
+
+void mcdi_pause(void)
+{
+ uint32_t m = mcdi_mbox_read(MCDI_MBOX_PAUSE_ACTION) | BIT(PAUSE_BIT);
+
+ mcdi_mbox_write(MCDI_MBOX_PAUSE_ACTION, m);
+
+ /* wait pause_ack */
+ while (!mcdi_mbox_read(MCDI_MBOX_PAUSE_ACK))
+ ;
+}
+
+void mcdi_unpause(void)
+{
+ uint32_t m = mcdi_mbox_read(MCDI_MBOX_PAUSE_ACTION) & ~BIT(PAUSE_BIT);
+
+ mcdi_mbox_write(MCDI_MBOX_PAUSE_ACTION, m);
+}
+
+void mcdi_hotplug_wait_ack(int cluster, int cpu_idx, bool on)
+{
+ uint32_t tgt = target_mask(cluster, cpu_idx, on);
+ uint32_t ack = mcdi_mbox_read(MCDI_MBOX_HP_ACK);
+
+ /* wait until ack */
+ while (!(ack & tgt))
+ ack = mcdi_mbox_read(MCDI_MBOX_HP_ACK);
+}
+
+void mcdi_hotplug_clr(int cluster, int cpu_idx, bool on)
+{
+ uint32_t tgt = target_mask(cluster, cpu_idx, on);
+ uint32_t tgt_cpu = target_mask(-1, cpu_idx, on);
+ uint32_t cmd = mcdi_mbox_read(MCDI_MBOX_HP_CMD);
+ uint32_t ack = mcdi_mbox_read(MCDI_MBOX_HP_ACK);
+
+ if (!(cmd & tgt))
+ return;
+
+ /* wait until ack */
+ while (!(ack & tgt_cpu))
+ ack = mcdi_mbox_read(MCDI_MBOX_HP_ACK);
+
+ cmd &= ~tgt;
+ mcdi_mbox_write(MCDI_MBOX_HP_CMD, cmd);
+}
+
+void mcdi_hotplug_set(int cluster, int cpu_idx, bool on)
+{
+ uint32_t tgt = target_mask(cluster, cpu_idx, on);
+ uint32_t tgt_cpu = target_mask(-1, cpu_idx, on);
+ uint32_t cmd = mcdi_mbox_read(MCDI_MBOX_HP_CMD);
+ uint32_t ack = mcdi_mbox_read(MCDI_MBOX_HP_ACK);
+
+ if ((cmd & tgt) == tgt)
+ return;
+
+ /* wait until ack clear */
+ while (ack & tgt_cpu)
+ ack = mcdi_mbox_read(MCDI_MBOX_HP_ACK);
+
+ cmd |= tgt;
+ mcdi_mbox_write(MCDI_MBOX_HP_CMD, cmd);
+}
+
+bool check_mcdi_ctl_stat(void)
+{
+ uint32_t clk_regs[] = {0x100010ac, 0x100010c8};
+ uint32_t clk_mask[] = {0x00028000, 0x00000018};
+ uint32_t tgt = target_mask(0, 0, true);
+ uint32_t m;
+ int i;
+
+ /* check clk status */
+ for (i = 0; i < ARRAY_SIZE(clk_regs); i++) {
+ if (mmio_read_32(clk_regs[i]) & clk_mask[i]) {
+ WARN("mcdi: clk check fail.\n");
+ return false;
+ }
+ }
+
+ /* check mcdi cmd handling */
+ m = mcdi_mbox_read(MCDI_MBOX_PAUSE_ACTION) | BIT(PAUSE_BIT);
+ mcdi_mbox_write(MCDI_MBOX_PAUSE_ACTION, m);
+
+ i = 500;
+ while (!mcdi_mbox_read(MCDI_MBOX_PAUSE_ACK) && --i > 0)
+ udelay(10);
+
+ m = mcdi_mbox_read(MCDI_MBOX_PAUSE_ACTION) & ~BIT(PAUSE_BIT);
+ mcdi_mbox_write(MCDI_MBOX_PAUSE_ACTION, m);
+
+ if (i == 0) {
+ WARN("mcdi: pause_action fail.\n");
+ return false;
+ }
+
+ /* check mcdi cmd handling */
+ if (mcdi_mbox_read(MCDI_MBOX_HP_CMD) ||
+ mcdi_mbox_read(MCDI_MBOX_HP_ACK)) {
+ WARN("mcdi: hp_cmd fail.\n");
+ return false;
+ }
+
+ mcdi_mbox_write(MCDI_MBOX_HP_CMD, tgt);
+
+ i = 500;
+ while ((mcdi_mbox_read(MCDI_MBOX_HP_ACK) & tgt) != tgt && --i > 0)
+ udelay(10);
+
+ mcdi_mbox_write(MCDI_MBOX_HP_CMD, 0);
+
+ if (i == 0) {
+ WARN("mcdi: hp_ack fail.\n");
+ return false;
+ }
+
+ return true;
+}
+
+void mcdi_init(void)
+{
+ mcdi_avail_cpu_mask_write(0x01); /* cpu0 default on */
+}
diff --git a/plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.h b/plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.h
new file mode 100644
index 0000000..9a40df1
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __MTK_MCDI_H__
+#define __MTK_MCDI_H__
+
+#include <stdbool.h>
+
+void sspm_set_bootaddr(uint32_t bootaddr);
+void sspm_standbywfi_irq_enable(uint32_t cpu_idx);
+void sspm_cluster_pwr_off_notify(uint32_t cluster);
+void sspm_cluster_pwr_on_notify(uint32_t cluster);
+
+uint32_t mcdi_avail_cpu_mask_read(void);
+uint32_t mcdi_avail_cpu_mask_write(uint32_t mask);
+uint32_t mcdi_avail_cpu_mask_set(uint32_t mask);
+uint32_t mcdi_avail_cpu_mask_clr(uint32_t mask);
+uint32_t mcdi_cpu_cluster_pwr_stat_read(void);
+
+void mcdi_pause(void);
+void mcdi_unpause(void);
+void mcdi_pause_set(int cluster, int cpu_idx, bool on);
+void mcdi_pause_clr(int cluster, int cpu_idx, bool on);
+void mcdi_hotplug_set(int cluster, int cpu_idx, bool on);
+void mcdi_hotplug_clr(int cluster, int cpu_idx, bool on);
+void mcdi_hotplug_wait_ack(int cluster, int cpu_idx, bool on);
+
+bool check_mcdi_ctl_stat(void);
+void mcdi_init(void);
+
+#endif /* __MTK_MCDI_H__ */
diff --git a/plat/mediatek/mt8183/drivers/mcsi/mcsi.c b/plat/mediatek/mt8183/drivers/mcsi/mcsi.c
new file mode 100644
index 0000000..cbe7f0a
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/mcsi/mcsi.c
@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <assert.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <scu.h>
+#include <mcucfg.h>
+#include <drivers/delay_timer.h>
+#include <mcsi/mcsi.h>
+
+#define MAX_CLUSTERS 5
+
+static unsigned long cci_base_addr;
+static unsigned int cci_cluster_ix_to_iface[MAX_CLUSTERS];
+
+void mcsi_init(unsigned long cci_base,
+ unsigned int num_cci_masters)
+{
+ int i;
+
+ assert(cci_base);
+ assert(num_cci_masters < MAX_CLUSTERS);
+
+ cci_base_addr = cci_base;
+
+ for (i = 0; i < num_cci_masters; i++)
+ cci_cluster_ix_to_iface[i] = SLAVE_IFACE_OFFSET(i);
+}
+
+void mcsi_cache_flush(void)
+{
+ /* timeout is 10ms */
+ int timeout = 10000;
+
+ /* to make flush by SF safe, need to disable BIU DCM */
+ mmio_clrbits_32(CCI_CLK_CTRL, 1 << 8);
+ mmio_write_32(cci_base_addr + FLUSH_SF, 0x1);
+
+ for (; timeout; timeout--, udelay(1)) {
+ if ((mmio_read_32(cci_base_addr + FLUSH_SF) & 0x1) == 0x0)
+ break;
+ }
+
+ if (!timeout) {
+ INFO("SF lush timeout\n");
+ return;
+ }
+
+ /* enable BIU DCM as it was */
+ mmio_setbits_32(CCI_CLK_CTRL, 1 << 8);
+}
+
+static inline unsigned long get_slave_iface_base(unsigned long mpidr)
+{
+ /*
+ * We assume the TF topology code allocates affinity instances
+ * consecutively from zero.
+ * It is a programming error if this is called without initializing
+ * the slave interface to use for this cluster.
+ */
+ unsigned int cluster_id =
+ (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
+
+ assert(cluster_id < MAX_CLUSTERS);
+ assert(cci_cluster_ix_to_iface[cluster_id] != 0);
+
+ return cci_base_addr + cci_cluster_ix_to_iface[cluster_id];
+}
+
+void cci_enable_cluster_coherency(unsigned long mpidr)
+{
+ unsigned long slave_base;
+ unsigned int support_ability;
+ unsigned int config = 0;
+ unsigned int pending = 0;
+
+ assert(cci_base_addr);
+ slave_base = get_slave_iface_base(mpidr);
+ support_ability = mmio_read_32(slave_base);
+
+ pending = (mmio_read_32(
+ cci_base_addr + SNP_PENDING_REG)) >> SNP_PENDING;
+ while (pending) {
+ pending = (mmio_read_32(
+ cci_base_addr + SNP_PENDING_REG)) >> SNP_PENDING;
+ }
+
+ if (support_ability & SNP_SUPPORT)
+ config |= SNOOP_EN_BIT;
+ if (support_ability & DVM_SUPPORT)
+ config |= DVM_EN_BIT;
+
+ mmio_write_32(slave_base, support_ability | config);
+
+ /* Wait for the dust to settle down */
+ while (mmio_read_32(cci_base_addr + SNP_PENDING_REG) >> SNP_PENDING)
+ ;
+}
+
+#if ERRATA_MCSIB_SW
+#pragma weak mcsib_sw_workaround_main
+#endif
+
+void cci_disable_cluster_coherency(unsigned long mpidr)
+{
+ unsigned long slave_base;
+ unsigned int config = 0;
+
+ assert(cci_base_addr);
+ slave_base = get_slave_iface_base(mpidr);
+
+ while (mmio_read_32(cci_base_addr + SNP_PENDING_REG) >> SNP_PENDING)
+ ;
+
+ config = mmio_read_32(slave_base);
+ config &= ~(DVM_EN_BIT | SNOOP_EN_BIT);
+
+ /* Disable Snoops and DVM messages */
+ mmio_write_32(slave_base, config);
+
+#if ERRATA_MCSIB_SW
+ mcsib_sw_workaround_main();
+#endif
+
+ /* Wait for the dust to settle down */
+ while (mmio_read_32(cci_base_addr + SNP_PENDING_REG) >> SNP_PENDING)
+ ;
+}
+
+void cci_secure_switch(unsigned int status)
+{
+ unsigned int config;
+
+ config = mmio_read_32(cci_base_addr + CENTRAL_CTRL_REG);
+ if (status == NS_ACC)
+ config |= SECURE_ACC_EN;
+ else
+ config &= ~SECURE_ACC_EN;
+ mmio_write_32(cci_base_addr + CENTRAL_CTRL_REG, config);
+}
+
+void cci_pmu_secure_switch(unsigned int status)
+{
+ unsigned int config;
+
+ config = mmio_read_32(cci_base_addr + CENTRAL_CTRL_REG);
+ if (status == NS_ACC)
+ config |= PMU_SECURE_ACC_EN;
+ else
+ config &= ~PMU_SECURE_ACC_EN;
+ mmio_write_32(cci_base_addr + CENTRAL_CTRL_REG, config);
+}
+
+void cci_init_sf(void)
+{
+ while (mmio_read_32(cci_base_addr + SNP_PENDING_REG) >> SNP_PENDING)
+ ;
+ /* init sf1 */
+ mmio_write_32(cci_base_addr + SF_INIT_REG, TRIG_SF1_INIT);
+ while (mmio_read_32(cci_base_addr + SF_INIT_REG) & TRIG_SF1_INIT)
+ ;
+ while (!(mmio_read_32(cci_base_addr + SF_INIT_REG) & SF1_INIT_DONE))
+ ;
+ /* init sf2 */
+ mmio_write_32(cci_base_addr + SF_INIT_REG, TRIG_SF2_INIT);
+ while (mmio_read_32(cci_base_addr + SF_INIT_REG) & TRIG_SF2_INIT)
+ ;
+ while (!(mmio_read_32(cci_base_addr + SF_INIT_REG) & SF2_INIT_DONE))
+ ;
+}
+
+void cci_interrupt_en(void)
+{
+ mmio_setbits_32(cci_base_addr + CENTRAL_CTRL_REG, INT_EN);
+}
+
+unsigned long cci_reg_access(unsigned int op, unsigned long offset,
+ unsigned long val)
+{
+ unsigned long ret = 0;
+
+ if ((cci_base_addr == 0) || (offset > MSCI_MEMORY_SZ))
+ panic();
+
+ switch (op) {
+ case MCSI_REG_ACCESS_READ:
+ ret = mmio_read_32(cci_base_addr + offset);
+ break;
+ case MCSI_REG_ACCESS_WRITE:
+ mmio_write_32(cci_base_addr + offset, val);
+ dsb();
+ break;
+ case MCSI_REG_ACCESS_SET_BITMASK:
+ mmio_setbits_32(cci_base_addr + offset, val);
+ dsb();
+ break;
+ case MCSI_REG_ACCESS_CLEAR_BITMASK:
+ mmio_clrbits_32(cci_base_addr + offset, val);
+ dsb();
+ break;
+ default:
+ break;
+ }
+ return ret;
+}
diff --git a/plat/mediatek/mt8183/drivers/mcsi/mcsi.h b/plat/mediatek/mt8183/drivers/mcsi/mcsi.h
new file mode 100644
index 0000000..863e7da
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/mcsi/mcsi.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MCSI_H
+#define MCSI_H
+
+#define SLAVE_IFACE7_OFFSET 0x1700
+#define SLAVE_IFACE6_OFFSET 0x1600
+#define SLAVE_IFACE5_OFFSET 0x1500
+#define SLAVE_IFACE4_OFFSET 0x1400
+#define SLAVE_IFACE3_OFFSET 0x1300
+#define SLAVE_IFACE2_OFFSET 0x1200
+#define SLAVE_IFACE1_OFFSET 0x1100
+#define SLAVE_IFACE0_OFFSET 0x1000
+#define SLAVE_IFACE_OFFSET(index) (SLAVE_IFACE0_OFFSET + \
+ (0x100 * (index)))
+/* Control and ID register offsets */
+#define CENTRAL_CTRL_REG 0x0
+#define ERR_FLAG_REG 0x4
+#define SF_INIT_REG 0x10
+#define SF_CTRL_REG 0x14
+#define DCM_CTRL_REG 0x18
+#define ERR_FLAG2_REG 0x20
+#define SNP_PENDING_REG 0x28
+#define ACP_PENDING_REG 0x2c
+#define FLUSH_SF 0x500
+#define SYS_CCE_CTRL 0x2000
+#define MST1_CTRL 0x2100
+#define MTS2_CTRL 0x2200
+#define XBAR_ARAW_ARB 0x3000
+#define XBAR_R_ARB 0x3004
+
+/* Slave interface register offsets */
+#define SNOOP_CTRL_REG 0x0
+#define QOS_CTRL_REG 0x4
+#define QOS_OVERRIDE_REG 0x8
+#define QOS_TARGET_REG 0xc
+#define BD_CTRL_REG 0x40
+
+/* Snoop Control register bit definitions */
+#define DVM_SUPPORT (1U << 31)
+#define SNP_SUPPORT (1 << 30)
+#define SHAREABLE_OVWRT (1 << 2)
+#define DVM_EN_BIT (1 << 1)
+#define SNOOP_EN_BIT (1 << 0)
+#define SF2_INIT_DONE (1 << 17)
+#define SF1_INIT_DONE (1 << 16)
+#define TRIG_SF2_INIT (1 << 1)
+#define TRIG_SF1_INIT (1 << 0)
+
+/* Status register bit definitions */
+#define SNP_PENDING 31
+
+/* Status bit */
+#define NS_ACC 1
+#define S_ACC 0
+
+/* Central control register bit definitions */
+#define PMU_SECURE_ACC_EN (1 << 4)
+#define INT_EN (1 << 3)
+#define SECURE_ACC_EN (1 << 2)
+#define DVM_DIS (1 << 1)
+#define SNOOP_DIS (1 << 0)
+
+#define MSCI_MEMORY_SZ (0x10000)
+
+#define MCSI_REG_ACCESS_READ (0x0)
+#define MCSI_REG_ACCESS_WRITE (0x1)
+#define MCSI_REG_ACCESS_SET_BITMASK (0x2)
+#define MCSI_REG_ACCESS_CLEAR_BITMASK (0x3)
+
+#define NR_MAX_SLV (7)
+
+/* ICCS */
+#define CACHE_INSTR_EN (1 << 2)
+#define IDLE_CACHE (1 << 3)
+#define USE_SHARED_CACHE (1 << 4)
+#define CACHE_SHARED_PRE_EN (1 << 5)
+#define CACHE_SHARED_POST_EN (1 << 6)
+
+#define ACP_PENDING_MASK (0x1007f)
+
+#define CCI_CLK_CTRL (MCUCFG_BASE + 0x660)
+
+#ifndef __ASSEMBLER__
+
+#include <plat/common/common_def.h>
+#include <stdint.h>
+
+/* Function declarations */
+
+/*
+ * The MCSI driver must be initialized with the base address of the
+ * MCSI device in the platform memory map, and the cluster indices for
+ * the MCSI slave interfaces 3 and 4 respectively. These are the fully
+ * coherent ACE slave interfaces of MCSI.
+ * The cluster indices must either be 0 or 1, corresponding to the level 1
+ * affinity instance of the mpidr representing the cluster. A negative cluster
+ * index indicates that no cluster is present on that slave interface.
+ */
+void mcsi_init(unsigned long cci_base,
+ unsigned int num_cci_masters);
+void mcsi_cache_flush(void);
+
+void cci_enable_cluster_coherency(unsigned long mpidr);
+void cci_disable_cluster_coherency(unsigned long mpidr);
+
+void cci_secure_switch(unsigned int ns);
+void cci_init_sf(void);
+unsigned long cci_reg_access(unsigned int op, unsigned long offset, unsigned long val);
+
+#endif /* __ASSEMBLER__ */
+#endif /* MCSI_H */
diff --git a/plat/mediatek/mt8183/drivers/pmic/pmic.c b/plat/mediatek/mt8183/drivers/pmic/pmic.c
new file mode 100644
index 0000000..b0f898e
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/pmic/pmic.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <pmic_wrap_init.h>
+#include <pmic.h>
+
+void bcpu_enable(uint32_t en)
+{
+ pwrap_write(PMIC_VPROC11_OP_EN, 0x1);
+ if (en)
+ pwrap_write(PMIC_VPROC11_CON0, 1);
+ else
+ pwrap_write(PMIC_VPROC11_CON0, 0);
+}
+
+void bcpu_sram_enable(uint32_t en)
+{
+ pwrap_write(PMIC_VSRAM_PROC11_OP_EN, 0x1);
+ if (en)
+ pwrap_write(PMIC_VSRAM_PROC11_CON0, 1);
+ else
+ pwrap_write(PMIC_VSRAM_PROC11_CON0, 0);
+}
+
+void wk_pmic_enable_sdn_delay(void)
+{
+ uint32_t con;
+
+ pwrap_write(PMIC_TMA_KEY, 0x9CA7);
+ pwrap_read(PMIC_PSEQ_ELR11, &con);
+ con &= ~PMIC_RG_SDN_DLY_ENB;
+ pwrap_write(PMIC_PSEQ_ELR11, con);
+ pwrap_write(PMIC_TMA_KEY, 0);
+}
+
+void pmic_power_off(void)
+{
+ pwrap_write(PMIC_PWRHOLD, 0x0);
+}
diff --git a/plat/mediatek/mt8183/drivers/pmic/pmic.h b/plat/mediatek/mt8183/drivers/pmic/pmic.h
new file mode 100644
index 0000000..f19f9f6
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/pmic/pmic.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PMIC_H
+#define PMIC_H
+
+enum {
+ PMIC_TMA_KEY = 0x03a8,
+ PMIC_PWRHOLD = 0x0a08,
+ PMIC_PSEQ_ELR11 = 0x0a62,
+ PMIC_VPROC11_CON0 = 0x1388,
+ PMIC_VPROC11_OP_EN = 0x1390,
+ PMIC_VSRAM_PROC11_CON0 = 0x1b46,
+ PMIC_VSRAM_PROC11_OP_EN = 0x1b4e
+};
+
+enum {
+ PMIC_RG_SDN_DLY_ENB = 1U << 10
+};
+
+/* external API */
+void bcpu_enable(uint32_t en);
+void bcpu_sram_enable(uint32_t en);
+void wk_pmic_enable_sdn_delay(void);
+void pmic_power_off(void);
+
+#endif /* PMIC_H */
diff --git a/plat/mediatek/mt8183/drivers/pmic/pmic_wrap_init.h b/plat/mediatek/mt8183/drivers/pmic/pmic_wrap_init.h
new file mode 100644
index 0000000..679c5e4
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/pmic/pmic_wrap_init.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PMIC_WRAP_INIT_H
+#define PMIC_WRAP_INIT_H
+
+#include <platform_def.h>
+#include <stdint.h>
+
+/* external API */
+int32_t pwrap_read(uint32_t adr, uint32_t *rdata);
+int32_t pwrap_write(uint32_t adr, uint32_t wdata);
+
+static struct mt8183_pmic_wrap_regs *const mtk_pwrap =
+ (void *)PMIC_WRAP_BASE;
+
+/* timeout setting */
+enum {
+ TIMEOUT_READ = 255, /* us */
+ TIMEOUT_WAIT_IDLE = 255 /* us */
+};
+
+/* PMIC_WRAP registers */
+struct mt8183_pmic_wrap_regs {
+ uint32_t reserved[776];
+ uint32_t wacs2_cmd;
+ uint32_t wacs2_rdata;
+ uint32_t wacs2_vldclr;
+ uint32_t reserved1[4];
+};
+
+enum {
+ RDATA_WACS_RDATA_SHIFT = 0,
+ RDATA_WACS_FSM_SHIFT = 16,
+ RDATA_WACS_REQ_SHIFT = 19,
+ RDATA_SYNC_IDLE_SHIFT,
+ RDATA_INIT_DONE_SHIFT,
+ RDATA_SYS_IDLE_SHIFT,
+};
+
+enum {
+ RDATA_WACS_RDATA_MASK = 0xffff,
+ RDATA_WACS_FSM_MASK = 0x7,
+ RDATA_WACS_REQ_MASK = 0x1,
+ RDATA_SYNC_IDLE_MASK = 0x1,
+ RDATA_INIT_DONE_MASK = 0x1,
+ RDATA_SYS_IDLE_MASK = 0x1,
+};
+
+/* WACS_FSM */
+enum {
+ WACS_FSM_IDLE = 0x00,
+ WACS_FSM_REQ = 0x02,
+ WACS_FSM_WFDLE = 0x04,
+ WACS_FSM_WFVLDCLR = 0x06,
+ WACS_INIT_DONE = 0x01,
+ WACS_SYNC_IDLE = 0x01,
+ WACS_SYNC_BUSY = 0x00
+};
+
+/* error information flag */
+enum {
+ E_PWR_INVALID_ARG = 1,
+ E_PWR_INVALID_RW = 2,
+ E_PWR_INVALID_ADDR = 3,
+ E_PWR_INVALID_WDAT = 4,
+ E_PWR_INVALID_OP_MANUAL = 5,
+ E_PWR_NOT_IDLE_STATE = 6,
+ E_PWR_NOT_INIT_DONE = 7,
+ E_PWR_NOT_INIT_DONE_READ = 8,
+ E_PWR_WAIT_IDLE_TIMEOUT = 9,
+ E_PWR_WAIT_IDLE_TIMEOUT_READ = 10,
+ E_PWR_INIT_SIDLY_FAIL = 11,
+ E_PWR_RESET_TIMEOUT = 12,
+ E_PWR_TIMEOUT = 13,
+ E_PWR_INIT_RESET_SPI = 20,
+ E_PWR_INIT_SIDLY = 21,
+ E_PWR_INIT_REG_CLOCK = 22,
+ E_PWR_INIT_ENABLE_PMIC = 23,
+ E_PWR_INIT_DIO = 24,
+ E_PWR_INIT_CIPHER = 25,
+ E_PWR_INIT_WRITE_TEST = 26,
+ E_PWR_INIT_ENABLE_CRC = 27,
+ E_PWR_INIT_ENABLE_DEWRAP = 28,
+ E_PWR_INIT_ENABLE_EVENT = 29,
+ E_PWR_READ_TEST_FAIL = 30,
+ E_PWR_WRITE_TEST_FAIL = 31,
+ E_PWR_SWITCH_DIO = 32
+};
+
+#endif /* PMIC_WRAP_INIT_H */
diff --git a/plat/mediatek/mt8183/drivers/rtc/rtc.c b/plat/mediatek/mt8183/drivers/rtc/rtc.c
new file mode 100644
index 0000000..a821c1b
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/rtc/rtc.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <rtc.h>
+
+static void RTC_Config_Interface(uint32_t addr, uint16_t data,
+ uint16_t MASK, uint16_t SHIFT)
+{
+ uint16_t pmic_reg = 0;
+
+ pmic_reg = RTC_Read(addr);
+
+ pmic_reg &= ~(MASK << SHIFT);
+ pmic_reg |= (data << SHIFT);
+
+ RTC_Write(addr, pmic_reg);
+}
+
+static void rtc_disable_2sec_reboot(void)
+{
+ uint16_t reboot;
+
+ reboot = (RTC_Read(RTC_AL_SEC) & ~RTC_BBPU_2SEC_EN) &
+ ~RTC_BBPU_AUTO_PDN_SEL;
+ RTC_Write(RTC_AL_SEC, reboot);
+ RTC_Write_Trigger();
+}
+
+static void rtc_xosc_write(uint16_t val, bool reload)
+{
+ uint16_t bbpu;
+
+ RTC_Write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK1);
+ rtc_busy_wait();
+ RTC_Write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK2);
+ rtc_busy_wait();
+
+ RTC_Write(RTC_OSC32CON, val);
+ rtc_busy_wait();
+
+ if (reload) {
+ bbpu = RTC_Read(RTC_BBPU) | RTC_BBPU_KEY | RTC_BBPU_RELOAD;
+ RTC_Write(RTC_BBPU, bbpu);
+ RTC_Write_Trigger();
+ }
+}
+
+static void rtc_enable_k_eosc(void)
+{
+ uint16_t osc32;
+ uint16_t rtc_eosc_cali_td = 8; /* eosc cali period time */
+
+ /* Truning on eosc cali mode clock */
+ RTC_Config_Interface(PMIC_RG_TOP_CON, 1,
+ PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK,
+ PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT);
+ RTC_Config_Interface(PMIC_RG_TOP_CON, 1,
+ PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK,
+ PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT);
+ RTC_Config_Interface(PMIC_RG_SCK_TOP_CKPDN_CON0, 0,
+ PMIC_RG_RTC_EOSC32_CK_PDN_MASK,
+ PMIC_RG_RTC_EOSC32_CK_PDN_SHIFT);
+
+ switch (rtc_eosc_cali_td) {
+ case 1:
+ RTC_Config_Interface(PMIC_RG_EOSC_CALI_CON0, 0x3,
+ PMIC_RG_EOSC_CALI_TD_MASK, PMIC_RG_EOSC_CALI_TD_SHIFT);
+ break;
+ case 2:
+ RTC_Config_Interface(PMIC_RG_EOSC_CALI_CON0, 0x4,
+ PMIC_RG_EOSC_CALI_TD_MASK, PMIC_RG_EOSC_CALI_TD_SHIFT);
+ break;
+ case 4:
+ RTC_Config_Interface(PMIC_RG_EOSC_CALI_CON0, 0x5,
+ PMIC_RG_EOSC_CALI_TD_MASK, PMIC_RG_EOSC_CALI_TD_SHIFT);
+ break;
+ case 16:
+ RTC_Config_Interface(PMIC_RG_EOSC_CALI_CON0, 0x7,
+ PMIC_RG_EOSC_CALI_TD_MASK, PMIC_RG_EOSC_CALI_TD_SHIFT);
+ break;
+ default:
+ RTC_Config_Interface(PMIC_RG_EOSC_CALI_CON0, 0x6,
+ PMIC_RG_EOSC_CALI_TD_MASK, PMIC_RG_EOSC_CALI_TD_SHIFT);
+ break;
+ }
+ /* Switch the DCXO from 32k-less mode to RTC mode,
+ * otherwise, EOSC cali will fail
+ */
+ /* RTC mode will have only OFF mode and FPM */
+ RTC_Config_Interface(PMIC_RG_DCXO_CW02, 0, PMIC_RG_XO_EN32K_MAN_MASK,
+ PMIC_RG_XO_EN32K_MAN_SHIFT);
+ RTC_Write(RTC_BBPU,
+ RTC_Read(RTC_BBPU) | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
+ RTC_Write_Trigger();
+ /* Enable K EOSC mode for normal power off and then plug out battery */
+ RTC_Write(RTC_AL_YEA, ((RTC_Read(RTC_AL_YEA) | RTC_K_EOSC_RSV_0)
+ & (~RTC_K_EOSC_RSV_1)) | RTC_K_EOSC_RSV_2);
+ RTC_Write_Trigger();
+
+ osc32 = RTC_Read(RTC_OSC32CON);
+ rtc_xosc_write(osc32 | RTC_EMBCK_SRC_SEL, true);
+ INFO("[RTC] RTC_enable_k_eosc\n");
+}
+
+void rtc_power_off_sequence(void)
+{
+ uint16_t bbpu;
+
+ rtc_disable_2sec_reboot();
+ rtc_enable_k_eosc();
+
+ /* clear alarm */
+ bbpu = RTC_BBPU_KEY | RTC_BBPU_CLR | RTC_BBPU_PWREN;
+ if (Writeif_unlock()) {
+ RTC_Write(RTC_BBPU, bbpu);
+
+ RTC_Write(RTC_AL_MASK, RTC_AL_MASK_DOW);
+ RTC_Write_Trigger();
+ mdelay(1);
+
+ bbpu = RTC_Read(RTC_BBPU) | RTC_BBPU_KEY | RTC_BBPU_RELOAD;
+ RTC_Write(RTC_BBPU, bbpu);
+ RTC_Write_Trigger();
+ INFO("[RTC] BBPU=0x%x, IRQ_EN=0x%x, AL_MSK=0x%x, AL_SEC=0x%x\n",
+ RTC_Read(RTC_BBPU), RTC_Read(RTC_IRQ_EN),
+ RTC_Read(RTC_AL_MASK), RTC_Read(RTC_AL_SEC));
+ }
+}
diff --git a/plat/mediatek/mt8183/drivers/rtc/rtc.h b/plat/mediatek/mt8183/drivers/rtc/rtc.h
new file mode 100644
index 0000000..66686b4
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/rtc/rtc.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RTC_H
+#define RTC_H
+
+/* RTC registers */
+enum {
+ RTC_BBPU = 0x0588,
+ RTC_IRQ_STA = 0x058A,
+ RTC_IRQ_EN = 0x058C,
+ RTC_CII_EN = 0x058E
+};
+
+enum {
+ RTC_AL_SEC = 0x05A0,
+ RTC_AL_MIN = 0x05A2,
+ RTC_AL_HOU = 0x05A4,
+ RTC_AL_DOM = 0x05A6,
+ RTC_AL_DOW = 0x05A8,
+ RTC_AL_MTH = 0x05AA,
+ RTC_AL_YEA = 0x05AC,
+ RTC_AL_MASK = 0x0590
+};
+
+enum {
+ RTC_OSC32CON = 0x05AE,
+ RTC_CON = 0x05C4,
+ RTC_WRTGR = 0x05C2
+};
+
+enum {
+ RTC_PDN1 = 0x05B4,
+ RTC_PDN2 = 0x05B6,
+ RTC_SPAR0 = 0x05B8,
+ RTC_SPAR1 = 0x05BA,
+ RTC_PROT = 0x05BC,
+ RTC_DIFF = 0x05BE,
+ RTC_CALI = 0x05C0
+};
+
+enum {
+ RTC_OSC32CON_UNLOCK1 = 0x1A57,
+ RTC_OSC32CON_UNLOCK2 = 0x2B68
+};
+
+enum {
+ RTC_PROT_UNLOCK1 = 0x586A,
+ RTC_PROT_UNLOCK2 = 0x9136
+};
+
+enum {
+ RTC_BBPU_PWREN = 1U << 0,
+ RTC_BBPU_CLR = 1U << 1,
+ RTC_BBPU_INIT = 1U << 2,
+ RTC_BBPU_AUTO = 1U << 3,
+ RTC_BBPU_CLRPKY = 1U << 4,
+ RTC_BBPU_RELOAD = 1U << 5,
+ RTC_BBPU_CBUSY = 1U << 6
+};
+
+enum {
+ RTC_AL_MASK_SEC = 1U << 0,
+ RTC_AL_MASK_MIN = 1U << 1,
+ RTC_AL_MASK_HOU = 1U << 2,
+ RTC_AL_MASK_DOM = 1U << 3,
+ RTC_AL_MASK_DOW = 1U << 4,
+ RTC_AL_MASK_MTH = 1U << 5,
+ RTC_AL_MASK_YEA = 1U << 6
+};
+
+enum {
+ RTC_BBPU_AUTO_PDN_SEL = 1U << 6,
+ RTC_BBPU_2SEC_CK_SEL = 1U << 7,
+ RTC_BBPU_2SEC_EN = 1U << 8,
+ RTC_BBPU_2SEC_MODE = 0x3 << 9,
+ RTC_BBPU_2SEC_STAT_CLEAR = 1U << 11,
+ RTC_BBPU_2SEC_STAT_STA = 1U << 12
+};
+
+enum {
+ RTC_BBPU_KEY = 0x43 << 8
+};
+
+enum {
+ RTC_EMBCK_SRC_SEL = 1 << 8,
+ RTC_EMBCK_SEL_MODE = 3 << 6,
+ RTC_XOSC32_ENB = 1 << 5,
+ RTC_REG_XOSC32_ENB = 1 << 15
+};
+
+enum {
+ RTC_K_EOSC_RSV_0 = 1 << 8,
+ RTC_K_EOSC_RSV_1 = 1 << 9,
+ RTC_K_EOSC_RSV_2 = 1 << 10
+};
+
+/* PMIC TOP Register Definition */
+enum {
+ PMIC_RG_TOP_CON = 0x001E,
+ PMIC_RG_TOP_CKPDN_CON1 = 0x0112,
+ PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114,
+ PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116,
+ PMIC_RG_TOP_CKSEL_CON0 = 0x0118,
+ PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A,
+ PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C
+};
+
+/* PMIC SCK Register Definition */
+enum {
+ PMIC_RG_SCK_TOP_CKPDN_CON0 = 0x051A,
+ PMIC_RG_SCK_TOP_CKPDN_CON0_SET = 0x051C,
+ PMIC_RG_SCK_TOP_CKPDN_CON0_CLR = 0x051E,
+ PMIC_RG_EOSC_CALI_CON0 = 0x540
+};
+
+/* PMIC DCXO Register Definition */
+enum {
+ PMIC_RG_DCXO_CW00 = 0x0788,
+ PMIC_RG_DCXO_CW02 = 0x0790
+};
+
+enum {
+ PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK = 0x1,
+ PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT = 1,
+ PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK = 0x1,
+ PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT = 3,
+ PMIC_RG_RTC_EOSC32_CK_PDN_MASK = 0x1,
+ PMIC_RG_RTC_EOSC32_CK_PDN_SHIFT = 2,
+ PMIC_RG_EOSC_CALI_TD_MASK = 0x7,
+ PMIC_RG_EOSC_CALI_TD_SHIFT = 5,
+ PMIC_RG_XO_EN32K_MAN_MASK = 0x1,
+ PMIC_RG_XO_EN32K_MAN_SHIFT = 0
+};
+
+/* external API */
+uint16_t RTC_Read(uint32_t addr);
+void RTC_Write(uint32_t addr, uint16_t data);
+int32_t rtc_busy_wait(void);
+int32_t RTC_Write_Trigger(void);
+int32_t Writeif_unlock(void);
+void rtc_power_off_sequence(void);
+
+#endif /* RTC_H */
diff --git a/plat/mediatek/mt8183/drivers/spm/spm.c b/plat/mediatek/mt8183/drivers/spm/spm.c
new file mode 100644
index 0000000..d6d2344
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/spm/spm.c
@@ -0,0 +1,363 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <lib/bakery_lock.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <spm.h>
+#include <spm_pmic_wrap.h>
+
+DEFINE_BAKERY_LOCK(spm_lock);
+
+/* SPM_DVS_LEVEL */
+#define SPM_VMODEM_LEVEL_MASK (0xff << 16)
+#define SPM_VMODEM_LEVEL (1U << 18)
+#define SPM_VCORE_LEVEL_MASK (0xff)
+#define SPM_VCORE_LEVEL (1U << 1)
+
+/* CLK_SCP_CFG_0 */
+#define SPM_CK_OFF_CONTROL (0x3FF)
+
+/* CLK_SCP_CFG_1 */
+#define SPM_AXI_26M_SEL (0x1)
+
+/* AP_PLL_CON3 */
+#define SPM_PLL_CONTROL (0x7FAAAAF)
+
+/* AP_PLL_CON4 */
+#define SPM_PLL_OUT_OFF_CONTROL (0xFA0A)
+
+/* AP_PLL_CON6 */
+#define PLL_DLY (0x20000)
+
+const char *wakeup_src_str[32] = {
+ [0] = "R12_PCM_TIMER",
+ [1] = "R12_SSPM_WDT_EVENT_B",
+ [2] = "R12_KP_IRQ_B",
+ [3] = "R12_APWDT_EVENT_B",
+ [4] = "R12_APXGPT1_EVENT_B",
+ [5] = "R12_CONN2AP_SPM_WAKEUP_B",
+ [6] = "R12_EINT_EVENT_B",
+ [7] = "R12_CONN_WDT_IRQ_B",
+ [8] = "R12_CCIF0_EVENT_B",
+ [9] = "R12_LOWBATTERY_IRQ_B",
+ [10] = "R12_SSPM_SPM_IRQ_B",
+ [11] = "R12_SCP_SPM_IRQ_B",
+ [12] = "R12_SCP_WDT_EVENT_B",
+ [13] = "R12_PCM_WDT_WAKEUP_B",
+ [14] = "R12_USB_CDSC_B ",
+ [15] = "R12_USB_POWERDWN_B",
+ [16] = "R12_SYS_TIMER_EVENT_B",
+ [17] = "R12_EINT_EVENT_SECURE_B",
+ [18] = "R12_CCIF1_EVENT_B",
+ [19] = "R12_UART0_IRQ_B",
+ [20] = "R12_AFE_IRQ_MCU_B",
+ [21] = "R12_THERM_CTRL_EVENT_B",
+ [22] = "R12_SYS_CIRQ_IRQ_B",
+ [23] = "R12_MD2AP_PEER_EVENT_B",
+ [24] = "R12_CSYSPWREQ_B",
+ [25] = "R12_MD1_WDT_B ",
+ [26] = "R12_CLDMA_EVENT_B",
+ [27] = "R12_SEJ_WDT_GPT_B",
+ [28] = "R12_ALL_SSPM_WAKEUP_B",
+ [29] = "R12_CPU_IRQ_B",
+ [30] = "R12_CPU_WFI_AND_B"
+};
+
+const char *spm_get_firmware_version(void)
+{
+ return "DYNAMIC_SPM_FW_VERSION";
+}
+
+void spm_lock_init(void)
+{
+ bakery_lock_init(&spm_lock);
+}
+
+void spm_lock_get(void)
+{
+ bakery_lock_get(&spm_lock);
+}
+
+void spm_lock_release(void)
+{
+ bakery_lock_release(&spm_lock);
+}
+
+void spm_set_bootaddr(unsigned long bootaddr)
+{
+ /* initialize core4~7 boot entry address */
+ mmio_write_32(SW2SPM_MAILBOX_3, bootaddr);
+}
+
+void spm_set_cpu_status(int cpu)
+{
+ if (cpu >= 0 && cpu < 4) {
+ mmio_write_32(ROOT_CPUTOP_ADDR, 0x10006204);
+ mmio_write_32(ROOT_CORE_ADDR, 0x10006208 + (cpu * 0x4));
+ } else if (cpu >= 4 && cpu < 8) {
+ mmio_write_32(ROOT_CPUTOP_ADDR, 0x10006218);
+ mmio_write_32(ROOT_CORE_ADDR, 0x1000621c + ((cpu - 4) * 0x4));
+ } else {
+ ERROR("%s: error cpu number %d\n", __func__, cpu);
+ }
+}
+
+void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
+{
+ mmio_write_32(SPM_AP_STANDBY_CON,
+ ((pwrctrl->wfi_op & 0x1) << 0) |
+ ((pwrctrl->mp0_cputop_idle_mask & 0x1) << 1) |
+ ((pwrctrl->mp1_cputop_idle_mask & 0x1) << 2) |
+ ((pwrctrl->mcusys_idle_mask & 0x1) << 4) |
+ ((pwrctrl->mm_mask_b & 0x3) << 16) |
+ ((pwrctrl->md_ddr_en_0_dbc_en & 0x1) << 18) |
+ ((pwrctrl->md_ddr_en_1_dbc_en & 0x1) << 19) |
+ ((pwrctrl->md_mask_b & 0x3) << 20) |
+ ((pwrctrl->sspm_mask_b & 0x1) << 22) |
+ ((pwrctrl->scp_mask_b & 0x1) << 23) |
+ ((pwrctrl->srcclkeni_mask_b & 0x1) << 24) |
+ ((pwrctrl->md_apsrc_1_sel & 0x1) << 25) |
+ ((pwrctrl->md_apsrc_0_sel & 0x1) << 26) |
+ ((pwrctrl->conn_ddr_en_dbc_en & 0x1) << 27) |
+ ((pwrctrl->conn_mask_b & 0x1) << 28) |
+ ((pwrctrl->conn_apsrc_sel & 0x1) << 29));
+
+ mmio_write_32(SPM_SRC_REQ,
+ ((pwrctrl->spm_apsrc_req & 0x1) << 0) |
+ ((pwrctrl->spm_f26m_req & 0x1) << 1) |
+ ((pwrctrl->spm_infra_req & 0x1) << 3) |
+ ((pwrctrl->spm_vrf18_req & 0x1) << 4) |
+ ((pwrctrl->spm_ddren_req & 0x1) << 7) |
+ ((pwrctrl->spm_rsv_src_req & 0x7) << 8) |
+ ((pwrctrl->spm_ddren_2_req & 0x1) << 11) |
+ ((pwrctrl->cpu_md_dvfs_sop_force_on & 0x1) << 16));
+
+ mmio_write_32(SPM_SRC_MASK,
+ ((pwrctrl->csyspwreq_mask & 0x1) << 0) |
+ ((pwrctrl->ccif0_md_event_mask_b & 0x1) << 1) |
+ ((pwrctrl->ccif0_ap_event_mask_b & 0x1) << 2) |
+ ((pwrctrl->ccif1_md_event_mask_b & 0x1) << 3) |
+ ((pwrctrl->ccif1_ap_event_mask_b & 0x1) << 4) |
+ ((pwrctrl->ccif2_md_event_mask_b & 0x1) << 5) |
+ ((pwrctrl->ccif2_ap_event_mask_b & 0x1) << 6) |
+ ((pwrctrl->ccif3_md_event_mask_b & 0x1) << 7) |
+ ((pwrctrl->ccif3_ap_event_mask_b & 0x1) << 8) |
+ ((pwrctrl->md_srcclkena_0_infra_mask_b & 0x1) << 9) |
+ ((pwrctrl->md_srcclkena_1_infra_mask_b & 0x1) << 10) |
+ ((pwrctrl->conn_srcclkena_infra_mask_b & 0x1) << 11) |
+ ((pwrctrl->ufs_infra_req_mask_b & 0x1) << 12) |
+ ((pwrctrl->srcclkeni_infra_mask_b & 0x1) << 13) |
+ ((pwrctrl->md_apsrc_req_0_infra_mask_b & 0x1) << 14) |
+ ((pwrctrl->md_apsrc_req_1_infra_mask_b & 0x1) << 15) |
+ ((pwrctrl->conn_apsrcreq_infra_mask_b & 0x1) << 16) |
+ ((pwrctrl->ufs_srcclkena_mask_b & 0x1) << 17) |
+ ((pwrctrl->md_vrf18_req_0_mask_b & 0x1) << 18) |
+ ((pwrctrl->md_vrf18_req_1_mask_b & 0x1) << 19) |
+ ((pwrctrl->ufs_vrf18_req_mask_b & 0x1) << 20) |
+ ((pwrctrl->gce_vrf18_req_mask_b & 0x1) << 21) |
+ ((pwrctrl->conn_infra_req_mask_b & 0x1) << 22) |
+ ((pwrctrl->gce_apsrc_req_mask_b & 0x1) << 23) |
+ ((pwrctrl->disp0_apsrc_req_mask_b & 0x1) << 24) |
+ ((pwrctrl->disp1_apsrc_req_mask_b & 0x1) << 25) |
+ ((pwrctrl->mfg_req_mask_b & 0x1) << 26) |
+ ((pwrctrl->vdec_req_mask_b & 0x1) << 27));
+
+ mmio_write_32(SPM_SRC2_MASK,
+ ((pwrctrl->md_ddr_en_0_mask_b & 0x1) << 0) |
+ ((pwrctrl->md_ddr_en_1_mask_b & 0x1) << 1) |
+ ((pwrctrl->conn_ddr_en_mask_b & 0x1) << 2) |
+ ((pwrctrl->ddren_sspm_apsrc_req_mask_b & 0x1) << 3) |
+ ((pwrctrl->ddren_scp_apsrc_req_mask_b & 0x1) << 4) |
+ ((pwrctrl->disp0_ddren_mask_b & 0x1) << 5) |
+ ((pwrctrl->disp1_ddren_mask_b & 0x1) << 6) |
+ ((pwrctrl->gce_ddren_mask_b & 0x1) << 7) |
+ ((pwrctrl->ddren_emi_self_refresh_ch0_mask_b & 0x1)
+ << 8) |
+ ((pwrctrl->ddren_emi_self_refresh_ch1_mask_b & 0x1)
+ << 9));
+
+ mmio_write_32(SPM_WAKEUP_EVENT_MASK,
+ ((pwrctrl->spm_wakeup_event_mask & 0xffffffff) << 0));
+
+ mmio_write_32(SPM_WAKEUP_EVENT_EXT_MASK,
+ ((pwrctrl->spm_wakeup_event_ext_mask & 0xffffffff)
+ << 0));
+
+ mmio_write_32(SPM_SRC3_MASK,
+ ((pwrctrl->md_ddr_en_2_0_mask_b & 0x1) << 0) |
+ ((pwrctrl->md_ddr_en_2_1_mask_b & 0x1) << 1) |
+ ((pwrctrl->conn_ddr_en_2_mask_b & 0x1) << 2) |
+ ((pwrctrl->ddren2_sspm_apsrc_req_mask_b & 0x1) << 3) |
+ ((pwrctrl->ddren2_scp_apsrc_req_mask_b & 0x1) << 4) |
+ ((pwrctrl->disp0_ddren2_mask_b & 0x1) << 5) |
+ ((pwrctrl->disp1_ddren2_mask_b & 0x1) << 6) |
+ ((pwrctrl->gce_ddren2_mask_b & 0x1) << 7) |
+ ((pwrctrl->ddren2_emi_self_refresh_ch0_mask_b & 0x1)
+ << 8) |
+ ((pwrctrl->ddren2_emi_self_refresh_ch1_mask_b & 0x1)
+ << 9));
+
+ mmio_write_32(MP0_CPU0_WFI_EN,
+ ((pwrctrl->mp0_cpu0_wfi_en & 0x1) << 0));
+ mmio_write_32(MP0_CPU1_WFI_EN,
+ ((pwrctrl->mp0_cpu1_wfi_en & 0x1) << 0));
+ mmio_write_32(MP0_CPU2_WFI_EN,
+ ((pwrctrl->mp0_cpu2_wfi_en & 0x1) << 0));
+ mmio_write_32(MP0_CPU3_WFI_EN,
+ ((pwrctrl->mp0_cpu3_wfi_en & 0x1) << 0));
+
+ mmio_write_32(MP1_CPU0_WFI_EN,
+ ((pwrctrl->mp1_cpu0_wfi_en & 0x1) << 0));
+ mmio_write_32(MP1_CPU1_WFI_EN,
+ ((pwrctrl->mp1_cpu1_wfi_en & 0x1) << 0));
+ mmio_write_32(MP1_CPU2_WFI_EN,
+ ((pwrctrl->mp1_cpu2_wfi_en & 0x1) << 0));
+ mmio_write_32(MP1_CPU3_WFI_EN,
+ ((pwrctrl->mp1_cpu3_wfi_en & 0x1) << 0));
+}
+
+void spm_disable_pcm_timer(void)
+{
+ mmio_clrsetbits_32(PCM_CON1, PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY);
+}
+
+void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
+{
+ uint32_t val, mask, isr;
+
+ val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX;
+ mmio_write_32(PCM_TIMER_VAL, val);
+ mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | PCM_TIMER_EN_LSB);
+
+ mask = pwrctrl->wake_src;
+
+ if (pwrctrl->csyspwreq_mask)
+ mask &= ~WAKE_SRC_R12_CSYSPWREQ_B;
+
+ mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~mask);
+
+ isr = mmio_read_32(SPM_IRQ_MASK) & SPM_TWAM_IRQ_MASK_LSB;
+ mmio_write_32(SPM_IRQ_MASK, isr | ISRM_RET_IRQ_AUX);
+}
+
+void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl)
+{
+ mmio_write_32(SPM_SW_FLAG, pwrctrl->pcm_flags);
+ mmio_write_32(SPM_SW_RSV_2, pwrctrl->pcm_flags1);
+}
+
+void spm_set_pcm_wdt(int en)
+{
+ if (en) {
+ mmio_clrsetbits_32(PCM_CON1, PCM_WDT_WAKE_MODE_LSB,
+ SPM_REGWR_CFG_KEY);
+
+ if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX)
+ mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX);
+ mmio_write_32(PCM_WDT_VAL,
+ mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT);
+ mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | PCM_WDT_EN_LSB);
+ } else {
+ mmio_clrsetbits_32(PCM_CON1, PCM_WDT_EN_LSB,
+ SPM_REGWR_CFG_KEY);
+ }
+}
+
+void spm_send_cpu_wakeup_event(void)
+{
+ mmio_write_32(PCM_REG_DATA_INI, 0);
+ mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1);
+}
+
+void spm_get_wakeup_status(struct wake_status *wakesta)
+{
+ wakesta->assert_pc = mmio_read_32(PCM_REG_DATA_INI);
+ wakesta->r12 = mmio_read_32(SPM_SW_RSV_0);
+ wakesta->r12_ext = mmio_read_32(PCM_REG12_EXT_DATA);
+ wakesta->raw_sta = mmio_read_32(SPM_WAKEUP_STA);
+ wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA);
+ wakesta->wake_misc = mmio_read_32(SPM_BSI_D0_SR);
+ wakesta->timer_out = mmio_read_32(SPM_BSI_D1_SR);
+ wakesta->r13 = mmio_read_32(PCM_REG13_DATA);
+ wakesta->idle_sta = mmio_read_32(SUBSYS_IDLE_STA);
+ wakesta->req_sta = mmio_read_32(SRC_REQ_STA);
+ wakesta->sw_flag = mmio_read_32(SPM_SW_FLAG);
+ wakesta->sw_flag1 = mmio_read_32(SPM_SW_RSV_2);
+ wakesta->r15 = mmio_read_32(PCM_REG15_DATA);
+ wakesta->debug_flag = mmio_read_32(SPM_SW_DEBUG);
+ wakesta->debug_flag1 = mmio_read_32(WDT_LATCH_SPARE0_FIX);
+ wakesta->event_reg = mmio_read_32(SPM_BSI_D2_SR);
+ wakesta->isr = mmio_read_32(SPM_IRQ_STA);
+}
+
+void spm_clean_after_wakeup(void)
+{
+ mmio_write_32(SPM_SW_RSV_0,
+ mmio_read_32(SPM_WAKEUP_STA) |
+ mmio_read_32(SPM_SW_RSV_0));
+ mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0);
+ mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~0);
+ mmio_setbits_32(SPM_IRQ_MASK, ISRM_ALL_EXC_TWAM);
+ mmio_write_32(SPM_IRQ_STA, ISRC_ALL_EXC_TWAM);
+ mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT_ALL);
+}
+
+void spm_output_wake_reason(struct wake_status *wakesta, const char *scenario)
+{
+ uint32_t i;
+
+ if (wakesta->assert_pc != 0) {
+ INFO("%s: PCM ASSERT AT %u, ULPOSC_CON = 0x%x\n",
+ scenario, wakesta->assert_pc, mmio_read_32(ULPOSC_CON));
+ goto spm_debug_flags;
+ }
+
+ for (i = 0; i <= 31; i++) {
+ if (wakesta->r12 & (1U << i)) {
+ INFO("%s: wake up by %s, timer_out = %u\n",
+ scenario, wakeup_src_str[i], wakesta->timer_out);
+ break;
+ }
+ }
+
+spm_debug_flags:
+ INFO("r15 = 0x%x, r13 = 0x%x, debug_flag = 0x%x 0x%x\n",
+ wakesta->r15, wakesta->r13, wakesta->debug_flag,
+ wakesta->debug_flag1);
+ INFO("sw_flag = 0x%x 0x%x, r12 = 0x%x, r12_ext = 0x%x\n",
+ wakesta->sw_flag, wakesta->sw_flag1, wakesta->r12,
+ wakesta->r12_ext);
+ INFO("idle_sta = 0x%x, req_sta = 0x%x, event_reg = 0x%x\n",
+ wakesta->idle_sta, wakesta->req_sta, wakesta->event_reg);
+ INFO("isr = 0x%x, raw_sta = 0x%x, raw_ext_sta = 0x%x\n",
+ wakesta->isr, wakesta->raw_sta, wakesta->raw_ext_sta);
+ INFO("wake_misc = 0x%x\n", wakesta->wake_misc);
+}
+
+void spm_boot_init(void)
+{
+ NOTICE("%s() start\n", __func__);
+
+ spm_lock_init();
+ mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE);
+
+ /* Set Vmodem / Vcore DVS init level */
+ mmio_clrsetbits_32(SPM_DVS_LEVEL,
+ SPM_VMODEM_LEVEL_MASK | SPM_VCORE_LEVEL_MASK,
+ SPM_VMODEM_LEVEL | SPM_VCORE_LEVEL);
+
+ /* switch ck_off/axi_26m control to SPM */
+ mmio_setbits_32(CLK_SCP_CFG_0, SPM_CK_OFF_CONTROL);
+ mmio_setbits_32(CLK_SCP_CFG_1, SPM_AXI_26M_SEL);
+
+ /* switch PLL/CLKSQ control to SPM */
+ mmio_clrbits_32(AP_PLL_CON3, SPM_PLL_CONTROL);
+ mmio_clrbits_32(AP_PLL_CON4, SPM_PLL_OUT_OFF_CONTROL);
+ mmio_clrbits_32(AP_PLL_CON6, PLL_DLY);
+
+ NOTICE("%s() end\n", __func__);
+}
diff --git a/plat/mediatek/mt8183/drivers/spm/spm.h b/plat/mediatek/mt8183/drivers/spm/spm.h
new file mode 100644
index 0000000..b2e83dc
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/spm/spm.h
@@ -0,0 +1,2552 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SPM_H
+#define SPM_H
+
+/**************************************
+ * Define and Declare
+ **************************************/
+
+#define POWERON_CONFIG_EN (SPM_BASE + 0x000)
+#define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004)
+#define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008)
+#define SPM_CLK_CON (SPM_BASE + 0x00C)
+#define SPM_CLK_SETTLE (SPM_BASE + 0x010)
+#define SPM_AP_STANDBY_CON (SPM_BASE + 0x014)
+#define PCM_CON0 (SPM_BASE + 0x018)
+#define PCM_CON1 (SPM_BASE + 0x01C)
+#define PCM_IM_PTR (SPM_BASE + 0x020)
+#define PCM_IM_LEN (SPM_BASE + 0x024)
+#define PCM_REG_DATA_INI (SPM_BASE + 0x028)
+#define PCM_PWR_IO_EN (SPM_BASE + 0x02C)
+#define PCM_TIMER_VAL (SPM_BASE + 0x030)
+#define PCM_WDT_VAL (SPM_BASE + 0x034)
+#define PCM_IM_HOST_RW_PTR (SPM_BASE + 0x038)
+#define PCM_IM_HOST_RW_DAT (SPM_BASE + 0x03C)
+#define PCM_EVENT_VECTOR0 (SPM_BASE + 0x040)
+#define PCM_EVENT_VECTOR1 (SPM_BASE + 0x044)
+#define PCM_EVENT_VECTOR2 (SPM_BASE + 0x048)
+#define PCM_EVENT_VECTOR3 (SPM_BASE + 0x04C)
+#define PCM_EVENT_VECTOR4 (SPM_BASE + 0x050)
+#define PCM_EVENT_VECTOR5 (SPM_BASE + 0x054)
+#define PCM_EVENT_VECTOR6 (SPM_BASE + 0x058)
+#define PCM_EVENT_VECTOR7 (SPM_BASE + 0x05C)
+#define PCM_EVENT_VECTOR8 (SPM_BASE + 0x060)
+#define PCM_EVENT_VECTOR9 (SPM_BASE + 0x064)
+#define PCM_EVENT_VECTOR10 (SPM_BASE + 0x068)
+#define PCM_EVENT_VECTOR11 (SPM_BASE + 0x06C)
+#define PCM_EVENT_VECTOR12 (SPM_BASE + 0x070)
+#define PCM_EVENT_VECTOR13 (SPM_BASE + 0x074)
+#define PCM_EVENT_VECTOR14 (SPM_BASE + 0x078)
+#define PCM_EVENT_VECTOR15 (SPM_BASE + 0x07C)
+#define PCM_EVENT_VECTOR_EN (SPM_BASE + 0x080)
+#define SPM_SRAM_RSV_CON (SPM_BASE + 0x088)
+#define SPM_SWINT (SPM_BASE + 0x08C)
+#define SPM_SWINT_SET (SPM_BASE + 0x090)
+#define SPM_SWINT_CLR (SPM_BASE + 0x094)
+#define SPM_SCP_MAILBOX (SPM_BASE + 0x098)
+#define SCP_SPM_MAILBOX (SPM_BASE + 0x09C)
+#define SPM_TWAM_CON (SPM_BASE + 0x0A0)
+#define SPM_TWAM_WINDOW_LEN (SPM_BASE + 0x0A4)
+#define SPM_TWAM_IDLE_SEL (SPM_BASE + 0x0A8)
+#define SPM_SCP_IRQ (SPM_BASE + 0x0AC)
+#define SPM_CPU_WAKEUP_EVENT (SPM_BASE + 0x0B0)
+#define SPM_IRQ_MASK (SPM_BASE + 0x0B4)
+#define SPM_SRC_REQ (SPM_BASE + 0x0B8)
+#define SPM_SRC_MASK (SPM_BASE + 0x0BC)
+#define SPM_SRC2_MASK (SPM_BASE + 0x0C0)
+#define SPM_WAKEUP_EVENT_MASK (SPM_BASE + 0x0C4)
+#define SPM_WAKEUP_EVENT_EXT_MASK (SPM_BASE + 0x0C8)
+#define SPM_TWAM_EVENT_CLEAR (SPM_BASE + 0x0CC)
+#define SCP_CLK_CON (SPM_BASE + 0x0D0)
+#define PCM_DEBUG_CON (SPM_BASE + 0x0D4)
+#define DDR_EN_DBC_LEN (SPM_BASE + 0x0D8)
+#define AHB_BUS_CON (SPM_BASE + 0x0DC)
+#define SPM_SRC3_MASK (SPM_BASE + 0x0E0)
+#define DDR_EN_EMI_DBC_CON (SPM_BASE + 0x0E4)
+#define SSPM_CLK_CON (SPM_BASE + 0x0E8)
+#define PCM_REG0_DATA (SPM_BASE + 0x100)
+#define PCM_REG1_DATA (SPM_BASE + 0x104)
+#define PCM_REG2_DATA (SPM_BASE + 0x108)
+#define PCM_REG3_DATA (SPM_BASE + 0x10C)
+#define PCM_REG4_DATA (SPM_BASE + 0x110)
+#define PCM_REG5_DATA (SPM_BASE + 0x114)
+#define PCM_REG6_DATA (SPM_BASE + 0x118)
+#define PCM_REG7_DATA (SPM_BASE + 0x11C)
+#define PCM_REG8_DATA (SPM_BASE + 0x120)
+#define PCM_REG9_DATA (SPM_BASE + 0x124)
+#define PCM_REG10_DATA (SPM_BASE + 0x128)
+#define PCM_REG11_DATA (SPM_BASE + 0x12C)
+#define PCM_REG12_DATA (SPM_BASE + 0x130)
+#define PCM_REG13_DATA (SPM_BASE + 0x134)
+#define PCM_REG14_DATA (SPM_BASE + 0x138)
+#define PCM_REG15_DATA (SPM_BASE + 0x13C)
+#define PCM_REG12_MASK_B_STA (SPM_BASE + 0x140)
+#define PCM_REG12_EXT_DATA (SPM_BASE + 0x144)
+#define PCM_REG12_EXT_MASK_B_STA (SPM_BASE + 0x148)
+#define PCM_EVENT_REG_STA (SPM_BASE + 0x14C)
+#define PCM_TIMER_OUT (SPM_BASE + 0x150)
+#define PCM_WDT_OUT (SPM_BASE + 0x154)
+#define SPM_IRQ_STA (SPM_BASE + 0x158)
+#define SPM_WAKEUP_STA (SPM_BASE + 0x15C)
+#define SPM_WAKEUP_EXT_STA (SPM_BASE + 0x160)
+#define SPM_WAKEUP_MISC (SPM_BASE + 0x164)
+#define BUS_PROTECT_RDY (SPM_BASE + 0x168)
+#define BUS_PROTECT2_RDY (SPM_BASE + 0x16C)
+#define SUBSYS_IDLE_STA (SPM_BASE + 0x170)
+#define CPU_IDLE_STA (SPM_BASE + 0x174)
+#define PCM_FSM_STA (SPM_BASE + 0x178)
+#define SRC_REQ_STA (SPM_BASE + 0x17C)
+#define PWR_STATUS (SPM_BASE + 0x180)
+#define PWR_STATUS_2ND (SPM_BASE + 0x184)
+#define CPU_PWR_STATUS (SPM_BASE + 0x188)
+#define CPU_PWR_STATUS_2ND (SPM_BASE + 0x18C)
+#define MISC_STA (SPM_BASE + 0x190)
+#define SPM_SRC_RDY_STA (SPM_BASE + 0x194)
+#define DRAMC_DBG_LATCH (SPM_BASE + 0x19C)
+#define SPM_TWAM_LAST_STA0 (SPM_BASE + 0x1A0)
+#define SPM_TWAM_LAST_STA1 (SPM_BASE + 0x1A4)
+#define SPM_TWAM_LAST_STA2 (SPM_BASE + 0x1A8)
+#define SPM_TWAM_LAST_STA3 (SPM_BASE + 0x1AC)
+#define SPM_TWAM_CURR_STA0 (SPM_BASE + 0x1B0)
+#define SPM_TWAM_CURR_STA1 (SPM_BASE + 0x1B4)
+#define SPM_TWAM_CURR_STA2 (SPM_BASE + 0x1B8)
+#define SPM_TWAM_CURR_STA3 (SPM_BASE + 0x1BC)
+#define SPM_TWAM_TIMER_OUT (SPM_BASE + 0x1C0)
+#define SPM_DVFS_STA (SPM_BASE + 0x1C8)
+#define BUS_PROTECT3_RDY (SPM_BASE + 0x1CC)
+#define SRC_DDREN_STA (SPM_BASE + 0x1E0)
+#define MCU_PWR_CON (SPM_BASE + 0x200)
+#define MP0_CPUTOP_PWR_CON (SPM_BASE + 0x204)
+#define MP0_CPU0_PWR_CON (SPM_BASE + 0x208)
+#define MP0_CPU1_PWR_CON (SPM_BASE + 0x20C)
+#define MP0_CPU2_PWR_CON (SPM_BASE + 0x210)
+#define MP0_CPU3_PWR_CON (SPM_BASE + 0x214)
+#define MP1_CPUTOP_PWR_CON (SPM_BASE + 0x218)
+#define MP1_CPU0_PWR_CON (SPM_BASE + 0x21C)
+#define MP1_CPU1_PWR_CON (SPM_BASE + 0x220)
+#define MP1_CPU2_PWR_CON (SPM_BASE + 0x224)
+#define MP1_CPU3_PWR_CON (SPM_BASE + 0x228)
+#define MP0_CPUTOP_L2_PDN (SPM_BASE + 0x240)
+#define MP0_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x244)
+#define MP0_CPU0_L1_PDN (SPM_BASE + 0x248)
+#define MP0_CPU1_L1_PDN (SPM_BASE + 0x24C)
+#define MP0_CPU2_L1_PDN (SPM_BASE + 0x250)
+#define MP0_CPU3_L1_PDN (SPM_BASE + 0x254)
+#define MP1_CPUTOP_L2_PDN (SPM_BASE + 0x258)
+#define MP1_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x25C)
+#define MP1_CPU0_L1_PDN (SPM_BASE + 0x260)
+#define MP1_CPU1_L1_PDN (SPM_BASE + 0x264)
+#define MP1_CPU2_L1_PDN (SPM_BASE + 0x268)
+#define MP1_CPU3_L1_PDN (SPM_BASE + 0x26C)
+#define CPU_EXT_BUCK_ISO (SPM_BASE + 0x290)
+#define DUMMY1_PWR_CON (SPM_BASE + 0x2B0)
+#define BYPASS_SPMC (SPM_BASE + 0x2B4)
+#define SPMC_DORMANT_ENABLE (SPM_BASE + 0x2B8)
+#define ARMPLL_CLK_CON (SPM_BASE + 0x2BC)
+#define SPMC_IN_RET (SPM_BASE + 0x2C0)
+#define VDE_PWR_CON (SPM_BASE + 0x300)
+#define VEN_PWR_CON (SPM_BASE + 0x304)
+#define ISP_PWR_CON (SPM_BASE + 0x308)
+#define DIS_PWR_CON (SPM_BASE + 0x30C)
+#define MFG_CORE1_PWR_CON (SPM_BASE + 0x310)
+#define AUDIO_PWR_CON (SPM_BASE + 0x314)
+#define IFR_PWR_CON (SPM_BASE + 0x318)
+#define DPY_PWR_CON (SPM_BASE + 0x31C)
+#define MD1_PWR_CON (SPM_BASE + 0x320)
+#define VPU_TOP_PWR_CON (SPM_BASE + 0x324)
+#define CONN_PWR_CON (SPM_BASE + 0x32C)
+#define VPU_CORE2_PWR_CON (SPM_BASE + 0x330)
+#define MFG_ASYNC_PWR_CON (SPM_BASE + 0x334)
+#define MFG_PWR_CON (SPM_BASE + 0x338)
+#define VPU_CORE0_PWR_CON (SPM_BASE + 0x33C)
+#define VPU_CORE1_PWR_CON (SPM_BASE + 0x340)
+#define CAM_PWR_CON (SPM_BASE + 0x344)
+#define MFG_2D_PWR_CON (SPM_BASE + 0x348)
+#define MFG_CORE0_PWR_CON (SPM_BASE + 0x34C)
+#define SYSRAM_CON (SPM_BASE + 0x350)
+#define SYSROM_CON (SPM_BASE + 0x354)
+#define SSPM_SRAM_CON (SPM_BASE + 0x358)
+#define SCP_SRAM_CON (SPM_BASE + 0x35C)
+#define UFS_SRAM_CON (SPM_BASE + 0x36C)
+#define DUMMY_SRAM_CON (SPM_BASE + 0x380)
+#define MD_EXT_BUCK_ISO_CON (SPM_BASE + 0x390)
+#define MD_SRAM_ISO_CON (SPM_BASE + 0x394)
+#define MD_EXTRA_PWR_CON (SPM_BASE + 0x398)
+#define EXT_BUCK_CON (SPM_BASE + 0x3A0)
+#define MBIST_EFUSE_REPAIR_ACK_STA (SPM_BASE + 0x3D0)
+#define SPM_DVFS_CON (SPM_BASE + 0x400)
+#define SPM_MDBSI_CON (SPM_BASE + 0x404)
+#define SPM_MAS_PAUSE_MASK_B (SPM_BASE + 0x408)
+#define SPM_MAS_PAUSE2_MASK_B (SPM_BASE + 0x40C)
+#define SPM_BSI_GEN (SPM_BASE + 0x410)
+#define SPM_BSI_EN_SR (SPM_BASE + 0x414)
+#define SPM_BSI_CLK_SR (SPM_BASE + 0x418)
+#define SPM_BSI_D0_SR (SPM_BASE + 0x41C)
+#define SPM_BSI_D1_SR (SPM_BASE + 0x420)
+#define SPM_BSI_D2_SR (SPM_BASE + 0x424)
+#define SPM_AP_SEMA (SPM_BASE + 0x428)
+#define SPM_SPM_SEMA (SPM_BASE + 0x42C)
+#define AP_MDSRC_REQ (SPM_BASE + 0x430)
+#define SPM2MD_DVFS_CON (SPM_BASE + 0x438)
+#define MD2SPM_DVFS_CON (SPM_BASE + 0x43C)
+#define DRAMC_DPY_CLK_SW_CON_RSV (SPM_BASE + 0x440)
+#define DPY_LP_CON (SPM_BASE + 0x444)
+#define CPU_DVFS_REQ (SPM_BASE + 0x448)
+#define SPM_PLL_CON (SPM_BASE + 0x44C)
+#define SPM_EMI_BW_MODE (SPM_BASE + 0x450)
+#define AP2MD_PEER_WAKEUP (SPM_BASE + 0x454)
+#define ULPOSC_CON (SPM_BASE + 0x458)
+#define SPM2MM_CON (SPM_BASE + 0x45C)
+#define DRAMC_DPY_CLK_SW_CON_SEL (SPM_BASE + 0x460)
+#define DRAMC_DPY_CLK_SW_CON (SPM_BASE + 0x464)
+#define SPM_S1_MODE_CH (SPM_BASE + 0x468)
+#define EMI_SELF_REFRESH_CH_STA (SPM_BASE + 0x46C)
+#define DRAMC_DPY_CLK_SW_CON_SEL2 (SPM_BASE + 0x470)
+#define DRAMC_DPY_CLK_SW_CON2 (SPM_BASE + 0x474)
+#define DRAMC_DMYRD_CON (SPM_BASE + 0x478)
+#define SPM_DRS_CON (SPM_BASE + 0x47C)
+#define SPM_SEMA_M0 (SPM_BASE + 0x480)
+#define SPM_SEMA_M1 (SPM_BASE + 0x484)
+#define SPM_SEMA_M2 (SPM_BASE + 0x488)
+#define SPM_SEMA_M3 (SPM_BASE + 0x48C)
+#define SPM_SEMA_M4 (SPM_BASE + 0x490)
+#define SPM_SEMA_M5 (SPM_BASE + 0x494)
+#define SPM_SEMA_M6 (SPM_BASE + 0x498)
+#define SPM_SEMA_M7 (SPM_BASE + 0x49C)
+#define SPM_MAS_PAUSE_MM_MASK_B (SPM_BASE + 0x4A0)
+#define SPM_MAS_PAUSE_MCU_MASK_B (SPM_BASE + 0x4A4)
+#define SRAM_DREQ_ACK (SPM_BASE + 0x4AC)
+#define SRAM_DREQ_CON (SPM_BASE + 0x4B0)
+#define SRAM_DREQ_CON_SET (SPM_BASE + 0x4B4)
+#define SRAM_DREQ_CON_CLR (SPM_BASE + 0x4B8)
+#define SPM2EMI_ENTER_ULPM (SPM_BASE + 0x4BC)
+#define SPM_SSPM_IRQ (SPM_BASE + 0x4C0)
+#define SPM2PMCU_INT (SPM_BASE + 0x4C4)
+#define SPM2PMCU_INT_SET (SPM_BASE + 0x4C8)
+#define SPM2PMCU_INT_CLR (SPM_BASE + 0x4CC)
+#define SPM2PMCU_MAILBOX_0 (SPM_BASE + 0x4D0)
+#define SPM2PMCU_MAILBOX_1 (SPM_BASE + 0x4D4)
+#define SPM2PMCU_MAILBOX_2 (SPM_BASE + 0x4D8)
+#define SPM2PMCU_MAILBOX_3 (SPM_BASE + 0x4DC)
+#define PMCU2SPM_INT (SPM_BASE + 0x4E0)
+#define PMCU2SPM_INT_SET (SPM_BASE + 0x4E4)
+#define PMCU2SPM_INT_CLR (SPM_BASE + 0x4E8)
+#define PMCU2SPM_MAILBOX_0 (SPM_BASE + 0x4EC)
+#define PMCU2SPM_MAILBOX_1 (SPM_BASE + 0x4F0)
+#define PMCU2SPM_MAILBOX_2 (SPM_BASE + 0x4F4)
+#define PMCU2SPM_MAILBOX_3 (SPM_BASE + 0x4F8)
+#define PMCU2SPM_CFG (SPM_BASE + 0x4FC)
+#define MP0_CPU0_IRQ_MASK (SPM_BASE + 0x500)
+#define MP0_CPU1_IRQ_MASK (SPM_BASE + 0x504)
+#define MP0_CPU2_IRQ_MASK (SPM_BASE + 0x508)
+#define MP0_CPU3_IRQ_MASK (SPM_BASE + 0x50C)
+#define MP1_CPU0_IRQ_MASK (SPM_BASE + 0x510)
+#define MP1_CPU1_IRQ_MASK (SPM_BASE + 0x514)
+#define MP1_CPU2_IRQ_MASK (SPM_BASE + 0x518)
+#define MP1_CPU3_IRQ_MASK (SPM_BASE + 0x51C)
+#define MP0_CPU0_WFI_EN (SPM_BASE + 0x530)
+#define MP0_CPU1_WFI_EN (SPM_BASE + 0x534)
+#define MP0_CPU2_WFI_EN (SPM_BASE + 0x538)
+#define MP0_CPU3_WFI_EN (SPM_BASE + 0x53C)
+#define MP1_CPU0_WFI_EN (SPM_BASE + 0x540)
+#define MP1_CPU1_WFI_EN (SPM_BASE + 0x544)
+#define MP1_CPU2_WFI_EN (SPM_BASE + 0x548)
+#define MP1_CPU3_WFI_EN (SPM_BASE + 0x54C)
+#define MP0_L2CFLUSH (SPM_BASE + 0x554)
+#define MP1_L2CFLUSH (SPM_BASE + 0x558)
+#define CPU_PTPOD2_CON (SPM_BASE + 0x560)
+#define ROOT_CPUTOP_ADDR (SPM_BASE + 0x570)
+#define ROOT_CORE_ADDR (SPM_BASE + 0x574)
+#define CPU_SPARE_CON (SPM_BASE + 0x580)
+#define CPU_SPARE_CON_SET (SPM_BASE + 0x584)
+#define CPU_SPARE_CON_CLR (SPM_BASE + 0x588)
+#define SPM2SW_MAILBOX_0 (SPM_BASE + 0x5D0)
+#define SPM2SW_MAILBOX_1 (SPM_BASE + 0x5D4)
+#define SPM2SW_MAILBOX_2 (SPM_BASE + 0x5D8)
+#define SPM2SW_MAILBOX_3 (SPM_BASE + 0x5DC)
+#define SW2SPM_INT (SPM_BASE + 0x5E0)
+#define SW2SPM_INT_SET (SPM_BASE + 0x5E4)
+#define SW2SPM_INT_CLR (SPM_BASE + 0x5E8)
+#define SW2SPM_MAILBOX_0 (SPM_BASE + 0x5EC)
+#define SW2SPM_MAILBOX_1 (SPM_BASE + 0x5F0)
+#define SW2SPM_MAILBOX_2 (SPM_BASE + 0x5F4)
+#define SW2SPM_MAILBOX_3 (SPM_BASE + 0x5F8)
+#define SW2SPM_CFG (SPM_BASE + 0x5FC)
+#define SPM_SW_FLAG (SPM_BASE + 0x600)
+#define SPM_SW_DEBUG (SPM_BASE + 0x604)
+#define SPM_SW_RSV_0 (SPM_BASE + 0x608)
+#define SPM_SW_RSV_1 (SPM_BASE + 0x60C)
+#define SPM_SW_RSV_2 (SPM_BASE + 0x610)
+#define SPM_SW_RSV_3 (SPM_BASE + 0x614)
+#define SPM_SW_RSV_4 (SPM_BASE + 0x618)
+#define SPM_SW_RSV_5 (SPM_BASE + 0x61C)
+#define SPM_RSV_CON (SPM_BASE + 0x620)
+#define SPM_RSV_STA (SPM_BASE + 0x624)
+#define SPM_RSV_CON1 (SPM_BASE + 0x628)
+#define SPM_RSV_STA1 (SPM_BASE + 0x62C)
+#define SPM_PASR_DPD_0 (SPM_BASE + 0x630)
+#define SPM_PASR_DPD_1 (SPM_BASE + 0x634)
+#define SPM_PASR_DPD_2 (SPM_BASE + 0x638)
+#define SPM_PASR_DPD_3 (SPM_BASE + 0x63C)
+#define SPM_SPARE_CON (SPM_BASE + 0x640)
+#define SPM_SPARE_CON_SET (SPM_BASE + 0x644)
+#define SPM_SPARE_CON_CLR (SPM_BASE + 0x648)
+#define SPM_SW_RSV_6 (SPM_BASE + 0x64C)
+#define SPM_SW_RSV_7 (SPM_BASE + 0x650)
+#define SPM_SW_RSV_8 (SPM_BASE + 0x654)
+#define SPM_SW_RSV_9 (SPM_BASE + 0x658)
+#define SPM_SW_RSV_10 (SPM_BASE + 0x65C)
+#define SPM_SW_RSV_18 (SPM_BASE + 0x67C)
+#define SPM_SW_RSV_19 (SPM_BASE + 0x680)
+#define DVFSRC_EVENT_MASK_CON (SPM_BASE + 0x690)
+#define DVFSRC_EVENT_FORCE_ON (SPM_BASE + 0x694)
+#define DVFSRC_EVENT_SEL (SPM_BASE + 0x698)
+#define SPM_DVFS_EVENT_STA (SPM_BASE + 0x69C)
+#define SPM_DVFS_EVENT_STA1 (SPM_BASE + 0x6A0)
+#define SPM_DVFS_LEVEL (SPM_BASE + 0x6A4)
+#define DVFS_ABORT_STA (SPM_BASE + 0x6A8)
+#define DVFS_ABORT_OTHERS_MASK (SPM_BASE + 0x6AC)
+#define SPM_DFS_LEVEL (SPM_BASE + 0x6B0)
+#define SPM_DVS_LEVEL (SPM_BASE + 0x6B4)
+#define SPM_DVFS_MISC (SPM_BASE + 0x6B8)
+#define SPARE_SRC_REQ_MASK (SPM_BASE + 0x6C0)
+#define SCP_VCORE_LEVEL (SPM_BASE + 0x6C4)
+#define SC_MM_CK_SEL_CON (SPM_BASE + 0x6C8)
+#define SPARE_ACK_STA (SPM_BASE + 0x6F0)
+#define SPARE_ACK_MASK (SPM_BASE + 0x6F4)
+#define SPM_DVFS_CON1 (SPM_BASE + 0x700)
+#define SPM_DVFS_CON1_STA (SPM_BASE + 0x704)
+#define SPM_DVFS_CMD0 (SPM_BASE + 0x710)
+#define SPM_DVFS_CMD1 (SPM_BASE + 0x714)
+#define SPM_DVFS_CMD2 (SPM_BASE + 0x718)
+#define SPM_DVFS_CMD3 (SPM_BASE + 0x71C)
+#define SPM_DVFS_CMD4 (SPM_BASE + 0x720)
+#define SPM_DVFS_CMD5 (SPM_BASE + 0x724)
+#define SPM_DVFS_CMD6 (SPM_BASE + 0x728)
+#define SPM_DVFS_CMD7 (SPM_BASE + 0x72C)
+#define SPM_DVFS_CMD8 (SPM_BASE + 0x730)
+#define SPM_DVFS_CMD9 (SPM_BASE + 0x734)
+#define SPM_DVFS_CMD10 (SPM_BASE + 0x738)
+#define SPM_DVFS_CMD11 (SPM_BASE + 0x73C)
+#define SPM_DVFS_CMD12 (SPM_BASE + 0x740)
+#define SPM_DVFS_CMD13 (SPM_BASE + 0x744)
+#define SPM_DVFS_CMD14 (SPM_BASE + 0x748)
+#define SPM_DVFS_CMD15 (SPM_BASE + 0x74C)
+#define WDT_LATCH_SPARE0_FIX (SPM_BASE + 0x780)
+#define WDT_LATCH_SPARE1_FIX (SPM_BASE + 0x784)
+#define WDT_LATCH_SPARE2_FIX (SPM_BASE + 0x788)
+#define WDT_LATCH_SPARE3_FIX (SPM_BASE + 0x78C)
+#define SPARE_ACK_IN_FIX (SPM_BASE + 0x790)
+#define DCHA_LATCH_RSV0_FIX (SPM_BASE + 0x794)
+#define DCHB_LATCH_RSV0_FIX (SPM_BASE + 0x798)
+#define PCM_WDT_LATCH_0 (SPM_BASE + 0x800)
+#define PCM_WDT_LATCH_1 (SPM_BASE + 0x804)
+#define PCM_WDT_LATCH_2 (SPM_BASE + 0x808)
+#define PCM_WDT_LATCH_3 (SPM_BASE + 0x80C)
+#define PCM_WDT_LATCH_4 (SPM_BASE + 0x810)
+#define PCM_WDT_LATCH_5 (SPM_BASE + 0x814)
+#define PCM_WDT_LATCH_6 (SPM_BASE + 0x818)
+#define PCM_WDT_LATCH_7 (SPM_BASE + 0x81C)
+#define PCM_WDT_LATCH_8 (SPM_BASE + 0x820)
+#define PCM_WDT_LATCH_9 (SPM_BASE + 0x824)
+#define WDT_LATCH_SPARE0 (SPM_BASE + 0x828)
+#define WDT_LATCH_SPARE1 (SPM_BASE + 0x82C)
+#define WDT_LATCH_SPARE2 (SPM_BASE + 0x830)
+#define WDT_LATCH_SPARE3 (SPM_BASE + 0x834)
+#define PCM_WDT_LATCH_10 (SPM_BASE + 0x838)
+#define PCM_WDT_LATCH_11 (SPM_BASE + 0x83C)
+#define DCHA_GATING_LATCH_0 (SPM_BASE + 0x840)
+#define DCHA_GATING_LATCH_1 (SPM_BASE + 0x844)
+#define DCHA_GATING_LATCH_2 (SPM_BASE + 0x848)
+#define DCHA_GATING_LATCH_3 (SPM_BASE + 0x84C)
+#define DCHA_GATING_LATCH_4 (SPM_BASE + 0x850)
+#define DCHA_GATING_LATCH_5 (SPM_BASE + 0x854)
+#define DCHA_GATING_LATCH_6 (SPM_BASE + 0x858)
+#define DCHA_GATING_LATCH_7 (SPM_BASE + 0x85C)
+#define DCHB_GATING_LATCH_0 (SPM_BASE + 0x860)
+#define DCHB_GATING_LATCH_1 (SPM_BASE + 0x864)
+#define DCHB_GATING_LATCH_2 (SPM_BASE + 0x868)
+#define DCHB_GATING_LATCH_3 (SPM_BASE + 0x86C)
+#define DCHB_GATING_LATCH_4 (SPM_BASE + 0x870)
+#define DCHB_GATING_LATCH_5 (SPM_BASE + 0x874)
+#define DCHB_GATING_LATCH_6 (SPM_BASE + 0x878)
+#define DCHB_GATING_LATCH_7 (SPM_BASE + 0x87C)
+#define DCHA_LATCH_RSV0 (SPM_BASE + 0x880)
+#define DCHB_LATCH_RSV0 (SPM_BASE + 0x884)
+#define PCM_WDT_LATCH_12 (SPM_BASE + 0x888)
+#define PCM_WDT_LATCH_13 (SPM_BASE + 0x88C)
+#define SPM_PC_TRACE_CON (SPM_BASE + 0x8C0)
+#define SPM_PC_TRACE_G0 (SPM_BASE + 0x8C4)
+#define SPM_PC_TRACE_G1 (SPM_BASE + 0x8C8)
+#define SPM_PC_TRACE_G2 (SPM_BASE + 0x8CC)
+#define SPM_PC_TRACE_G3 (SPM_BASE + 0x8D0)
+#define SPM_PC_TRACE_G4 (SPM_BASE + 0x8D4)
+#define SPM_PC_TRACE_G5 (SPM_BASE + 0x8D8)
+#define SPM_PC_TRACE_G6 (SPM_BASE + 0x8DC)
+#define SPM_PC_TRACE_G7 (SPM_BASE + 0x8E0)
+#define SPM_ACK_CHK_CON (SPM_BASE + 0x900)
+#define SPM_ACK_CHK_PC (SPM_BASE + 0x904)
+#define SPM_ACK_CHK_SEL (SPM_BASE + 0x908)
+#define SPM_ACK_CHK_TIMER (SPM_BASE + 0x90C)
+#define SPM_ACK_CHK_STA (SPM_BASE + 0x910)
+#define SPM_ACK_CHK_LATCH (SPM_BASE + 0x914)
+#define SPM_ACK_CHK_CON2 (SPM_BASE + 0x920)
+#define SPM_ACK_CHK_PC2 (SPM_BASE + 0x924)
+#define SPM_ACK_CHK_SEL2 (SPM_BASE + 0x928)
+#define SPM_ACK_CHK_TIMER2 (SPM_BASE + 0x92C)
+#define SPM_ACK_CHK_STA2 (SPM_BASE + 0x930)
+#define SPM_ACK_CHK_LATCH2 (SPM_BASE + 0x934)
+#define SPM_ACK_CHK_CON3 (SPM_BASE + 0x940)
+#define SPM_ACK_CHK_PC3 (SPM_BASE + 0x944)
+#define SPM_ACK_CHK_SEL3 (SPM_BASE + 0x948)
+#define SPM_ACK_CHK_TIMER3 (SPM_BASE + 0x94C)
+#define SPM_ACK_CHK_STA3 (SPM_BASE + 0x950)
+#define SPM_ACK_CHK_LATCH3 (SPM_BASE + 0x954)
+#define SPM_ACK_CHK_CON4 (SPM_BASE + 0x960)
+#define SPM_ACK_CHK_PC4 (SPM_BASE + 0x964)
+#define SPM_ACK_CHK_SEL4 (SPM_BASE + 0x968)
+#define SPM_ACK_CHK_TIMER4 (SPM_BASE + 0x96C)
+#define SPM_ACK_CHK_STA4 (SPM_BASE + 0x970)
+#define SPM_ACK_CHK_LATCH4 (SPM_BASE + 0x974)
+
+/* POWERON_CONFIG_EN (0x10006000+0x000) */
+#define BCLK_CG_EN_LSB (1U << 0) /* 1b */
+#define MD_BCLK_CG_EN_LSB (1U << 1) /* 1b */
+#define PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* SPM_POWER_ON_VAL0 (0x10006000+0x004) */
+#define POWER_ON_VAL0_LSB (1U << 0) /* 32b */
+/* SPM_POWER_ON_VAL1 (0x10006000+0x008) */
+#define POWER_ON_VAL1_LSB (1U << 0) /* 32b */
+/* SPM_CLK_CON (0x10006000+0x00C) */
+#define SYSCLK0_EN_CTRL_LSB (1U << 0) /* 2b */
+#define SYSCLK1_EN_CTRL_LSB (1U << 2) /* 2b */
+#define SYS_SETTLE_SEL_LSB (1U << 4) /* 1b */
+#define SPM_LOCK_INFRA_DCM_LSB (1U << 5) /* 1b */
+#define EXT_SRCCLKEN_MASK_LSB (1U << 6) /* 3b */
+#define CXO32K_REMOVE_EN_MD1_LSB (1U << 9) /* 1b */
+#define CXO32K_REMOVE_EN_MD2_LSB (1U << 10) /* 1b */
+#define CLKSQ0_SEL_CTRL_LSB (1U << 11) /* 1b */
+#define CLKSQ1_SEL_CTRL_LSB (1U << 12) /* 1b */
+#define SRCLKEN0_EN_LSB (1U << 13) /* 1b */
+#define SRCLKEN1_EN_LSB (1U << 14) /* 1b */
+#define SCP_DCM_EN_LSB (1U << 15) /* 1b */
+#define SYSCLK0_SRC_MASK_B_LSB (1U << 16) /* 7b */
+#define SYSCLK1_SRC_MASK_B_LSB (1U << 23) /* 7b */
+/* SPM_CLK_SETTLE (0x10006000+0x010) */
+#define SYSCLK_SETTLE_LSB (1U << 0) /* 28b */
+/* SPM_AP_STANDBY_CON (0x10006000+0x014) */
+#define WFI_OP_LSB (1U << 0) /* 1b */
+#define MP0_CPUTOP_IDLE_MASK_LSB (1U << 1) /* 1b */
+#define MP1_CPUTOP_IDLE_MASK_LSB (1U << 2) /* 1b */
+#define MCUSYS_IDLE_MASK_LSB (1U << 4) /* 1b */
+#define MM_MASK_B_LSB (1U << 16) /* 2b */
+#define MD_DDR_EN_0_DBC_EN_LSB (1U << 18) /* 1b */
+#define MD_DDR_EN_1_DBC_EN_LSB (1U << 19) /* 1b */
+#define MD_MASK_B_LSB (1U << 20) /* 2b */
+#define SSPM_MASK_B_LSB (1U << 22) /* 1b */
+#define SCP_MASK_B_LSB (1U << 23) /* 1b */
+#define SRCCLKENI_MASK_B_LSB (1U << 24) /* 1b */
+#define MD_APSRC_1_SEL_LSB (1U << 25) /* 1b */
+#define MD_APSRC_0_SEL_LSB (1U << 26) /* 1b */
+#define CONN_DDR_EN_DBC_EN_LSB (1U << 27) /* 1b */
+#define CONN_MASK_B_LSB (1U << 28) /* 1b */
+#define CONN_APSRC_SEL_LSB (1U << 29) /* 1b */
+/* PCM_CON0 (0x10006000+0x018) */
+#define PCM_KICK_L_LSB (1U << 0) /* 1b */
+#define IM_KICK_L_LSB (1U << 1) /* 1b */
+#define PCM_CK_EN_LSB (1U << 2) /* 1b */
+#define EN_IM_SLEEP_DVS_LSB (1U << 3) /* 1b */
+#define IM_AUTO_PDN_EN_LSB (1U << 4) /* 1b */
+#define PCM_SW_RESET_LSB (1U << 15) /* 1b */
+#define PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* PCM_CON1 (0x10006000+0x01C) */
+#define IM_SLAVE_LSB (1U << 0) /* 1b */
+#define IM_SLEEP_LSB (1U << 1) /* 1b */
+#define MIF_APBEN_LSB (1U << 3) /* 1b */
+#define IM_PDN_LSB (1U << 4) /* 1b */
+#define PCM_TIMER_EN_LSB (1U << 5) /* 1b */
+#define IM_NONRP_EN_LSB (1U << 6) /* 1b */
+#define DIS_MIF_PROT_LSB (1U << 7) /* 1b */
+#define PCM_WDT_EN_LSB (1U << 8) /* 1b */
+#define PCM_WDT_WAKE_MODE_LSB (1U << 9) /* 1b */
+#define SPM_SRAM_SLEEP_B_LSB (1U << 10) /* 1b */
+#define SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */
+#define EVENT_LOCK_EN_LSB (1U << 12) /* 1b */
+#define SRCCLKEN_FAST_RESP_LSB (1U << 13) /* 1b */
+#define SCP_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */
+#define PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* PCM_IM_PTR (0x10006000+0x020) */
+#define PCM_IM_PTR_LSB (1U << 0) /* 32b */
+/* PCM_IM_LEN (0x10006000+0x024) */
+#define PCM_IM_LEN_LSB (1U << 0) /* 13b */
+/* PCM_REG_DATA_INI (0x10006000+0x028) */
+#define PCM_REG_DATA_INI_LSB (1U << 0) /* 32b */
+/* PCM_PWR_IO_EN (0x10006000+0x02C) */
+#define PCM_PWR_IO_EN_LSB (1U << 0) /* 8b */
+#define PCM_RF_SYNC_EN_LSB (1U << 16) /* 8b */
+/* PCM_TIMER_VAL (0x10006000+0x030) */
+#define PCM_TIMER_VAL_LSB (1U << 0) /* 32b */
+/* PCM_WDT_VAL (0x10006000+0x034) */
+#define PCM_WDT_VAL_LSB (1U << 0) /* 32b */
+/* PCM_IM_HOST_RW_PTR (0x10006000+0x038) */
+#define PCM_IM_HOST_RW_PTR_LSB (1U << 0) /* 12b */
+#define PCM_IM_HOST_W_EN_LSB (1U << 30) /* 1b */
+#define PCM_IM_HOST_EN_LSB (1U << 31) /* 1b */
+/* PCM_IM_HOST_RW_DAT (0x10006000+0x03C) */
+#define PCM_IM_HOST_RW_DAT_LSB (1U << 0) /* 32b */
+/* PCM_EVENT_VECTOR0 (0x10006000+0x040) */
+#define PCM_EVENT_VECTOR_0_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_0_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_0_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_0_LSB (1U << 16) /* 11b */
+/* PCM_EVENT_VECTOR1 (0x10006000+0x044) */
+#define PCM_EVENT_VECTOR_1_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_1_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_1_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_1_LSB (1U << 16) /* 11b */
+/* PCM_EVENT_VECTOR2 (0x10006000+0x048) */
+#define PCM_EVENT_VECTOR_2_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_2_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_2_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_2_LSB (1U << 16) /* 11b */
+/* PCM_EVENT_VECTOR3 (0x10006000+0x04C) */
+#define PCM_EVENT_VECTOR_3_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_3_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_3_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_3_LSB (1U << 16) /* 11b */
+/* PCM_EVENT_VECTOR4 (0x10006000+0x050) */
+#define PCM_EVENT_VECTOR_4_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_4_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_4_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_4_LSB (1U << 16) /* 11b */
+/* PCM_EVENT_VECTOR5 (0x10006000+0x054) */
+#define PCM_EVENT_VECTOR_5_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_5_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_5_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_5_LSB (1U << 16) /* 11b */
+/* PCM_EVENT_VECTOR6 (0x10006000+0x058) */
+#define PCM_EVENT_VECTOR_6_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_6_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_6_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_6_LSB (1U << 16) /* 11b */
+/* PCM_EVENT_VECTOR7 (0x10006000+0x05C) */
+#define PCM_EVENT_VECTOR_7_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_7_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_7_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_7_LSB (1U << 16) /* 11b */
+/* PCM_EVENT_VECTOR8 (0x10006000+0x060) */
+#define PCM_EVENT_VECTOR_8_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_8_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_8_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_8_LSB (1U << 16) /* 11b */
+/* PCM_EVENT_VECTOR9 (0x10006000+0x064) */
+#define PCM_EVENT_VECTOR_9_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_9_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_9_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_9_LSB (1U << 16) /* 11b */
+/* PCM_EVENT_VECTOR10 (0x10006000+0x068) */
+#define PCM_EVENT_VECTOR_10_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_10_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_10_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_10_LSB (1U << 16) /* 11b */
+/* PCM_EVENT_VECTOR11 (0x10006000+0x06C) */
+#define PCM_EVENT_VECTOR_11_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_11_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_11_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_11_LSB (1U << 16) /* 11b */
+/* PCM_EVENT_VECTOR12 (0x10006000+0x070) */
+#define PCM_EVENT_VECTOR_12_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_12_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_12_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_12_LSB (1U << 16) /* 11b */
+/* PCM_EVENT_VECTOR13 (0x10006000+0x074) */
+#define PCM_EVENT_VECTOR_13_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_13_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_13_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_13_LSB (1U << 16) /* 11b */
+/* PCM_EVENT_VECTOR14 (0x10006000+0x078) */
+#define PCM_EVENT_VECTOR_14_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_14_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_14_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_14_LSB (1U << 16) /* 11b */
+/* PCM_EVENT_VECTOR15 (0x10006000+0x07C) */
+#define PCM_EVENT_VECTOR_15_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_15_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_15_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_15_LSB (1U << 16) /* 11b */
+/* PCM_EVENT_VECTOR_EN (0x10006000+0x080) */
+#define PCM_EVENT_VECTOR_EN_LSB (1U << 0) /* 16b */
+/* SPM_SRAM_RSV_CON (0x10006000+0x088) */
+#define SPM_SRAM_SLEEP_B_ECO_EN_LSB (1U << 0) /* 1b */
+/* SPM_SWINT (0x10006000+0x08C) */
+#define SPM_SWINT_LSB (1U << 0) /* 10b */
+/* SPM_SWINT_SET (0x10006000+0x090) */
+#define SPM_SWINT_SET_LSB (1U << 0) /* 10b */
+/* SPM_SWINT_CLR (0x10006000+0x094) */
+#define SPM_SWINT_CLR_LSB (1U << 0) /* 10b */
+/* SPM_SCP_MAILBOX (0x10006000+0x098) */
+#define SPM_SCP_MAILBOX_LSB (1U << 0) /* 32b */
+/* SCP_SPM_MAILBOX (0x10006000+0x09C) */
+#define SCP_SPM_MAILBOX_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CON (0x10006000+0x0A0) */
+#define TWAM_ENABLE_LSB (1U << 0) /* 1b */
+#define TWAM_SPEED_MODE_ENABLE_LSB (1U << 1) /* 1b */
+#define TWAM_SW_RST_LSB (1U << 2) /* 1b */
+#define TWAM_MON_TYPE0_LSB (1U << 4) /* 2b */
+#define TWAM_MON_TYPE1_LSB (1U << 6) /* 2b */
+#define TWAM_MON_TYPE2_LSB (1U << 8) /* 2b */
+#define TWAM_MON_TYPE3_LSB (1U << 10) /* 2b */
+#define TWAM_SIGNAL_SEL0_LSB (1U << 12) /* 5b */
+#define TWAM_SIGNAL_SEL1_LSB (1U << 17) /* 5b */
+#define TWAM_SIGNAL_SEL2_LSB (1U << 22) /* 5b */
+#define TWAM_SIGNAL_SEL3_LSB (1U << 27) /* 5b */
+/* SPM_TWAM_WINDOW_LEN (0x10006000+0x0A4) */
+#define TWAM_WINDOW_LEN_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_IDLE_SEL (0x10006000+0x0A8) */
+#define TWAM_IDLE_SEL_LSB (1U << 0) /* 5b */
+/* SPM_SCP_IRQ (0x10006000+0x0AC) */
+#define SPM_SCP_IRQ_LSB (1U << 0) /* 1b */
+#define SPM_SCP_IRQ_SEL_LSB (1U << 4) /* 1b */
+/* SPM_CPU_WAKEUP_EVENT (0x10006000+0x0B0) */
+#define SPM_CPU_WAKEUP_EVENT_LSB (1U << 0) /* 1b */
+/* SPM_IRQ_MASK (0x10006000+0x0B4) */
+#define SPM_TWAM_IRQ_MASK_LSB (1U << 2) /* 1b */
+#define PCM_IRQ_ROOT_MASK_LSB (1U << 3) /* 1b */
+#define SPM_IRQ_MASK_LSB (1U << 8) /* 10b */
+/* SPM_SRC_REQ (0x10006000+0x0B8) */
+#define SPM_APSRC_REQ_LSB (1U << 0) /* 1b */
+#define SPM_F26M_REQ_LSB (1U << 1) /* 1b */
+#define SPM_INFRA_REQ_LSB (1U << 3) /* 1b */
+#define SPM_VRF18_REQ_LSB (1U << 4) /* 1b */
+#define SPM_DDREN_REQ_LSB (1U << 7) /* 1b */
+#define SPM_RSV_SRC_REQ_LSB (1U << 8) /* 3b */
+#define SPM_DDREN_2_REQ_LSB (1U << 11) /* 1b */
+#define CPU_MD_DVFS_SOP_FORCE_ON_LSB (1U << 16) /* 1b */
+/* SPM_SRC_MASK (0x10006000+0x0BC) */
+#define CSYSPWREQ_MASK_LSB (1U << 0) /* 1b */
+#define CCIF0_MD_EVENT_MASK_B_LSB (1U << 1) /* 1b */
+#define CCIF0_AP_EVENT_MASK_B_LSB (1U << 2) /* 1b */
+#define CCIF1_MD_EVENT_MASK_B_LSB (1U << 3) /* 1b */
+#define CCIF1_AP_EVENT_MASK_B_LSB (1U << 4) /* 1b */
+#define CCIF2_MD_EVENT_MASK_B_LSB (1U << 5) /* 1b */
+#define CCIF2_AP_EVENT_MASK_B_LSB (1U << 6) /* 1b */
+#define CCIF3_MD_EVENT_MASK_B_LSB (1U << 7) /* 1b */
+#define CCIF3_AP_EVENT_MASK_B_LSB (1U << 8) /* 1b */
+#define MD_SRCCLKENA_0_INFRA_MASK_B_LSB (1U << 9) /* 1b */
+#define MD_SRCCLKENA_1_INFRA_MASK_B_LSB (1U << 10) /* 1b */
+#define CONN_SRCCLKENA_INFRA_MASK_B_LSB (1U << 11) /* 1b */
+#define UFS_INFRA_REQ_MASK_B_LSB (1U << 12) /* 1b */
+#define SRCCLKENI_INFRA_MASK_B_LSB (1U << 13) /* 1b */
+#define MD_APSRC_REQ_0_INFRA_MASK_B_LSB (1U << 14) /* 1b */
+#define MD_APSRC_REQ_1_INFRA_MASK_B_LSB (1U << 15) /* 1b */
+#define CONN_APSRCREQ_INFRA_MASK_B_LSB (1U << 16) /* 1b */
+#define UFS_SRCCLKENA_MASK_B_LSB (1U << 17) /* 1b */
+#define MD_VRF18_REQ_0_MASK_B_LSB (1U << 18) /* 1b */
+#define MD_VRF18_REQ_1_MASK_B_LSB (1U << 19) /* 1b */
+#define UFS_VRF18_REQ_MASK_B_LSB (1U << 20) /* 1b */
+#define GCE_VRF18_REQ_MASK_B_LSB (1U << 21) /* 1b */
+#define CONN_INFRA_REQ_MASK_B_LSB (1U << 22) /* 1b */
+#define GCE_APSRC_REQ_MASK_B_LSB (1U << 23) /* 1b */
+#define DISP0_APSRC_REQ_MASK_B_LSB (1U << 24) /* 1b */
+#define DISP1_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */
+#define MFG_REQ_MASK_B_LSB (1U << 26) /* 1b */
+#define VDEC_REQ_MASK_B_LSB (1U << 27) /* 1b */
+/* SPM_SRC2_MASK (0x10006000+0x0C0) */
+#define MD_DDR_EN_0_MASK_B_LSB (1U << 0) /* 1b */
+#define MD_DDR_EN_1_MASK_B_LSB (1U << 1) /* 1b */
+#define CONN_DDR_EN_MASK_B_LSB (1U << 2) /* 1b */
+#define DDREN_SSPM_APSRC_REQ_MASK_B_LSB (1U << 3) /* 1b */
+#define DDREN_SCP_APSRC_REQ_MASK_B_LSB (1U << 4) /* 1b */
+#define DISP0_DDREN_MASK_B_LSB (1U << 5) /* 1b */
+#define DISP1_DDREN_MASK_B_LSB (1U << 6) /* 1b */
+#define GCE_DDREN_MASK_B_LSB (1U << 7) /* 1b */
+#define DDREN_EMI_SELF_REFRESH_CH0_MASK_B_LSB (1U << 8) /* 1b */
+#define DDREN_EMI_SELF_REFRESH_CH1_MASK_B_LSB (1U << 9) /* 1b */
+/* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0C4) */
+#define SPM_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */
+/* SPM_WAKEUP_EVENT_EXT_MASK (0x10006000+0x0C8) */
+#define SPM_WAKEUP_EVENT_EXT_MASK_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_EVENT_CLEAR (0x10006000+0x0CC) */
+#define SPM_TWAM_EVENT_CLEAR_LSB (1U << 0) /* 1b */
+/* SCP_CLK_CON (0x10006000+0x0D0) */
+#define SCP_26M_CK_SEL_LSB (1U << 0) /* 1b */
+#define SCP_SECURE_V_REQ_MASK_LSB (1U << 1) /* 1b */
+#define SCP_SLP_REQ_LSB (1U << 2) /* 1b */
+#define SCP_SLP_ACK_LSB (1U << 3) /* 1b */
+/* PCM_DEBUG_CON (0x10006000+0x0D4) */
+#define PCM_DEBUG_OUT_ENABLE_LSB (1U << 0) /* 1b */
+/* DDR_EN_DBC_LEN (0x10006000+0x0D8) */
+#define MD_DDR_EN_0_DBC_LEN_LSB (1U << 0) /* 10b */
+#define MD_DDR_EN_1_DBC_LEN_LSB (1U << 10) /* 10b */
+#define CONN_DDR_EN_DBC_LEN_LSB (1U << 20) /* 10b */
+/* AHB_BUS_CON (0x10006000+0x0DC) */
+#define AHB_HADDR_EXT_LSB (1U << 0) /* 2b */
+#define REG_AHB_LOCK_LSB (1U << 8) /* 1b */
+/* SPM_SRC3_MASK (0x10006000+0x0E0) */
+#define MD_DDR_EN_2_0_MASK_B_LSB (1U << 0) /* 1b */
+#define MD_DDR_EN_2_1_MASK_B_LSB (1U << 1) /* 1b */
+#define CONN_DDR_EN_2_MASK_B_LSB (1U << 2) /* 1b */
+#define DDREN2_SSPM_APSRC_REQ_MASK_B_LSB (1U << 3) /* 1b */
+#define DDREN2_SCP_APSRC_REQ_MASK_B_LSB (1U << 4) /* 1b */
+#define DISP0_DDREN2_MASK_B_LSB (1U << 5) /* 1b */
+#define DISP1_DDREN2_MASK_B_LSB (1U << 6) /* 1b */
+#define GCE_DDREN2_MASK_B_LSB (1U << 7) /* 1b */
+#define DDREN2_EMI_SELF_REFRESH_CH0_MASK_B_LSB (1U << 8) /* 1b */
+#define DDREN2_EMI_SELF_REFRESH_CH1_MASK_B_LSB (1U << 9) /* 1b */
+/* DDR_EN_EMI_DBC_CON (0x10006000+0x0E4) */
+#define EMI_SELF_REFRESH_CH0_DBC_LEN_LSB (1U << 0) /* 10b */
+#define EMI_SELF_REFRESH_CH0_DBC_EN_LSB (1U << 10) /* 1b */
+#define EMI_SELF_REFRESH_CH1_DBC_LEN_LSB (1U << 16) /* 10b */
+#define EMI_SELF_REFRESH_CH1_DBC_EN_LSB (1U << 26) /* 1b */
+/* SSPM_CLK_CON (0x10006000+0x0E8) */
+#define SSPM_26M_CK_SEL_LSB (1U << 0) /* 1b */
+/* PCM_REG0_DATA (0x10006000+0x100) */
+#define PCM_REG0_DATA_LSB (1U << 0) /* 32b */
+/* PCM_REG1_DATA (0x10006000+0x104) */
+#define PCM_REG1_DATA_LSB (1U << 0) /* 32b */
+/* PCM_REG2_DATA (0x10006000+0x108) */
+#define PCM_REG2_DATA_LSB (1U << 0) /* 32b */
+/* PCM_REG3_DATA (0x10006000+0x10C) */
+#define PCM_REG3_DATA_LSB (1U << 0) /* 32b */
+/* PCM_REG4_DATA (0x10006000+0x110) */
+#define PCM_REG4_DATA_LSB (1U << 0) /* 32b */
+/* PCM_REG5_DATA (0x10006000+0x114) */
+#define PCM_REG5_DATA_LSB (1U << 0) /* 32b */
+/* PCM_REG6_DATA (0x10006000+0x118) */
+#define PCM_REG6_DATA_LSB (1U << 0) /* 32b */
+/* PCM_REG7_DATA (0x10006000+0x11C) */
+#define PCM_REG7_DATA_LSB (1U << 0) /* 32b */
+/* PCM_REG8_DATA (0x10006000+0x120) */
+#define PCM_REG8_DATA_LSB (1U << 0) /* 32b */
+/* PCM_REG9_DATA (0x10006000+0x124) */
+#define PCM_REG9_DATA_LSB (1U << 0) /* 32b */
+/* PCM_REG10_DATA (0x10006000+0x128) */
+#define PCM_REG10_DATA_LSB (1U << 0) /* 32b */
+/* PCM_REG11_DATA (0x10006000+0x12C) */
+#define PCM_REG11_DATA_LSB (1U << 0) /* 32b */
+/* PCM_REG12_DATA (0x10006000+0x130) */
+#define PCM_REG12_DATA_LSB (1U << 0) /* 32b */
+/* PCM_REG13_DATA (0x10006000+0x134) */
+#define PCM_REG13_DATA_LSB (1U << 0) /* 32b */
+/* PCM_REG14_DATA (0x10006000+0x138) */
+#define PCM_REG14_DATA_LSB (1U << 0) /* 32b */
+/* PCM_REG15_DATA (0x10006000+0x13C) */
+#define PCM_REG15_DATA_LSB (1U << 0) /* 32b */
+/* PCM_REG12_MASK_B_STA (0x10006000+0x140) */
+#define PCM_REG12_MASK_B_STA_LSB (1U << 0) /* 32b */
+/* PCM_REG12_EXT_DATA (0x10006000+0x144) */
+#define PCM_REG12_EXT_DATA_LSB (1U << 0) /* 32b */
+/* PCM_REG12_EXT_MASK_B_STA (0x10006000+0x148) */
+#define PCM_REG12_EXT_MASK_B_STA_LSB (1U << 0) /* 32b */
+/* PCM_EVENT_REG_STA (0x10006000+0x14C) */
+#define PCM_EVENT_REG_STA_LSB (1U << 0) /* 32b */
+/* PCM_TIMER_OUT (0x10006000+0x150) */
+#define PCM_TIMER_OUT_LSB (1U << 0) /* 32b */
+/* PCM_WDT_OUT (0x10006000+0x154) */
+#define PCM_WDT_OUT_LSB (1U << 0) /* 32b */
+/* SPM_IRQ_STA (0x10006000+0x158) */
+#define SPM_ACK_CHK_WAKEUP_LSB (1U << 1) /* 1b */
+#define TWAM_IRQ_LSB (1U << 2) /* 1b */
+#define PCM_IRQ_LSB (1U << 3) /* 1b */
+/* #define SPM_SWINT_LSB (1U << 4) */ /* 10b */
+/* SPM_WAKEUP_STA (0x10006000+0x15C) */
+#define SPM_WAKEUP_EVENT_STA_LSB (1U << 0) /* 32b */
+/* SPM_WAKEUP_EXT_STA (0x10006000+0x160) */
+#define SPM_WAKEUP_EVENT_EXT_STA_LSB (1U << 0) /* 32b */
+/* SPM_WAKEUP_MISC (0x10006000+0x164) */
+#define SPM_WAKEUP_EVENT_MISC_LSB (1U << 0) /* 30b */
+#define SPM_PWRAP_IRQ_ACK_LSB (1U << 30) /* 1b */
+#define SPM_PWRAP_IRQ_LSB (1U << 31) /* 1b */
+/* BUS_PROTECT_RDY (0x10006000+0x168) */
+#define BUS_PROTECT_RDY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT2_RDY (0x10006000+0x16C) */
+#define BUS_PROTECT2_RDY_LSB (1U << 0) /* 32b */
+/* SUBSYS_IDLE_STA (0x10006000+0x170) */
+#define SUBSYS_IDLE_STA_LSB (1U << 0) /* 32b */
+/* CPU_IDLE_STA (0x10006000+0x174) */
+#define MP0_CPU0_STANDBYWFI_AFTER_SEL_LSB (1U << 0) /* 1b */
+#define MP0_CPU1_STANDBYWFI_AFTER_SEL_LSB (1U << 1) /* 1b */
+#define MP0_CPU2_STANDBYWFI_AFTER_SEL_LSB (1U << 2) /* 1b */
+#define MP0_CPU3_STANDBYWFI_AFTER_SEL_LSB (1U << 3) /* 1b */
+#define MP1_CPU0_STANDBYWFI_AFTER_SEL_LSB (1U << 4) /* 1b */
+#define MP1_CPU1_STANDBYWFI_AFTER_SEL_LSB (1U << 5) /* 1b */
+#define MP1_CPU2_STANDBYWFI_AFTER_SEL_LSB (1U << 6) /* 1b */
+#define MP1_CPU3_STANDBYWFI_AFTER_SEL_LSB (1U << 7) /* 1b */
+#define MP0_CPU0_STANDBYWFI_LSB (1U << 10) /* 1b */
+#define MP0_CPU1_STANDBYWFI_LSB (1U << 11) /* 1b */
+#define MP0_CPU2_STANDBYWFI_LSB (1U << 12) /* 1b */
+#define MP0_CPU3_STANDBYWFI_LSB (1U << 13) /* 1b */
+#define MP1_CPU0_STANDBYWFI_LSB (1U << 14) /* 1b */
+#define MP1_CPU1_STANDBYWFI_LSB (1U << 15) /* 1b */
+#define MP1_CPU2_STANDBYWFI_LSB (1U << 16) /* 1b */
+#define MP1_CPU3_STANDBYWFI_LSB (1U << 17) /* 1b */
+#define MP0_CPUTOP_IDLE_LSB (1U << 20) /* 1b */
+#define MP1_CPUTOP_IDLE_LSB (1U << 21) /* 1b */
+#define MCU_BIU_IDLE_LSB (1U << 22) /* 1b */
+#define MCUSYS_IDLE_LSB (1U << 23) /* 1b */
+/* PCM_FSM_STA (0x10006000+0x178) */
+#define EXEC_INST_OP_LSB (1U << 0) /* 4b */
+#define PC_STATE_LSB (1U << 4) /* 3b */
+#define IM_STATE_LSB (1U << 7) /* 3b */
+#define MASTER_STATE_LSB (1U << 10) /* 5b */
+#define EVENT_FSM_LSB (1U << 15) /* 3b */
+#define PCM_CLK_SEL_STA_LSB (1U << 18) /* 3b */
+#define PCM_KICK_LSB (1U << 21) /* 1b */
+#define IM_KICK_LSB (1U << 22) /* 1b */
+#define EXT_SRCCLKEN_STA_LSB (1U << 23) /* 2b */
+#define EXT_SRCVOLTEN_STA_LSB (1U << 25) /* 1b */
+/* SRC_REQ_STA (0x10006000+0x17C) */
+#define SRC_REQ_STA_LSB (1U << 0) /* 32b */
+/* PWR_STATUS (0x10006000+0x180) */
+#define PWR_STATUS_LSB (1U << 0) /* 32b */
+/* PWR_STATUS_2ND (0x10006000+0x184) */
+#define PWR_STATUS_2ND_LSB (1U << 0) /* 32b */
+/* CPU_PWR_STATUS (0x10006000+0x188) */
+#define CPU_PWR_STATUS_LSB (1U << 0) /* 32b */
+/* CPU_PWR_STATUS_2ND (0x10006000+0x18C) */
+#define CPU_PWR_STATUS_2ND_LSB (1U << 0) /* 32b */
+/* MISC_STA (0x10006000+0x190) */
+#define MM_DVFS_HALT_AF_MASK_LSB (1U << 0) /* 5b */
+/* SPM_SRC_RDY_STA (0x10006000+0x194) */
+#define SPM_INFRA_SRC_ACK_LSB (1U << 0) /* 1b */
+#define SPM_VRF18_SRC_ACK_LSB (1U << 1) /* 1b */
+/* DRAMC_DBG_LATCH (0x10006000+0x19C) */
+#define DRAMC_DEBUG_LATCH_STATUS_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_LAST_STA0 (0x10006000+0x1A0) */
+#define SPM_TWAM_LAST_STA0_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_LAST_STA1 (0x10006000+0x1A4) */
+#define SPM_TWAM_LAST_STA1_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_LAST_STA2 (0x10006000+0x1A8) */
+#define SPM_TWAM_LAST_STA2_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_LAST_STA3 (0x10006000+0x1AC) */
+#define SPM_TWAM_LAST_STA3_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CURR_STA0 (0x10006000+0x1B0) */
+#define SPM_TWAM_CURR_STA0_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CURR_STA1 (0x10006000+0x1B4) */
+#define SPM_TWAM_CURR_STA1_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CURR_STA2 (0x10006000+0x1B8) */
+#define SPM_TWAM_CURR_STA2_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CURR_STA3 (0x10006000+0x1BC) */
+#define SPM_TWAM_CURR_STA3_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_TIMER_OUT (0x10006000+0x1C0) */
+#define SPM_TWAM_TIMER_OUT_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_STA (0x10006000+0x1C8) */
+#define MD_DVFS_ERROR_STATUS_LSB (1U << 0) /* 1b */
+/* BUS_PROTECT3_RDY (0x10006000+0x1CC) */
+#define BUS_PROTECT_MM_RDY_LSB (1U << 0) /* 16b */
+#define BUS_PROTECT_MCU_RDY_LSB (1U << 16) /* 16b */
+/* SRC_DDREN_STA (0x10006000+0x1E0) */
+#define SRC_DDREN_STA_LSB (1U << 0) /* 32b */
+/* MCU_PWR_CON (0x10006000+0x200) */
+#define MCU_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MCU_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MCU_PWR_ON_LSB (1U << 2) /* 1b */
+#define MCU_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MCU_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MCU_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define MCU_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define MCU_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */
+#define MCU_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define MCU_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */
+#define SC_MCU_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+#define SC_MCU_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */
+/* MP0_CPUTOP_PWR_CON (0x10006000+0x204) */
+#define MP0_CPUTOP_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MP0_CPUTOP_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MP0_CPUTOP_PWR_ON_LSB (1U << 2) /* 1b */
+#define MP0_CPUTOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MP0_CPUTOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MP0_CPUTOP_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define MP0_CPUTOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define MP0_CPUTOP_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */
+#define MP0_CPUTOP_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define MP0_CPUTOP_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */
+#define SC_MP0_CPUTOP_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+#define SC_MP0_CPUTOP_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */
+/* MP0_CPU0_PWR_CON (0x10006000+0x208) */
+#define MP0_CPU0_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MP0_CPU0_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MP0_CPU0_PWR_ON_LSB (1U << 2) /* 1b */
+#define MP0_CPU0_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MP0_CPU0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MP0_CPU0_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define MP0_CPU0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define MP0_CPU0_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */
+#define MP0_CPU0_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define MP0_CPU0_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */
+#define SC_MP0_CPU0_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+#define SC_MP0_CPU0_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */
+/* MP0_CPU1_PWR_CON (0x10006000+0x20C) */
+#define MP0_CPU1_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MP0_CPU1_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MP0_CPU1_PWR_ON_LSB (1U << 2) /* 1b */
+#define MP0_CPU1_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MP0_CPU1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MP0_CPU1_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define MP0_CPU1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define MP0_CPU1_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */
+#define MP0_CPU1_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define MP0_CPU1_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */
+#define SC_MP0_CPU1_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+#define SC_MP0_CPU1_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */
+/* MP0_CPU2_PWR_CON (0x10006000+0x210) */
+#define MP0_CPU2_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MP0_CPU2_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MP0_CPU2_PWR_ON_LSB (1U << 2) /* 1b */
+#define MP0_CPU2_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MP0_CPU2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MP0_CPU2_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define MP0_CPU2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define MP0_CPU2_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */
+#define MP0_CPU2_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define MP0_CPU2_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */
+#define SC_MP0_CPU2_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+#define SC_MP0_CPU2_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */
+/* MP0_CPU3_PWR_CON (0x10006000+0x214) */
+#define MP0_CPU3_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MP0_CPU3_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MP0_CPU3_PWR_ON_LSB (1U << 2) /* 1b */
+#define MP0_CPU3_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MP0_CPU3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MP0_CPU3_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define MP0_CPU3_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define MP0_CPU3_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */
+#define MP0_CPU3_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define MP0_CPU3_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */
+#define SC_MP0_CPU3_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+#define SC_MP0_CPU3_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */
+/* MP1_CPUTOP_PWR_CON (0x10006000+0x218) */
+#define MP1_CPUTOP_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MP1_CPUTOP_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MP1_CPUTOP_PWR_ON_LSB (1U << 2) /* 1b */
+#define MP1_CPUTOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MP1_CPUTOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MP1_CPUTOP_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define MP1_CPUTOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define MP1_CPUTOP_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */
+#define MP1_CPUTOP_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define MP1_CPUTOP_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */
+#define SC_MP1_CPUTOP_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+#define SC_MP1_CPUTOP_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */
+/* MP1_CPU0_PWR_CON (0x10006000+0x21C) */
+#define MP1_CPU0_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MP1_CPU0_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MP1_CPU0_PWR_ON_LSB (1U << 2) /* 1b */
+#define MP1_CPU0_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MP1_CPU0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MP1_CPU0_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define MP1_CPU0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define MP1_CPU0_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */
+#define MP1_CPU0_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define MP1_CPU0_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */
+#define SC_MP1_CPU0_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+#define SC_MP1_CPU0_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */
+/* MP1_CPU1_PWR_CON (0x10006000+0x220) */
+#define MP1_CPU1_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MP1_CPU1_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MP1_CPU1_PWR_ON_LSB (1U << 2) /* 1b */
+#define MP1_CPU1_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MP1_CPU1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MP1_CPU1_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define MP1_CPU1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define MP1_CPU1_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */
+#define MP1_CPU1_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define MP1_CPU1_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */
+#define SC_MP1_CPU1_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+#define SC_MP1_CPU1_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */
+/* MP1_CPU2_PWR_CON (0x10006000+0x224) */
+#define MP1_CPU2_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MP1_CPU2_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MP1_CPU2_PWR_ON_LSB (1U << 2) /* 1b */
+#define MP1_CPU2_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MP1_CPU2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MP1_CPU2_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define MP1_CPU2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define MP1_CPU2_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */
+#define MP1_CPU2_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define MP1_CPU2_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */
+#define SC_MP1_CPU2_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+#define SC_MP1_CPU2_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */
+/* MP1_CPU3_PWR_CON (0x10006000+0x228) */
+#define MP1_CPU3_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MP1_CPU3_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MP1_CPU3_PWR_ON_LSB (1U << 2) /* 1b */
+#define MP1_CPU3_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MP1_CPU3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MP1_CPU3_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define MP1_CPU3_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define MP1_CPU3_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */
+#define MP1_CPU3_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define MP1_CPU3_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */
+#define SC_MP1_CPU3_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+#define SC_MP1_CPU3_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */
+/* MP0_CPUTOP_L2_PDN (0x10006000+0x240) */
+#define MP0_CPUTOP_L2_SRAM_PDN_LSB (1U << 0) /* 1b */
+#define MP0_CPUTOP_L2_SRAM_PDN_ACK_LSB (1U << 8) /* 1b */
+/* MP0_CPUTOP_L2_SLEEP_B (0x10006000+0x244) */
+#define MP0_CPUTOP_L2_SRAM_SLEEP_B_LSB (1U << 0) /* 1b */
+#define MP0_CPUTOP_L2_SRAM_SLEEP_B_ACK_LSB (1U << 8) /* 1b */
+/* MP0_CPU0_L1_PDN (0x10006000+0x248) */
+#define MP0_CPU0_L1_PDN_LSB (1U << 0) /* 1b */
+#define MP0_CPU0_L1_PDN_ACK_LSB (1U << 8) /* 1b */
+/* MP0_CPU1_L1_PDN (0x10006000+0x24C) */
+#define MP0_CPU1_L1_PDN_LSB (1U << 0) /* 1b */
+#define MP0_CPU1_L1_PDN_ACK_LSB (1U << 8) /* 1b */
+/* MP0_CPU2_L1_PDN (0x10006000+0x250) */
+#define MP0_CPU2_L1_PDN_LSB (1U << 0) /* 1b */
+#define MP0_CPU2_L1_PDN_ACK_LSB (1U << 8) /* 1b */
+/* MP0_CPU3_L1_PDN (0x10006000+0x254) */
+#define MP0_CPU3_L1_PDN_LSB (1U << 0) /* 1b */
+#define MP0_CPU3_L1_PDN_ACK_LSB (1U << 8) /* 1b */
+/* MP1_CPUTOP_L2_PDN (0x10006000+0x258) */
+#define MP1_CPUTOP_L2_SRAM_PDN_LSB (1U << 0) /* 1b */
+#define MP1_CPUTOP_L2_SRAM_PDN_ACK_LSB (1U << 8) /* 1b */
+/* MP1_CPUTOP_L2_SLEEP_B (0x10006000+0x25C) */
+#define MP1_CPUTOP_L2_SRAM_SLEEP_B_LSB (1U << 0) /* 1b */
+#define MP1_CPUTOP_L2_SRAM_SLEEP_B_ACK_LSB (1U << 8) /* 1b */
+/* MP1_CPU0_L1_PDN (0x10006000+0x260) */
+#define MP1_CPU0_L1_PDN_LSB (1U << 0) /* 1b */
+#define MP1_CPU0_L1_PDN_ACK_LSB (1U << 8) /* 1b */
+/* MP1_CPU1_L1_PDN (0x10006000+0x264) */
+#define MP1_CPU1_L1_PDN_LSB (1U << 0) /* 1b */
+#define MP1_CPU1_L1_PDN_ACK_LSB (1U << 8) /* 1b */
+/* MP1_CPU2_L1_PDN (0x10006000+0x268) */
+#define MP1_CPU2_L1_PDN_LSB (1U << 0) /* 1b */
+#define MP1_CPU2_L1_PDN_ACK_LSB (1U << 8) /* 1b */
+/* MP1_CPU3_L1_PDN (0x10006000+0x26C) */
+#define MP1_CPU3_L1_PDN_LSB (1U << 0) /* 1b */
+#define MP1_CPU3_L1_PDN_ACK_LSB (1U << 8) /* 1b */
+/* CPU_EXT_BUCK_ISO (0x10006000+0x290) */
+#define MP0_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */
+#define MP1_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */
+#define MP_EXT_BUCK_ISO_LSB (1U << 2) /* 1b */
+/* DUMMY1_PWR_CON (0x10006000+0x2B0) */
+#define DUMMY1_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define DUMMY1_PWR_ISO_LSB (1U << 1) /* 1b */
+#define DUMMY1_PWR_ON_LSB (1U << 2) /* 1b */
+#define DUMMY1_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define DUMMY1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+/* BYPASS_SPMC (0x10006000+0x2B4) */
+#define BYPASS_CPU_SPMC_MODE_LSB (1U << 0) /* 1b */
+/* SPMC_DORMANT_ENABLE (0x10006000+0x2B8) */
+#define MP0_SPMC_SRAM_DORMANT_EN_LSB (1U << 0) /* 1b */
+#define MP1_SPMC_SRAM_DORMANT_EN_LSB (1U << 1) /* 1b */
+/* ARMPLL_CLK_CON (0x10006000+0x2BC) */
+#define REG_SC_ARM_FHC_PAUSE_LSB (1U << 0) /* 3b */
+#define REG_SC_ARM_CLK_OFF_LSB (1U << 3) /* 3b */
+#define REG_SC_ARMPLLOUT_OFF_LSB (1U << 6) /* 3b */
+#define REG_SC_ARMPLL_OFF_LSB (1U << 9) /* 3b */
+#define REG_SC_ARMPLL_S_OFF_LSB (1U << 12) /* 3b */
+/* SPMC_IN_RET (0x10006000+0x2C0) */
+#define SPMC_STATUS_LSB (1U << 0) /* 8b */
+/* VDE_PWR_CON (0x10006000+0x300) */
+#define VDE_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define VDE_PWR_ISO_LSB (1U << 1) /* 1b */
+#define VDE_PWR_ON_LSB (1U << 2) /* 1b */
+#define VDE_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define VDE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define VDE_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define VDE_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+/* VEN_PWR_CON (0x10006000+0x304) */
+#define VEN_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define VEN_PWR_ISO_LSB (1U << 1) /* 1b */
+#define VEN_PWR_ON_LSB (1U << 2) /* 1b */
+#define VEN_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define VEN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define VEN_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define VEN_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+/* ISP_PWR_CON (0x10006000+0x308) */
+#define ISP_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define ISP_PWR_ISO_LSB (1U << 1) /* 1b */
+#define ISP_PWR_ON_LSB (1U << 2) /* 1b */
+#define ISP_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define ISP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define ISP_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define ISP_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+/* DIS_PWR_CON (0x10006000+0x30C) */
+#define DIS_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define DIS_PWR_ISO_LSB (1U << 1) /* 1b */
+#define DIS_PWR_ON_LSB (1U << 2) /* 1b */
+#define DIS_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define DIS_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define DIS_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define DIS_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+/* MFG_CORE1_PWR_CON (0x10006000+0x310) */
+#define MFG_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG_CORE1_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG_CORE1_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG_CORE1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG_CORE1_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define MFG_CORE1_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+/* AUDIO_PWR_CON (0x10006000+0x314) */
+#define AUD_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define AUD_PWR_ISO_LSB (1U << 1) /* 1b */
+#define AUD_PWR_ON_LSB (1U << 2) /* 1b */
+#define AUD_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define AUD_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define AUD_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define AUD_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+/* IFR_PWR_CON (0x10006000+0x318) */
+#define IFR_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define IFR_PWR_ISO_LSB (1U << 1) /* 1b */
+#define IFR_PWR_ON_LSB (1U << 2) /* 1b */
+#define IFR_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define IFR_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define IFR_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define IFR_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+/* DPY_PWR_CON (0x10006000+0x31C) */
+#define DPY_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define DPY_PWR_ISO_LSB (1U << 1) /* 1b */
+#define DPY_PWR_ON_LSB (1U << 2) /* 1b */
+#define DPY_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define DPY_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define DPY_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define DPY_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+/* MD1_PWR_CON (0x10006000+0x320) */
+#define MD1_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MD1_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MD1_PWR_ON_LSB (1U << 2) /* 1b */
+#define MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MD1_SRAM_PDN_LSB (1U << 8) /* 1b */
+/* VPU_TOP_PWR_CON (0x10006000+0x324) */
+#define VPU_TOP_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define VPU_TOP_PWR_ISO_LSB (1U << 1) /* 1b */
+#define VPU_TOP_PWR_ON_LSB (1U << 2) /* 1b */
+#define VPU_TOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define VPU_TOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define VPU_TOP_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define VPU_TOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define VPU_TOP_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define VPU_TOP_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+#define VPU_TOP_SRAM_SLPB_LSB (1U << 16) /* 4b */
+#define VPU_TOP_SRAM_SLPB_ACK_LSB (1U << 28) /* 4b */
+/* CONN_PWR_CON (0x10006000+0x32C) */
+#define CONN_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define CONN_PWR_ISO_LSB (1U << 1) /* 1b */
+#define CONN_PWR_ON_LSB (1U << 2) /* 1b */
+#define CONN_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define CONN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define CONN_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define CONN_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* VPU_CORE2_PWR_CON (0x10006000+0x330) */
+#define VPU_CORE2_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define VPU_CORE2_PWR_ISO_LSB (1U << 1) /* 1b */
+#define VPU_CORE2_PWR_ON_LSB (1U << 2) /* 1b */
+#define VPU_CORE2_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define VPU_CORE2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define VPU_CORE2_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define VPU_CORE2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define VPU_CORE2_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define VPU_CORE2_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+#define VPU_CORE2_SRAM_SLPB_LSB (1U << 16) /* 4b */
+#define VPU_CORE2_SRAM_SLPB_ACK_LSB (1U << 28) /* 4b */
+/* MFG_ASYNC_PWR_CON (0x10006000+0x334) */
+#define MFG_ASYNC_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG_ASYNC_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG_ASYNC_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG_ASYNC_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG_ASYNC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG_ASYNC_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define MFG_ASYNC_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+/* MFG_PWR_CON (0x10006000+0x338) */
+#define MFG_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define MFG_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+/* VPU_CORE0_PWR_CON (0x10006000+0x33C) */
+#define VPU_CORE0_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define VPU_CORE0_PWR_ISO_LSB (1U << 1) /* 1b */
+#define VPU_CORE0_PWR_ON_LSB (1U << 2) /* 1b */
+#define VPU_CORE0_ON_2ND_LSB (1U << 3) /* 1b */
+#define VPU_CORE0_CLK_DIS_LSB (1U << 4) /* 1b */
+#define VPU_CORE0_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define VPU_CORE0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define VPU_CORE0_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define VPU_CORE0_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+#define VPU_CORE0_SRAM_SLPB_LSB (1U << 16) /* 4b */
+#define VPU_CORE0_SRAM_SLPB_ACK_LSB (1U << 28) /* 4b */
+/* VPU_CORE1_PWR_CON (0x10006000+0x340) */
+#define VPU_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define VPU_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */
+#define VPU_CORE1_PWR_ON_LSB (1U << 2) /* 1b */
+#define VPU_CORE1_ON_2ND_LSB (1U << 3) /* 1b */
+#define VPU_CORE1_CLK_DIS_LSB (1U << 4) /* 1b */
+#define VPU_CORE1_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define VPU_CORE1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define VPU_CORE1_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define VPU_CORE1_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+#define VPU_CORE1_SRAM_SLPB_LSB (1U << 16) /* 4b */
+#define VPU_CORE1_SRAM_SLPB_ACK_LSB (1U << 28) /* 4b */
+/* CAM_PWR_CON (0x10006000+0x344) */
+#define CAM_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define CAM_PWR_ISO_LSB (1U << 1) /* 1b */
+#define CAM_PWR_ON_LSB (1U << 2) /* 1b */
+#define CAM_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define CAM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define CAM_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define CAM_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+/* MFG_2D_PWR_CON (0x10006000+0x348) */
+#define MFG_2D_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG_2D_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG_2D_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG_2D_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG_2D_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG_2D_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define MFG_2D_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+/* MFG_CORE0_PWR_CON (0x10006000+0x34C) */
+#define MFG_CORE0_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG_CORE0_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG_CORE0_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG_CORE0_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG_CORE0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG_CORE0_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define MFG_CORE0_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+/* SYSRAM_CON (0x10006000+0x350) */
+#define IFR_SRAMROM_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define IFR_SRAMROM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define IFR_SRAMROM_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */
+#define IFR_SRAMROM_SRAM_PDN_LSB (1U << 16) /* 8b */
+/* SYSROM_CON (0x10006000+0x354) */
+#define IFR_SRAMROM_ROM_PDN_LSB (1U << 0) /* 6b */
+/* SSPM_SRAM_CON (0x10006000+0x358) */
+#define SSPM_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define SSPM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define SSPM_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define SSPM_SRAM_PDN_LSB (1U << 16) /* 1b */
+/* SCP_SRAM_CON (0x10006000+0x35C) */
+#define SCP_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define SCP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define SCP_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define SCP_SRAM_PDN_LSB (1U << 16) /* 1b */
+/* UFS_SRAM_CON (0x10006000+0x36C) */
+#define UFS_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define UFS_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define UFS_SRAM_SLEEP_B_LSB (1U << 4) /* 5b */
+#define UFS_SRAM_PDN_LSB (1U << 16) /* 5b */
+/* DUMMY_SRAM_CON (0x10006000+0x380) */
+#define DUMMY_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DUMMY_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DUMMY_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */
+#define DUMMY_SRAM_PDN_LSB (1U << 16) /* 8b */
+/* MD_EXT_BUCK_ISO_CON (0x10006000+0x390) */
+#define VMODEM_BUCK_ELS_EN_LSB (1U << 0) /* 1b */
+#define VMD_BUCK_ELS_EN_LSB (1U << 1) /* 1b */
+/* MD_SRAM_ISO_CON (0x10006000+0x394) */
+#define MD1_SRAM_ISOINT_B_LSB (1U << 0) /* 1b */
+/* MD_EXTRA_PWR_CON (0x10006000+0x398) */
+#define MD1_PWR_PROT_REQ_STA_LSB (1U << 0) /* 1b */
+#define MD2_PWR_PROT_REQ_STA_LSB (1U << 1) /* 1b */
+/* EXT_BUCK_CON (0x10006000+0x3A0) */
+#define RG_VA09_ON_LSB (1U << 0) /* 1b */
+/* MBIST_EFUSE_REPAIR_ACK_STA (0x10006000+0x3D0) */
+#define MBIST_EFUSE_REPAIR_ACK_STA_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CON (0x10006000+0x400) */
+#define SPM_DVFS_CON_LSB (1U << 0) /* 4b */
+#define SPM_DVFS_ACK_LSB (1U << 30) /* 2b */
+/* SPM_MDBSI_CON (0x10006000+0x404) */
+#define SPM_MDBSI_CON_LSB (1U << 0) /* 3b */
+/* SPM_MAS_PAUSE_MASK_B (0x10006000+0x408) */
+#define SPM_MAS_PAUSE_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_MAS_PAUSE2_MASK_B (0x10006000+0x40C) */
+#define SPM_MAS_PAUSE2_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_BSI_GEN (0x10006000+0x410) */
+#define SPM_BSI_START_LSB (1U << 0) /* 1b */
+/* SPM_BSI_EN_SR (0x10006000+0x414) */
+#define SPM_BSI_EN_SR_LSB (1U << 0) /* 32b */
+/* SPM_BSI_CLK_SR (0x10006000+0x418) */
+#define SPM_BSI_CLK_SR_LSB (1U << 0) /* 32b */
+/* SPM_BSI_D0_SR (0x10006000+0x41C) */
+#define SPM_BSI_D0_SR_LSB (1U << 0) /* 32b */
+/* SPM_BSI_D1_SR (0x10006000+0x420) */
+#define SPM_BSI_D1_SR_LSB (1U << 0) /* 32b */
+/* SPM_BSI_D2_SR (0x10006000+0x424) */
+#define SPM_BSI_D2_SR_LSB (1U << 0) /* 32b */
+/* SPM_AP_SEMA (0x10006000+0x428) */
+#define SPM_AP_SEMA_LSB (1U << 0) /* 1b */
+/* SPM_SPM_SEMA (0x10006000+0x42C) */
+#define SPM_SPM_SEMA_LSB (1U << 0) /* 1b */
+/* AP_MDSRC_REQ (0x10006000+0x430) */
+#define AP_MDSMSRC_REQ_LSB (1U << 0) /* 1b */
+#define AP_L1SMSRC_REQ_LSB (1U << 1) /* 1b */
+#define AP_MD2SRC_REQ_LSB (1U << 2) /* 1b */
+#define AP_MDSMSRC_ACK_LSB (1U << 4) /* 1b */
+#define AP_L1SMSRC_ACK_LSB (1U << 5) /* 1b */
+#define AP_MD2SRC_ACK_LSB (1U << 6) /* 1b */
+/* SPM2MD_DVFS_CON (0x10006000+0x438) */
+#define SPM2MD_DVFS_CON_LSB (1U << 0) /* 32b */
+/* MD2SPM_DVFS_CON (0x10006000+0x43C) */
+#define MD2SPM_DVFS_CON_LSB (1U << 0) /* 32b */
+/* DRAMC_DPY_CLK_SW_CON_RSV (0x10006000+0x440) */
+#define SPM2DRAMC_SHUFFLE_START_LSB (1U << 0) /* 1b */
+#define SPM2DRAMC_SHUFFLE_SWITCH_LSB (1U << 1) /* 1b */
+#define SPM2DPY_DIV2_SYNC_LSB (1U << 2) /* 1b */
+#define SPM2DPY_1PLL_SWITCH_LSB (1U << 3) /* 1b */
+#define SPM2DPY_TEST_CK_MUX_LSB (1U << 4) /* 1b */
+#define SPM2DPY_ASYNC_MODE_LSB (1U << 5) /* 1b */
+#define SPM2TOP_ASYNC_MODE_LSB (1U << 6) /* 1b */
+/* DPY_LP_CON (0x10006000+0x444) */
+#define SC_DDRPHY_LP_SIGNALS_LSB (1U << 0) /* 3b */
+/* CPU_DVFS_REQ (0x10006000+0x448) */
+#define CPU_DVFS_REQ_LSB (1U << 0) /* 32b */
+/* SPM_PLL_CON (0x10006000+0x44C) */
+#define SC_MAINPLLOUT_OFF_LSB (1U << 0) /* 1b */
+#define SC_UNIPLLOUT_OFF_LSB (1U << 1) /* 1b */
+#define SC_MAINPLL_OFF_LSB (1U << 4) /* 1b */
+#define SC_UNIPLL_OFF_LSB (1U << 5) /* 1b */
+#define SC_MAINPLL_S_OFF_LSB (1U << 8) /* 1b */
+#define SC_UNIPLL_S_OFF_LSB (1U << 9) /* 1b */
+#define SC_SMI_CK_OFF_LSB (1U << 16) /* 1b */
+#define SC_SSPMK_CK_OFF_LSB (1U << 17) /* 1b */
+/* SPM_EMI_BW_MODE (0x10006000+0x450) */
+#define EMI_BW_MODE_LSB (1U << 0) /* 1b */
+#define EMI_BOOST_MODE_LSB (1U << 1) /* 1b */
+#define EMI_BW_MODE_2_LSB (1U << 2) /* 1b */
+#define EMI_BOOST_MODE_2_LSB (1U << 3) /* 1b */
+/* AP2MD_PEER_WAKEUP (0x10006000+0x454) */
+#define AP2MD_PEER_WAKEUP_LSB (1U << 0) /* 1b */
+/* ULPOSC_CON (0x10006000+0x458) */
+#define ULPOSC_EN_LSB (1U << 0) /* 1b */
+#define ULPOSC_RST_LSB (1U << 1) /* 1b */
+#define ULPOSC_CG_EN_LSB (1U << 2) /* 1b */
+#define ULPOSC_CLK_SEL_LSB (1U << 3) /* 1b */
+/* SPM2MM_CON (0x10006000+0x45C) */
+#define SPM2MM_FORCE_ULTRA_LSB (1U << 0) /* 1b */
+#define SPM2MM_DBL_OSTD_ACT_LSB (1U << 1) /* 1b */
+#define SPM2MM_ULTRAREQ_LSB (1U << 2) /* 1b */
+#define SPM2MD_ULTRAREQ_LSB (1U << 3) /* 1b */
+#define SPM2ISP_ULTRAREQ_LSB (1U << 4) /* 1b */
+#define MM2SPM_FORCE_ULTRA_ACK_LSB (1U << 16) /* 1b */
+#define MM2SPM_DBL_OSTD_ACT_ACK_LSB (1U << 17) /* 1b */
+#define SPM2ISP_ULTRAACK_D2T_LSB (1U << 18) /* 1b */
+#define SPM2MM_ULTRAACK_D2T_LSB (1U << 19) /* 1b */
+#define SPM2MD_ULTRAACK_D2T_LSB (1U << 20) /* 1b */
+/* DRAMC_DPY_CLK_SW_CON_SEL (0x10006000+0x460) */
+#define SW_DR_GATE_RETRY_EN_SEL_LSB (1U << 0) /* 2b */
+#define SW_EMI_CLK_OFF_SEL_LSB (1U << 2) /* 2b */
+#define SW_DPY_MODE_SW_SEL_LSB (1U << 4) /* 2b */
+#define SW_DMSUS_OFF_SEL_LSB (1U << 6) /* 2b */
+#define SW_MEM_CK_OFF_SEL_LSB (1U << 8) /* 2b */
+#define SW_DPY_2ND_DLL_EN_SEL_LSB (1U << 10) /* 2b */
+#define SW_DPY_DLL_EN_SEL_LSB (1U << 12) /* 2b */
+#define SW_DPY_DLL_CK_EN_SEL_LSB (1U << 14) /* 2b */
+#define SW_DPY_VREF_EN_SEL_LSB (1U << 16) /* 2b */
+#define SW_PHYPLL_EN_SEL_LSB (1U << 18) /* 2b */
+#define SW_DDRPHY_FB_CK_EN_SEL_LSB (1U << 20) /* 2b */
+#define SEPERATE_PHY_PWR_SEL_LSB (1U << 23) /* 1b */
+#define SW_DMDRAMCSHU_ACK_SEL_LSB (1U << 24) /* 2b */
+#define SW_EMI_CLK_OFF_ACK_SEL_LSB (1U << 26) /* 2b */
+#define SW_DR_SHORT_QUEUE_ACK_SEL_LSB (1U << 28) /* 2b */
+#define SW_DRAMC_DFS_STA_SEL_LSB (1U << 30) /* 2b */
+/* DRAMC_DPY_CLK_SW_CON (0x10006000+0x464) */
+#define SW_DR_GATE_RETRY_EN_LSB (1U << 0) /* 2b */
+#define SW_EMI_CLK_OFF_LSB (1U << 2) /* 2b */
+#define SW_DPY_MODE_SW_LSB (1U << 4) /* 2b */
+#define SW_DMSUS_OFF_LSB (1U << 6) /* 2b */
+#define SW_MEM_CK_OFF_LSB (1U << 8) /* 2b */
+#define SW_DPY_2ND_DLL_EN_LSB (1U << 10) /* 2b */
+#define SW_DPY_DLL_EN_LSB (1U << 12) /* 2b */
+#define SW_DPY_DLL_CK_EN_LSB (1U << 14) /* 2b */
+#define SW_DPY_VREF_EN_LSB (1U << 16) /* 2b */
+#define SW_PHYPLL_EN_LSB (1U << 18) /* 2b */
+#define SW_DDRPHY_FB_CK_EN_LSB (1U << 20) /* 2b */
+#define SC_DR_SHU_EN_ACK_LSB (1U << 24) /* 2b */
+#define EMI_CLK_OFF_ACK_LSB (1U << 26) /* 2b */
+#define SC_DR_SHORT_QUEUE_ACK_LSB (1U << 28) /* 2b */
+#define SC_DRAMC_DFS_STA_LSB (1U << 30) /* 2b */
+/* SPM_S1_MODE_CH (0x10006000+0x468) */
+#define SPM_S1_MODE_CH_LSB (1U << 0) /* 2b */
+#define S1_EMI_CK_SWITCH_LSB (1U << 8) /* 2b */
+/* EMI_SELF_REFRESH_CH_STA (0x10006000+0x46C) */
+#define EMI_SELF_REFRESH_CH_LSB (1U << 0) /* 2b */
+/* DRAMC_DPY_CLK_SW_CON_SEL2 (0x10006000+0x470) */
+#define SW_PHYPLL_SHU_EN_SEL_LSB (1U << 0) /* 1b */
+#define SW_PHYPLL2_SHU_EN_SEL_LSB (1U << 1) /* 1b */
+#define SW_PHYPLL_MODE_SW_SEL_LSB (1U << 2) /* 1b */
+#define SW_PHYPLL2_MODE_SW_SEL_LSB (1U << 3) /* 1b */
+#define SW_DR_SHORT_QUEUE_SEL_LSB (1U << 4) /* 1b */
+#define SW_DR_SHU_EN_SEL_LSB (1U << 5) /* 1b */
+#define SW_DR_SHU_LEVEL_SEL_LSB (1U << 6) /* 1b */
+#define SW_DPY_BCLK_ENABLE_SEL_LSB (1U << 8) /* 2b */
+#define SW_SHU_RESTORE_SEL_LSB (1U << 10) /* 2b */
+#define SW_DPHY_PRECAL_UP_SEL_LSB (1U << 12) /* 2b */
+#define SW_DPHY_RXDLY_TRACK_EN_SEL_LSB (1U << 14) /* 2b */
+#define SW_TX_TRACKING_DIS_SEL_LSB (1U << 16) /* 2b */
+/* DRAMC_DPY_CLK_SW_CON2 (0x10006000+0x474) */
+#define SW_PHYPLL_SHU_EN_LSB (1U << 0) /* 1b */
+#define SW_PHYPLL2_SHU_EN_LSB (1U << 1) /* 1b */
+#define SW_PHYPLL_MODE_SW_LSB (1U << 2) /* 1b */
+#define SW_PHYPLL2_MODE_SW_LSB (1U << 3) /* 1b */
+#define SW_DR_SHORT_QUEUE_LSB (1U << 4) /* 1b */
+#define SW_DR_SHU_EN_LSB (1U << 5) /* 1b */
+#define SW_DR_SHU_LEVEL_LSB (1U << 6) /* 2b */
+#define SW_DPY_BCLK_ENABLE_LSB (1U << 8) /* 2b */
+#define SW_SHU_RESTORE_LSB (1U << 10) /* 2b */
+#define SW_DPHY_PRECAL_UP_LSB (1U << 12) /* 2b */
+#define SW_DPHY_RXDLY_TRACK_EN_LSB (1U << 14) /* 2b */
+#define SW_TX_TRACKING_DIS_LSB (1U << 16) /* 2b */
+/* DRAMC_DMYRD_CON (0x10006000+0x478) */
+#define DRAMC_DMYRD_EN_CH0_LSB (1U << 0) /* 1b */
+#define DRAMC_DMYRD_INTV_SEL_CH0_LSB (1U << 1) /* 1b */
+#define DRAMC_DMYRD_EN_MOD_SEL_CH0_LSB (1U << 2) /* 1b */
+#define DRAMC_DMYRD_EN_CH1_LSB (1U << 8) /* 1b */
+#define DRAMC_DMYRD_INTV_SEL_CH1_LSB (1U << 9) /* 1b */
+#define DRAMC_DMYRD_EN_MOD_SEL_CH1_LSB (1U << 10) /* 1b */
+/* SPM_DRS_CON (0x10006000+0x47C) */
+#define SPM_DRS_DIS_REQ_CH0_LSB (1U << 0) /* 1b */
+#define SPM_DRS_DIS_REQ_CH1_LSB (1U << 1) /* 1b */
+#define SPM_DRS_DIS_ACK_CH0_LSB (1U << 8) /* 1b */
+#define SPM_DRS_DIS_ACK_CH1_LSB (1U << 9) /* 1b */
+/* SPM_SEMA_M0 (0x10006000+0x480) */
+#define SPM_SEMA_M0_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M1 (0x10006000+0x484) */
+#define SPM_SEMA_M1_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M2 (0x10006000+0x488) */
+#define SPM_SEMA_M2_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M3 (0x10006000+0x48C) */
+#define SPM_SEMA_M3_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M4 (0x10006000+0x490) */
+#define SPM_SEMA_M4_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M5 (0x10006000+0x494) */
+#define SPM_SEMA_M5_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M6 (0x10006000+0x498) */
+#define SPM_SEMA_M6_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M7 (0x10006000+0x49C) */
+#define SPM_SEMA_M7_LSB (1U << 0) /* 8b */
+/* SPM_MAS_PAUSE_MM_MASK_B (0x10006000+0x4A0) */
+#define SPM_MAS_PAUSE_MM_MASK_B_LSB (1U << 0) /* 16b */
+/* SPM_MAS_PAUSE_MCU_MASK_B (0x10006000+0x4A4) */
+#define SPM_MAS_PAUSE_MCU_MASK_B_LSB (1U << 0) /* 16b */
+/* SRAM_DREQ_ACK (0x10006000+0x4AC) */
+#define SRAM_DREQ_ACK_LSB (1U << 0) /* 16b */
+/* SRAM_DREQ_CON (0x10006000+0x4B0) */
+#define SRAM_DREQ_CON_LSB (1U << 0) /* 16b */
+/* SRAM_DREQ_CON_SET (0x10006000+0x4B4) */
+#define SRAM_DREQ_CON_SET_LSB (1U << 0) /* 16b */
+/* SRAM_DREQ_CON_CLR (0x10006000+0x4B8) */
+#define SRAM_DREQ_CON_CLR_LSB (1U << 0) /* 16b */
+/* SPM2EMI_ENTER_ULPM (0x10006000+0x4BC) */
+#define SPM2EMI_ENTER_ULPM_LSB (1U << 0) /* 1b */
+/* SPM_SSPM_IRQ (0x10006000+0x4C0) */
+#define SPM_SSPM_IRQ_LSB (1U << 0) /* 1b */
+#define SPM_SSPM_IRQ_SEL_LSB (1U << 4) /* 1b */
+/* SPM2PMCU_INT (0x10006000+0x4C4) */
+#define SPM2PMCU_INT_LSB (1U << 0) /* 4b */
+/* SPM2PMCU_INT_SET (0x10006000+0x4C8) */
+#define SPM2PMCU_INT_SET_LSB (1U << 0) /* 4b */
+/* SPM2PMCU_INT_CLR (0x10006000+0x4CC) */
+#define SPM2PMCU_INT_CLR_LSB (1U << 0) /* 4b */
+/* SPM2PMCU_MAILBOX_0 (0x10006000+0x4D0) */
+#define SPM2PMCU_MAILBOX_0_LSB (1U << 0) /* 32b */
+/* SPM2PMCU_MAILBOX_1 (0x10006000+0x4D4) */
+#define SPM2PMCU_MAILBOX_1_LSB (1U << 0) /* 32b */
+/* SPM2PMCU_MAILBOX_2 (0x10006000+0x4D8) */
+#define SPM2PMCU_MAILBOX_2_LSB (1U << 0) /* 32b */
+/* SPM2PMCU_MAILBOX_3 (0x10006000+0x4DC) */
+#define SPM2PMCU_MAILBOX_3_LSB (1U << 0) /* 32b */
+/* PMCU2SPM_INT (0x10006000+0x4E0) */
+#define PMCU2SPM_INT_LSB (1U << 0) /* 4b */
+/* PMCU2SPM_INT_SET (0x10006000+0x4E4) */
+#define PMCU2SPM_INT_SET_LSB (1U << 0) /* 4b */
+/* PMCU2SPM_INT_CLR (0x10006000+0x4E8) */
+#define PMCU2SPM_INT_CLR_LSB (1U << 0) /* 4b */
+/* PMCU2SPM_MAILBOX_0 (0x10006000+0x4EC) */
+#define PMCU2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */
+/* PMCU2SPM_MAILBOX_1 (0x10006000+0x4F0) */
+#define PMCU2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */
+/* PMCU2SPM_MAILBOX_2 (0x10006000+0x4F4) */
+#define PMCU2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */
+/* PMCU2SPM_MAILBOX_3 (0x10006000+0x4F8) */
+#define PMCU2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */
+/* PMCU2SPM_CFG (0x10006000+0x4FC) */
+#define PMCU2SPM_INT_MASK_B_LSB (1U << 0) /* 4b */
+#define SPM_PMCU_MAILBOX_REQ_LSB (1U << 8) /* 1b */
+/* MP0_CPU0_IRQ_MASK (0x10006000+0x500) */
+#define MP0_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP0_CPU0_AUX_LSB (1U << 8) /* 11b */
+/* MP0_CPU1_IRQ_MASK (0x10006000+0x504) */
+#define MP0_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP0_CPU1_AUX_LSB (1U << 8) /* 11b */
+/* MP0_CPU2_IRQ_MASK (0x10006000+0x508) */
+#define MP0_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP0_CPU2_AUX_LSB (1U << 8) /* 11b */
+/* MP0_CPU3_IRQ_MASK (0x10006000+0x50C) */
+#define MP0_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP0_CPU3_AUX_LSB (1U << 8) /* 11b */
+/* MP1_CPU0_IRQ_MASK (0x10006000+0x510) */
+#define MP1_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP1_CPU0_AUX_LSB (1U << 8) /* 11b */
+/* MP1_CPU1_IRQ_MASK (0x10006000+0x514) */
+#define MP1_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP1_CPU1_AUX_LSB (1U << 8) /* 11b */
+/* MP1_CPU2_IRQ_MASK (0x10006000+0x518) */
+#define MP1_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP1_CPU2_AUX_LSB (1U << 8) /* 11b */
+/* MP1_CPU3_IRQ_MASK (0x10006000+0x51C) */
+#define MP1_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP1_CPU3_AUX_LSB (1U << 8) /* 11b */
+/* MP0_CPU0_WFI_EN (0x10006000+0x530) */
+#define MP0_CPU0_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU1_WFI_EN (0x10006000+0x534) */
+#define MP0_CPU1_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU2_WFI_EN (0x10006000+0x538) */
+#define MP0_CPU2_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU3_WFI_EN (0x10006000+0x53C) */
+#define MP0_CPU3_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP1_CPU0_WFI_EN (0x10006000+0x540) */
+#define MP1_CPU0_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP1_CPU1_WFI_EN (0x10006000+0x544) */
+#define MP1_CPU1_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP1_CPU2_WFI_EN (0x10006000+0x548) */
+#define MP1_CPU2_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP1_CPU3_WFI_EN (0x10006000+0x54C) */
+#define MP1_CPU3_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_L2CFLUSH (0x10006000+0x554) */
+#define MP0_L2CFLUSH_REQ_LSB (1U << 0) /* 1b */
+#define MP0_L2CFLUSH_DONE_LSB (1U << 4) /* 1b */
+/* MP1_L2CFLUSH (0x10006000+0x558) */
+#define MP1_L2CFLUSH_REQ_LSB (1U << 0) /* 1b */
+#define MP1_L2CFLUSH_DONE_LSB (1U << 4) /* 1b */
+/* CPU_PTPOD2_CON (0x10006000+0x560) */
+#define MP0_PTPOD2_FBB_EN_LSB (1U << 0) /* 1b */
+#define MP1_PTPOD2_FBB_EN_LSB (1U << 1) /* 1b */
+#define MP0_PTPOD2_SPARK_EN_LSB (1U << 2) /* 1b */
+#define MP1_PTPOD2_SPARK_EN_LSB (1U << 3) /* 1b */
+#define MP0_PTPOD2_FBB_ACK_LSB (1U << 4) /* 1b */
+#define MP1_PTPOD2_FBB_ACK_LSB (1U << 5) /* 1b */
+/* ROOT_CPUTOP_ADDR (0x10006000+0x570) */
+#define ROOT_CPUTOP_ADDR_LSB (1U << 0) /* 32b */
+/* ROOT_CORE_ADDR (0x10006000+0x574) */
+#define ROOT_CORE_ADDR_LSB (1U << 0) /* 32b */
+/* CPU_SPARE_CON (0x10006000+0x580) */
+#define CPU_SPARE_CON_LSB (1U << 0) /* 32b */
+/* CPU_SPARE_CON_SET (0x10006000+0x584) */
+#define CPU_SPARE_CON_SET_LSB (1U << 0) /* 32b */
+/* CPU_SPARE_CON_CLR (0x10006000+0x588) */
+#define CPU_SPARE_CON_CLR_LSB (1U << 0) /* 32b */
+/* SPM2SW_MAILBOX_0 (0x10006000+0x5D0) */
+#define SPM2SW_MAILBOX_0_LSB (1U << 0) /* 32b */
+/* SPM2SW_MAILBOX_1 (0x10006000+0x5D4) */
+#define SPM2SW_MAILBOX_1_LSB (1U << 0) /* 32b */
+/* SPM2SW_MAILBOX_2 (0x10006000+0x5D8) */
+#define SPM2SW_MAILBOX_2_LSB (1U << 0) /* 32b */
+/* SPM2SW_MAILBOX_3 (0x10006000+0x5DC) */
+#define SPM2SW_MAILBOX_3_LSB (1U << 0) /* 32b */
+/* SW2SPM_INT (0x10006000+0x5E0) */
+#define SW2SPM_INT_LSB (1U << 0) /* 4b */
+/* SW2SPM_INT_SET (0x10006000+0x5E4) */
+#define SW2SPM_INT_SET_LSB (1U << 0) /* 4b */
+/* SW2SPM_INT_CLR (0x10006000+0x5E8) */
+#define SW2SPM_INT_CLR_LSB (1U << 0) /* 4b */
+/* SW2SPM_MAILBOX_0 (0x10006000+0x5EC) */
+#define SW2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */
+/* SW2SPM_MAILBOX_1 (0x10006000+0x5F0) */
+#define SW2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */
+/* SW2SPM_MAILBOX_2 (0x10006000+0x5F4) */
+#define SW2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */
+/* SW2SPM_MAILBOX_3 (0x10006000+0x5F8) */
+#define SW2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */
+/* SW2SPM_CFG (0x10006000+0x5FC) */
+#define SWU2SPM_INT_MASK_B_LSB (1U << 0) /* 4b */
+#define SPM_SW_MAILBOX_REQ_LSB (1U << 8) /* 1b */
+/* SPM_SW_FLAG (0x10006000+0x600) */
+#define SPM_SW_FLAG_LSB (1U << 0) /* 32b */
+/* SPM_SW_DEBUG (0x10006000+0x604) */
+#define SPM_SW_DEBUG_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_0 (0x10006000+0x608) */
+#define SPM_SW_RSV_0_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_1 (0x10006000+0x60C) */
+#define SPM_SW_RSV_1_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_2 (0x10006000+0x610) */
+#define SPM_SW_RSV_2_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_3 (0x10006000+0x614) */
+#define SPM_SW_RSV_3_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_4 (0x10006000+0x618) */
+#define SPM_SW_RSV_4_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_5 (0x10006000+0x61C) */
+#define SPM_SW_RSV_5_LSB (1U << 0) /* 32b */
+/* SPM_RSV_CON (0x10006000+0x620) */
+#define SPM_RSV_CON_LSB (1U << 0) /* 16b */
+/* SPM_RSV_STA (0x10006000+0x624) */
+#define SPM_RSV_STA_LSB (1U << 0) /* 16b */
+/* SPM_RSV_CON1 (0x10006000+0x628) */
+#define SPM_RSV_CON1_LSB (1U << 0) /* 16b */
+/* SPM_RSV_STA1 (0x10006000+0x62C) */
+#define SPM_RSV_STA1_LSB (1U << 0) /* 16b */
+/* SPM_PASR_DPD_0 (0x10006000+0x630) */
+#define SPM_PASR_DPD_0_LSB (1U << 0) /* 32b */
+/* SPM_PASR_DPD_1 (0x10006000+0x634) */
+#define SPM_PASR_DPD_1_LSB (1U << 0) /* 32b */
+/* SPM_PASR_DPD_2 (0x10006000+0x638) */
+#define SPM_PASR_DPD_2_LSB (1U << 0) /* 32b */
+/* SPM_PASR_DPD_3 (0x10006000+0x63C) */
+#define SPM_PASR_DPD_3_LSB (1U << 0) /* 32b */
+/* SPM_SPARE_CON (0x10006000+0x640) */
+#define SPM_SPARE_CON_LSB (1U << 0) /* 32b */
+/* SPM_SPARE_CON_SET (0x10006000+0x644) */
+#define SPM_SPARE_CON_SET_LSB (1U << 0) /* 32b */
+/* SPM_SPARE_CON_CLR (0x10006000+0x648) */
+#define SPM_SPARE_CON_CLR_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_6 (0x10006000+0x64C) */
+#define SPM_SW_RSV_6_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_7 (0x10006000+0x650) */
+#define SPM_SW_RSV_7_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_8 (0x10006000+0x654) */
+#define SPM_SW_RSV_8_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_9 (0x10006000+0x658) */
+#define SPM_SW_RSV_9_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_10 (0x10006000+0x65C) */
+#define SPM_SW_RSV_10_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_18 (0x10006000+0x67C) */
+#define SPM_SW_RSV_18_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_19 (0x10006000+0x680) */
+#define SPM_SW_RSV_19_LSB (1U << 0) /* 32b */
+/* DVFSRC_EVENT_MASK_CON (0x10006000+0x690) */
+#define DVFSRC_EVENT_MASK_B_LSB (1U << 0) /* 16b */
+#define DVFSRC_EVENT_TRIGGER_MASK_B_LSB (1U << 16) /* 1b */
+/* DVFSRC_EVENT_FORCE_ON (0x10006000+0x694) */
+#define DVFSRC_EVENT_FORCE_ON_LSB (1U << 0) /* 16b */
+#define DVFSRC_EVENT_TRIGGER_FORCE_ON_LSB (1U << 16) /* 1b */
+/* DVFSRC_EVENT_SEL (0x10006000+0x698) */
+#define DVFSRC_EVENT_SEL_LSB (1U << 0) /* 16b */
+/* SPM_DVFS_EVENT_STA (0x10006000+0x69C) */
+#define SPM_DVFS_EVENT_STA_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_EVENT_STA1 (0x10006000+0x6A0) */
+#define SPM_DVFS_EVENT_STA1_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_LEVEL (0x10006000+0x6A4) */
+#define SPM_DVFS_LEVEL_LSB (1U << 0) /* 16b */
+/* DVFS_ABORT_STA (0x10006000+0x6A8) */
+#define RC2SPM_EVENT_ABORT_D2T_LSB (1U << 0) /* 16b */
+#define RC2SPM_EVENT_ABORT_MASK_OR_LSB (1U << 16) /* 1b */
+/* DVFS_ABORT_OTHERS_MASK (0x10006000+0x6AC) */
+#define DVFS_ABORT_OTHERS_MASK_B_LSB (1U << 0) /* 16b */
+/* SPM_DFS_LEVEL (0x10006000+0x6B0) */
+#define SPM_DFS_LEVEL_LSB (1U << 0) /* 4b */
+/* SPM_DVS_LEVEL (0x10006000+0x6B4) */
+#define SPM_VCORE_LEVEL_LSB (1U << 0) /* 8b */
+#define SPM_VSRAM_LEVEL_LSB (1U << 8) /* 8b */
+#define SPM_VMODEM_LEVEL_LSB (1U << 16) /* 8b */
+/* SPM_DVFS_MISC (0x10006000+0x6B8) */
+#define MSDC_DVFS_REQUEST_LSB (1U << 0) /* 1b */
+#define MSDC_DVFS_LEVEL_LSB (1U << 1) /* 4b */
+#define SDIO_READY_TO_SPM_LSB (1U << 7) /* 1b */
+#define MD2AP_CENTRAL_BUCK_GEAR_REQ_D2T_LSB (1U << 8) /* 1b */
+#define MD2AP_CENTRAL_BUCK_GEAR_RDY_D2T_LSB (1U << 9) /* 1b */
+/* SPARE_SRC_REQ_MASK (0x10006000+0x6C0) */
+#define SPARE1_DDREN_MASK_B_LSB (1U << 0) /* 1b */
+#define SPARE1_APSRC_REQ_MASK_B_LSB (1U << 1) /* 1b */
+#define SPARE1_VRF18_REQ_MASK_B_LSB (1U << 2) /* 1b */
+#define SPARE1_INFRA_REQ_MASK_B_LSB (1U << 3) /* 1b */
+#define SPARE1_SRCCLKENA_MASK_B_LSB (1U << 4) /* 1b */
+#define SPARE1_DDREN_2_MASK_B_LSB (1U << 5) /* 1b */
+#define SPARE2_DDREN_MASK_B_LSB (1U << 8) /* 1b */
+#define SPARE2_APSRC_REQ_MASK_B_LSB (1U << 9) /* 1b */
+#define SPARE2_VRF18_REQ_MASK_B_LSB (1U << 10) /* 1b */
+#define SPARE2_INFRA_REQ_MASK_B_LSB (1U << 11) /* 1b */
+#define SPARE2_SRCCLKENA_MASK_B_LSB (1U << 12) /* 1b */
+#define SPARE2_DDREN_2_MASK_B_LSB (1U << 13) /* 1b */
+/* SCP_VCORE_LEVEL (0x10006000+0x6C4) */
+#define SCP_VCORE_LEVEL_LSB (1U << 0) /* 8b */
+/* SC_MM_CK_SEL_CON (0x10006000+0x6C8) */
+#define SC_MM_CK_SEL_LSB (1U << 0) /* 4b */
+#define SC_MM_CK_SEL_EN_LSB (1U << 4) /* 1b */
+/* SPARE_ACK_STA (0x10006000+0x6F0) */
+#define SPARE_ACK_SYNC_LSB (1U << 0) /* 32b */
+/* SPARE_ACK_MASK (0x10006000+0x6F4) */
+#define SPARE_ACK_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CON1 (0x10006000+0x700) */
+#define SPM_DVFS_CON1_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CON1_STA (0x10006000+0x704) */
+#define SPM_DVFS_CON1_STA_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD0 (0x10006000+0x710) */
+#define SPM_DVFS_CMD0_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD1 (0x10006000+0x714) */
+#define SPM_DVFS_CMD1_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD2 (0x10006000+0x718) */
+#define SPM_DVFS_CMD2_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD3 (0x10006000+0x71C) */
+#define SPM_DVFS_CMD3_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD4 (0x10006000+0x720) */
+#define SPM_DVFS_CMD4_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD5 (0x10006000+0x724) */
+#define SPM_DVFS_CMD5_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD6 (0x10006000+0x728) */
+#define SPM_DVFS_CMD6_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD7 (0x10006000+0x72C) */
+#define SPM_DVFS_CMD7_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD8 (0x10006000+0x730) */
+#define SPM_DVFS_CMD8_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD9 (0x10006000+0x734) */
+#define SPM_DVFS_CMD9_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD10 (0x10006000+0x738) */
+#define SPM_DVFS_CMD10_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD11 (0x10006000+0x73C) */
+#define SPM_DVFS_CMD11_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD12 (0x10006000+0x740) */
+#define SPM_DVFS_CMD12_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD13 (0x10006000+0x744) */
+#define SPM_DVFS_CMD13_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD14 (0x10006000+0x748) */
+#define SPM_DVFS_CMD14_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD15 (0x10006000+0x74C) */
+#define SPM_DVFS_CMD15_LSB (1U << 0) /* 32b */
+/* WDT_LATCH_SPARE0_FIX (0x10006000+0x780) */
+#define WDT_LATCH_SPARE0_FIX_LSB (1U << 0) /* 32b */
+/* WDT_LATCH_SPARE1_FIX (0x10006000+0x784) */
+#define WDT_LATCH_SPARE1_FIX_LSB (1U << 0) /* 32b */
+/* WDT_LATCH_SPARE2_FIX (0x10006000+0x788) */
+#define WDT_LATCH_SPARE2_FIX_LSB (1U << 0) /* 32b */
+/* WDT_LATCH_SPARE3_FIX (0x10006000+0x78C) */
+#define WDT_LATCH_SPARE3_FIX_LSB (1U << 0) /* 32b */
+/* SPARE_ACK_IN_FIX (0x10006000+0x790) */
+#define SPARE_ACK_IN_FIX_LSB (1U << 0) /* 32b */
+/* DCHA_LATCH_RSV0_FIX (0x10006000+0x794) */
+#define DCHA_LATCH_RSV0_FIX_LSB (1U << 0) /* 32b */
+/* DCHB_LATCH_RSV0_FIX (0x10006000+0x798) */
+#define DCHB_LATCH_RSV0_FIX_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_0 (0x10006000+0x800) */
+#define PCM_WDT_LATCH_0_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_1 (0x10006000+0x804) */
+#define PCM_WDT_LATCH_1_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_2 (0x10006000+0x808) */
+#define PCM_WDT_LATCH_2_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_3 (0x10006000+0x80C) */
+#define PCM_WDT_LATCH_3_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_4 (0x10006000+0x810) */
+#define PCM_WDT_LATCH_4_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_5 (0x10006000+0x814) */
+#define PCM_WDT_LATCH_5_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_6 (0x10006000+0x818) */
+#define PCM_WDT_LATCH_6_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_7 (0x10006000+0x81C) */
+#define PCM_WDT_LATCH_7_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_8 (0x10006000+0x820) */
+#define PCM_WDT_LATCH_8_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_9 (0x10006000+0x824) */
+#define PCM_WDT_LATCH_9_LSB (1U << 0) /* 32b */
+/* WDT_LATCH_SPARE0 (0x10006000+0x828) */
+#define WDT_LATCH_SPARE0_LSB (1U << 0) /* 32b */
+/* WDT_LATCH_SPARE1 (0x10006000+0x82C) */
+#define WDT_LATCH_SPARE1_LSB (1U << 0) /* 32b */
+/* WDT_LATCH_SPARE2 (0x10006000+0x830) */
+#define WDT_LATCH_SPARE2_LSB (1U << 0) /* 32b */
+/* WDT_LATCH_SPARE3 (0x10006000+0x834) */
+#define WDT_LATCH_SPARE3_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_10 (0x10006000+0x838) */
+#define PCM_WDT_LATCH_10_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_11 (0x10006000+0x83C) */
+#define PCM_WDT_LATCH_11_LSB (1U << 0) /* 32b */
+/* DCHA_GATING_LATCH_0 (0x10006000+0x840) */
+#define DCHA_GATING_LATCH_0_LSB (1U << 0) /* 32b */
+/* DCHA_GATING_LATCH_1 (0x10006000+0x844) */
+#define DCHA_GATING_LATCH_1_LSB (1U << 0) /* 32b */
+/* DCHA_GATING_LATCH_2 (0x10006000+0x848) */
+#define DCHA_GATING_LATCH_2_LSB (1U << 0) /* 32b */
+/* DCHA_GATING_LATCH_3 (0x10006000+0x84C) */
+#define DCHA_GATING_LATCH_3_LSB (1U << 0) /* 32b */
+/* DCHA_GATING_LATCH_4 (0x10006000+0x850) */
+#define DCHA_GATING_LATCH_4_LSB (1U << 0) /* 32b */
+/* DCHA_GATING_LATCH_5 (0x10006000+0x854) */
+#define DCHA_GATING_LATCH_5_LSB (1U << 0) /* 32b */
+/* DCHA_GATING_LATCH_6 (0x10006000+0x858) */
+#define DCHA_GATING_LATCH_6_LSB (1U << 0) /* 32b */
+/* DCHA_GATING_LATCH_7 (0x10006000+0x85C) */
+#define DCHA_GATING_LATCH_7_LSB (1U << 0) /* 32b */
+/* DCHB_GATING_LATCH_0 (0x10006000+0x860) */
+#define DCHB_GATING_LATCH_0_LSB (1U << 0) /* 32b */
+/* DCHB_GATING_LATCH_1 (0x10006000+0x864) */
+#define DCHB_GATING_LATCH_1_LSB (1U << 0) /* 32b */
+/* DCHB_GATING_LATCH_2 (0x10006000+0x868) */
+#define DCHB_GATING_LATCH_2_LSB (1U << 0) /* 32b */
+/* DCHB_GATING_LATCH_3 (0x10006000+0x86C) */
+#define DCHB_GATING_LATCH_3_LSB (1U << 0) /* 32b */
+/* DCHB_GATING_LATCH_4 (0x10006000+0x870) */
+#define DCHB_GATING_LATCH_4_LSB (1U << 0) /* 32b */
+/* DCHB_GATING_LATCH_5 (0x10006000+0x874) */
+#define DCHB_GATING_LATCH_5_LSB (1U << 0) /* 32b */
+/* DCHB_GATING_LATCH_6 (0x10006000+0x878) */
+#define DCHB_GATING_LATCH_6_LSB (1U << 0) /* 32b */
+/* DCHB_GATING_LATCH_7 (0x10006000+0x87C) */
+#define DCHB_GATING_LATCH_7_LSB (1U << 0) /* 32b */
+/* DCHA_LATCH_RSV0 (0x10006000+0x880) */
+#define DCHA_LATCH_RSV0_LSB (1U << 0) /* 32b */
+/* DCHB_LATCH_RSV0 (0x10006000+0x884) */
+#define DCHB_LATCH_RSV0_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_12 (0x10006000+0x888) */
+#define PCM_WDT_LATCH_12_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_13 (0x10006000+0x88C) */
+#define PCM_WDT_LATCH_13_LSB (1U << 0) /* 32b */
+/* SPM_PC_TRACE_CON (0x10006000+0x8C0) */
+#define SPM_PC_TRACE_OFFSET_LSB (1U << 0) /* 12b */
+#define SPM_PC_TRACE_HW_EN_LSB (1U << 16) /* 1b */
+#define SPM_PC_TRACE_SW_LSB (1U << 17) /* 1b */
+/* SPM_PC_TRACE_G0 (0x10006000+0x8C4) */
+#define SPM_PC_TRACE0_LSB (1U << 0) /* 12b */
+#define SPM_PC_TRACE1_LSB (1U << 16) /* 12b */
+/* SPM_PC_TRACE_G1 (0x10006000+0x8C8) */
+#define SPM_PC_TRACE2_LSB (1U << 0) /* 12b */
+#define SPM_PC_TRACE3_LSB (1U << 16) /* 12b */
+/* SPM_PC_TRACE_G2 (0x10006000+0x8CC) */
+#define SPM_PC_TRACE4_LSB (1U << 0) /* 12b */
+#define SPM_PC_TRACE5_LSB (1U << 16) /* 12b */
+/* SPM_PC_TRACE_G3 (0x10006000+0x8D0) */
+#define SPM_PC_TRACE6_LSB (1U << 0) /* 12b */
+#define SPM_PC_TRACE7_LSB (1U << 16) /* 12b */
+/* SPM_PC_TRACE_G4 (0x10006000+0x8D4) */
+#define SPM_PC_TRACE8_LSB (1U << 0) /* 12b */
+#define SPM_PC_TRACE9_LSB (1U << 16) /* 12b */
+/* SPM_PC_TRACE_G5 (0x10006000+0x8D8) */
+#define SPM_PC_TRACE10_LSB (1U << 0) /* 12b */
+#define SPM_PC_TRACE11_LSB (1U << 16) /* 12b */
+/* SPM_PC_TRACE_G6 (0x10006000+0x8DC) */
+#define SPM_PC_TRACE12_LSB (1U << 0) /* 12b */
+#define SPM_PC_TRACE13_LSB (1U << 16) /* 12b */
+/* SPM_PC_TRACE_G7 (0x10006000+0x8E0) */
+#define SPM_PC_TRACE14_LSB (1U << 0) /* 12b */
+#define SPM_PC_TRACE15_LSB (1U << 16) /* 12b */
+/* SPM_ACK_CHK_CON (0x10006000+0x900) */
+#define SPM_ACK_CHK_SW_EN_LSB (1U << 0) /* 1b */
+#define SPM_ACK_CHK_CLR_ALL_LSB (1U << 1) /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_LSB (1U << 2) /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_LSB (1U << 3) /* 1b */
+#define SPM_ACK_CHK_STA_EN_LSB (1U << 4) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_LSB (1U << 5) /* 1b */
+#define SPM_ACK_CHK_WDT_EN_LSB (1U << 6) /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_LSB (1U << 7) /* 1b */
+#define SPM_ACK_CHK_HW_EN_LSB (1U << 8) /* 1b */
+#define SPM_ACK_CHK_HW_MODE_LSB (1U << 9) /* 3b */
+#define SPM_ACK_CHK_FAIL_LSB (1U << 15) /* 1b */
+#define SPM_ACK_CHK_SWINT_EN_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_PC (0x10006000+0x904) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_SEL (0x10006000+0x908) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_LSB (1U << 0) /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_LSB (1U << 5) /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_LSB (1U << 16) /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_LSB (1U << 21) /* 3b */
+/* SPM_ACK_CHK_TIMER (0x10006000+0x90C) */
+#define SPM_ACK_CHK_TIMER_VAL_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_TIMER_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_STA (0x10006000+0x910) */
+#define SPM_ACK_CHK_STA_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_LATCH (0x10006000+0x914) */
+#define SPM_ACK_CHK_LATCH_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_CON2 (0x10006000+0x920) */
+#define SPM_ACK_CHK_SW_EN2_LSB (1U << 0) /* 1b */
+#define SPM_ACK_CHK_CLR_ALL2_LSB (1U << 1) /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER2_LSB (1U << 2) /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ2_LSB (1U << 3) /* 1b */
+#define SPM_ACK_CHK_STA_EN2_LSB (1U << 4) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN2_LSB (1U << 5) /* 1b */
+#define SPM_ACK_CHK_WDT_EN2_LSB (1U << 6) /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN2_LSB (1U << 7) /* 1b */
+#define SPM_ACK_CHK_HW_EN2_LSB (1U << 8) /* 1b */
+#define SPM_ACK_CHK_HW_MODE2_LSB (1U << 9) /* 3b */
+#define SPM_ACK_CHK_FAIL2_LSB (1U << 15) /* 1b */
+#define SPM_ACK_CHK_SWINT_EN2_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_PC2 (0x10006000+0x924) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL2_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL2_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_SEL2 (0x10006000+0x928) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL2_LSB (1U << 0) /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL2_LSB (1U << 5) /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL2_LSB (1U << 16) /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL2_LSB (1U << 21) /* 3b */
+/* SPM_ACK_CHK_TIMER2 (0x10006000+0x92C) */
+#define SPM_ACK_CHK_TIMER_VAL2_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_TIMER2_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_STA2 (0x10006000+0x930) */
+#define SPM_ACK_CHK_STA2_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_LATCH2 (0x10006000+0x934) */
+#define SPM_ACK_CHK_LATCH2_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_CON3 (0x10006000+0x940) */
+#define SPM_ACK_CHK_SW_EN3_LSB (1U << 0) /* 1b */
+#define SPM_ACK_CHK_CLR_ALL3_LSB (1U << 1) /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER3_LSB (1U << 2) /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ3_LSB (1U << 3) /* 1b */
+#define SPM_ACK_CHK_STA_EN3_LSB (1U << 4) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN3_LSB (1U << 5) /* 1b */
+#define SPM_ACK_CHK_WDT_EN3_LSB (1U << 6) /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN3_LSB (1U << 7) /* 1b */
+#define SPM_ACK_CHK_HW_EN3_LSB (1U << 8) /* 1b */
+#define SPM_ACK_CHK_HW_MODE3_LSB (1U << 9) /* 3b */
+#define SPM_ACK_CHK_FAIL3_LSB (1U << 15) /* 1b */
+#define SPM_ACK_CHK_SWINT_EN3_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_PC3 (0x10006000+0x944) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL3_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL3_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_SEL3 (0x10006000+0x948) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL3_LSB (1U << 0) /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL3_LSB (1U << 5) /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL3_LSB (1U << 16) /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL3_LSB (1U << 21) /* 3b */
+/* SPM_ACK_CHK_TIMER3 (0x10006000+0x94C) */
+#define SPM_ACK_CHK_TIMER_VAL3_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_TIMER3_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_STA3 (0x10006000+0x950) */
+#define SPM_ACK_CHK_STA3_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_LATCH3 (0x10006000+0x954) */
+#define SPM_ACK_CHK_LATCH3_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_CON4 (0x10006000+0x960) */
+#define SPM_ACK_CHK_SW_EN4_LSB (1U << 0) /* 1b */
+#define SPM_ACK_CHK_CLR_ALL4_LSB (1U << 1) /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER4_LSB (1U << 2) /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ4_LSB (1U << 3) /* 1b */
+#define SPM_ACK_CHK_STA_EN4_LSB (1U << 4) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN4_LSB (1U << 5) /* 1b */
+#define SPM_ACK_CHK_WDT_EN4_LSB (1U << 6) /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN4_LSB (1U << 7) /* 1b */
+#define SPM_ACK_CHK_HW_EN4_LSB (1U << 8) /* 1b */
+#define SPM_ACK_CHK_HW_MODE4_LSB (1U << 9) /* 3b */
+#define SPM_ACK_CHK_FAIL4_LSB (1U << 15) /* 1b */
+#define SPM_ACK_CHK_SWINT_EN4_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_PC4 (0x10006000+0x964) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL4_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL4_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_SEL4 (0x10006000+0x968) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL4_LSB (1U << 0) /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL4_LSB (1U << 5) /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL4_LSB (1U << 16) /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL4_LSB (1U << 21) /* 3b */
+/* SPM_ACK_CHK_TIMER4 (0x10006000+0x96C) */
+#define SPM_ACK_CHK_TIMER_VAL4_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_TIMER4_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_STA4 (0x10006000+0x970) */
+#define SPM_ACK_CHK_STA4_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_LATCH4 (0x10006000+0x974) */
+#define SPM_ACK_CHK_LATCH4_LSB (1U << 0) /* 32b */
+
+/* --- SPM Flag Define --- */
+#define SPM_FLAG_DIS_CPU_PDN (1U << 0)
+#define SPM_FLAG_DIS_INFRA_PDN (1U << 1)
+#define SPM_FLAG_DIS_DDRPHY_PDN (1U << 2)
+#define SPM_FLAG_DIS_VCORE_DVS (1U << 3)
+#define SPM_FLAG_DIS_VCORE_DFS (1U << 4)
+#define SPM_FLAG_DIS_COMMON_SCENARIO (1U << 5)
+#define SPM_FLAG_DIS_BUS_CLOCK_OFF (1U << 6)
+#define SPM_FLAG_DIS_ATF_ABORT (1U << 7)
+#define SPM_FLAG_KEEP_CSYSPWRUPACK_HIGH (1U << 8)
+#define SPM_FLAG_DIS_VPROC_VSRAM_DVS (1U << 9)
+#define SPM_FLAG_RUN_COMMON_SCENARIO (1U << 10)
+#define SPM_FLAG_EN_MET_DEBUG_USAGE (1U << 11)
+#define SPM_FLAG_SODI_CG_MODE (1U << 12)
+#define SPM_FLAG_SODI_NO_EVENT (1U << 13)
+#define SPM_FLAG_ENABLE_SODI3 (1U << 14)
+#define SPM_FLAG_DISABLE_MMSYS_DVFS (1U << 15)
+#define SPM_FLAG_DIS_SYSRAM_SLEEP (1U << 16)
+#define SPM_FLAG_DIS_SSPM_SRAM_SLEEP (1U << 17)
+#define SPM_FLAG_DIS_VMODEM_DVS (1U << 18)
+#define SPM_FLAG_SUSPEND_OPTION (1U << 19)
+#define SPM_FLAG_DEEPIDLE_OPTION (1U << 20)
+#define SPM_FLAG_SODI_OPTION (1U << 21)
+#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT22 (1U << 22)
+#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT23 (1U << 23)
+#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT24 (1U << 24)
+#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT25 (1U << 25)
+#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT26 (1U << 26)
+#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT27 (1U << 27)
+#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT28 (1U << 28)
+#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT29 (1U << 29)
+#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT30 (1U << 30)
+#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT31 (1U << 31)
+
+/* --- SPM Flag1 Define --- */
+#define SPM_FLAG1_RESERVED_BIT0 (1U << 0)
+#define SPM_FLAG1_ENABLE_CPU_DORMANT (1U << 1)
+#define SPM_FLAG1_ENABLE_CPU_SLEEP_VOLT (1U << 2)
+#define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH (1U << 3)
+#define SPM_FLAG1_DISABLE_ULPOSC_OFF (1U << 4)
+#define SPM_FLAG1_VCORE_LP_0P7V (1U << 5)
+#define SPM_FLAG1_DISABLE_MCDSR (1U << 6)
+#define SPM_FLAG1_DISABLE_NO_RESUME (1U << 7)
+#define SPM_FLAG1_BIG_BUCK_OFF_ENABLE (1U << 8)
+#define SPM_FLAG1_BIG_BUCK_ON_ENABLE (1U << 9)
+#define SPM_FLAG1_RESERVED_BIT10 (1U << 10)
+#define SPM_FLAG1_RESERVED_BIT11 (1U << 11)
+#define SPM_FLAG1_RESERVED_BIT12 (1U << 12)
+#define SPM_FLAG1_RESERVED_BIT13 (1U << 13)
+#define SPM_FLAG1_RESERVED_BIT14 (1U << 14)
+#define SPM_FLAG1_DIS_ARMPLL_OFF (1U << 15)
+#define SPM_FLAG1_DIS_AXI_BUS_TO_26M (1U << 16)
+#define SPM_FLAG1_DIS_IMP_DIS (1U << 17)
+#define SPM_FLAG1_DIS_IMP_COPY (1U << 18)
+#define SPM_FLAG1_DIS_EMI_TOGGLE_WORKAROUND (1U << 19)
+#define SPM_FLAG1_DIS_DRAM_ENTER_SREF (1U << 20)
+#define SPM_FLAG1_DIS_DRAM_DLL_OFF (1U << 21)
+#define SPM_FLAG1_DIS_PHYPLL_OFF (1U << 22)
+#define SPM_FLAG1_DIS_MPLL_OFF (1U << 23)
+#define SPM_FLAG1_DIS_SYSPLL_OFF (1U << 24)
+#define SPM_FLAG1_DIS_TOP_AXI_CLK_OFF (1U << 25)
+#define SPM_FLAG1_DIS_PCM_26M_SWITCH (1U << 26)
+#define SPM_FLAG1_DIS_CKSQ_OFF (1U << 27)
+#define SPM_FLAG1_DIS_SRCVOLTEN_OFF (1U << 28)
+#define SPM_FLAG1_DIS_CHB_CG_FREE_EN (1U << 29)
+#define SPM_FLAG1_DIS_CHA_DCM_RES (1U << 30)
+#define SPM_FLAG1_DIS_SW_MR4 (1U << 31)
+
+/* --- SPM DEBUG Define --- */
+#define SPM_DBG_DEBUG_IDX_26M_WAKE (1U << 0)
+#define SPM_DBG_DEBUG_IDX_26M_SLEEP (1U << 1)
+#define SPM_DBG_DEBUG_IDX_INFRA_WAKE (1U << 2)
+#define SPM_DBG_DEBUG_IDX_INFRA_SLEEP (1U << 3)
+#define SPM_DBG_DEBUG_IDX_APSRC_WAKE (1U << 4)
+#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP (1U << 5)
+#define SPM_DBG_DEBUG_IDX_VRF18_WAKE (1U << 6)
+#define SPM_DBG_DEBUG_IDX_VRF18_SLEEP (1U << 7)
+#define SPM_DBG_DEBUG_IDX_DDREN_WAKE (1U << 8)
+#define SPM_DBG_DEBUG_IDX_DDREN_SLEEP (1U << 9)
+#define SPM_DBG_DEBUG_IDX_NFC_CKBUF_ON (1U << 10)
+#define SPM_DBG_DEBUG_IDX_NFC_CKBUF_OFF (1U << 11)
+#define SPM_DBG_DEBUG_IDX_CPU_PDN (1U << 12)
+#define SPM_DBG_DEBUG_IDX_DPD (1U << 13)
+#define SPM_DBG_DEBUG_IDX_CONN_CKBUF_ON (1U << 14)
+#define SPM_DBG_DEBUG_IDX_CONN_CKBUF_OFF (1U << 15)
+#define SPM_DBG_DEBUG_IDX_VCORE_DVFS_START (1U << 16)
+#define SPM_DBG_DEBUG_IDX_DDREN2_WAKE (1U << 17)
+#define SPM_DBG_DEBUG_IDX_DDREN2_SLEEP (1U << 18)
+#define SPM_DBG_DEBUG_IDX_SSPM_WFI (1U << 19)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP (1U << 20)
+#define SPM_DBG_RESERVED_BIT21 (1U << 21)
+#define SPM_DBG_RESERVED_BIT22 (1U << 22)
+#define SPM_DBG_RESERVED_BIT23 (1U << 23)
+#define SPM_DBG_RESERVED_BIT24 (1U << 24)
+#define SPM_DBG_RESERVED_BIT25 (1U << 25)
+#define SPM_DBG_RESERVED_BIT26 (1U << 26)
+#define SPM_DBG_SODI1_FLAG (1U << 27)
+#define SPM_DBG_SODI3_FLAG (1U << 28)
+#define SPM_DBG_VCORE_DVFS_FLAG (1U << 29)
+#define SPM_DBG_DEEPIDLE_FLAG (1U << 30)
+#define SPM_DBG_SUSPEND_FLAG (1U << 31)
+
+/* --- SPM DEBUG1 Define --- */
+#define SPM_DBG1_DRAM_SREF_ACK_TO (1U << 0)
+#define SPM_DBG1_PWRAP_SLEEP_ACK_TO (1U << 1)
+#define SPM_DBG1_PWRAP_SPI_ACK_TO (1U << 2)
+#define SPM_DBG1_DRAM_GATE_ERR_DDREN_WAKEUP (1U << 3)
+#define SPM_DBG1_DRAM_GATE_ERR_LEAVE_LP_SCN (1U << 4)
+#define SPM_DBG1_RESERVED_BIT5 (1U << 5)
+#define SPM_DBG1_RESERVED_BIT6 (1U << 6)
+#define SPM_DBG1_RESERVED_BIT7 (1U << 7)
+#define SPM_DBG1_RESERVED_BIT8 (1U << 8)
+#define SPM_DBG1_RESERVED_BIT9 (1U << 9)
+#define SPM_DBG1_RESERVED_BIT10 (1U << 10)
+#define SPM_DBG1_RESERVED_BIT11 (1U << 11)
+#define SPM_DBG1_RESERVED_BIT12 (1U << 12)
+#define SPM_DBG1_RESERVED_BIT13 (1U << 13)
+#define SPM_DBG1_RESERVED_BIT14 (1U << 14)
+#define SPM_DBG1_RESERVED_BIT15 (1U << 15)
+#define SPM_DBG1_RESERVED_BIT16 (1U << 16)
+#define SPM_DBG1_RESERVED_BIT17 (1U << 17)
+#define SPM_DBG1_RESERVED_BIT18 (1U << 18)
+#define SPM_DBG1_RESERVED_BIT19 (1U << 19)
+#define SPM_DBG1_RESERVED_BIT20 (1U << 20)
+#define SPM_DBG1_RESERVED_BIT21 (1U << 21)
+#define SPM_DBG1_RESERVED_BIT22 (1U << 22)
+#define SPM_DBG1_RESERVED_BIT23 (1U << 23)
+#define SPM_DBG1_RESERVED_BIT24 (1U << 24)
+#define SPM_DBG1_RESERVED_BIT25 (1U << 25)
+#define SPM_DBG1_RESERVED_BIT26 (1U << 26)
+#define SPM_DBG1_RESERVED_BIT27 (1U << 27)
+#define SPM_DBG1_RESERVED_BIT28 (1U << 28)
+#define SPM_DBG1_RESERVED_BIT29 (1U << 29)
+#define SPM_DBG1_RESERVED_BIT30 (1U << 30)
+#define SPM_DBG1_RESERVED_BIT31 (1U << 31)
+
+/* --- R0 Define --- */
+#define R0_SC_26M_CK_OFF (1U << 0)
+#define R0_BIT1 (1U << 1)
+#define R0_SC_MEM_CK_OFF (1U << 2)
+#define R0_SC_AXI_CK_OFF (1U << 3)
+#define R0_SC_DR_GATE_RETRY_EN_PCM (1U << 4)
+#define R0_SC_MD26M_CK_OFF (1U << 5)
+#define R0_SC_DPY_MODE_SW_PCM (1U << 6)
+#define R0_SC_DMSUS_OFF_PCM (1U << 7)
+#define R0_SC_DPY_2ND_DLL_EN_PCM (1U << 8)
+#define R0_BIT9 (1U << 9)
+#define R0_SC_MPLLOUT_OFF (1U << 10)
+#define R0_SC_TX_TRACKING_DIS (1U << 11)
+#define R0_SC_DPY_DLL_EN_PCM (1U << 12)
+#define R0_SC_DPY_DLL_CK_EN_PCM (1U << 13)
+#define R0_SC_DPY_VREF_EN_PCM (1U << 14)
+#define R0_SC_PHYPLL_EN_PCM (1U << 15)
+#define R0_SC_DDRPHY_FB_CK_EN_PCM (1U << 16)
+#define R0_SC_DPY_BCLK_ENABLE (1U << 17)
+#define R0_SC_MPLL_OFF (1U << 18)
+#define R0_SC_SHU_RESTORE (1U << 19)
+#define R0_SC_CKSQ0_OFF (1U << 20)
+#define R0_SC_CKSQ1_OFF (1U << 21)
+#define R0_SC_DR_SHU_EN_PCM (1U << 22)
+#define R0_SC_DPHY_PRECAL_UP (1U << 23)
+#define R0_SC_MPLL_S_OFF (1U << 24)
+#define R0_SC_DPHY_RXDLY_TRACK_EN (1U << 25)
+#define R0_SC_PHYPLL_SHU_EN_PCM (1U << 26)
+#define R0_SC_PHYPLL2_SHU_EN_PCM (1U << 27)
+#define R0_SC_PHYPLL_MODE_SW_PCM (1U << 28)
+#define R0_SC_PHYPLL2_MODE_SW_PCM (1U << 29)
+#define R0_SC_DR_SHU_LEVEL_PCM0 (1U << 30)
+#define R0_SC_DR_SHU_LEVEL_PCM1 (1U << 31)
+
+/* --- R7 Define --- */
+#define R7_PWRAP_SLEEP_REQ (1U << 0)
+#define R7_EMI_CLK_OFF_REQ (1U << 1)
+#define R7_TOP_MAS_PAU_REQ (1U << 2)
+#define R7_SPM2CKSYS_MEM_CK_MUX_UPDATE (1U << 3)
+#define R7_PCM_CK_SEL0 (1U << 4)
+#define R7_PCM_CK_SEL1 (1U << 5)
+#define R7_SPM2RC_DVS_DONE (1U << 6)
+#define R7_FREQH_PAUSE_MPLL (1U << 7)
+#define R7_SC_26M_CK_SEL (1U << 8)
+#define R7_PCM_TIMER_SET (1U << 9)
+#define R7_PCM_TIMER_CLR (1U << 10)
+#define R7_SRCVOLTEN (1U << 11)
+#define R7_CSYSPWRUPACK (1U << 12)
+#define R7_IM_SLEEP_ENABLE (1U << 13)
+#define R7_SRCCLKENO_0 (1U << 14)
+#define R7_SYSRST (1U << 15)
+#define R7_MD_APSRC_ACK (1U << 16)
+#define R7_CPU_SYS_TIMER_CLK_SEL (1U << 17)
+#define R7_SC_AXI_DCM_DIS (1U << 18)
+#define R7_FREQH_PAUSE_MAIN (1U << 19)
+#define R7_FREQH_PAUSE_MEM (1U << 20)
+#define R7_SRCCLKENO_1 (1U << 21)
+#define R7_WDT_KICK_P (1U << 22)
+#define R7_SPM2RC_EVENT_ABORT_ACK (1U << 23)
+#define R7_WAKEUP_EXT_W_SEL (1U << 24)
+#define R7_WAKEUP_EXT_R_SEL (1U << 25)
+#define R7_PMIC_IRQ_REQ_EN (1U << 26)
+#define R7_FORCE_26M_WAKE (1U << 27)
+#define R7_FORCE_APSRC_WAKE (1U << 28)
+#define R7_FORCE_INFRA_WAKE (1U << 29)
+#define R7_FORCE_VRF18_WAKE (1U << 30)
+#define R7_SC_DR_SHORT_QUEUE_PCM (1U << 31)
+
+/* --- R12 Define --- */
+#define R12_PCM_TIMER (1U << 0)
+#define R12_SSPM_WDT_EVENT_B (1U << 1)
+#define R12_KP_IRQ_B (1U << 2)
+#define R12_APWDT_EVENT_B (1U << 3)
+#define R12_APXGPT1_EVENT_B (1U << 4)
+#define R12_CONN2AP_SPM_WAKEUP_B (1U << 5)
+#define R12_EINT_EVENT_B (1U << 6)
+#define R12_CONN_WDT_IRQ_B (1U << 7)
+#define R12_CCIF0_EVENT_B (1U << 8)
+#define R12_LOWBATTERY_IRQ_B (1U << 9)
+#define R12_SSPM_SPM_IRQ_B (1U << 10)
+#define R12_SCP_SPM_IRQ_B (1U << 11)
+#define R12_SCP_WDT_EVENT_B (1U << 12)
+#define R12_PCM_WDT_WAKEUP_B (1U << 13)
+#define R12_USB_CDSC_B (1U << 14)
+#define R12_USB_POWERDWN_B (1U << 15)
+#define R12_SYS_TIMER_EVENT_B (1U << 16)
+#define R12_EINT_EVENT_SECURE_B (1U << 17)
+#define R12_CCIF1_EVENT_B (1U << 18)
+#define R12_UART0_IRQ_B (1U << 19)
+#define R12_AFE_IRQ_MCU_B (1U << 20)
+#define R12_THERM_CTRL_EVENT_B (1U << 21)
+#define R12_SYS_CIRQ_IRQ_B (1U << 22)
+#define R12_MD2AP_PEER_EVENT_B (1U << 23)
+#define R12_CSYSPWREQ_B (1U << 24)
+#define R12_MD1_WDT_B (1U << 25)
+#define R12_CLDMA_EVENT_B (1U << 26)
+#define R12_SEJ_WDT_GPT_B (1U << 27)
+#define R12_ALL_SSPM_WAKEUP_B (1U << 28)
+#define R12_CPU_IRQ_B (1U << 29)
+#define R12_CPU_WFI_AND_B (1U << 30)
+#define R12_MCUSYS_IDLE_TO_EMI_ALL_B (1U << 31)
+
+/* --- R12ext Define --- */
+#define R12EXT_26M_WAKE (1U << 0)
+#define R12EXT_26M_SLEEP (1U << 1)
+#define R12EXT_INFRA_WAKE (1U << 2)
+#define R12EXT_INFRA_SLEEP (1U << 3)
+#define R12EXT_APSRC_WAKE (1U << 4)
+#define R12EXT_APSRC_SLEEP (1U << 5)
+#define R12EXT_VRF18_WAKE (1U << 6)
+#define R12EXT_VRF18_SLEEP (1U << 7)
+#define R12EXT_DVFS_ALL_STATE (1U << 8)
+#define R12EXT_DVFS_LEVEL_STATE0 (1U << 9)
+#define R12EXT_DVFS_LEVEL_STATE1 (1U << 10)
+#define R12EXT_DVFS_LEVEL_STATE2 (1U << 11)
+#define R12EXT_DDREN_WAKE (1U << 12)
+#define R12EXT_DDREN_SLEEP (1U << 13)
+#define R12EXT_NFC_CLK_BUF_WAKE (1U << 14)
+#define R12EXT_NFC_CLK_BUF_SLEEP (1U << 15)
+#define R12EXT_CONN_CLK_BUF_WAKE (1U << 16)
+#define R12EXT_CONN_CLK_BUF_SLEEP (1U << 17)
+#define R12EXT_MD_DVFS_ERROR_STATUS (1U << 18)
+#define R12EXT_DVFS_LEVEL_STATE3 (1U << 19)
+#define R12EXT_DVFS_LEVEL_STATE4 (1U << 20)
+#define R12EXT_DVFS_LEVEL_STATE5 (1U << 21)
+#define R12EXT_DVFS_LEVEL_STATE6 (1U << 22)
+#define R12EXT_DVFS_LEVEL_STATE7 (1U << 23)
+#define R12EXT_DVFS_LEVEL_STATE8 (1U << 24)
+#define R12EXT_DVFS_LEVEL_STATE9 (1U << 25)
+#define R12EXT_DVFS_LEVEL_STATE_G0 (1U << 26)
+#define R12EXT_DVFS_LEVEL_STATE_G1 (1U << 27)
+#define R12EXT_DVFS_LEVEL_STATE_G2 (1U << 28)
+#define R12EXT_DVFS_LEVEL_STATE_G3 (1U << 29)
+#define R12EXT_HYBRID_DDREN_SLEEP (1U << 30)
+#define R12EXT_HYBRID_DDREN_WAKE (1U << 31)
+
+/* --- R13 Define --- */
+#define R13_EXT_SRCCLKENI_0 (1U << 0)
+#define R13_EXT_SRCCLKENI_1 (1U << 1)
+#define R13_MD1_SRCCLKENA (1U << 2)
+#define R13_MD1_APSRC_REQ (1U << 3)
+#define R13_CONN_DDR_EN (1U << 4)
+#define R13_MD2_SRCCLKENA (1U << 5)
+#define R13_SSPM_SRCCLKENA (1U << 6)
+#define R13_SSPM_APSRC_REQ (1U << 7)
+#define R13_MD_STATE (1U << 8)
+#define R13_EMI_CLK_OFF_2_ACK (1U << 9)
+#define R13_MM_STATE (1U << 10)
+#define R13_SSPM_STATE (1U << 11)
+#define R13_MD_DDR_EN (1U << 12)
+#define R13_CONN_STATE (1U << 13)
+#define R13_CONN_SRCCLKENA (1U << 14)
+#define R13_CONN_APSRC_REQ (1U << 15)
+#define R13_SLEEP_EVENT_STA (1U << 16)
+#define R13_WAKE_EVENT_STA (1U << 17)
+#define R13_EMI_IDLE (1U << 18)
+#define R13_CSYSPWRUPREQ (1U << 19)
+#define R13_PWRAP_SLEEP_ACK (1U << 20)
+#define R13_EMI_CLK_OFF_ACK_ALL (1U << 21)
+#define R13_TOP_MAS_PAU_ACK (1U << 22)
+#define R13_SW_DMDRAMCSHU_ACK_ALL (1U << 23)
+#define R13_RC2SPM_EVENT_ABORT_MASK_OR (1U << 24)
+#define R13_DR_SHORT_QUEUE_ACK_ALL (1U << 25)
+#define R13_INFRA_AUX_IDLE (1U << 26)
+#define R13_DVFS_ALL_STATE (1U << 27)
+#define R13_RC2SPM_EVENT_ABORT_OR (1U << 28)
+#define R13_DRAMC_SPCMD_APSRC_REQ (1U << 29)
+#define R13_MD1_VRF18_REQ (1U << 30)
+#define R13_C2K_VRF18_REQ (1U << 31)
+
+#define is_cpu_pdn(flags) (!((flags) & SPM_FLAG_DIS_CPU_PDN))
+#define is_infra_pdn(flags) (!((flags) & SPM_FLAG_DIS_INFRA_PDN))
+#define is_ddrphy_pdn(flags) (!((flags) & SPM_FLAG_DIS_DDRPHY_PDN))
+
+#define MP0_SPMC_SRAM_DORMANT_EN (1<<0)
+#define MP1_SPMC_SRAM_DORMANT_EN (1<<1)
+#define MP2_SPMC_SRAM_DORMANT_EN (1<<2)
+
+#define EVENT_VEC(event, resume, imme, pc) \
+ (((pc) << 16) | \
+ (!!(imme) << 7) | \
+ (!!(resume) << 6) | \
+ ((event) & 0x3f))
+
+#define SPM_PROJECT_CODE 0xb16
+#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16)
+
+/**************************************
+ * Config and Parameter
+ **************************************/
+#define POWER_ON_VAL1_DEF 0x00015800
+#define PCM_FSM_STA_DEF 0x00108490
+#define SPM_WAKEUP_EVENT_MASK_DEF 0xF0F92218
+#define PCM_WDT_TIMEOUT (30 * 32768) /* 30s */
+#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT)
+
+/**************************************
+ * Define and Declare
+ **************************************/
+/* PCM_PWR_IO_EN */
+#define PCM_PWRIO_EN_R0 (1U << 0)
+#define PCM_PWRIO_EN_R7 (1U << 7)
+#define PCM_RF_SYNC_R0 (1U << 16)
+#define PCM_RF_SYNC_R6 (1U << 22)
+#define PCM_RF_SYNC_R7 (1U << 23)
+
+/* SPM_SWINT */
+#define PCM_SW_INT0 (1U << 0)
+#define PCM_SW_INT1 (1U << 1)
+#define PCM_SW_INT2 (1U << 2)
+#define PCM_SW_INT3 (1U << 3)
+#define PCM_SW_INT4 (1U << 4)
+#define PCM_SW_INT5 (1U << 5)
+#define PCM_SW_INT6 (1U << 6)
+#define PCM_SW_INT7 (1U << 7)
+#define PCM_SW_INT8 (1U << 8)
+#define PCM_SW_INT9 (1U << 9)
+#define PCM_SW_INT_ALL (PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \
+ PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \
+ PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \
+ PCM_SW_INT0)
+/* SPM_IRQ_MASK */
+#define ISRM_TWAM (1U << 2)
+#define ISRM_PCM_RETURN (1U << 3)
+#define ISRM_RET_IRQ0 (1U << 8)
+#define ISRM_RET_IRQ1 (1U << 9)
+#define ISRM_RET_IRQ2 (1U << 10)
+#define ISRM_RET_IRQ3 (1U << 11)
+#define ISRM_RET_IRQ4 (1U << 12)
+#define ISRM_RET_IRQ5 (1U << 13)
+#define ISRM_RET_IRQ6 (1U << 14)
+#define ISRM_RET_IRQ7 (1U << 15)
+#define ISRM_RET_IRQ8 (1U << 16)
+#define ISRM_RET_IRQ9 (1U << 17)
+#define ISRM_RET_IRQ_AUX (ISRM_RET_IRQ9 | ISRM_RET_IRQ8 | \
+ ISRM_RET_IRQ7 | ISRM_RET_IRQ6 | \
+ ISRM_RET_IRQ5 | ISRM_RET_IRQ4 | \
+ ISRM_RET_IRQ3 | ISRM_RET_IRQ2 | \
+ ISRM_RET_IRQ1)
+#define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX)
+#define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM)
+
+/* SPM_IRQ_STA */
+#define ISRS_TWAM (1U << 2)
+#define ISRS_PCM_RETURN (1U << 3)
+#define ISRS_SW_INT0 (1U << 4)
+#define ISRC_TWAM ISRS_TWAM
+#define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN
+#define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM)
+
+/* SPM_WAKEUP_MISC */
+#define WAKE_MISC_TWAM (1U << 18)
+#define WAKE_MISC_PCM_TIMER (1U << 19)
+#define WAKE_MISC_CPU_WAKE (1U << 20)
+
+enum SPM_WAKE_SRC_LIST {
+ WAKE_SRC_R12_PCM_TIMER = (1U << 0),
+ WAKE_SRC_R12_SSPM_WDT_EVENT_B = (1U << 1),
+ WAKE_SRC_R12_KP_IRQ_B = (1U << 2),
+ WAKE_SRC_R12_APWDT_EVENT_B = (1U << 3),
+ WAKE_SRC_R12_APXGPT1_EVENT_B = (1U << 4),
+ WAKE_SRC_R12_CONN2AP_SPM_WAKEUP_B = (1U << 5),
+ WAKE_SRC_R12_EINT_EVENT_B = (1U << 6),
+ WAKE_SRC_R12_CONN_WDT_IRQ_B = (1U << 7),
+ WAKE_SRC_R12_CCIF0_EVENT_B = (1U << 8),
+ WAKE_SRC_R12_LOWBATTERY_IRQ_B = (1U << 9),
+ WAKE_SRC_R12_SSPM_SPM_IRQ_B = (1U << 10),
+ WAKE_SRC_R12_SCP_SPM_IRQ_B = (1U << 11),
+ WAKE_SRC_R12_SCP_WDT_EVENT_B = (1U << 12),
+ WAKE_SRC_R12_PCM_WDT_WAKEUP_B = (1U << 13),
+ WAKE_SRC_R12_USB_CDSC_B = (1U << 14),
+ WAKE_SRC_R12_USB_POWERDWN_B = (1U << 15),
+ WAKE_SRC_R12_SYS_TIMER_EVENT_B = (1U << 16),
+ WAKE_SRC_R12_EINT_EVENT_SECURE_B = (1U << 17),
+ WAKE_SRC_R12_CCIF1_EVENT_B = (1U << 18),
+ WAKE_SRC_R12_UART0_IRQ_B = (1U << 19),
+ WAKE_SRC_R12_AFE_IRQ_MCU_B = (1U << 20),
+ WAKE_SRC_R12_THERM_CTRL_EVENT_B = (1U << 21),
+ WAKE_SRC_R12_SYS_CIRQ_IRQ_B = (1U << 22),
+ WAKE_SRC_R12_MD2AP_PEER_EVENT_B = (1U << 23),
+ WAKE_SRC_R12_CSYSPWREQ_B = (1U << 24),
+ WAKE_SRC_R12_MD1_WDT_B = (1U << 25),
+ WAKE_SRC_R12_CLDMA_EVENT_B = (1U << 26),
+ WAKE_SRC_R12_SEJ_WDT_GPT_B = (1U << 27),
+ WAKE_SRC_R12_ALL_SSPM_WAKEUP_B = (1U << 28),
+ WAKE_SRC_R12_CPU_IRQ_B = (1U << 29),
+ WAKE_SRC_R12_CPU_WFI_AND_B = (1U << 30),
+};
+
+struct pcm_desc {
+ const char *version;
+ const uint32_t *base;
+ const uint32_t base_dma;
+ const uint32_t size;
+ const uint32_t sess;
+ const uint32_t replace;
+ const uint32_t addr_2nd;
+ const uint32_t reserved;
+
+ uint32_t vec0;
+ uint32_t vec1;
+ uint32_t vec2;
+ uint32_t vec3;
+ uint32_t vec4;
+ uint32_t vec5;
+ uint32_t vec6;
+ uint32_t vec7;
+ uint32_t vec8;
+ uint32_t vec9;
+ uint32_t vec10;
+ uint32_t vec11;
+ uint32_t vec12;
+ uint32_t vec13;
+ uint32_t vec14;
+ uint32_t vec15;
+};
+
+struct pwr_ctrl {
+ uint32_t pcm_flags;
+ uint32_t pcm_flags1;
+ uint32_t timer_val;
+ uint32_t wake_src;
+
+ /* SPM_AP_STANDBY_CON */
+ uint8_t wfi_op;
+ uint8_t mp0_cputop_idle_mask;
+ uint8_t mp1_cputop_idle_mask;
+ uint8_t mcusys_idle_mask;
+ uint8_t mm_mask_b;
+ uint8_t md_ddr_en_0_dbc_en;
+ uint8_t md_ddr_en_1_dbc_en;
+ uint8_t md_mask_b;
+ uint8_t sspm_mask_b;
+ uint8_t scp_mask_b;
+ uint8_t srcclkeni_mask_b;
+ uint8_t md_apsrc_1_sel;
+ uint8_t md_apsrc_0_sel;
+ uint8_t conn_ddr_en_dbc_en;
+ uint8_t conn_mask_b;
+ uint8_t conn_apsrc_sel;
+
+ /* SPM_SRC_REQ */
+ uint8_t spm_apsrc_req;
+ uint8_t spm_f26m_req;
+ uint8_t spm_infra_req;
+ uint8_t spm_vrf18_req;
+ uint8_t spm_ddren_req;
+ uint8_t spm_rsv_src_req;
+ uint8_t spm_ddren_2_req;
+ uint8_t cpu_md_dvfs_sop_force_on;
+
+ /* SPM_SRC_MASK */
+ uint8_t csyspwreq_mask;
+ uint8_t ccif0_md_event_mask_b;
+ uint8_t ccif0_ap_event_mask_b;
+ uint8_t ccif1_md_event_mask_b;
+ uint8_t ccif1_ap_event_mask_b;
+ uint8_t ccif2_md_event_mask_b;
+ uint8_t ccif2_ap_event_mask_b;
+ uint8_t ccif3_md_event_mask_b;
+ uint8_t ccif3_ap_event_mask_b;
+ uint8_t md_srcclkena_0_infra_mask_b;
+ uint8_t md_srcclkena_1_infra_mask_b;
+ uint8_t conn_srcclkena_infra_mask_b;
+ uint8_t ufs_infra_req_mask_b;
+ uint8_t srcclkeni_infra_mask_b;
+ uint8_t md_apsrc_req_0_infra_mask_b;
+ uint8_t md_apsrc_req_1_infra_mask_b;
+ uint8_t conn_apsrcreq_infra_mask_b;
+ uint8_t ufs_srcclkena_mask_b;
+ uint8_t md_vrf18_req_0_mask_b;
+ uint8_t md_vrf18_req_1_mask_b;
+ uint8_t ufs_vrf18_req_mask_b;
+ uint8_t gce_vrf18_req_mask_b;
+ uint8_t conn_infra_req_mask_b;
+ uint8_t gce_apsrc_req_mask_b;
+ uint8_t disp0_apsrc_req_mask_b;
+ uint8_t disp1_apsrc_req_mask_b;
+ uint8_t mfg_req_mask_b;
+ uint8_t vdec_req_mask_b;
+
+ /* SPM_SRC2_MASK */
+ uint8_t md_ddr_en_0_mask_b;
+ uint8_t md_ddr_en_1_mask_b;
+ uint8_t conn_ddr_en_mask_b;
+ uint8_t ddren_sspm_apsrc_req_mask_b;
+ uint8_t ddren_scp_apsrc_req_mask_b;
+ uint8_t disp0_ddren_mask_b;
+ uint8_t disp1_ddren_mask_b;
+ uint8_t gce_ddren_mask_b;
+ uint8_t ddren_emi_self_refresh_ch0_mask_b;
+ uint8_t ddren_emi_self_refresh_ch1_mask_b;
+
+ /* SPM_WAKEUP_EVENT_MASK */
+ uint32_t spm_wakeup_event_mask;
+
+ /* SPM_WAKEUP_EVENT_EXT_MASK */
+ uint32_t spm_wakeup_event_ext_mask;
+
+ /* SPM_SRC3_MASK */
+ uint8_t md_ddr_en_2_0_mask_b;
+ uint8_t md_ddr_en_2_1_mask_b;
+ uint8_t conn_ddr_en_2_mask_b;
+ uint8_t ddren2_sspm_apsrc_req_mask_b;
+ uint8_t ddren2_scp_apsrc_req_mask_b;
+ uint8_t disp0_ddren2_mask_b;
+ uint8_t disp1_ddren2_mask_b;
+ uint8_t gce_ddren2_mask_b;
+ uint8_t ddren2_emi_self_refresh_ch0_mask_b;
+ uint8_t ddren2_emi_self_refresh_ch1_mask_b;
+
+ uint8_t mp0_cpu0_wfi_en;
+ uint8_t mp0_cpu1_wfi_en;
+ uint8_t mp0_cpu2_wfi_en;
+ uint8_t mp0_cpu3_wfi_en;
+
+ uint8_t mp1_cpu0_wfi_en;
+ uint8_t mp1_cpu1_wfi_en;
+ uint8_t mp1_cpu2_wfi_en;
+ uint8_t mp1_cpu3_wfi_en;
+};
+
+struct wake_status {
+ uint32_t assert_pc;
+ uint32_t r12;
+ uint32_t r12_ext;
+ uint32_t raw_sta;
+ uint32_t raw_ext_sta;
+ uint32_t wake_misc;
+ uint32_t timer_out;
+ uint32_t r13;
+ uint32_t r15;
+ uint32_t idle_sta;
+ uint32_t req_sta;
+ uint32_t debug_flag;
+ uint32_t debug_flag1;
+ uint32_t event_reg;
+ uint32_t isr;
+ uint32_t sw_flag;
+ uint32_t sw_flag1;
+ uint32_t log_index;
+};
+
+typedef struct spm_data {
+ unsigned int cmd;
+ union {
+ struct {
+ unsigned int sys_timestamp_l;
+ unsigned int sys_timestamp_h;
+ unsigned int sys_src_clk_l;
+ unsigned int sys_src_clk_h;
+ unsigned int spm_opt;
+ } suspend;
+ struct {
+ unsigned int args1;
+ unsigned int args2;
+ unsigned int args3;
+ unsigned int args4;
+ unsigned int args5;
+ unsigned int args6;
+ unsigned int args7;
+ } args;
+ } u;
+} spm_data_t;
+
+enum {
+ SPM_SUSPEND,
+ SPM_RESUME
+};
+
+extern void spm_disable_pcm_timer(void);
+extern void spm_set_bootaddr(unsigned long bootaddr);
+extern void spm_set_cpu_status(int cpu);
+extern void spm_set_power_control(const struct pwr_ctrl *pwrctrl);
+extern void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl);
+extern void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl);
+extern void spm_send_cpu_wakeup_event(void);
+extern void spm_get_wakeup_status(struct wake_status *wakesta);
+extern void spm_clean_after_wakeup(void);
+extern void spm_output_wake_reason(struct wake_status *wakesta,
+ const char *scenario);
+extern void spm_set_pcm_wdt(int en);
+extern void spm_lock_get(void);
+extern void spm_lock_release(void);
+extern void spm_boot_init(void);
+extern const char *spm_get_firmware_version(void);
+
+#endif /* SPM_H */
diff --git a/plat/mediatek/mt8183/drivers/spm/spm_pmic_wrap.c b/plat/mediatek/mt8183/drivers/spm/spm_pmic_wrap.c
new file mode 100644
index 0000000..ce85272
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/spm/spm_pmic_wrap.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <platform_def.h>
+#include <spm.h>
+#include <spm_pmic_wrap.h>
+#include <lib/libc/string.h>
+
+#define SLEEP_REG_MD_SPM_DVFS_CMD20 (SLEEP_REG_MD_BASE + 0x010)
+#define SLEEP_REG_MD_SPM_DVFS_CMD21 (SLEEP_REG_MD_BASE + 0x014)
+#define SLEEP_REG_MD_SPM_DVFS_CMD22 (SLEEP_REG_MD_BASE + 0x018)
+#define SLEEP_REG_MD_SPM_DVFS_CMD23 (SLEEP_REG_MD_BASE + 0x01C)
+
+/* PMIC_WRAP -> PMIC MT6358 */
+#define VCORE_BASE_UV 50000
+#define VOLT_TO_PMIC_VAL(volt) (((volt) - VCORE_BASE_UV + 625 - 1) / 625)
+#define PMIC_VAL_TO_VOLT(pmic) (((pmic) * 625) + VCORE_BASE_UV)
+
+#define DEFAULT_VOLT_VSRAM (100000)
+#define DEFAULT_VOLT_VCORE (100000)
+#define NR_PMIC_WRAP_CMD (NR_IDX_ALL)
+#define MAX_RETRY_COUNT (100)
+#define SPM_DATA_SHIFT (16)
+
+#define BUCK_VCORE_ELR0 0x14AA
+#define BUCK_VPROC12_CON0 0x1408
+#define BUCK_VPROC11_CON0 0x1388
+#define TOP_SPI_CON0 0x044C
+#define LDO_VSRAM_PROC12_CON0 0x1B88
+#define LDO_VSRAM_PROC11_CON0 0x1B46
+#define BUCK_VMODEM_ELR0 0x15A6
+
+struct pmic_wrap_cmd {
+ unsigned long cmd_addr;
+ unsigned long cmd_wdata;
+};
+
+struct pmic_wrap_setting {
+ enum pmic_wrap_phase_id phase;
+ struct pmic_wrap_cmd addr[NR_PMIC_WRAP_CMD];
+ struct {
+ struct {
+ unsigned long cmd_addr;
+ unsigned long cmd_wdata;
+ } _[NR_PMIC_WRAP_CMD];
+ const int nr_idx;
+ } set[NR_PMIC_WRAP_PHASE];
+};
+
+static struct pmic_wrap_setting pw = {
+ .phase = NR_PMIC_WRAP_PHASE,
+ .addr = {{0, 0} },
+ .set[PMIC_WRAP_PHASE_ALLINONE] = {
+ ._[CMD_0] = {BUCK_VCORE_ELR0, VOLT_TO_PMIC_VAL(70000),},
+ ._[CMD_1] = {BUCK_VCORE_ELR0, VOLT_TO_PMIC_VAL(80000),},
+ ._[CMD_2] = {BUCK_VPROC12_CON0, 0x3,},
+ ._[CMD_3] = {BUCK_VPROC12_CON0, 0x1,},
+ ._[CMD_4] = {BUCK_VPROC11_CON0, 0x3,},
+ ._[CMD_5] = {BUCK_VPROC11_CON0, 0x1,},
+ ._[CMD_6] = {TOP_SPI_CON0, 0x1,},
+ ._[CMD_7] = {TOP_SPI_CON0, 0x0,},
+ ._[CMD_8] = {BUCK_VPROC12_CON0, 0x0,},
+ ._[CMD_9] = {BUCK_VPROC12_CON0, 0x1,},
+ ._[CMD_10] = {BUCK_VPROC11_CON0, 0x0,},
+ ._[CMD_11] = {BUCK_VPROC11_CON0, 0x1,},
+ ._[CMD_12] = {LDO_VSRAM_PROC12_CON0, 0x0,},
+ ._[CMD_13] = {LDO_VSRAM_PROC12_CON0, 0x1,},
+ ._[CMD_14] = {LDO_VSRAM_PROC11_CON0, 0x0,},
+ ._[CMD_15] = {LDO_VSRAM_PROC11_CON0, 0x1,},
+ ._[CMD_20] = {BUCK_VMODEM_ELR0, VOLT_TO_PMIC_VAL(55000),},
+ ._[CMD_21] = {BUCK_VCORE_ELR0, VOLT_TO_PMIC_VAL(60000),},
+ ._[CMD_22] = {LDO_VSRAM_PROC11_CON0, 0x3,},
+ ._[CMD_23] = {LDO_VSRAM_PROC11_CON0, 0x1,},
+ .nr_idx = NR_IDX_ALL
+ }
+};
+
+void _mt_spm_pmic_table_init(void)
+{
+ struct pmic_wrap_cmd pwrap_cmd_default[NR_PMIC_WRAP_CMD] = {
+ {(uint32_t)SPM_DVFS_CMD0, (uint32_t)SPM_DVFS_CMD0,},
+ {(uint32_t)SPM_DVFS_CMD1, (uint32_t)SPM_DVFS_CMD1,},
+ {(uint32_t)SPM_DVFS_CMD2, (uint32_t)SPM_DVFS_CMD2,},
+ {(uint32_t)SPM_DVFS_CMD3, (uint32_t)SPM_DVFS_CMD3,},
+ {(uint32_t)SPM_DVFS_CMD4, (uint32_t)SPM_DVFS_CMD4,},
+ {(uint32_t)SPM_DVFS_CMD5, (uint32_t)SPM_DVFS_CMD5,},
+ {(uint32_t)SPM_DVFS_CMD6, (uint32_t)SPM_DVFS_CMD6,},
+ {(uint32_t)SPM_DVFS_CMD7, (uint32_t)SPM_DVFS_CMD7,},
+ {(uint32_t)SPM_DVFS_CMD8, (uint32_t)SPM_DVFS_CMD8,},
+ {(uint32_t)SPM_DVFS_CMD9, (uint32_t)SPM_DVFS_CMD9,},
+ {(uint32_t)SPM_DVFS_CMD10, (uint32_t)SPM_DVFS_CMD10,},
+ {(uint32_t)SPM_DVFS_CMD11, (uint32_t)SPM_DVFS_CMD11,},
+ {(uint32_t)SPM_DVFS_CMD12, (uint32_t)SPM_DVFS_CMD12,},
+ {(uint32_t)SPM_DVFS_CMD13, (uint32_t)SPM_DVFS_CMD13,},
+ {(uint32_t)SPM_DVFS_CMD14, (uint32_t)SPM_DVFS_CMD14,},
+ {(uint32_t)SPM_DVFS_CMD15, (uint32_t)SPM_DVFS_CMD15,},
+ {(uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD20,
+ (uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD20,},
+ {(uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD21,
+ (uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD21,},
+ {(uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD22,
+ (uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD22,},
+ {(uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD23,
+ (uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD23,}
+ };
+
+ memcpy(pw.addr, pwrap_cmd_default, sizeof(pwrap_cmd_default));
+}
+
+void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase)
+{
+ uint32_t idx, addr, data;
+
+ if (phase >= NR_PMIC_WRAP_PHASE)
+ return;
+
+ if (pw.phase == phase)
+ return;
+
+ if (pw.addr[0].cmd_addr == 0)
+ _mt_spm_pmic_table_init();
+
+ pw.phase = phase;
+
+ mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY |
+ BCLK_CG_EN_LSB | MD_BCLK_CG_EN_LSB);
+ for (idx = 0; idx < pw.set[phase].nr_idx; idx++) {
+ addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT;
+ data = pw.set[phase]._[idx].cmd_wdata;
+ mmio_write_32(pw.addr[idx].cmd_addr, addr | data);
+ }
+}
+
+void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, uint32_t idx,
+ uint32_t cmd_wdata)
+{
+ uint32_t addr;
+
+ if (phase >= NR_PMIC_WRAP_PHASE)
+ return;
+
+ if (idx >= pw.set[phase].nr_idx)
+ return;
+
+ pw.set[phase]._[idx].cmd_wdata = cmd_wdata;
+
+ mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY |
+ BCLK_CG_EN_LSB | MD_BCLK_CG_EN_LSB);
+ if (pw.phase == phase) {
+ addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT;
+ mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata);
+ }
+}
+
+uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, uint32_t idx)
+{
+ if (phase >= NR_PMIC_WRAP_PHASE)
+ return 0;
+
+ if (idx >= pw.set[phase].nr_idx)
+ return 0;
+
+ return pw.set[phase]._[idx].cmd_wdata;
+}
+
diff --git a/plat/mediatek/mt8183/drivers/spm/spm_pmic_wrap.h b/plat/mediatek/mt8183/drivers/spm/spm_pmic_wrap.h
new file mode 100644
index 0000000..194d347
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/spm/spm_pmic_wrap.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/****************************************************************
+ * Auto generated by DE, please DO NOT modify this file directly.
+ *****************************************************************/
+
+#ifndef SPM_PMIC_WRAP__H
+#define SPM_PMIC_WRAP__H
+
+enum pmic_wrap_phase_id {
+ PMIC_WRAP_PHASE_ALLINONE,
+ NR_PMIC_WRAP_PHASE
+};
+
+/* IDX mapping */
+enum {
+ CMD_0, /* 0x0 *//* PMIC_WRAP_PHASE_ALLINONE */
+ CMD_1, /* 0x1 */
+ CMD_2, /* 0x2 */
+ CMD_3, /* 0x3 */
+ CMD_4, /* 0x4 */
+ CMD_5, /* 0x5 */
+ CMD_6, /* 0x6 */
+ CMD_7, /* 0x7 */
+ CMD_8, /* 0x8 */
+ CMD_9, /* 0x9 */
+ CMD_10, /* 0xA */
+ CMD_11, /* 0xB */
+ CMD_12, /* 0xC */
+ CMD_13, /* 0xD */
+ CMD_14, /* 0xE */
+ CMD_15, /* 0xF */
+ CMD_20, /* 0x14 */
+ CMD_21, /* 0x15 */
+ CMD_22, /* 0x16 */
+ CMD_23, /* 0x17 */
+ NR_IDX_ALL
+};
+
+/* APIs */
+void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase);
+void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase,
+ uint32_t idx, uint32_t cmd_wdata);
+uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, uint32_t idx);
+#endif /* SPM_PMIC_WRAP__H */
+
diff --git a/plat/mediatek/mt8183/drivers/spm/spm_suspend.c b/plat/mediatek/mt8183/drivers/spm/spm_suspend.c
new file mode 100644
index 0000000..b9ac19f
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/spm/spm_suspend.c
@@ -0,0 +1,255 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <mt_gic_v3.h>
+#include <lib/mmio.h>
+#include <platform_def.h>
+#include <pmic.h>
+#include <spm.h>
+#include <uart.h>
+
+#define SPM_SYSCLK_SETTLE 99
+
+#define WAKE_SRC_FOR_SUSPEND \
+ (WAKE_SRC_R12_PCM_TIMER | \
+ WAKE_SRC_R12_SSPM_WDT_EVENT_B | \
+ WAKE_SRC_R12_KP_IRQ_B | \
+ WAKE_SRC_R12_CONN2AP_SPM_WAKEUP_B | \
+ WAKE_SRC_R12_EINT_EVENT_B | \
+ WAKE_SRC_R12_CONN_WDT_IRQ_B | \
+ WAKE_SRC_R12_CCIF0_EVENT_B | \
+ WAKE_SRC_R12_SSPM_SPM_IRQ_B | \
+ WAKE_SRC_R12_SCP_SPM_IRQ_B | \
+ WAKE_SRC_R12_SCP_WDT_EVENT_B | \
+ WAKE_SRC_R12_USB_CDSC_B | \
+ WAKE_SRC_R12_USB_POWERDWN_B | \
+ WAKE_SRC_R12_SYS_TIMER_EVENT_B | \
+ WAKE_SRC_R12_EINT_EVENT_SECURE_B | \
+ WAKE_SRC_R12_CCIF1_EVENT_B | \
+ WAKE_SRC_R12_MD2AP_PEER_EVENT_B | \
+ WAKE_SRC_R12_MD1_WDT_B | \
+ WAKE_SRC_R12_CLDMA_EVENT_B | \
+ WAKE_SRC_R12_SEJ_WDT_GPT_B)
+
+#define SLP_PCM_FLAGS \
+ (SPM_FLAG_DIS_VCORE_DVS | SPM_FLAG_DIS_VCORE_DFS | \
+ SPM_FLAG_DIS_ATF_ABORT | SPM_FLAG_DISABLE_MMSYS_DVFS | \
+ SPM_FLAG_DIS_INFRA_PDN | SPM_FLAG_SUSPEND_OPTION)
+
+#define SLP_PCM_FLAGS1 \
+ (SPM_FLAG1_DISABLE_MCDSR)
+
+static const struct pwr_ctrl suspend_ctrl = {
+ .wake_src = WAKE_SRC_FOR_SUSPEND,
+ .pcm_flags = SLP_PCM_FLAGS,
+ .pcm_flags1 = SLP_PCM_FLAGS1,
+
+ /* SPM_AP_STANDBY_CON */
+ .wfi_op = 0x1,
+ .mp0_cputop_idle_mask = 0,
+ .mp1_cputop_idle_mask = 0,
+ .mcusys_idle_mask = 0,
+ .mm_mask_b = 0,
+ .md_ddr_en_0_dbc_en = 0x1,
+ .md_ddr_en_1_dbc_en = 0,
+ .md_mask_b = 0x1,
+ .sspm_mask_b = 0x1,
+ .scp_mask_b = 0x1,
+ .srcclkeni_mask_b = 0x1,
+ .md_apsrc_1_sel = 0,
+ .md_apsrc_0_sel = 0,
+ .conn_ddr_en_dbc_en = 0x1,
+ .conn_mask_b = 0x1,
+ .conn_apsrc_sel = 0,
+
+ /* SPM_SRC_REQ */
+ .spm_apsrc_req = 0,
+ .spm_f26m_req = 0,
+ .spm_infra_req = 0,
+ .spm_vrf18_req = 0,
+ .spm_ddren_req = 0,
+ .spm_rsv_src_req = 0,
+ .spm_ddren_2_req = 0,
+ .cpu_md_dvfs_sop_force_on = 0,
+
+ /* SPM_SRC_MASK */
+ .csyspwreq_mask = 0x1,
+ .ccif0_md_event_mask_b = 0x1,
+ .ccif0_ap_event_mask_b = 0x1,
+ .ccif1_md_event_mask_b = 0x1,
+ .ccif1_ap_event_mask_b = 0x1,
+ .ccif2_md_event_mask_b = 0x1,
+ .ccif2_ap_event_mask_b = 0x1,
+ .ccif3_md_event_mask_b = 0x1,
+ .ccif3_ap_event_mask_b = 0x1,
+ .md_srcclkena_0_infra_mask_b = 0x1,
+ .md_srcclkena_1_infra_mask_b = 0,
+ .conn_srcclkena_infra_mask_b = 0,
+ .ufs_infra_req_mask_b = 0,
+ .srcclkeni_infra_mask_b = 0,
+ .md_apsrc_req_0_infra_mask_b = 0x1,
+ .md_apsrc_req_1_infra_mask_b = 0x1,
+ .conn_apsrcreq_infra_mask_b = 0x1,
+ .ufs_srcclkena_mask_b = 0,
+ .md_vrf18_req_0_mask_b = 0,
+ .md_vrf18_req_1_mask_b = 0,
+ .ufs_vrf18_req_mask_b = 0,
+ .gce_vrf18_req_mask_b = 0,
+ .conn_infra_req_mask_b = 0x1,
+ .gce_apsrc_req_mask_b = 0,
+ .disp0_apsrc_req_mask_b = 0,
+ .disp1_apsrc_req_mask_b = 0,
+ .mfg_req_mask_b = 0,
+ .vdec_req_mask_b = 0,
+
+ /* SPM_SRC2_MASK */
+ .md_ddr_en_0_mask_b = 0x1,
+ .md_ddr_en_1_mask_b = 0,
+ .conn_ddr_en_mask_b = 0x1,
+ .ddren_sspm_apsrc_req_mask_b = 0x1,
+ .ddren_scp_apsrc_req_mask_b = 0x1,
+ .disp0_ddren_mask_b = 0x1,
+ .disp1_ddren_mask_b = 0x1,
+ .gce_ddren_mask_b = 0x1,
+ .ddren_emi_self_refresh_ch0_mask_b = 0,
+ .ddren_emi_self_refresh_ch1_mask_b = 0,
+
+ /* SPM_WAKEUP_EVENT_MASK */
+ .spm_wakeup_event_mask = 0xF1782218,
+
+ /* SPM_WAKEUP_EVENT_EXT_MASK */
+ .spm_wakeup_event_ext_mask = 0xFFFFFFFF,
+
+ /* SPM_SRC3_MASK */
+ .md_ddr_en_2_0_mask_b = 0x1,
+ .md_ddr_en_2_1_mask_b = 0,
+ .conn_ddr_en_2_mask_b = 0x1,
+ .ddren2_sspm_apsrc_req_mask_b = 0x1,
+ .ddren2_scp_apsrc_req_mask_b = 0x1,
+ .disp0_ddren2_mask_b = 0,
+ .disp1_ddren2_mask_b = 0,
+ .gce_ddren2_mask_b = 0,
+ .ddren2_emi_self_refresh_ch0_mask_b = 0,
+ .ddren2_emi_self_refresh_ch1_mask_b = 0,
+
+ .mp0_cpu0_wfi_en = 0x1,
+ .mp0_cpu1_wfi_en = 0x1,
+ .mp0_cpu2_wfi_en = 0x1,
+ .mp0_cpu3_wfi_en = 0x1,
+
+ .mp1_cpu0_wfi_en = 0x1,
+ .mp1_cpu1_wfi_en = 0x1,
+ .mp1_cpu2_wfi_en = 0x1,
+ .mp1_cpu3_wfi_en = 0x1
+};
+
+static uint32_t spm_set_sysclk_settle(void)
+{
+ mmio_write_32(SPM_CLK_SETTLE, SPM_SYSCLK_SETTLE);
+ return mmio_read_32(SPM_CLK_SETTLE);
+}
+
+void go_to_sleep_before_wfi(void)
+{
+ int cpu = MPIDR_AFFLVL0_VAL(read_mpidr());
+ uint32_t settle;
+
+ settle = spm_set_sysclk_settle();
+ spm_set_cpu_status(cpu);
+ spm_set_power_control(&suspend_ctrl);
+ spm_set_wakeup_event(&suspend_ctrl);
+ spm_set_pcm_flags(&suspend_ctrl);
+ spm_send_cpu_wakeup_event();
+ spm_set_pcm_wdt(0);
+ spm_disable_pcm_timer();
+
+ if (is_infra_pdn(suspend_ctrl.pcm_flags))
+ mt_uart_save();
+
+ if (!mt_console_uart_cg_status())
+ console_switch_state(CONSOLE_FLAG_BOOT);
+
+ INFO("cpu%d: \"%s\", wakesrc = 0x%x, pcm_con1 = 0x%x\n",
+ cpu, spm_get_firmware_version(), suspend_ctrl.wake_src,
+ mmio_read_32(PCM_CON1));
+ INFO("settle = %u, sec = %u, sw_flag = 0x%x 0x%x, src_req = 0x%x\n",
+ settle, mmio_read_32(PCM_TIMER_VAL) / 32768,
+ suspend_ctrl.pcm_flags, suspend_ctrl.pcm_flags1,
+ mmio_read_32(SPM_SRC_REQ));
+
+ if (!mt_console_uart_cg_status())
+ console_switch_state(CONSOLE_FLAG_RUNTIME);
+}
+
+static void go_to_sleep_after_wfi(void)
+{
+ struct wake_status spm_wakesta;
+
+ if (is_infra_pdn(suspend_ctrl.pcm_flags))
+ mt_uart_restore();
+
+ spm_set_pcm_wdt(0);
+ spm_get_wakeup_status(&spm_wakesta);
+ spm_clean_after_wakeup();
+
+ if (!mt_console_uart_cg_status())
+ console_switch_state(CONSOLE_FLAG_BOOT);
+
+ spm_output_wake_reason(&spm_wakesta, "suspend");
+
+ if (!mt_console_uart_cg_status())
+ console_switch_state(CONSOLE_FLAG_RUNTIME);
+}
+
+static void spm_enable_armpll_l(void)
+{
+ /* power on */
+ mmio_setbits_32(ARMPLL_L_PWR_CON0, 0x1);
+
+ /* clear isolation */
+ mmio_clrbits_32(ARMPLL_L_PWR_CON0, 0x2);
+
+ /* enable pll */
+ mmio_setbits_32(ARMPLL_L_CON0, 0x1);
+
+ /* Add 20us delay for turning on PLL */
+ udelay(20);
+}
+
+static void spm_disable_armpll_l(void)
+{
+ /* disable pll */
+ mmio_clrbits_32(ARMPLL_L_CON0, 0x1);
+
+ /* isolation */
+ mmio_setbits_32(ARMPLL_L_PWR_CON0, 0x2);
+
+ /* power off */
+ mmio_clrbits_32(ARMPLL_L_PWR_CON0, 0x1);
+}
+
+void spm_system_suspend(void)
+{
+ spm_disable_armpll_l();
+ bcpu_enable(0);
+ bcpu_sram_enable(0);
+ spm_lock_get();
+ go_to_sleep_before_wfi();
+ spm_lock_release();
+}
+
+void spm_system_suspend_finish(void)
+{
+ spm_lock_get();
+ go_to_sleep_after_wfi();
+ spm_lock_release();
+ spm_enable_armpll_l();
+ bcpu_sram_enable(1);
+ bcpu_enable(1);
+}
diff --git a/plat/mediatek/mt8183/drivers/spm/spm_suspend.h b/plat/mediatek/mt8183/drivers/spm/spm_suspend.h
new file mode 100644
index 0000000..e127c2e
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/spm/spm_suspend.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SPM_SUSPEND_H__
+#define __SPM_SUSPEND_H__
+
+void spm_system_suspend(void);
+void spm_system_suspend_finish(void);
+
+#endif /* __SPM_SUSPEND_H__*/
diff --git a/plat/mediatek/mt8183/drivers/spmc/mtspmc.c b/plat/mediatek/mt8183/drivers/spmc/mtspmc.c
new file mode 100644
index 0000000..ac8e1b4
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/spmc/mtspmc.c
@@ -0,0 +1,366 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <arch_helpers.h>
+#include <cortex_a53.h>
+#include <cortex_a73.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <platform_def.h>
+#include <mcucfg.h>
+#include <spm.h>
+#include <drivers/delay_timer.h>
+#include <mtspmc.h>
+
+#include "mtspmc_private.h"
+
+
+static void set_retention(int cluster, int tick)
+{
+ uint64_t cpuectlr;
+
+ if (cluster)
+ cpuectlr = read_a73_cpuectlr_el1();
+ else
+ cpuectlr = read_a53_cpuectlr_el1();
+
+ cpuectlr &= ~0x7ULL;
+ cpuectlr |= tick & 0x7;
+
+ if (cluster)
+ write_a73_cpuectlr_el1(cpuectlr);
+ else
+ write_a53_cpuectlr_el1(cpuectlr);
+}
+
+void spm_enable_cpu_auto_off(int cluster, int cpu)
+{
+ uintptr_t reg = per_cpu(cluster, cpu, MCUCFG_SPARK);
+
+ set_retention(cluster, 1);
+ mmio_clrbits_32(reg, SW_NO_WAIT_Q);
+}
+
+void spm_disable_cpu_auto_off(int cluster, int cpu)
+{
+ uintptr_t reg = per_cpu(cluster, cpu, MCUCFG_SPARK);
+
+ mmio_setbits_32(reg, SW_NO_WAIT_Q);
+ set_retention(cluster, 0);
+}
+
+void spm_set_cpu_power_off(int cluster, int cpu)
+{
+ mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON);
+}
+
+void spm_enable_cluster_auto_off(int cluster)
+{
+ assert(cluster);
+
+ mmio_clrbits_32(MCUCFG_MP2_SPMC, SW_NO_WAIT_Q);
+ mmio_clrbits_32(MCUCFG_MP2_COQ, BIT(0));
+
+ mmio_clrbits_32(SPM_SPMC_DORMANT_ENABLE, MP1_SPMC_SRAM_DORMANT_EN);
+
+ mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON);
+}
+
+void mcucfg_set_bootaddr(int cluster, int cpu, uintptr_t bootaddr)
+{
+ uintptr_t reg;
+ const uintptr_t mp2_bootreg[] = {
+ MCUCFG_MP2_RVADDR0, MCUCFG_MP2_RVADDR1,
+ MCUCFG_MP2_RVADDR2, MCUCFG_MP2_RVADDR3 };
+
+ if (cluster) {
+ assert(cpu >= 0 && cpu < 4);
+ reg = mp2_bootreg[cpu];
+ } else {
+ reg = per_cpu(cluster, cpu, MCUCFG_BOOTADDR);
+ }
+
+ mmio_write_32(reg, bootaddr);
+}
+
+uintptr_t mcucfg_get_bootaddr(int cluster, int cpu)
+{
+ uintptr_t reg;
+ const uintptr_t mp2_bootreg[] = {
+ MCUCFG_MP2_RVADDR0, MCUCFG_MP2_RVADDR1,
+ MCUCFG_MP2_RVADDR2, MCUCFG_MP2_RVADDR3 };
+
+ if (cluster) {
+ assert(cpu >= 0 && cpu < 4);
+ reg = mp2_bootreg[cpu];
+ } else {
+ reg = per_cpu(cluster, cpu, MCUCFG_BOOTADDR);
+ }
+
+ return mmio_read_32(reg);
+}
+
+void mcucfg_init_archstate(int cluster, int cpu, int arm64)
+{
+ uintptr_t reg;
+ int i;
+
+ reg = per_cluster(cluster, MCUCFG_INITARCH);
+ i = cluster ? 16 : 12;
+
+ mmio_setbits_32(reg, (arm64 & 1) << (i + cpu));
+}
+
+/**
+ * Return power state of specified subsystem
+ *
+ * @mask: mask to SPM_PWR_STATUS to query the power state
+ * of one subsystem.
+ * RETURNS:
+ * 0 (the subsys was powered off)
+ * 1 (the subsys was powered on)
+ */
+int spm_get_powerstate(uint32_t mask)
+{
+ return mmio_read_32(SPM_PWR_STATUS) & mask;
+}
+
+int spm_get_cluster_powerstate(int cluster)
+{
+ uint32_t mask;
+
+ mask = cluster ? PWR_STATUS_MP1_CPUTOP : PWR_STATUS_MP0_CPUTOP;
+
+ return spm_get_powerstate(mask);
+}
+
+int spm_get_cpu_powerstate(int cluster, int cpu)
+{
+ uint32_t i;
+
+ /*
+ * a quick way to specify the mask of cpu[0-3]/cpu[4-7] in PWR_STATUS
+ * register which are the BITS[9:12](MP0_CPU0~3) and
+ * BITS[16:19](MP1_CPU0~3)
+ */
+ i = (cluster) ? 16 : 9;
+ i = 1 << (i + cpu);
+
+ return spm_get_powerstate(i);
+}
+
+int spmc_init(void)
+{
+ /* enable SPM register control */
+ mmio_write_32(SPM_POWERON_CONFIG_EN,
+ PROJECT_CODE | MD_BCLK_CG_EN | BCLK_CG_EN);
+
+#if SPMC_MODE == 1
+ INFO("SPM: enable SPMC mode\n");
+
+ /* 0: SPMC mode 1: Legacy mode */
+ mmio_write_32(SPM_BYPASS_SPMC, 0);
+
+ mmio_clrbits_32(per_cluster(0, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON_2ND);
+
+ mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
+ mmio_clrbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
+ mmio_clrbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
+ mmio_clrbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
+
+ mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
+ mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
+ mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
+#endif
+
+ mmio_clrbits_32(per_cluster(1, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON_2ND);
+ mmio_setbits_32(per_cluster(1, SPM_CLUSTER_PWR), PWRCTRL_PWR_RST_B);
+ mmio_clrbits_32(per_cluster(1, SPM_CLUSTER_PWR), PWRCTRL_PWR_CLK_DIS);
+
+ mmio_clrbits_32(per_cpu(1, 0, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
+ mmio_clrbits_32(per_cpu(1, 1, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
+ mmio_clrbits_32(per_cpu(1, 2, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
+ mmio_clrbits_32(per_cpu(1, 3, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
+
+ mmio_setbits_32(per_cpu(1, 0, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
+ mmio_setbits_32(per_cpu(1, 1, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
+ mmio_setbits_32(per_cpu(1, 2, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
+ mmio_setbits_32(per_cpu(1, 3, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
+
+ return 0;
+}
+
+/**
+ * Power on a core with specified cluster and core index
+ *
+ * @cluster: the cluster ID of the CPU which to be powered on
+ * @cpu: the CPU ID of the CPU which to be powered on
+ */
+void spm_poweron_cpu(int cluster, int cpu)
+{
+ INFO("spmc: power on core %d.%d\n", cluster, cpu);
+
+ /* STA_POWER_ON */
+ /* Start to turn on MP0_CPU0 */
+
+ /* Set PWR_RST_B = 1 */
+ mmio_setbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
+
+ /* Set PWR_ON = 1 */
+ mmio_setbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON);
+
+ /* Wait until MP0_CPU0_PWR_STA_MASK = 1 */
+ while (!spm_get_cpu_powerstate(cluster, cpu))
+ ;
+
+ /* Finish to turn on MP0_CPU0 */
+ INFO("spmc: power on core %d.%d successfully\n", cluster, cpu);
+}
+
+/**
+ * Power off a core with specified cluster and core index
+ *
+ * @cluster: the cluster ID of the CPU which to be powered off
+ * @cpu: the CPU ID of the CPU which to be powered off
+ */
+void spm_poweroff_cpu(int cluster, int cpu)
+{
+ INFO("spmc: power off core %d.%d\n", cluster, cpu);
+
+ /* Start to turn off MP0_CPU0 */
+ /* Set PWR_ON_2ND = 0 */
+ mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
+
+ /* Set PWR_ON = 0 */
+ mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON);
+
+ /* Wait until MP0_CPU0_PWR_STA_MASK = 0 */
+ while (spm_get_cpu_powerstate(cluster, cpu))
+ ;
+
+ /* Set PWR_RST_B = 0 */
+ mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
+
+ /* Finish to turn off MP0_CPU0 */
+ INFO("spmc: power off core %d.%d successfully\n", cluster, cpu);
+}
+
+/**
+ * Power off a cluster with specified index
+ *
+ * @cluster: the cluster index which to be powered off
+ */
+void spm_poweroff_cluster(int cluster)
+{
+ uint32_t mask;
+ uint32_t pwr_rst_ctl;
+
+ INFO("spmc: power off cluster %d\n", cluster);
+
+ /* Start to turn off MP0_CPUTOP */
+ /* Set bus protect - step1 : 0 */
+ mask = (cluster) ? MP1_CPUTOP_PROT_STEP1_0_MASK :
+ MP0_CPUTOP_PROT_STEP1_0_MASK;
+ mmio_write_32(INFRA_TOPAXI_PROTECTEN_1_SET, mask);
+
+ while ((mmio_read_32(INFRA_TOPAXI_PROTECTEN_STA1_1) & mask) != mask)
+ ;
+
+ /* Set PWR_ON_2ND = 0 */
+ mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR),
+ PWRCTRL_PWR_ON_2ND);
+
+ /* SPMC_DORMANT_ENABLE[0]=0 */
+ mask = (cluster) ? MP1_SPMC_SRAM_DORMANT_EN : MP0_SPMC_SRAM_DORMANT_EN;
+ mmio_clrbits_32(SPM_SPMC_DORMANT_ENABLE, mask);
+
+ /* Set PWR_ON = 0" */
+ mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON);
+
+ /* Wait until MP0_CPUTOP_PWR_STA_MASK = 0 */
+ while (spm_get_cluster_powerstate(cluster))
+ ;
+
+ /* NOTE
+ * Following flow only for BIG core cluster. It was from
+ * application note but not covered in mtcmos_ctrl.c
+ */
+ if (cluster) {
+ pwr_rst_ctl = mmio_read_32(MCUCFG_MP2_PWR_RST_CTL);
+ mmio_write_32(MCUCFG_MP2_PWR_RST_CTL,
+ (pwr_rst_ctl & ~SW_RST_B) | TOPAON_APB_MASK);
+ }
+
+ /* CPU_EXT_BUCK_ISO[0]=1 */
+ if (cluster)
+ mmio_setbits_32(SPM_CPU_EXT_BUCK_ISO, MP1_EXT_BUCK_ISO);
+
+ /* Finish to turn off MP0_CPUTOP */
+ INFO("spmc: power off cluster %d successfully\n", cluster);
+}
+
+/**
+ * Power on a cluster with specified index
+ *
+ * @cluster: the cluster index which to be powered on
+ */
+void spm_poweron_cluster(int cluster)
+{
+ uint32_t mask;
+ uint32_t pwr_rst_ctl;
+
+ INFO("spmc: power on cluster %d\n", cluster);
+
+ /* Start to turn on MP1_CPUTOP */
+
+ /* NOTE
+ * Following flow only for BIG core cluster. It was from
+ * application note but not covered in mtcmos_ctrl.c
+ */
+ if (cluster) {
+ mmio_clrbits_32(MCUCFG_MP2_PWR_RST_CTL, SW_RST_B);
+
+ /* CPU_EXT_BUCK_ISO[1]=0 */
+ /* Set mp<n>_vproc_ext_off to 0 to release vproc isolation control */
+ mmio_clrbits_32(SPM_CPU_EXT_BUCK_ISO, MP1_EXT_BUCK_ISO);
+
+ /* NOTE
+ * Following flow only for BIG core cluster. It was from
+ * application note but not covered in mtcmos_ctrl.c
+ */
+ pwr_rst_ctl = mmio_read_32(MCUCFG_MP2_PWR_RST_CTL);
+ mmio_write_32(MCUCFG_MP2_PWR_RST_CTL,
+ (pwr_rst_ctl | SW_RST_B) & ~TOPAON_APB_MASK);
+ }
+
+ /* Set PWR_ON_2ND = 0 */
+ mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR),
+ PWRCTRL_PWR_ON_2ND);
+
+ /* Set PWR_RST_B = 1 */
+ mmio_setbits_32(per_cluster(cluster, SPM_CLUSTER_PWR),
+ PWRCTRL_PWR_RST_B);
+
+ /* Set PWR_CLK_DIS = 0 */
+ mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR),
+ PWRCTRL_PWR_CLK_DIS);
+
+ /* Set PWR_ON = 1 */
+ mmio_setbits_32(per_cluster(cluster, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON);
+
+ /* Wait until MP1_CPUTOP_PWR_STA_MASK = 1 */
+ while (!spm_get_cluster_powerstate(cluster))
+ ;
+
+ /* Release bus protect - step1 : 0 */
+ mask = (cluster) ? MP1_CPUTOP_PROT_STEP1_0_MASK :
+ MP0_CPUTOP_PROT_STEP1_0_MASK;
+ mmio_write_32(INFRA_TOPAXI_PROTECTEN_1_CLR, mask);
+
+ /* Finish to turn on MP1_CPUTOP */
+ INFO("spmc: power on cluster %d successfully\n", cluster);
+}
diff --git a/plat/mediatek/mt8183/drivers/spmc/mtspmc.h b/plat/mediatek/mt8183/drivers/spmc/mtspmc.h
new file mode 100644
index 0000000..4cf3bcf
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/spmc/mtspmc.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MTSPMC_H
+#define MTSPMC_H
+
+/*
+ * CONFIG_SPMC_MODE: Select CPU power control mode.
+ *
+ * 0: Legacy
+ * Control power flow from SW through SPM register (MP*_PWR_CON).
+ * 1: HW
+ * Control power flow from SPMC. Most control flow and timing are handled
+ * by SPMC.
+ */
+#define SPMC_MODE 1
+
+int spmc_init(void);
+
+void spm_poweron_cpu(int cluster, int cpu);
+void spm_poweroff_cpu(int cluster, int cpu);
+
+void spm_poweroff_cluster(int cluster);
+void spm_poweron_cluster(int cluster);
+
+int spm_get_cpu_powerstate(int cluster, int cpu);
+int spm_get_cluster_powerstate(int cluster);
+int spm_get_powerstate(uint32_t mask);
+
+void spm_enable_cpu_auto_off(int cluster, int cpu);
+void spm_disable_cpu_auto_off(int cluster, int cpu);
+void spm_set_cpu_power_off(int cluster, int cpu);
+void spm_enable_cluster_auto_off(int cluster);
+
+void mcucfg_init_archstate(int cluster, int cpu, int arm64);
+void mcucfg_set_bootaddr(int cluster, int cpu, uintptr_t bootaddr);
+uintptr_t mcucfg_get_bootaddr(int cluster, int cpu);
+
+#endif /* MTSPMC_H */
diff --git a/plat/mediatek/mt8183/drivers/spmc/mtspmc_private.h b/plat/mediatek/mt8183/drivers/spmc/mtspmc_private.h
new file mode 100644
index 0000000..2228e63
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/spmc/mtspmc_private.h
@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MTSPMC_PRIVATE_H
+#define MTSPMC_PRIVATE_H
+
+/*
+ * per_cpu/cluster helper
+ */
+struct per_cpu_reg {
+ int cluster_addr;
+ int cpu_stride;
+};
+
+#define per_cpu(cluster, cpu, reg) (reg[cluster].cluster_addr + \
+ (cpu << reg[cluster].cpu_stride))
+#define per_cluster(cluster, reg) (reg[cluster].cluster_addr)
+
+/* SPMC related registers */
+#define SPM_POWERON_CONFIG_EN (SPM_BASE + 0x000)
+/* bit-fields of SPM_POWERON_CONFIG_EN */
+#define BCLK_CG_EN (1 << 0)
+#define MD_BCLK_CG_EN (1 << 1)
+#define PROJECT_CODE (0xb16 << 16)
+
+#define SPM_PWR_STATUS (SPM_BASE + 0x180)
+#define SPM_PWR_STATUS_2ND (SPM_BASE + 0x184)
+
+#define SPM_BYPASS_SPMC (SPM_BASE + 0x2b4)
+#define SPM_SPMC_DORMANT_ENABLE (SPM_BASE + 0x2b8)
+
+#define SPM_MP0_CPUTOP_PWR_CON (SPM_BASE + 0x204)
+#define SPM_MP0_CPU0_PWR_CON (SPM_BASE + 0x208)
+#define SPM_MP0_CPU1_PWR_CON (SPM_BASE + 0x20C)
+#define SPM_MP0_CPU2_PWR_CON (SPM_BASE + 0x210)
+#define SPM_MP0_CPU3_PWR_CON (SPM_BASE + 0x214)
+#define SPM_MP1_CPUTOP_PWR_CON (SPM_BASE + 0x218)
+#define SPM_MP1_CPU0_PWR_CON (SPM_BASE + 0x21C)
+#define SPM_MP1_CPU1_PWR_CON (SPM_BASE + 0x220)
+#define SPM_MP1_CPU2_PWR_CON (SPM_BASE + 0x224)
+#define SPM_MP1_CPU3_PWR_CON (SPM_BASE + 0x228)
+#define SPM_MP0_CPUTOP_L2_PDN (SPM_BASE + 0x240)
+#define SPM_MP0_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x244)
+#define SPM_MP0_CPU0_L1_PDN (SPM_BASE + 0x248)
+#define SPM_MP0_CPU1_L1_PDN (SPM_BASE + 0x24C)
+#define SPM_MP0_CPU2_L1_PDN (SPM_BASE + 0x250)
+#define SPM_MP0_CPU3_L1_PDN (SPM_BASE + 0x254)
+#define SPM_MP1_CPUTOP_L2_PDN (SPM_BASE + 0x258)
+#define SPM_MP1_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x25C)
+#define SPM_MP1_CPU0_L1_PDN (SPM_BASE + 0x260)
+#define SPM_MP1_CPU1_L1_PDN (SPM_BASE + 0x264)
+#define SPM_MP1_CPU2_L1_PDN (SPM_BASE + 0x268)
+#define SPM_MP1_CPU3_L1_PDN (SPM_BASE + 0x26C)
+
+#define SPM_CPU_EXT_BUCK_ISO (SPM_BASE + 0x290)
+/* bit-fields of SPM_CPU_EXT_BUCK_ISO */
+#define MP0_EXT_BUCK_ISO (1 << 0)
+#define MP1_EXT_BUCK_ISO (1 << 1)
+#define MP_EXT_BUCK_ISO (1 << 2)
+
+/* bit-fields of SPM_PWR_STATUS */
+#define PWR_STATUS_MD (1 << 0)
+#define PWR_STATUS_CONN (1 << 1)
+#define PWR_STATUS_DDRPHY (1 << 2)
+#define PWR_STATUS_DISP (1 << 3)
+#define PWR_STATUS_MFG (1 << 4)
+#define PWR_STATUS_ISP (1 << 5)
+#define PWR_STATUS_INFRA (1 << 6)
+#define PWR_STATUS_VDEC (1 << 7)
+#define PWR_STATUS_MP0_CPUTOP (1 << 8)
+#define PWR_STATUS_MP0_CPU0 (1 << 9)
+#define PWR_STATUS_MP0_CPU1 (1 << 10)
+#define PWR_STATUS_MP0_CPU2 (1 << 11)
+#define PWR_STATUS_MP0_CPU3 (1 << 12)
+#define PWR_STATUS_MCUSYS (1 << 14)
+#define PWR_STATUS_MP1_CPUTOP (1 << 15)
+#define PWR_STATUS_MP1_CPU0 (1 << 16)
+#define PWR_STATUS_MP1_CPU1 (1 << 17)
+#define PWR_STATUS_MP1_CPU2 (1 << 18)
+#define PWR_STATUS_MP1_CPU3 (1 << 19)
+#define PWR_STATUS_VEN (1 << 21)
+#define PWR_STATUS_MFG_ASYNC (1 << 23)
+#define PWR_STATUS_AUDIO (1 << 24)
+#define PWR_STATUS_C2K (1 << 28)
+#define PWR_STATUS_MD_INFRA (1 << 29)
+
+
+/* bit-fields of SPM_*_PWR_CON */
+#define PWRCTRL_PWR_RST_B (1 << 0)
+#define PWRCTRL_PWR_ISO (1 << 1)
+#define PWRCTRL_PWR_ON (1 << 2)
+#define PWRCTRL_PWR_ON_2ND (1 << 3)
+#define PWRCTRL_PWR_CLK_DIS (1 << 4)
+#define PWRCTRL_PWR_SRAM_CKISO (1 << 5)
+#define PWRCTRL_PWR_SRAM_ISOINT_B (1 << 6)
+#define PWRCTRL_PWR_SRAM_PD_SLPB_CLAMP (1 << 7)
+#define PWRCTRL_PWR_SRAM_PDN (1 << 8)
+#define PWRCTRL_PWR_SRAM_SLEEP_B (1 << 12)
+#define PWRCTRL_PWR_SRAM_PDN_ACK (1 << 24)
+#define PWRCTRL_PWR_SRAM_SLEEP_B_ACK (1 << 28)
+
+/* per_cpu registers for SPM_MP?_CPU?_PWR_CON */
+static const struct per_cpu_reg SPM_CPU_PWR[] = {
+ [0] = { .cluster_addr = SPM_MP0_CPU0_PWR_CON, .cpu_stride = 2 },
+ [1] = { .cluster_addr = SPM_MP1_CPU0_PWR_CON, .cpu_stride = 2 },
+};
+
+/* per_cluster registers for SPM_MP?_CPUTOP_PWR_CON */
+static const struct per_cpu_reg SPM_CLUSTER_PWR[] = {
+ [0] = { .cluster_addr = SPM_MP0_CPUTOP_PWR_CON },
+ [1] = { .cluster_addr = SPM_MP1_CPUTOP_PWR_CON },
+};
+
+/* APB Module infracfg_ao */
+#define INFRA_TOPAXI_PROTECTEN_1 (INFRACFG_AO_BASE + 0x250)
+#define INFRA_TOPAXI_PROTECTEN_STA1_1 (INFRACFG_AO_BASE + 0x258)
+#define INFRA_TOPAXI_PROTECTEN_1_SET (INFRACFG_AO_BASE + 0x2A8)
+#define INFRA_TOPAXI_PROTECTEN_1_CLR (INFRACFG_AO_BASE + 0x2AC)
+
+/* bit-fields of INFRA_TOPAXI_PROTECTEN_1_SET */
+#define MP0_CPUTOP_PROT_STEP1_0_MASK ((1 << 10)|(1 << 12)| \
+ (1 << 13)|(1 << 26))
+#define MP1_CPUTOP_PROT_STEP1_0_MASK ((1 << 11)|(1 << 14)| \
+ (1 << 15)|(1 << 27))
+
+/* bit-fields of INFRA_TOPAXI_PROTECTEN_STA1_1 */
+#define MP0_CPUTOP_PROT_STEP1_0_ACK_MASK ((1 << 10)|(1 << 12)| \
+ (1 << 13)|(1 << 26))
+#define MP1_CPUTOP_PROT_STEP1_0_ACK_MASK ((1 << 11)|(1 << 14)| \
+ (1 << 15)|(1 << 27))
+
+
+/*
+ * MCU configuration registers
+ */
+
+/* bit-fields of MCUCFG_MP?_AXI_CONFIG */
+#define MCUCFG_AXI_CONFIG_BROADCASTINNER (1 << 0)
+#define MCUCFG_AXI_CONFIG_BROADCASTOUTER (1 << 1)
+#define MCUCFG_AXI_CONFIG_BROADCASTCACHEMAINT (1 << 2)
+#define MCUCFG_AXI_CONFIG_SYSBARDISABLE (1 << 3)
+#define MCUCFG_AXI_CONFIG_ACINACTM (1 << 4)
+#define MCUCFG_AXI_CONFIG_AINACTS (1 << 5)
+
+
+#define MCUCFG_MP0_MISC_CONFIG2 ((uintptr_t)&mt8183_mcucfg->mp0_misc_config[2])
+#define MCUCFG_MP0_MISC_CONFIG3 ((uintptr_t)&mt8183_mcucfg->mp0_misc_config[3])
+#define MCUCFG_MP1_MISC_CONFIG2 ((uintptr_t)&mt8183_mcucfg->mp1_misc_config[2])
+#define MCUCFG_MP1_MISC_CONFIG3 ((uintptr_t)&mt8183_mcucfg->mp1_misc_config[3])
+
+#define MCUCFG_CPUSYS0_SPARKVRETCNTRL (MCUCFG_BASE + 0x1c00)
+/* bit-fields of MCUCFG_CPUSYS0_SPARKVRETCNTRL */
+#define CPU0_SPARK_VRET_CTRL (0x3f << 0)
+#define CPU1_SPARK_VRET_CTRL (0x3f << 8)
+#define CPU2_SPARK_VRET_CTRL (0x3f << 16)
+#define CPU3_SPARK_VRET_CTRL (0x3f << 24)
+
+/* SPARK control in little cores */
+#define MCUCFG_CPUSYS0_CPU0_SPMC_CTL (MCUCFG_BASE + 0x1c30)
+#define MCUCFG_CPUSYS0_CPU1_SPMC_CTL (MCUCFG_BASE + 0x1c34)
+#define MCUCFG_CPUSYS0_CPU2_SPMC_CTL (MCUCFG_BASE + 0x1c38)
+#define MCUCFG_CPUSYS0_CPU3_SPMC_CTL (MCUCFG_BASE + 0x1c3c)
+/* bit-fields of MCUCFG_CPUSYS0_CPU?_SPMC_CTL */
+#define SW_SPARK_EN (1 << 0)
+#define SW_NO_WAIT_Q (1 << 1)
+
+/* the MCUCFG which BIG cores used is at (MCUCFG_BASE + 0x2000) */
+#define MCUCFG_MP2_BASE (MCUCFG_BASE + 0x2000)
+#define MCUCFG_MP2_PWR_RST_CTL (MCUCFG_MP2_BASE + 0x8)
+/* bit-fields of MCUCFG_MP2_PWR_RST_CTL */
+#define SW_RST_B (1 << 0)
+#define TOPAON_APB_MASK (1 << 1)
+
+#define MCUCFG_MP2_CPUCFG (MCUCFG_MP2_BASE + 0x208)
+
+#define MCUCFG_MP2_RVADDR0 (MCUCFG_MP2_BASE + 0x290)
+#define MCUCFG_MP2_RVADDR1 (MCUCFG_MP2_BASE + 0x298)
+#define MCUCFG_MP2_RVADDR2 (MCUCFG_MP2_BASE + 0x2c0)
+#define MCUCFG_MP2_RVADDR3 (MCUCFG_MP2_BASE + 0x2c8)
+
+/* SPMC control */
+#define MCUCFG_MP0_SPMC (MCUCFG_BASE + 0x788)
+#define MCUCFG_MP2_SPMC (MCUCFG_MP2_BASE + 0x2a0)
+#define MCUCFG_MP2_COQ (MCUCFG_MP2_BASE + 0x2bC)
+
+/* per_cpu registers for MCUCFG_MP?_MISC_CONFIG2 */
+static const struct per_cpu_reg MCUCFG_BOOTADDR[] = {
+ [0] = { .cluster_addr = MCUCFG_MP0_MISC_CONFIG2, .cpu_stride = 3 },
+};
+
+/* per_cpu registers for MCUCFG_MP?_MISC_CONFIG3 */
+static const struct per_cpu_reg MCUCFG_INITARCH[] = {
+ [0] = { .cluster_addr = MCUCFG_MP0_MISC_CONFIG3 },
+ [1] = { .cluster_addr = MCUCFG_MP2_CPUCFG },
+};
+
+/* SPARK control in BIG cores */
+#define MCUCFG_MP2_PTP3_CPU0_SPMC0 (MCUCFG_MP2_BASE + 0x430)
+#define MCUCFG_MP2_PTP3_CPU0_SPMC1 (MCUCFG_MP2_BASE + 0x434)
+#define MCUCFG_MP2_PTP3_CPU1_SPMC0 (MCUCFG_MP2_BASE + 0x438)
+#define MCUCFG_MP2_PTP3_CPU1_SPMC1 (MCUCFG_MP2_BASE + 0x43c)
+#define MCUCFG_MP2_PTP3_CPU2_SPMC0 (MCUCFG_MP2_BASE + 0x440)
+#define MCUCFG_MP2_PTP3_CPU2_SPMC1 (MCUCFG_MP2_BASE + 0x444)
+#define MCUCFG_MP2_PTP3_CPU3_SPMC0 (MCUCFG_MP2_BASE + 0x448)
+#define MCUCFG_MP2_PTP3_CPU3_SPMC1 (MCUCFG_MP2_BASE + 0x44c)
+/* bit-fields of MCUCFG_MP2_PTP3_CPU?_SPMC? */
+#define SW_SPARK_EN (1 << 0)
+#define SW_NO_WAIT_Q (1 << 1)
+
+#define MCUCFG_MP2_SPARK2LDO (MCUCFG_MP2_BASE + 0x700)
+/* bit-fields of MCUCFG_MP2_SPARK2LDO */
+#define SPARK_VRET_CTRL (0x3f << 0)
+#define CPU0_SPARK_LDO_AMUXSEL (0xf << 6)
+#define CPU1_SPARK_LDO_AMUXSEL (0xf << 10)
+#define CPU2_SPARK_LDO_AMUXSEL (0xf << 14)
+#define CPU3_SPARK_LDO_AMUXSEL (0xf << 18)
+
+/* per_cpu registers for SPARK */
+static const struct per_cpu_reg MCUCFG_SPARK[] = {
+ [0] = { .cluster_addr = MCUCFG_CPUSYS0_CPU0_SPMC_CTL, .cpu_stride = 2 },
+ [1] = { .cluster_addr = MCUCFG_MP2_PTP3_CPU0_SPMC0, .cpu_stride = 3 },
+};
+
+/* per_cpu registers for SPARK2LDO */
+static const struct per_cpu_reg MCUCFG_SPARK2LDO[] = {
+ [0] = { .cluster_addr = MCUCFG_CPUSYS0_SPARKVRETCNTRL },
+ [1] = { .cluster_addr = MCUCFG_MP2_SPARK2LDO },
+};
+
+#endif /* MTSPMC_PRIVATE_H */
diff --git a/plat/mediatek/mt8183/drivers/sspm/sspm.c b/plat/mediatek/mt8183/drivers/sspm/sspm.c
new file mode 100644
index 0000000..6e76124
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/sspm/sspm.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <errno.h>
+#include <lib/mmio.h>
+#include <sspm.h>
+
+static void memcpy_to_sspm(uint32_t dst, uint32_t *src, uint32_t len)
+{
+ while (len--) {
+ mmio_write_32(dst, *src);
+ dst += sizeof(uint32_t);
+ src++;
+ }
+}
+
+static void memcpy_from_sspm(uint32_t *dst, uint32_t src, uint32_t len)
+{
+ while (len--) {
+ *dst = mmio_read_32(src);
+ dst++;
+ src += sizeof(uint32_t);
+ }
+}
+
+int sspm_mbox_read(uint32_t slot, uint32_t *data, uint32_t len)
+{
+ if (slot >= 32) {
+ ERROR("%s:slot = %d\n", __func__, slot);
+ return -EINVAL;
+ }
+
+ if (data)
+ memcpy_from_sspm(data,
+ MBOX3_BASE + slot * 4,
+ len);
+
+ return 0;
+}
+
+int sspm_mbox_write(uint32_t slot, uint32_t *data, uint32_t len)
+{
+ if (slot >= 32) {
+ ERROR("%s:slot = %d\n", __func__, slot);
+ return -EINVAL;
+ }
+
+ if (data)
+ memcpy_to_sspm(MBOX3_BASE + slot * 4,
+ data,
+ len);
+
+ return 0;
+}
+
+static int sspm_ipi_check_ack(uint32_t id)
+{
+ int ret = 0;
+
+ if (id == IPI_ID_PLATFORM) {
+ if ((mmio_read_32(MBOX0_BASE + MBOX_IN_IRQ_OFS) & 0x1) == 0x1)
+ ret = -EINPROGRESS;
+ } else if (id == IPI_ID_SUSPEND) {
+ if ((mmio_read_32(MBOX1_BASE + MBOX_IN_IRQ_OFS) & 0x2) == 0x2)
+ ret = -EINPROGRESS;
+ } else {
+ ERROR("%s: id = %d\n", __func__, id);
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+int sspm_ipi_send_non_blocking(uint32_t id, uint32_t *data)
+{
+ int ret = 0;
+
+ ret = sspm_ipi_check_ack(id);
+ if (ret)
+ return ret;
+
+ if (id == IPI_ID_PLATFORM) {
+ memcpy_to_sspm(MBOX0_BASE + PINR_OFFSET_PLATFORM * 4,
+ data,
+ PINR_SIZE_PLATFORM);
+ dsb();
+ mmio_write_32(MBOX0_BASE + MBOX_OUT_IRQ_OFS, 0x1);
+ } else if (id == IPI_ID_SUSPEND) {
+ memcpy_to_sspm(MBOX1_BASE + PINR_OFFSET_SUSPEND * 4,
+ data,
+ PINR_SIZE_SUSPEND);
+ dsb();
+ mmio_write_32(MBOX1_BASE + MBOX_OUT_IRQ_OFS,
+ 0x2);
+ }
+
+ return 0;
+}
+
+int sspm_ipi_recv_non_blocking(uint32_t id, uint32_t *data, uint32_t len)
+{
+ int ret = 0;
+
+ ret = sspm_ipi_check_ack(id);
+ if (ret == -EINPROGRESS) {
+ if (id == IPI_ID_PLATFORM) {
+ memcpy_from_sspm(data,
+ MBOX0_BASE + PINR_OFFSET_PLATFORM * 4,
+ len);
+ dsb();
+ /* clear interrupt bit*/
+ mmio_write_32(MBOX0_BASE + MBOX_IN_IRQ_OFS,
+ 0x1);
+ ret = 0;
+ } else if (id == IPI_ID_SUSPEND) {
+ memcpy_from_sspm(data,
+ MBOX1_BASE + PINR_OFFSET_SUSPEND * 4,
+ len);
+ dsb();
+ /* clear interrupt bit*/
+ mmio_write_32(MBOX1_BASE + MBOX_IN_IRQ_OFS,
+ 0x2);
+ ret = 0;
+ }
+ } else if (ret == 0) {
+ ret = -EBUSY;
+ }
+
+ return ret;
+}
+
+int sspm_alive_show(void)
+{
+ uint32_t ipi_data, count;
+ int ret = 0;
+
+ count = 5;
+ ipi_data = 0xdead;
+
+ if (sspm_ipi_send_non_blocking(IPI_ID_PLATFORM, &ipi_data) != 0) {
+ ERROR("sspm init send fail! ret=%d\n", ret);
+ return -1;
+ }
+
+ while (sspm_ipi_recv_non_blocking(IPI_ID_PLATFORM,
+ &ipi_data,
+ sizeof(ipi_data) / sizeof(uint32_t))
+ && count) {
+ mdelay(100);
+ count--;
+ }
+
+ return (ipi_data == 1) ? 0 : -1;
+}
diff --git a/plat/mediatek/mt8183/drivers/sspm/sspm.h b/plat/mediatek/mt8183/drivers/sspm/sspm.h
new file mode 100644
index 0000000..2c2cc10
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/sspm/sspm.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef __SSPM_H__
+#define __SSPM_H__
+/* These should sync with sspm.bin */
+#define IPI_ID_PLATFORM 0
+#define IPI_ID_SUSPEND 6
+#define PINR_OFFSET_PLATFORM 0
+#define PINR_SIZE_PLATFORM 3
+#define PINR_OFFSET_SUSPEND 2
+#define PINR_SIZE_SUSPEND 8
+
+#define MBOX0_BASE 0x10450000
+#define MBOX1_BASE 0x10460000
+#define MBOX3_BASE 0x10480000
+#define MBOX_OUT_IRQ_OFS 0x1000
+#define MBOX_IN_IRQ_OFS 0x1004
+
+#define SHAREMBOX_OFFSET_MCDI 0
+#define SHAREMBOX_SIZE_MCDI 20
+#define SHAREMBOX_OFFSET_SUSPEND 26
+#define SHAREMBOX_SIZE_SUSPEND 6
+
+int sspm_mbox_read(uint32_t slot, uint32_t *data, uint32_t len);
+int sspm_mbox_write(uint32_t slot, uint32_t *data, uint32_t len);
+int sspm_ipi_send_non_blocking(uint32_t id, uint32_t *data);
+int sspm_ipi_recv_non_blocking(uint32_t slot, uint32_t *data, uint32_t len);
+int sspm_alive_show(void);
+#endif /* __SSPM_H__ */
diff --git a/plat/mediatek/mt8183/drivers/timer/mt_timer.c b/plat/mediatek/mt8183/drivers/timer/mt_timer.c
new file mode 100644
index 0000000..0da4815
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/timer/mt_timer.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <mcucfg.h>
+#include <mt_timer.h>
+#include <platform_def.h>
+
+static void enable_systimer_compensation(void)
+{
+ unsigned int reg;
+
+ reg = mmio_read_32(CNTCR_REG);
+ reg &= ~COMP_15_EN;
+ reg |= COMP_20_EN;
+ mmio_write_32(CNTCR_REG, reg);
+
+ NOTICE("[systimer] CNTCR_REG(0x%x)\n", mmio_read_32(CNTCR_REG));
+}
+
+void mt_systimer_init(void)
+{
+ /* systimer is default on, so we only enable systimer compensation */
+ enable_systimer_compensation();
+}
diff --git a/plat/mediatek/mt8183/drivers/timer/mt_timer.h b/plat/mediatek/mt8183/drivers/timer/mt_timer.h
new file mode 100644
index 0000000..0b8edc5
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/timer/mt_timer.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_TIMER_H
+#define MT_TIMER_H
+
+
+#define SYSTIMER_BASE (0x10017000)
+#define CNTCR_REG (SYSTIMER_BASE + 0x0)
+#define CNTSR_REG (SYSTIMER_BASE + 0x4)
+
+#define COMP_15_EN (1 << 10)
+#define COMP_20_EN (1 << 11)
+
+void mt_systimer_init(void);
+
+#endif /* MT_TIMER_H */
diff --git a/plat/mediatek/mt8183/include/mcucfg.h b/plat/mediatek/mt8183/include/mcucfg.h
new file mode 100644
index 0000000..6b03818
--- /dev/null
+++ b/plat/mediatek/mt8183/include/mcucfg.h
@@ -0,0 +1,568 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT8183_MCUCFG_H
+#define MT8183_MCUCFG_H
+
+#include <platform_def.h>
+#include <stdint.h>
+
+struct mt8183_mcucfg_regs {
+ uint32_t mp0_ca7l_cache_config; /* 0x0 */
+ struct {
+ uint32_t mem_delsel0;
+ uint32_t mem_delsel1;
+ } mp0_cpu[4]; /* 0x4 */
+ uint32_t mp0_cache_mem_delsel0; /* 0x24 */
+ uint32_t mp0_cache_mem_delsel1; /* 0x28 */
+ uint32_t mp0_axi_config; /* 0x2C */
+ uint32_t mp0_misc_config[10]; /* 0x30 */
+ uint32_t mp0_ca7l_cfg_dis; /* 0x58 */
+ uint32_t mp0_ca7l_clken_ctrl; /* 0x5C */
+ uint32_t mp0_ca7l_rst_ctrl; /* 0x60 */
+ uint32_t mp0_ca7l_misc_config; /* 0x64 */
+ uint32_t mp0_ca7l_dbg_pwr_ctrl; /* 0x68 */
+ uint32_t mp0_rw_rsvd0; /* 0x6C */
+ uint32_t mp0_rw_rsvd1; /* 0x70 */
+ uint32_t mp0_ro_rsvd; /* 0x74 */
+ uint32_t reserved0_0; /* 0x78 */
+ uint32_t mp0_l2_cache_parity1_rdata; /* 0x7C */
+ uint32_t mp0_l2_cache_parity2_rdata; /* 0x80 */
+ uint32_t reserved0_1; /* 0x84 */
+ uint32_t mp0_rgu_dcm_config; /* 0x88 */
+ uint32_t mp0_ca53_specific_ctrl; /* 0x8C */
+ uint32_t mp0_esr_case; /* 0x90 */
+ uint32_t mp0_esr_mask; /* 0x94 */
+ uint32_t mp0_esr_trig_en; /* 0x98 */
+ uint32_t reserved_0_2; /* 0x9C */
+ uint32_t mp0_ses_cg_en; /* 0xA0 */
+ uint32_t reserved0_3[216]; /* 0xA4 */
+ uint32_t mp_dbg_ctrl; /* 0x404 */
+ uint32_t reserved0_4[34]; /* 0x408 */
+ uint32_t mp_dfd_ctrl; /* 0x490 */
+ uint32_t dfd_cnt_l; /* 0x494 */
+ uint32_t dfd_cnt_h; /* 0x498 */
+ uint32_t misccfg_ro_rsvd; /* 0x49C */
+ uint32_t reserved0_5[24]; /* 0x4A0 */
+ uint32_t mp1_rst_status; /* 0x500 */
+ uint32_t mp1_dbg_ctrl; /* 0x504 */
+ uint32_t mp1_dbg_flag; /* 0x508 */
+ uint32_t mp1_ca7l_ir_mon; /* 0x50C */
+ uint32_t reserved0_6[32]; /* 0x510 */
+ uint32_t mcusys_dbg_mon_sel_a; /* 0x590 */
+ uint32_t mcucys_dbg_mon; /* 0x594 */
+ uint32_t misccfg_sec_voi_status0; /* 0x598 */
+ uint32_t misccfg_sec_vio_status1; /* 0x59C */
+ uint32_t reserved0_7[18]; /* 0x5A0 */
+ uint32_t gic500_int_mask; /* 0x5E8 */
+ uint32_t core_rst_en_latch; /* 0x5EC */
+ uint32_t reserved0_8[3]; /* 0x5F0 */
+ uint32_t dbg_core_ret; /* 0x5FC */
+ uint32_t mcusys_config_a; /* 0x600 */
+ uint32_t mcusys_config1_a; /* 0x604 */
+ uint32_t mcusys_gic_prebase_a; /* 0x608 */
+ uint32_t mcusys_pinmux; /* 0x60C */
+ uint32_t sec_range0_start; /* 0x610 */
+ uint32_t sec_range0_end; /* 0x614 */
+ uint32_t sec_range_enable; /* 0x618 */
+ uint32_t l2c_mm_base; /* 0x61C */
+ uint32_t reserved0_9[8]; /* 0x620 */
+ uint32_t aclken_div; /* 0x640 */
+ uint32_t pclken_div; /* 0x644 */
+ uint32_t l2c_sram_ctrl; /* 0x648 */
+ uint32_t armpll_jit_ctrl; /* 0x64C */
+ uint32_t cci_addrmap; /* 0x650 */
+ uint32_t cci_config; /* 0x654 */
+ uint32_t cci_periphbase; /* 0x658 */
+ uint32_t cci_nevntcntovfl; /* 0x65C */
+ uint32_t cci_clk_ctrl; /* 0x660 */
+ uint32_t cci_acel_s1_ctrl; /* 0x664 */
+ uint32_t mcusys_bus_fabric_dcm_ctrl; /* 0x668 */
+ uint32_t mcu_misc_dcm_ctrl; /* 0x66C */
+ uint32_t xgpt_ctl; /* 0x670 */
+ uint32_t xgpt_idx; /* 0x674 */
+ uint32_t reserved0_10[3]; /* 0x678 */
+ uint32_t mcusys_rw_rsvd0; /* 0x684 */
+ uint32_t mcusys_rw_rsvd1; /* 0x688 */
+ uint32_t reserved0_11[13]; /* 0x68C */
+ uint32_t gic_500_delsel_ctl; /* 0x6C0 */
+ uint32_t etb_delsel_ctl; /* 0x6C4 */
+ uint32_t etb_rst_ctl; /* 0x6C8 */
+ uint32_t reserved0_12[29]; /* 0x6CC */
+ uint32_t cci_adb400_dcm_config; /* 0x740 */
+ uint32_t sync_dcm_config; /* 0x744 */
+ uint32_t reserved0_13; /* 0x748 */
+ uint32_t sync_dcm_cluster_config; /* 0x74C */
+ uint32_t sw_udi; /* 0x750 */
+ uint32_t reserved0_14; /* 0x754 */
+ uint32_t gic_sync_dcm; /* 0x758 */
+ uint32_t big_dbg_pwr_ctrl; /* 0x75C */
+ uint32_t gic_cpu_periphbase; /* 0x760 */
+ uint32_t axi_cpu_config; /* 0x764 */
+ uint32_t reserved0_15[2]; /* 0x768 */
+ uint32_t mcsib_sys_ctrl1; /* 0x770 */
+ uint32_t mcsib_sys_ctrl2; /* 0x774 */
+ uint32_t mcsib_sys_ctrl3; /* 0x778 */
+ uint32_t mcsib_sys_ctrl4; /* 0x77C */
+ uint32_t mcsib_dbg_ctrl1; /* 0x780 */
+ uint32_t pwrmcu_apb2to1; /* 0x784 */
+ uint32_t mp0_spmc; /* 0x788 */
+ uint32_t reserved0_16; /* 0x78C */
+ uint32_t mp0_spmc_sram_ctl; /* 0x790 */
+ uint32_t reserved0_17; /* 0x794 */
+ uint32_t mp0_sw_rst_wait_cycle; /* 0x798 */
+ uint32_t reserved0_18; /* 0x79C */
+ uint32_t mp0_pll_divider_cfg; /* 0x7A0 */
+ uint32_t reserved0_19; /* 0x7A4 */
+ uint32_t mp2_pll_divider_cfg; /* 0x7A8 */
+ uint32_t reserved0_20[5]; /* 0x7AC */
+ uint32_t bus_pll_divider_cfg; /* 0x7C0 */
+ uint32_t reserved0_21[7]; /* 0x7C4 */
+ uint32_t clusterid_aff1; /* 0x7E0 */
+ uint32_t clusterid_aff2; /* 0x7E4 */
+ uint32_t reserved0_22[2]; /* 0x7E8 */
+ uint32_t l2_cfg_mp0; /* 0x7F0 */
+ uint32_t l2_cfg_mp1; /* 0x7F4 */
+ uint32_t reserved0_23[218]; /* 0x7F8 */
+ uint32_t mscib_dcm_en; /* 0xB60 */
+ uint32_t reserved0_24[1063]; /* 0xB64 */
+ uint32_t cpusys0_sparkvretcntrl; /* 0x1C00 */
+ uint32_t cpusys0_sparken; /* 0x1C04 */
+ uint32_t cpusys0_amuxsel; /* 0x1C08 */
+ uint32_t reserved0_25[9]; /* 0x1C0C */
+ uint32_t cpusys0_cpu0_spmc_ctl; /* 0x1C30 */
+ uint32_t cpusys0_cpu1_spmc_ctl; /* 0x1C34 */
+ uint32_t cpusys0_cpu2_spmc_ctl; /* 0x1C38 */
+ uint32_t cpusys0_cpu3_spmc_ctl; /* 0x1C3C */
+ uint32_t reserved0_26[8]; /* 0x1C40 */
+ uint32_t mp0_sync_dcm_cgavg_ctrl; /* 0x1C60 */
+ uint32_t mp0_sync_dcm_cgavg_fact; /* 0x1C64 */
+ uint32_t mp0_sync_dcm_cgavg_rfact; /* 0x1C68 */
+ uint32_t mp0_sync_dcm_cgavg; /* 0x1C6C */
+ uint32_t mp0_l2_parity_clr; /* 0x1C70 */
+ uint32_t reserved0_27[357]; /* 0x1C74 */
+ uint32_t mp2_cpucfg; /* 0x2208 */
+ uint32_t mp2_axi_config; /* 0x220C */
+ uint32_t reserved0_28[25]; /* 0x2210 */
+ uint32_t mp2_sync_dcm; /* 0x2274 */
+ uint32_t reserved0_29[10]; /* 0x2278 */
+ uint32_t ptp3_cputop_spmc0; /* 0x22A0 */
+ uint32_t ptp3_cputop_spmc1; /* 0x22A4 */
+ uint32_t reserved0_30[98]; /* 0x22A8 */
+ uint32_t ptp3_cpu0_spmc0; /* 0x2430 */
+ uint32_t ptp3_cpu0_spmc1; /* 0x2434 */
+ uint32_t ptp3_cpu1_spmc0; /* 0x2438 */
+ uint32_t ptp3_cpu1_spmc1; /* 0x243C */
+ uint32_t ptp3_cpu2_spmc0; /* 0x2440 */
+ uint32_t ptp3_cpu2_spmc1; /* 0x2444 */
+ uint32_t ptp3_cpu3_spmc0; /* 0x2448 */
+ uint32_t ptp3_cpu3_spmc1; /* 0x244C */
+ uint32_t ptp3_cpux_spmc; /* 0x2450 */
+ uint32_t reserved0_31[171]; /* 0x2454 */
+ uint32_t spark2ld0; /* 0x2700 */
+};
+
+static struct mt8183_mcucfg_regs *const mt8183_mcucfg = (void *)MCUCFG_BASE;
+
+enum {
+ SW_SPARK_EN = 1 << 0,
+ SW_NO_WAIT_FOR_Q_CHANNEL = 1 << 1,
+ SW_FSM_OVERRIDE = 1 << 2,
+ SW_LOGIC_PRE1_PDB = 1 << 3,
+ SW_LOGIC_PRE2_PDB = 1 << 4,
+ SW_LOGIC_PDB = 1 << 5,
+ SW_ISO = 1 << 6,
+ SW_SRAM_SLEEPB = 0x3f << 7,
+ SW_SRAM_ISOINTB = 1 << 13,
+ SW_CLK_DIS = 1 << 14,
+ SW_CKISO = 1 << 15,
+ SW_PD = 0x3f << 16,
+ SW_HOT_PLUG_RESET = 1 << 22,
+ SW_PWR_ON_OVERRIDE_EN = 1 << 23,
+ SW_PWR_ON = 1 << 24,
+ SW_COQ_DIS = 1 << 25,
+ LOGIC_PDBO_ALL_OFF_ACK = 1 << 26,
+ LOGIC_PDBO_ALL_ON_ACK = 1 << 27,
+ LOGIC_PRE2_PDBO_ALL_ON_ACK = 1 << 28,
+ LOGIC_PRE1_PDBO_ALL_ON_ACK = 1 << 29
+};
+
+enum {
+ CPU_SW_SPARK_EN = 1 << 0,
+ CPU_SW_NO_WAIT_FOR_Q_CHANNEL = 1 << 1,
+ CPU_SW_FSM_OVERRIDE = 1 << 2,
+ CPU_SW_LOGIC_PRE1_PDB = 1 << 3,
+ CPU_SW_LOGIC_PRE2_PDB = 1 << 4,
+ CPU_SW_LOGIC_PDB = 1 << 5,
+ CPU_SW_ISO = 1 << 6,
+ CPU_SW_SRAM_SLEEPB = 1 << 7,
+ CPU_SW_SRAM_ISOINTB = 1 << 8,
+ CPU_SW_CLK_DIS = 1 << 9,
+ CPU_SW_CKISO = 1 << 10,
+ CPU_SW_PD = 0x1f << 11,
+ CPU_SW_HOT_PLUG_RESET = 1 << 16,
+ CPU_SW_POWR_ON_OVERRIDE_EN = 1 << 17,
+ CPU_SW_PWR_ON = 1 << 18,
+ CPU_SPARK2LDO_ALLSWOFF = 1 << 19,
+ CPU_PDBO_ALL_ON_ACK = 1 << 20,
+ CPU_PRE2_PDBO_ALLON_ACK = 1 << 21,
+ CPU_PRE1_PDBO_ALLON_ACK = 1 << 22
+};
+
+enum {
+ MP2_AXI_CONFIG_ACINACTM = 1 << 0,
+ MPx_AXI_CONFIG_ACINACTM = 1 << 4,
+ MPX_CA7_MISC_CONFIG_STANDBYWFIL2 = 1 << 28
+};
+
+enum {
+ MP0_CPU0_STANDBYWFE = 1 << 20,
+ MP0_CPU1_STANDBYWFE = 1 << 21,
+ MP0_CPU2_STANDBYWFE = 1 << 22,
+ MP0_CPU3_STANDBYWFE = 1 << 23
+};
+
+enum {
+ MP1_CPU0_STANDBYWFE = 1 << 20,
+ MP1_CPU1_STANDBYWFE = 1 << 21,
+ MP1_CPU2_STANDBYWFE = 1 << 22,
+ MP1_CPU3_STANDBYWFE = 1 << 23
+};
+
+enum {
+ B_SW_HOT_PLUG_RESET = 1 << 30,
+ B_SW_PD_OFFSET = 18,
+ B_SW_PD = 0x3f << B_SW_PD_OFFSET,
+ B_SW_SRAM_SLEEPB_OFFSET = 12,
+ B_SW_SRAM_SLEEPB = 0x3f << B_SW_SRAM_SLEEPB_OFFSET
+};
+
+enum {
+ B_SW_SRAM_ISOINTB = 1 << 9,
+ B_SW_ISO = 1 << 8,
+ B_SW_LOGIC_PDB = 1 << 7,
+ B_SW_LOGIC_PRE2_PDB = 1 << 6,
+ B_SW_LOGIC_PRE1_PDB = 1 << 5,
+ B_SW_FSM_OVERRIDE = 1 << 4,
+ B_SW_PWR_ON = 1 << 3,
+ B_SW_PWR_ON_OVERRIDE_EN = 1 << 2
+};
+
+enum {
+ B_FSM_STATE_OUT_OFFSET = 6,
+ B_FSM_STATE_OUT_MASK = 0x1f << B_FSM_STATE_OUT_OFFSET,
+ B_SW_LOGIC_PDBO_ALL_OFF_ACK = 1 << 5,
+ B_SW_LOGIC_PDBO_ALL_ON_ACK = 1 << 4,
+ B_SW_LOGIC_PRE2_PDBO_ALL_ON_ACK = 1 << 3,
+ B_SW_LOGIC_PRE1_PDBO_ALL_ON_ACK = 1 << 2,
+ B_FSM_OFF = 0 << B_FSM_STATE_OUT_OFFSET,
+ B_FSM_ON = 1 << B_FSM_STATE_OUT_OFFSET,
+ B_FSM_RET = 2 << B_FSM_STATE_OUT_OFFSET
+};
+
+/* APB Module infracfg_ao */
+enum {
+ INFRA_TOPAXI_PROTECTEN_1 = INFRACFG_AO_BASE + 0x250,
+ INFRA_TOPAXI_PROTECTSTA1_1 = INFRACFG_AO_BASE + 0x258,
+ INFRA_TOPAXI_PROTECTEN_1_SET = INFRACFG_AO_BASE + 0x2A8,
+ INFRA_TOPAXI_PROTECTEN_1_CLR = INFRACFG_AO_BASE + 0x2AC
+};
+
+enum {
+ IDX_PROTECT_MP0_CACTIVE = 10,
+ IDX_PROTECT_MP1_CACTIVE = 11,
+ IDX_PROTECT_ICC0_CACTIVE = 12,
+ IDX_PROTECT_ICD0_CACTIVE = 13,
+ IDX_PROTECT_ICC1_CACTIVE = 14,
+ IDX_PROTECT_ICD1_CACTIVE = 15,
+ IDX_PROTECT_L2C0_CACTIVE = 26,
+ IDX_PROTECT_L2C1_CACTIVE = 27
+};
+
+/* cpu boot mode */
+enum {
+ MP0_CPUCFG_64BIT_SHIFT = 12,
+ MP1_CPUCFG_64BIT_SHIFT = 28,
+ MP0_CPUCFG_64BIT = 0xf << MP0_CPUCFG_64BIT_SHIFT,
+ MP1_CPUCFG_64BIT = 0xfu << MP1_CPUCFG_64BIT_SHIFT
+};
+
+/* scu related */
+enum {
+ MP0_ACINACTM_SHIFT = 4,
+ MP1_ACINACTM_SHIFT = 4,
+ MP2_ACINACTM_SHIFT = 0,
+ MP0_ACINACTM = 1 << MP0_ACINACTM_SHIFT,
+ MP1_ACINACTM = 1 << MP1_ACINACTM_SHIFT,
+ MP2_ACINACTM = 1 << MP2_ACINACTM_SHIFT
+};
+
+enum {
+ MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0,
+ MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4,
+ MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8,
+ MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12,
+ MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16,
+
+ MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK =
+ 0xf << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT,
+ MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK =
+ 0xf << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT,
+ MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK =
+ 0xf << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT,
+ MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK =
+ 0xf << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT,
+ MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK =
+ 0xf << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT
+};
+
+enum {
+ MP1_AINACTS_SHIFT = 4,
+ MP1_AINACTS = 1 << MP1_AINACTS_SHIFT
+};
+
+enum {
+ MP1_SW_CG_GEN_SHIFT = 12,
+ MP1_SW_CG_GEN = 1 << MP1_SW_CG_GEN_SHIFT
+};
+
+enum {
+ MP1_L2RSTDISABLE_SHIFT = 14,
+ MP1_L2RSTDISABLE = 1 << MP1_L2RSTDISABLE_SHIFT
+};
+
+/* bus pll divider dcm related */
+enum {
+ BUS_PLLDIVIDER_DCM_DBC_CNT_0_SHIFT = 11,
+ BUS_PLLDIV_ARMWFI_DCM_EN_SHIFT = 24,
+ BUS_PLLDIV_ARMWFE_DCM_EN_SHIFT = 25,
+
+ BUS_PLLDIV_DCM = (1 << BUS_PLLDIVIDER_DCM_DBC_CNT_0_SHIFT) |
+ (1 << BUS_PLLDIV_ARMWFI_DCM_EN_SHIFT) |
+ (1 << BUS_PLLDIV_ARMWFE_DCM_EN_SHIFT)
+};
+
+/* mp0 pll divider dcm related */
+enum {
+ MP0_PLLDIV_DCM_DBC_CNT_0_SHIFT = 11,
+ MP0_PLLDIV_ARMWFI_DCM_EN_SHIFT = 24,
+ MP0_PLLDIV_ARMWFE_DCM_EN_SHIFT = 25,
+ MP0_PLLDIV_LASTCORE_IDLE_EN_SHIFT = 31,
+ MP0_PLLDIV_DCM = (1 << MP0_PLLDIV_DCM_DBC_CNT_0_SHIFT) |
+ (1 << MP0_PLLDIV_ARMWFI_DCM_EN_SHIFT) |
+ (1 << MP0_PLLDIV_ARMWFE_DCM_EN_SHIFT) |
+ (1u << MP0_PLLDIV_LASTCORE_IDLE_EN_SHIFT)
+};
+
+/* mp2 pll divider dcm related */
+enum {
+ MP2_PLLDIV_DCM_DBC_CNT_0_SHIFT = 11,
+ MP2_PLLDIV_ARMWFI_DCM_EN_SHIFT = 24,
+ MP2_PLLDIV_ARMWFE_DCM_EN_SHIFT = 25,
+ MP2_PLLDIV_LASTCORE_IDLE_EN_SHIFT = 31,
+ MP2_PLLDIV_DCM = (1 << MP2_PLLDIV_DCM_DBC_CNT_0_SHIFT) |
+ (1 << MP2_PLLDIV_ARMWFI_DCM_EN_SHIFT) |
+ (1 << MP2_PLLDIV_ARMWFE_DCM_EN_SHIFT) |
+ (1u << MP2_PLLDIV_LASTCORE_IDLE_EN_SHIFT)
+};
+
+/* mcsib dcm related */
+enum {
+ MCSIB_CACTIVE_SEL_SHIFT = 0,
+ MCSIB_DCM_EN_SHIFT = 16,
+
+ MCSIB_CACTIVE_SEL_MASK = 0xffff << MCSIB_CACTIVE_SEL_SHIFT,
+ MCSIB_CACTIVE_SEL = 0xffff << MCSIB_CACTIVE_SEL_SHIFT,
+
+ MCSIB_DCM_MASK = 0xffffu << MCSIB_DCM_EN_SHIFT,
+ MCSIB_DCM = 0xffffu << MCSIB_DCM_EN_SHIFT,
+};
+
+/* cci adb400 dcm related */
+enum {
+ CCI_M0_ADB400_DCM_EN_SHIFT = 0,
+ CCI_M1_ADB400_DCM_EN_SHIFT = 1,
+ CCI_M2_ADB400_DCM_EN_SHIFT = 2,
+ CCI_S2_ADB400_DCM_EN_SHIFT = 3,
+ CCI_S3_ADB400_DCM_EN_SHIFT = 4,
+ CCI_S4_ADB400_DCM_EN_SHIFT = 5,
+ CCI_S5_ADB400_DCM_EN_SHIFT = 6,
+ ACP_S3_ADB400_DCM_EN_SHIFT = 11,
+
+ CCI_ADB400_DCM_MASK = (1 << CCI_M0_ADB400_DCM_EN_SHIFT) |
+ (1 << CCI_M1_ADB400_DCM_EN_SHIFT) |
+ (1 << CCI_M2_ADB400_DCM_EN_SHIFT) |
+ (1 << CCI_S2_ADB400_DCM_EN_SHIFT) |
+ (1 << CCI_S4_ADB400_DCM_EN_SHIFT) |
+ (1 << CCI_S4_ADB400_DCM_EN_SHIFT) |
+ (1 << CCI_S5_ADB400_DCM_EN_SHIFT) |
+ (1 << ACP_S3_ADB400_DCM_EN_SHIFT),
+ CCI_ADB400_DCM = (1 << CCI_M0_ADB400_DCM_EN_SHIFT) |
+ (1 << CCI_M1_ADB400_DCM_EN_SHIFT) |
+ (1 << CCI_M2_ADB400_DCM_EN_SHIFT) |
+ (0 << CCI_S2_ADB400_DCM_EN_SHIFT) |
+ (0 << CCI_S4_ADB400_DCM_EN_SHIFT) |
+ (0 << CCI_S4_ADB400_DCM_EN_SHIFT) |
+ (0 << CCI_S5_ADB400_DCM_EN_SHIFT) |
+ (1 << ACP_S3_ADB400_DCM_EN_SHIFT)
+};
+
+/* sync dcm related */
+enum {
+ CCI_SYNC_DCM_DIV_EN_SHIFT = 0,
+ CCI_SYNC_DCM_UPDATE_TOG_SHIFT = 1,
+ CCI_SYNC_DCM_DIV_SEL_SHIFT = 2,
+ MP0_SYNC_DCM_DIV_EN_SHIFT = 10,
+ MP0_SYNC_DCM_UPDATE_TOG_SHIFT = 11,
+ MP0_SYNC_DCM_DIV_SEL_SHIFT = 12,
+
+ SYNC_DCM_MASK = (1 << CCI_SYNC_DCM_DIV_EN_SHIFT) |
+ (1 << CCI_SYNC_DCM_UPDATE_TOG_SHIFT) |
+ (0x7f << CCI_SYNC_DCM_DIV_SEL_SHIFT) |
+ (1 << MP0_SYNC_DCM_DIV_EN_SHIFT) |
+ (1 << MP0_SYNC_DCM_UPDATE_TOG_SHIFT) |
+ (0x7f << MP0_SYNC_DCM_DIV_SEL_SHIFT),
+ SYNC_DCM = (1 << CCI_SYNC_DCM_DIV_EN_SHIFT) |
+ (1 << CCI_SYNC_DCM_UPDATE_TOG_SHIFT) |
+ (0 << CCI_SYNC_DCM_DIV_SEL_SHIFT) |
+ (1 << MP0_SYNC_DCM_DIV_EN_SHIFT) |
+ (1 << MP0_SYNC_DCM_UPDATE_TOG_SHIFT) |
+ (0 << MP0_SYNC_DCM_DIV_SEL_SHIFT)
+};
+
+/* mcu bus dcm related */
+enum {
+ MCU_BUS_DCM_EN_SHIFT = 8,
+ MCU_BUS_DCM = 1 << MCU_BUS_DCM_EN_SHIFT
+};
+
+/* mcusys bus fabric dcm related */
+enum {
+ ACLK_INFRA_DYNAMIC_CG_EN_SHIFT = 0,
+ EMI2_ADB400_S_DCM_CTRL_SHIFT = 1,
+ ACLK_GPU_DYNAMIC_CG_EN_SHIFT = 2,
+ ACLK_PSYS_DYNAMIC_CG_EN_SHIFT = 3,
+ MP0_ADB400_S_DCM_CTRL_SHIFT = 4,
+ MP0_ADB400_M_DCM_CTRL_SHIFT = 5,
+ MP1_ADB400_S_DCM_CTRL_SHIFT = 6,
+ MP1_ADB400_M_DCM_CTRL_SHIFT = 7,
+ EMICLK_EMI_DYNAMIC_CG_EN_SHIFT = 8,
+ INFRACLK_INFRA_DYNAMIC_CG_EN_SHIFT = 9,
+ EMICLK_GPU_DYNAMIC_CG_EN_SHIFT = 10,
+ INFRACLK_PSYS_DYNAMIC_CG_EN_SHIFT = 11,
+ EMICLK_EMI1_DYNAMIC_CG_EN_SHIFT = 12,
+ EMI1_ADB400_S_DCM_CTRL_SHIFT = 16,
+ MP2_ADB400_M_DCM_CTRL_SHIFT = 17,
+ MP0_ICC_AXI_STREAM_ARCH_CG_SHIFT = 18,
+ MP1_ICC_AXI_STREAM_ARCH_CG_SHIFT = 19,
+ MP2_ICC_AXI_STREAM_ARCH_CG_SHIFT = 20,
+ L2_SHARE_ADB400_DCM_CTRL_SHIFT = 21,
+ MP1_AGGRESS_DCM_CTRL_SHIFT = 22,
+ MP0_AGGRESS_DCM_CTRL_SHIFT = 23,
+ MP0_ADB400_ACP_S_DCM_CTRL_SHIFT = 24,
+ MP0_ADB400_ACP_M_DCM_CTRL_SHIFT = 25,
+ MP1_ADB400_ACP_S_DCM_CTRL_SHIFT = 26,
+ MP1_ADB400_ACP_M_DCM_CTRL_SHIFT = 27,
+ MP3_ADB400_M_DCM_CTRL_SHIFT = 28,
+ MP3_ICC_AXI_STREAM_ARCH_CG_SHIFT = 29,
+
+ MCUSYS_BUS_FABRIC_DCM_MASK = (1 << ACLK_INFRA_DYNAMIC_CG_EN_SHIFT) |
+ (1 << EMI2_ADB400_S_DCM_CTRL_SHIFT) |
+ (1 << ACLK_GPU_DYNAMIC_CG_EN_SHIFT) |
+ (1 << ACLK_PSYS_DYNAMIC_CG_EN_SHIFT) |
+ (1 << MP0_ADB400_S_DCM_CTRL_SHIFT) |
+ (1 << MP0_ADB400_M_DCM_CTRL_SHIFT) |
+ (1 << MP1_ADB400_S_DCM_CTRL_SHIFT) |
+ (1 << MP1_ADB400_M_DCM_CTRL_SHIFT) |
+ (1 << EMICLK_EMI_DYNAMIC_CG_EN_SHIFT) |
+ (1 << INFRACLK_INFRA_DYNAMIC_CG_EN_SHIFT) |
+ (1 << EMICLK_GPU_DYNAMIC_CG_EN_SHIFT) |
+ (1 << INFRACLK_PSYS_DYNAMIC_CG_EN_SHIFT) |
+ (1 << EMICLK_EMI1_DYNAMIC_CG_EN_SHIFT) |
+ (1 << EMI1_ADB400_S_DCM_CTRL_SHIFT) |
+ (1 << MP2_ADB400_M_DCM_CTRL_SHIFT) |
+ (1 << MP0_ICC_AXI_STREAM_ARCH_CG_SHIFT) |
+ (1 << MP1_ICC_AXI_STREAM_ARCH_CG_SHIFT) |
+ (1 << MP2_ICC_AXI_STREAM_ARCH_CG_SHIFT) |
+ (1 << L2_SHARE_ADB400_DCM_CTRL_SHIFT) |
+ (1 << MP1_AGGRESS_DCM_CTRL_SHIFT) |
+ (1 << MP0_AGGRESS_DCM_CTRL_SHIFT) |
+ (1 << MP0_ADB400_ACP_S_DCM_CTRL_SHIFT) |
+ (1 << MP0_ADB400_ACP_M_DCM_CTRL_SHIFT) |
+ (1 << MP1_ADB400_ACP_S_DCM_CTRL_SHIFT) |
+ (1 << MP1_ADB400_ACP_M_DCM_CTRL_SHIFT) |
+ (1 << MP3_ADB400_M_DCM_CTRL_SHIFT) |
+ (1 << MP3_ICC_AXI_STREAM_ARCH_CG_SHIFT),
+
+ MCUSYS_BUS_FABRIC_DCM = (1 << ACLK_INFRA_DYNAMIC_CG_EN_SHIFT) |
+ (1 << EMI2_ADB400_S_DCM_CTRL_SHIFT) |
+ (1 << ACLK_GPU_DYNAMIC_CG_EN_SHIFT) |
+ (1 << ACLK_PSYS_DYNAMIC_CG_EN_SHIFT) |
+ (0 << MP0_ADB400_S_DCM_CTRL_SHIFT) |
+ (0 << MP0_ADB400_M_DCM_CTRL_SHIFT) |
+ (1 << MP1_ADB400_S_DCM_CTRL_SHIFT) |
+ (1 << MP1_ADB400_M_DCM_CTRL_SHIFT) |
+ (1 << EMICLK_EMI_DYNAMIC_CG_EN_SHIFT) |
+ (1 << INFRACLK_INFRA_DYNAMIC_CG_EN_SHIFT) |
+ (1 << EMICLK_GPU_DYNAMIC_CG_EN_SHIFT) |
+ (1 << INFRACLK_PSYS_DYNAMIC_CG_EN_SHIFT) |
+ (1 << EMICLK_EMI1_DYNAMIC_CG_EN_SHIFT) |
+ (1 << EMI1_ADB400_S_DCM_CTRL_SHIFT) |
+ (0 << MP2_ADB400_M_DCM_CTRL_SHIFT) |
+ (1 << MP0_ICC_AXI_STREAM_ARCH_CG_SHIFT) |
+ (1 << MP1_ICC_AXI_STREAM_ARCH_CG_SHIFT) |
+ (1 << MP2_ICC_AXI_STREAM_ARCH_CG_SHIFT) |
+ (1 << L2_SHARE_ADB400_DCM_CTRL_SHIFT) |
+ (1 << MP1_AGGRESS_DCM_CTRL_SHIFT) |
+ (1 << MP0_AGGRESS_DCM_CTRL_SHIFT) |
+ (1 << MP0_ADB400_ACP_S_DCM_CTRL_SHIFT) |
+ (1 << MP0_ADB400_ACP_M_DCM_CTRL_SHIFT) |
+ (1 << MP1_ADB400_ACP_S_DCM_CTRL_SHIFT) |
+ (1 << MP1_ADB400_ACP_M_DCM_CTRL_SHIFT) |
+ (1 << MP3_ADB400_M_DCM_CTRL_SHIFT) |
+ (1 << MP3_ICC_AXI_STREAM_ARCH_CG_SHIFT)
+};
+
+/* l2c_sram dcm related */
+enum {
+ L2C_SRAM_DCM_EN_SHIFT = 0,
+ L2C_SRAM_DCM = 1 << L2C_SRAM_DCM_EN_SHIFT
+};
+
+/* mcu misc dcm related */
+enum {
+ MP0_CNTVALUEB_DCM_EN_SHIFT = 0,
+ MP_CNTVALUEB_DCM_EN = 8,
+
+ CNTVALUEB_DCM = (1 << MP0_CNTVALUEB_DCM_EN_SHIFT) |
+ (1 << MP_CNTVALUEB_DCM_EN)
+};
+
+/* sync dcm cluster config related */
+enum {
+ MP0_SYNC_DCM_STALL_WR_EN_SHIFT = 7,
+ MCUSYS_MAX_ACCESS_LATENCY_SHIFT = 24,
+
+ MCU0_SYNC_DCM_STALL_WR_EN = 1 << MP0_SYNC_DCM_STALL_WR_EN_SHIFT,
+
+ MCUSYS_MAX_ACCESS_LATENCY_MASK = 0xf << MCUSYS_MAX_ACCESS_LATENCY_SHIFT,
+ MCUSYS_MAX_ACCESS_LATENCY = 0x5 << MCUSYS_MAX_ACCESS_LATENCY_SHIFT
+};
+
+/* cpusys rgu dcm related */
+enum {
+ CPUSYS_RGU_DCM_CONFIG_SHIFT = 0,
+
+ CPUSYS_RGU_DCM_CINFIG = 1 << CPUSYS_RGU_DCM_CONFIG_SHIFT
+};
+
+/* mp2 sync dcm related */
+enum {
+ MP2_DCM_EN_SHIFT = 0,
+
+ MP2_DCM_EN = 1 << MP2_DCM_EN_SHIFT
+};
+#endif /* MT8183_MCUCFG_H */
diff --git a/plat/mediatek/mt8183/include/mt_gic_v3.h b/plat/mediatek/mt8183/include/mt_gic_v3.h
new file mode 100644
index 0000000..b6fc29b
--- /dev/null
+++ b/plat/mediatek/mt8183/include/mt_gic_v3.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_GIC_V3_H
+#define MT_GIC_V3_H
+
+#include <lib/mmio.h>
+
+#define GIC_INT_MASK (MCUCFG_BASE + 0x5e8)
+#define GIC500_ACTIVE_SEL_SHIFT 3
+#define GIC500_ACTIVE_SEL_MASK (0x7 << GIC500_ACTIVE_SEL_SHIFT)
+#define GIC500_ACTIVE_CPU_SHIFT 16
+#define GIC500_ACTIVE_CPU_MASK (0xff << GIC500_ACTIVE_CPU_SHIFT)
+
+#define NR_INT_POL_CTL 20
+
+void mt_gic_driver_init(void);
+void mt_gic_init(void);
+void mt_gic_set_pending(uint32_t irq);
+uint32_t mt_gic_get_pending(uint32_t irq);
+void mt_gic_cpuif_enable(void);
+void mt_gic_cpuif_disable(void);
+void mt_gic_rdistif_init(void);
+void mt_gic_distif_save(void);
+void mt_gic_distif_restore(void);
+void mt_gic_rdistif_save(void);
+void mt_gic_rdistif_restore(void);
+void mt_gic_sync_dcm_enable(void);
+void mt_gic_sync_dcm_disable(void);
+
+#endif /* MT_GIC_V3_H */
diff --git a/plat/mediatek/mt8183/include/plat_dcm.h b/plat/mediatek/mt8183/include/plat_dcm.h
new file mode 100644
index 0000000..afa9b63
--- /dev/null
+++ b/plat/mediatek/mt8183/include/plat_dcm.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_DCM_H
+#define PLAT_DCM_H
+
+#define MP2_SYNC_DCM (MCUCFG_BASE + 0x2274)
+#define MP2_SYNC_DCM_MASK (0x1 << 0)
+#define MP2_SYNC_DCM_ON (0x1 << 0)
+#define MP2_SYNC_DCM_OFF (0x0 << 0)
+
+extern uint64_t plat_dcm_mcsi_a_addr;
+extern uint32_t plat_dcm_mcsi_a_val;
+extern int plat_dcm_initiated;
+
+extern void plat_dcm_mcsi_a_backup(void);
+extern void plat_dcm_mcsi_a_restore(void);
+extern void plat_dcm_rgu_enable(void);
+extern void plat_dcm_restore_cluster_on(unsigned long mpidr);
+extern void plat_dcm_msg_handler(uint64_t x1);
+extern unsigned long plat_dcm_get_enabled_cnt(uint64_t type);
+extern void plat_dcm_init(void);
+
+#define ALL_DCM_TYPE (ARMCORE_DCM_TYPE | MCUSYS_DCM_TYPE \
+ | STALL_DCM_TYPE | BIG_CORE_DCM_TYPE \
+ | GIC_SYNC_DCM_TYPE | RGU_DCM_TYPE \
+ | INFRA_DCM_TYPE \
+ | DDRPHY_DCM_TYPE | EMI_DCM_TYPE | DRAMC_DCM_TYPE \
+ | MCSI_DCM_TYPE)
+
+enum {
+ ARMCORE_DCM_TYPE = (1U << 0),
+ MCUSYS_DCM_TYPE = (1U << 1),
+ INFRA_DCM_TYPE = (1U << 2),
+ PERI_DCM_TYPE = (1U << 3),
+ EMI_DCM_TYPE = (1U << 4),
+ DRAMC_DCM_TYPE = (1U << 5),
+ DDRPHY_DCM_TYPE = (1U << 6),
+ STALL_DCM_TYPE = (1U << 7),
+ BIG_CORE_DCM_TYPE = (1U << 8),
+ GIC_SYNC_DCM_TYPE = (1U << 9),
+ LAST_CORE_DCM_TYPE = (1U << 10),
+ RGU_DCM_TYPE = (1U << 11),
+ TOPCKG_DCM_TYPE = (1U << 12),
+ LPDMA_DCM_TYPE = (1U << 13),
+ MCSI_DCM_TYPE = (1U << 14),
+ NR_DCM_TYPE = 15,
+};
+
+#endif /* PLAT_DCM_H */ \ No newline at end of file
diff --git a/plat/mediatek/mt8183/include/plat_debug.h b/plat/mediatek/mt8183/include/plat_debug.h
new file mode 100644
index 0000000..c9d73cc
--- /dev/null
+++ b/plat/mediatek/mt8183/include/plat_debug.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEBUG_H
+#define PLATFORM_DEBUG_H
+
+#define sync_writel(addr, val) \
+ do { mmio_write_32((addr), (val)); dsbsy(); } while (0)
+
+#define MCU_BIU_BASE 0x0c530000
+#define MISC1_CFG_BASE 0xb00
+#define CA15M_CFG_BASE 0x2000
+#define DFD_INTERNAL_CTL (MCU_BIU_BASE + MISC1_CFG_BASE + 0x00)
+#define CA15M_DBG_CONTROL (MCU_BIU_BASE + CA15M_CFG_BASE + 0x728)
+#define CA15M_PWR_RST_CTL (MCU_BIU_BASE + CA15M_CFG_BASE + 0x08)
+#define VPROC_EXT_CTL 0x10006290
+
+#define CFG_SF_CTRL 0x0c510014
+#define CFG_SF_INI 0x0c510010
+
+#define BIT_CA15M_L2PARITY_EN (1 << 1)
+#define BIT_CA15M_LASTPC_DIS (1 << 8)
+
+#define MCU_ALL_PWR_ON_CTRL 0x0c530b58
+#define PLAT_MTK_CIRCULAR_BUFFER_UNLOCK 0xefab4133
+#define PLAT_MTK_CIRCULAR_BUFFER_LOCK 0xefab4134
+
+extern void circular_buffer_setup(void);
+extern void l2c_parity_check_setup(void);
+extern void clear_all_on_mux(void);
+#endif /* PLATFORM_DEBUG_H */
diff --git a/plat/mediatek/mt8183/include/plat_macros.S b/plat/mediatek/mt8183/include/plat_macros.S
new file mode 100644
index 0000000..cac7769
--- /dev/null
+++ b/plat/mediatek/mt8183/include/plat_macros.S
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/arm/cci.h>
+#include <drivers/arm/gic_common.h>
+#include <drivers/arm/gicv2.h>
+#include <platform_def.h>
+
+.section .rodata.gic_reg_name, "aS"
+gicc_regs:
+ .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
+gicd_pend_reg:
+ .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \
+ " Offset:\t\t\tvalue\n"
+newline:
+ .asciz "\n"
+spacer:
+ .asciz ":\t\t0x"
+
+.section .rodata.cci_reg_name, "aS"
+cci_iface_regs:
+ .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
+
+ /* ---------------------------------------------
+ * The below macro prints out relevant GIC and
+ * CCI registers whenever an unhandled exception
+ * is taken in BL31.
+ * Clobbers: x0 - x10, x26, x27, sp
+ * ---------------------------------------------
+ */
+ .macro plat_crash_print_regs
+ mov_imm x26, BASE_GICD_BASE
+ mov_imm x27, BASE_GICC_BASE
+ /* Load the gicc reg list to x6 */
+ adr x6, gicc_regs
+ /* Load the gicc regs to gp regs used by str_in_crash_buf_print */
+ ldr w8, [x27, #GICC_HPPIR]
+ ldr w9, [x27, #GICC_AHPPIR]
+ ldr w10, [x27, #GICC_CTLR]
+ /* Store to the crash buf and print to console */
+ bl str_in_crash_buf_print
+
+ /* Print the GICD_ISPENDR regs */
+ add x7, x26, #GICD_ISPENDR
+ adr x4, gicd_pend_reg
+ bl asm_print_str
+gicd_ispendr_loop:
+ sub x4, x7, x26
+ cmp x4, #0x280
+ b.eq exit_print_gic_regs
+ bl asm_print_hex
+
+ adr x4, spacer
+ bl asm_print_str
+
+ ldr x4, [x7], #8
+ bl asm_print_hex
+
+ adr x4, newline
+ bl asm_print_str
+ b gicd_ispendr_loop
+exit_print_gic_regs:
+
+ adr x6, cci_iface_regs
+ /* Store in x7 the base address of the first interface */
+ mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \
+ PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX))
+ ldr w8, [x7, #SNOOP_CTRL_REG]
+ /* Store in x7 the base address of the second interface */
+ mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \
+ PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX))
+ ldr w9, [x7, #SNOOP_CTRL_REG]
+ /* Store to the crash buf and print to console */
+ bl str_in_crash_buf_print
+ .endm
diff --git a/plat/mediatek/mt8183/include/plat_private.h b/plat/mediatek/mt8183/include/plat_private.h
new file mode 100644
index 0000000..0853934
--- /dev/null
+++ b/plat/mediatek/mt8183/include/plat_private.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_PRIVATE_H
+#define PLAT_PRIVATE_H
+
+/*******************************************************************************
+ * Function and variable prototypes
+ ******************************************************************************/
+void plat_configure_mmu_el3(uintptr_t total_base,
+ uintptr_t total_size,
+ uintptr_t ro_start,
+ uintptr_t ro_limit,
+ uintptr_t coh_start,
+ uintptr_t coh_limit);
+
+void plat_mtk_cci_init(void);
+void plat_mtk_cci_enable(void);
+void plat_mtk_cci_disable(void);
+void plat_mtk_cci_init_sf(void);
+
+/* Declarations for plat_topology.c */
+int mt_setup_topology(void);
+
+#endif /* PLAT_PRIVATE_H */
diff --git a/plat/mediatek/mt8183/include/platform_def.h b/plat/mediatek/mt8183/include/platform_def.h
new file mode 100644
index 0000000..25ccfbc
--- /dev/null
+++ b/plat/mediatek/mt8183/include/platform_def.h
@@ -0,0 +1,321 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <arch.h>
+#include <drivers/arm/gic_common.h>
+
+#define PLAT_PRIMARY_CPU 0x0
+
+#define IO_PHYS 0x10000000
+#define INFRACFG_AO_BASE (IO_PHYS + 0x1000)
+#define PERI_BASE (IO_PHYS + 0x3000)
+#define GPIO_BASE (IO_PHYS + 0x5000)
+#define SPM_BASE (IO_PHYS + 0x6000)
+#define SLEEP_REG_MD_BASE (IO_PHYS + 0xf000)
+#define RGU_BASE (IO_PHYS + 0x7000)
+#define I2C4_BASE_SE (IO_PHYS + 0x1008000)
+#define I2C2_BASE_SE (IO_PHYS + 0x1009000)
+#define PMIC_WRAP_BASE (IO_PHYS + 0xd000)
+#define MCUCFG_BASE 0x0c530000
+#define CFG_SF_CTRL 0x0c510014
+#define CFG_SF_INI 0x0c510010
+#define EMI_BASE (IO_PHYS + 0x219000)
+#define EMI_MPU_BASE (IO_PHYS + 0x226000)
+#define TRNG_base (IO_PHYS + 0x20f000)
+#define MT_GIC_BASE 0x0c000000
+#define PLAT_MT_CCI_BASE 0x0c500000
+#define CCI_SIZE 0x00010000
+#define EINT_BASE 0x1000b000
+#define DVFSRC_BASE (IO_PHYS + 0x12000)
+
+#define SSPM_CFGREG_BASE (IO_PHYS + 0x440000)
+#define SSPM_MBOX_3_BASE (IO_PHYS + 0x480000)
+
+#define INFRACFG_AO_BASE (IO_PHYS + 0x1000)
+
+#define TOPCKGEN_BASE (IO_PHYS + 0x0)
+#define CLK_SCP_CFG_0 (TOPCKGEN_BASE + 0x200)
+#define CLK_SCP_CFG_1 (TOPCKGEN_BASE + 0x204)
+
+#define APMIXEDSYS (IO_PHYS + 0xC000)
+#define AP_PLL_CON3 (APMIXEDSYS + 0xC)
+#define AP_PLL_CON4 (APMIXEDSYS + 0x10)
+#define AP_PLL_CON6 (APMIXEDSYS + 0x18)
+#define ARMPLL_LL_CON0 (APMIXEDSYS + 0x200)
+#define ARMPLL_L_CON0 (APMIXEDSYS + 0x210)
+#define ARMPLL_L_PWR_CON0 (APMIXEDSYS + 0x21c)
+#define MAINPLL_CON0 (APMIXEDSYS + 0x220)
+#define CCIPLL_CON0 (APMIXEDSYS + 0x290)
+
+#define TOP_CKMUXSEL (INFRACFG_AO_BASE + 0x0)
+
+#define armpll_mux1_sel_big_mask (0xf << 4)
+#define armpll_mux1_sel_big_ARMSPLL (0x1 << 4)
+#define armpll_mux1_sel_sml_mask (0xf << 8)
+#define armpll_mux1_sel_sml_ARMSPLL (0x1 << 8)
+
+
+/* Aggregate of all devices in the first GB */
+#define MTK_DEV_RNG0_BASE IO_PHYS
+#define MTK_DEV_RNG0_SIZE 0x490000
+#define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000)
+#define MTK_DEV_RNG1_SIZE 0x4000000
+#define MTK_DEV_RNG2_BASE 0x0c000000
+#define MTK_DEV_RNG2_SIZE 0x600000
+#define MT_MCUSYS_SIZE 0x90000
+#define RAM_CONSOLE_BASE 0x11d000
+#define RAM_CONSOLE_SIZE 0x1000
+
+/*******************************************************************************
+ * MSDC
+ ******************************************************************************/
+#define MSDC0_BASE (IO_PHYS + 0x01230000)
+
+/*******************************************************************************
+ * MCUSYS related constants
+ ******************************************************************************/
+#define MT_L2_WRITE_ACCESS_RATE (MCUCFG_BASE + 0x604)
+#define MP0_CA7L_CACHE_CONFIG (MCUCFG_BASE + 0x7f0)
+#define MP1_CA7L_CACHE_CONFIG (MCUCFG_BASE + 0x7f4)
+#define EMI_WFIFO (MCUCFG_BASE + 0x0b5c)
+
+/*******************************************************************************
+ * GIC related constants
+ ******************************************************************************/
+#define MT_POLARITY_LOW 0
+#define MT_POLARITY_HIGH 1
+#define MT_EDGE_SENSITIVE 1
+#define MT_LEVEL_SENSITIVE 0
+
+/*******************************************************************************
+ * UART related constants
+ ******************************************************************************/
+#define UART0_BASE (IO_PHYS + 0x01002000)
+#define UART1_BASE (IO_PHYS + 0x01003000)
+
+#define UART_BAUDRATE 115200
+#define UART_CLOCK 26000000
+
+/*******************************************************************************
+ * System counter frequency related constants
+ ******************************************************************************/
+#define SYS_COUNTER_FREQ_IN_TICKS 13000000
+#define SYS_COUNTER_FREQ_IN_MHZ 13
+
+/*******************************************************************************
+ * GIC-400 & interrupt handling related constants
+ ******************************************************************************/
+
+/* Base MTK_platform compatible GIC memory map */
+#define BASE_GICD_BASE MT_GIC_BASE
+#define BASE_GICC_BASE (MT_GIC_BASE + 0x400000)
+#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x100000)
+#define BASE_GICR_BASE (MT_GIC_BASE + 0x100000)
+#define BASE_GICH_BASE (MT_GIC_BASE + 0x4000)
+#define BASE_GICV_BASE (MT_GIC_BASE + 0x6000)
+#define INT_POL_CTL0 (MCUCFG_BASE + 0xa80)
+#define SEC_POL_CTL_EN0 (MCUCFG_BASE + 0xa00)
+#define GIC_SYNC_DCM (MCUCFG_BASE + 0x758)
+#define GIC_SYNC_DCM_MASK 0x3
+#define GIC_SYNC_DCM_ON 0x3
+#define GIC_SYNC_DCM_OFF 0x0
+#define GIC_PRIVATE_SIGNALS 32
+
+#define PLAT_ARM_GICD_BASE BASE_GICD_BASE
+#define PLAT_ARM_GICC_BASE BASE_GICC_BASE
+
+#define PLAT_ARM_G1S_IRQ_PROPS(grp) ( \
+INTR_PROP_DESC(MT_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+INTR_PROP_DESC(MT_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+INTR_PROP_DESC(MT_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+INTR_PROP_DESC(MT_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+INTR_PROP_DESC(MT_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+INTR_PROP_DESC(MT_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+INTR_PROP_DESC(MT_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+INTR_PROP_DESC(MT_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE)) \
+
+#define PLAT_ARM_G0_IRQ_PROPS(grp)
+
+/*******************************************************************************
+ * CCI-400 related constants
+ ******************************************************************************/
+#define PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX 4
+#define PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX 3
+
+/*******************************************************************************
+ * WDT Registers
+ ******************************************************************************/
+#define MTK_WDT_BASE (IO_PHYS + 0x00007000)
+#define MTK_WDT_SIZE 0x1000
+#define MTK_WDT_MODE (MTK_WDT_BASE + 0x0000)
+#define MTK_WDT_LENGTH (MTK_WDT_BASE + 0x0004)
+#define MTK_WDT_RESTART (MTK_WDT_BASE + 0x0008)
+#define MTK_WDT_STATUS (MTK_WDT_BASE + 0x000C)
+#define MTK_WDT_INTERVAL (MTK_WDT_BASE + 0x0010)
+#define MTK_WDT_SWRST (MTK_WDT_BASE + 0x0014)
+#define MTK_WDT_SWSYSRST (MTK_WDT_BASE + 0x0018)
+#define MTK_WDT_NONRST_REG (MTK_WDT_BASE + 0x0020)
+#define MTK_WDT_NONRST_REG2 (MTK_WDT_BASE + 0x0024)
+#define MTK_WDT_REQ_MODE (MTK_WDT_BASE + 0x0030)
+#define MTK_WDT_REQ_IRQ_EN (MTK_WDT_BASE + 0x0034)
+#define MTK_WDT_EXT_REQ_CON (MTK_WDT_BASE + 0x0038)
+#define MTK_WDT_DEBUG_CTL (MTK_WDT_BASE + 0x0040)
+#define MTK_WDT_LATCH_CTL (MTK_WDT_BASE + 0x0044)
+#define MTK_WDT_DEBUG_CTL2 (MTK_WDT_BASE + 0x00A0)
+#define MTK_WDT_COUNTER (MTK_WDT_BASE + 0x0514)
+
+/* WDT_STATUS */
+#define MTK_WDT_STATUS_SPM_THERMAL_RST (1 << 0)
+#define MTK_WDT_STATUS_SPM_RST (1 << 1)
+#define MTK_WDT_STATUS_EINT_RST (1 << 2)
+#define MTK_WDT_STATUS_SYSRST_RST (1 << 3) /* from PMIC */
+#define MTK_WDT_STATUS_DVFSP_RST (1 << 4)
+#define MTK_WDT_STATUS_PMCU_RST (1 << 16)
+#define MTK_WDT_STATUS_MDDBG_RST (1 << 17)
+#define MTK_WDT_STATUS_THERMAL_DIRECT_RST (1 << 18)
+#define MTK_WDT_STATUS_DEBUG_RST (1 << 19)
+#define MTK_WDT_STATUS_SECURITY_RST (1 << 28)
+#define MTK_WDT_STATUS_IRQ_ASSERT (1 << 29)
+#define MTK_WDT_STATUS_SW_WDT_RST (1 << 30)
+#define MTK_WDT_STATUS_HW_WDT_RST (1U << 31)
+
+/* RGU other related */
+#define MTK_WDT_MODE_DUAL_MODE 0x0040
+#define MTK_WDT_MODE_IRQ 0x0008
+#define MTK_WDT_MODE_KEY 0x22000000
+#define MTK_WDT_MODE_EXTEN 0x0004
+#define MTK_WDT_SWRST_KEY 0x1209
+#define MTK_WDT_RESTART_KEY 0x1971
+
+/*******************************************************************************
+ * TRNG Registers
+ ******************************************************************************/
+#define TRNG_BASE_ADDR TRNG_base
+#define TRNG_BASE_SIZE 0x1000
+#define TRNG_CTRL (TRNG_base + 0x0000)
+#define TRNG_TIME (TRNG_base + 0x0004)
+#define TRNG_DATA (TRNG_base + 0x0008)
+#define TRNG_PDN_base 0x10001000
+#define TRNG_PDN_BASE_ADDR TRNG_PDN_BASE_ADDR
+#define TRNG_PDN_BASE_SIZE 0x1000
+#define TRNG_PDN_SET (TRNG_PDN_base + 0x0088)
+#define TRNG_PDN_CLR (TRNG_PDN_base + 0x008c)
+#define TRNG_PDN_STATUS (TRNG_PDN_base + 0x0094)
+#define TRNG_CTRL_RDY 0x80000000
+#define TRNG_CTRL_START 0x00000001
+#define TRNG_PDN_VALUE 0x200
+
+/* FIQ platform related define */
+#define MT_IRQ_SEC_SGI_0 8
+#define MT_IRQ_SEC_SGI_1 9
+#define MT_IRQ_SEC_SGI_2 10
+#define MT_IRQ_SEC_SGI_3 11
+#define MT_IRQ_SEC_SGI_4 12
+#define MT_IRQ_SEC_SGI_5 13
+#define MT_IRQ_SEC_SGI_6 14
+#define MT_IRQ_SEC_SGI_7 15
+
+#define FIQ_SMP_CALL_SGI 13
+#define WDT_IRQ_BIT_ID 174
+#define ATF_LOG_IRQ_ID 277
+
+#define ATF_AMMS_IRQ_ID 338
+#define PCCIF1_IRQ0_BIT_ID 185
+#define PCCIF1_IRQ1_BIT_ID 186
+
+#define DEBUG_XLAT_TABLE 0
+
+/*******************************************************************************
+ * Platform binary types for linking
+ ******************************************************************************/
+#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH aarch64
+
+/*******************************************************************************
+ * Generic platform constants
+ ******************************************************************************/
+
+/* Size of cacheable stacks */
+#if DEBUG_XLAT_TABLE
+#define PLATFORM_STACK_SIZE 0x800
+#elif IMAGE_BL1
+#define PLATFORM_STACK_SIZE 0x440
+#elif IMAGE_BL2
+#define PLATFORM_STACK_SIZE 0x400
+#elif IMAGE_BL31
+#define PLATFORM_STACK_SIZE 0x800
+#elif IMAGE_BL32
+#define PLATFORM_STACK_SIZE 0x440
+#endif
+
+#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
+#define PLAT_MAX_PWR_LVL U(2)
+#define PLAT_MAX_RET_STATE U(1)
+#define PLAT_MAX_OFF_STATE U(2)
+
+#define PLATFORM_CACHE_LINE_SIZE 64
+#define PLATFORM_SYSTEM_COUNT U(1)
+#define PLATFORM_CLUSTER_COUNT U(2)
+#define PLATFORM_CLUSTER0_CORE_COUNT U(4)
+#define PLATFORM_CLUSTER1_CORE_COUNT U(4)
+#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
+ PLATFORM_CLUSTER0_CORE_COUNT)
+#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
+#define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \
+ PLATFORM_CLUSTER_COUNT + \
+ PLATFORM_CORE_COUNT)
+
+#define SOC_CHIP_ID U(0x8183)
+
+/*******************************************************************************
+ * Platform memory map related constants
+ ******************************************************************************/
+
+#define TZRAM_BASE 0x54600000
+#define TZRAM_SIZE 0x00030000
+
+/*******************************************************************************
+ * BL31 specific defines.
+ ******************************************************************************/
+/*
+ * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if
+ * present). BL31_BASE is calculated using the current BL31 debug size plus a
+ * little space for growth.
+ */
+#define BL31_BASE (TZRAM_BASE + 0x1000)
+#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
+
+/*******************************************************************************
+ * Platform specific page table and MMU setup constants
+ ******************************************************************************/
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
+#define MAX_XLAT_TABLES 16
+#define MAX_MMAP_REGIONS 16
+
+/*******************************************************************************
+ * Declarations and constants to access the mailboxes safely. Each mailbox is
+ * aligned on the biggest cache line size in the platform. This is known only
+ * to the platform as it might have a combination of integrated and external
+ * caches. Such alignment ensures that two maiboxes do not sit on the same cache
+ * line at any cache level. They could belong to different cpus/clusters &
+ * get written while being protected by different locks causing corruption of
+ * a valid mailbox address.
+ ******************************************************************************/
+#define CACHE_WRITEBACK_SHIFT 6
+#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/mediatek/mt8183/include/power_tracer.h b/plat/mediatek/mt8183/include/power_tracer.h
new file mode 100644
index 0000000..c93be64
--- /dev/null
+++ b/plat/mediatek/mt8183/include/power_tracer.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef POWER_TRACER_H
+#define POWER_TRACER_H
+
+#define CPU_UP 0
+#define CPU_DOWN 1
+#define CPU_SUSPEND 2
+#define CLUSTER_UP 3
+#define CLUSTER_DOWN 4
+#define CLUSTER_SUSPEND 5
+
+void trace_power_flow(u_register_t mpidr, unsigned char mode);
+
+#endif /* POWER_TRACER_H */
+
diff --git a/plat/mediatek/mt8183/include/scu.h b/plat/mediatek/mt8183/include/scu.h
new file mode 100644
index 0000000..96b80c5
--- /dev/null
+++ b/plat/mediatek/mt8183/include/scu.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SCU_H
+#define SCU_H
+
+void disable_scu(u_register_t mpidr);
+void enable_scu(u_register_t mpidr);
+
+#endif /* SCU_H */
diff --git a/plat/mediatek/mt8183/include/sspm_reg.h b/plat/mediatek/mt8183/include/sspm_reg.h
new file mode 100644
index 0000000..3f1ac86
--- /dev/null
+++ b/plat/mediatek/mt8183/include/sspm_reg.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SSPM_REG_H__
+#define __SSPM_REG_H__
+
+#include "platform_def.h"
+
+#define SSPM_CFGREG_RSV_RW_REG0 (SSPM_CFGREG_BASE + 0x0100)
+#define SSPM_CFGREG_ACAO_INT_SET (SSPM_CFGREG_BASE + 0x00D8)
+#define SSPM_CFGREG_ACAO_INT_CLR (SSPM_CFGREG_BASE + 0x00DC)
+#define SSPM_CFGREG_ACAO_WAKEUP_EN (SSPM_CFGREG_BASE + 0x0204)
+
+#define STANDBYWFI_EN(n) (1 << (n + 8))
+#define GIC_IRQOUT_EN(n) (1 << (n + 0))
+
+#define NF_MCDI_MBOX 19
+#define MCDI_MBOX_CLUSTER_0_CAN_POWER_OFF 0
+#define MCDI_MBOX_CLUSTER_1_CAN_POWER_OFF 1
+#define MCDI_MBOX_BUCK_POWER_OFF_MASK 2
+#define MCDI_MBOX_CLUSTER_0_ATF_ACTION_DONE 3
+#define MCDI_MBOX_CLUSTER_1_ATF_ACTION_DONE 4
+#define MCDI_MBOX_BOOTADDR 5
+#define MCDI_MBOX_PAUSE_ACTION 6
+#define MCDI_MBOX_AVAIL_CPU_MASK 7
+#define MCDI_MBOX_CPU_CLUSTER_PWR_STAT 8
+#define MCDI_MBOX_ACTION_STAT 9
+#define MCDI_MBOX_CLUSTER_0_CNT 10
+#define MCDI_MBOX_CLUSTER_1_CNT 11
+#define MCDI_MBOX_CPU_ISOLATION_MASK 12
+#define MCDI_MBOX_PAUSE_ACK 13
+#define MCDI_MBOX_PENDING_ON_EVENT 14
+#define MCDI_MBOX_PROF_CMD 15
+#define MCDI_MBOX_DRCC_CALI_DONE 16
+#define MCDI_MBOX_HP_CMD 17
+#define MCDI_MBOX_HP_ACK 18
+
+#endif /* __SSPM_REG_H__ */
diff --git a/plat/mediatek/mt8183/plat_dcm.c b/plat/mediatek/mt8183/plat_dcm.c
new file mode 100644
index 0000000..8ee77f1
--- /dev/null
+++ b/plat/mediatek/mt8183/plat_dcm.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <lib/bakery_lock.h>
+#include <drivers/console.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <plat_dcm.h>
+#include <plat_private.h>
+#include <plat_dcm.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
+#include <mtk_plat_common.h>
+
+#define PWR_STATUS (SPM_BASE + 0x180)
+
+uint64_t plat_dcm_mcsi_a_addr;
+uint32_t plat_dcm_mcsi_a_val;
+static int plat_dcm_init_type;
+static unsigned int dcm_big_core_cnt;
+int plat_dcm_initiated;
+
+#define PWR_STA_BIG_MP_MASK (0x1 << 15)
+
+DEFINE_BAKERY_LOCK(dcm_lock);
+
+void dcm_lock_init(void)
+{
+ bakery_lock_init(&dcm_lock);
+}
+
+void dcm_lock_get(void)
+{
+ bakery_lock_get(&dcm_lock);
+}
+
+void dcm_lock_release(void)
+{
+ bakery_lock_release(&dcm_lock);
+}
+
+void plat_dcm_mcsi_a_backup(void)
+{
+}
+
+void plat_dcm_mcsi_a_restore(void)
+{
+}
+
+void plat_dcm_rgu_enable(void)
+{
+}
+
+void plat_dcm_big_core_sync(short on)
+{
+ /* Check if Big cluster power is existed */
+ if (!(mmio_read_32(PWR_STATUS) & PWR_STA_BIG_MP_MASK))
+ return;
+
+ if (on) {
+ mmio_write_32(MP2_SYNC_DCM,
+ (mmio_read_32(MP2_SYNC_DCM) & ~MP2_SYNC_DCM_MASK)
+ | MP2_SYNC_DCM_ON);
+ dcm_big_core_cnt++;
+ } else
+ mmio_write_32(MP2_SYNC_DCM,
+ (mmio_read_32(MP2_SYNC_DCM) & ~MP2_SYNC_DCM_MASK)
+ | MP2_SYNC_DCM_OFF);
+}
+
+void plat_dcm_restore_cluster_on(unsigned long mpidr)
+{
+ unsigned long cluster_id =
+ (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS;
+
+ switch (cluster_id) {
+ case 0x1:
+ dcm_lock_get();
+ if (plat_dcm_init_type & BIG_CORE_DCM_TYPE)
+ plat_dcm_big_core_sync(1);
+ else
+ plat_dcm_big_core_sync(0);
+ dcm_lock_release();
+ break;
+ default:
+ break;
+ }
+}
+
+void plat_dcm_msg_handler(uint64_t x1)
+{
+ plat_dcm_init_type = x1 & ALL_DCM_TYPE;
+}
+
+unsigned long plat_dcm_get_enabled_cnt(uint64_t type)
+{
+ switch (type) {
+ case BIG_CORE_DCM_TYPE:
+ return dcm_big_core_cnt;
+ default:
+ return 0;
+ }
+}
+
+void plat_dcm_init(void)
+{
+ dcm_lock_init();
+}
diff --git a/plat/mediatek/mt8183/plat_debug.c b/plat/mediatek/mt8183/plat_debug.c
new file mode 100644
index 0000000..2f0b67d
--- /dev/null
+++ b/plat/mediatek/mt8183/plat_debug.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <plat_debug.h>
+#include <platform_def.h>
+#include <spm.h>
+
+void circular_buffer_setup(void)
+{
+ /* Clear DBG_CONTROL.lastpc_disable to enable circular buffer */
+ sync_writel(CA15M_DBG_CONTROL,
+ mmio_read_32(CA15M_DBG_CONTROL) & ~(BIT_CA15M_LASTPC_DIS));
+}
+
+void circular_buffer_unlock(void)
+{
+ unsigned int i;
+
+ /* Disable big vproc external off (set CPU_EXT_BUCK_ISO to 0x0) */
+ sync_writel(VPROC_EXT_CTL, mmio_read_32(VPROC_EXT_CTL) & ~(0x1 << 1));
+
+ /* Release vproc apb mask (set 0x0C53_2008[1] to 0x0) */
+ sync_writel(CA15M_PWR_RST_CTL, mmio_read_32(CA15M_PWR_RST_CTL) & ~(0x1 << 1));
+
+ for (i = 1; i <= 4; ++i)
+ sync_writel(MP1_CPUTOP_PWR_CON + i * 4,
+ (mmio_read_32(MP1_CPUTOP_PWR_CON + i * 4) & ~(0x4))|(0x4));
+
+ /* Set DFD.en */
+ sync_writel(DFD_INTERNAL_CTL, 0x1);
+}
+
+void circular_buffer_lock(void)
+{
+ /* Clear DFD.en */
+ sync_writel(DFD_INTERNAL_CTL, 0x0);
+}
+
+void clear_all_on_mux(void)
+{
+ sync_writel(MCU_ALL_PWR_ON_CTRL,
+ mmio_read_32(MCU_ALL_PWR_ON_CTRL) & ~(1 << 2));
+ sync_writel(MCU_ALL_PWR_ON_CTRL,
+ mmio_read_32(MCU_ALL_PWR_ON_CTRL) & ~(1 << 1));
+}
+
+void l2c_parity_check_setup(void)
+{
+ /* Enable DBG_CONTROL.l2parity_en */
+ sync_writel(CA15M_DBG_CONTROL,
+ mmio_read_32(CA15M_DBG_CONTROL) | BIT_CA15M_L2PARITY_EN);
+}
diff --git a/plat/mediatek/mt8183/plat_mt_gic.c b/plat/mediatek/mt8183/plat_mt_gic.c
new file mode 100644
index 0000000..35792b2
--- /dev/null
+++ b/plat/mediatek/mt8183/plat_mt_gic.c
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <drivers/arm/gicv3.h>
+#include <bl31/interrupt_mgmt.h>
+#include <mt_gic_v3.h>
+#include <mtk_plat_common.h>
+#include "../drivers/arm/gic/v3/gicv3_private.h"
+#include "plat_private.h"
+#include <plat/common/platform.h>
+#include <platform_def.h>
+#include <stdint.h>
+#include <stdio.h>
+
+uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
+static uint32_t rdist_has_saved[PLATFORM_CORE_COUNT];
+
+/* we save and restore the GICv3 context on system suspend */
+gicv3_dist_ctx_t dist_ctx;
+
+static unsigned int mt_mpidr_to_core_pos(u_register_t mpidr)
+{
+ return plat_core_pos_by_mpidr(mpidr);
+}
+
+gicv3_driver_data_t mt_gicv3_data = {
+ .gicd_base = MT_GIC_BASE,
+ .gicr_base = MT_GIC_RDIST_BASE,
+ .rdistif_num = PLATFORM_CORE_COUNT,
+ .rdistif_base_addrs = rdistif_base_addrs,
+ .mpidr_to_core_pos = mt_mpidr_to_core_pos,
+};
+
+struct gic_chip_data {
+ unsigned int saved_group;
+ unsigned int saved_enable;
+ unsigned int saved_conf0;
+ unsigned int saved_conf1;
+ unsigned int saved_grpmod;
+};
+
+static struct gic_chip_data gic_data;
+
+void clear_sec_pol_ctl_en(void)
+{
+ unsigned int i;
+
+ /* total 19 polarity ctrl registers */
+ for (i = 0; i <= NR_INT_POL_CTL - 1; i++) {
+ mmio_write_32((SEC_POL_CTL_EN0 + (i * 4)), 0);
+ }
+ dsb();
+}
+
+void mt_gic_driver_init(void)
+{
+ gicv3_driver_init(&mt_gicv3_data);
+}
+
+void mt_gic_set_pending(uint32_t irq)
+{
+ gicv3_set_interrupt_pending(irq, plat_my_core_pos());
+}
+
+void mt_gic_cpuif_enable(void)
+{
+ gicv3_cpuif_enable(plat_my_core_pos());
+}
+
+void mt_gic_cpuif_disable(void)
+{
+ gicv3_cpuif_disable(plat_my_core_pos());
+}
+
+void mt_gic_rdistif_init(void)
+{
+ unsigned int proc_num;
+ unsigned int index;
+ uintptr_t gicr_base;
+
+ proc_num = plat_my_core_pos();
+ gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
+
+ /* set all SGI/PPI as non-secure GROUP1 by default */
+ mmio_write_32(gicr_base + GICR_IGROUPR0, ~0U);
+ mmio_write_32(gicr_base + GICR_IGRPMODR0, 0x0);
+
+ /* setup the default PPI/SGI priorities */
+ for (index = 0; index < TOTAL_PCPU_INTR_NUM; index += 4U)
+ gicr_write_ipriorityr(gicr_base, index,
+ GICD_IPRIORITYR_DEF_VAL);
+}
+
+void mt_gic_distif_save(void)
+{
+ gicv3_distif_save(&dist_ctx);
+}
+
+void mt_gic_distif_restore(void)
+{
+ gicv3_distif_init_restore(&dist_ctx);
+}
+
+void mt_gic_rdistif_save(void)
+{
+ unsigned int proc_num;
+ uintptr_t gicr_base;
+
+ proc_num = plat_my_core_pos();
+ gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
+
+ gic_data.saved_group = mmio_read_32(gicr_base + GICR_IGROUPR0);
+ gic_data.saved_enable = mmio_read_32(gicr_base + GICR_ISENABLER0);
+ gic_data.saved_conf0 = mmio_read_32(gicr_base + GICR_ICFGR0);
+ gic_data.saved_conf1 = mmio_read_32(gicr_base + GICR_ICFGR1);
+ gic_data.saved_grpmod = mmio_read_32(gicr_base + GICR_IGRPMODR0);
+
+ rdist_has_saved[proc_num] = 1;
+}
+
+void mt_gic_rdistif_restore(void)
+{
+ unsigned int proc_num;
+ uintptr_t gicr_base;
+
+ proc_num = plat_my_core_pos();
+ if (rdist_has_saved[proc_num] == 1) {
+ gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
+ mmio_write_32(gicr_base + GICR_IGROUPR0, gic_data.saved_group);
+ mmio_write_32(gicr_base + GICR_ISENABLER0, gic_data.saved_enable);
+ mmio_write_32(gicr_base + GICR_ICFGR0, gic_data.saved_conf0);
+ mmio_write_32(gicr_base + GICR_ICFGR1, gic_data.saved_conf1);
+ mmio_write_32(gicr_base + GICR_IGRPMODR0, gic_data.saved_grpmod);
+ }
+}
+
+void mt_gic_sync_dcm_enable(void)
+{
+ mmio_clrsetbits_32(GIC_SYNC_DCM, GIC_SYNC_DCM_MASK, GIC_SYNC_DCM_ON);
+}
+
+void mt_gic_sync_dcm_disable(void)
+{
+ mmio_clrsetbits_32(GIC_SYNC_DCM, GIC_SYNC_DCM_MASK, GIC_SYNC_DCM_OFF);
+}
+
+void mt_gic_init(void)
+{
+ gicv3_distif_init();
+ gicv3_cpuif_enable(plat_my_core_pos());
+ mt_gic_rdistif_init();
+
+ clear_sec_pol_ctl_en();
+}
diff --git a/plat/mediatek/mt8183/plat_pm.c b/plat/mediatek/mt8183/plat_pm.c
new file mode 100644
index 0000000..6094a17
--- /dev/null
+++ b/plat/mediatek/mt8183/plat_pm.c
@@ -0,0 +1,589 @@
+/*
+ * Copyright (c) 2019-2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* common headers */
+#include <arch_helpers.h>
+#include <assert.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <lib/psci/psci.h>
+#include <errno.h>
+
+/* mediatek platform specific headers */
+#include <platform_def.h>
+#include <scu.h>
+#include <mt_gic_v3.h>
+#include <mtk_mcdi.h>
+#include <mtk_plat_common.h>
+#include <mtgpio.h>
+#include <mtspmc.h>
+#include <plat_dcm.h>
+#include <plat_debug.h>
+#include <plat_params.h>
+#include <plat_private.h>
+#include <power_tracer.h>
+#include <pmic.h>
+#include <spm.h>
+#include <spm_suspend.h>
+#include <sspm.h>
+#include <rtc.h>
+
+/* Local power state for power domains in Run state. */
+#define MTK_LOCAL_STATE_RUN 0
+/* Local power state for retention. */
+#define MTK_LOCAL_STATE_RET 1
+/* Local power state for OFF/power-down. */
+#define MTK_LOCAL_STATE_OFF 2
+
+#if PSCI_EXTENDED_STATE_ID
+/*
+ * Macros used to parse state information from State-ID if it is using the
+ * recommended encoding for State-ID.
+ */
+#define MTK_LOCAL_PSTATE_WIDTH 4
+#define MTK_LOCAL_PSTATE_MASK ((1 << MTK_LOCAL_PSTATE_WIDTH) - 1)
+
+/* Macros to construct the composite power state */
+
+/* Make composite power state parameter till power level 0 */
+
+#define mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
+ (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT))
+
+#else /* !PSCI_EXTENDED_STATE_ID */
+
+#define mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
+ (((lvl0_state) << PSTATE_ID_SHIFT) | \
+ ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \
+ ((type) << PSTATE_TYPE_SHIFT))
+
+#endif /* PSCI_EXTENDED_STATE_ID */
+
+/* Make composite power state parameter till power level 1 */
+#define mtk_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \
+ (((lvl1_state) << MTK_LOCAL_PSTATE_WIDTH) | \
+ mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type))
+
+/* Make composite power state parameter till power level 2 */
+#define mtk_make_pwrstate_lvl2( \
+ lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \
+ (((lvl2_state) << (MTK_LOCAL_PSTATE_WIDTH * 2)) | \
+ mtk_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type))
+
+#define MTK_PWR_LVL0 0
+#define MTK_PWR_LVL1 1
+#define MTK_PWR_LVL2 2
+
+/* Macros to read the MTK power domain state */
+#define MTK_CORE_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL0]
+#define MTK_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL1]
+#define MTK_SYSTEM_PWR_STATE(state) ((PLAT_MAX_PWR_LVL > MTK_PWR_LVL1) ? \
+ (state)->pwr_domain_state[MTK_PWR_LVL2] : 0)
+
+#if PSCI_EXTENDED_STATE_ID
+/*
+ * The table storing the valid idle power states. Ensure that the
+ * array entries are populated in ascending order of state-id to
+ * enable us to use binary search during power state validation.
+ * The table must be terminated by a NULL entry.
+ */
+const unsigned int mtk_pm_idle_states[] = {
+ /* State-id - 0x001 */
+ mtk_make_pwrstate_lvl2(MTK_LOCAL_STATE_RUN, MTK_LOCAL_STATE_RUN,
+ MTK_LOCAL_STATE_RET, MTK_PWR_LVL0, PSTATE_TYPE_STANDBY),
+ /* State-id - 0x002 */
+ mtk_make_pwrstate_lvl2(MTK_LOCAL_STATE_RUN, MTK_LOCAL_STATE_RUN,
+ MTK_LOCAL_STATE_OFF, MTK_PWR_LVL0, PSTATE_TYPE_POWERDOWN),
+ /* State-id - 0x022 */
+ mtk_make_pwrstate_lvl2(MTK_LOCAL_STATE_RUN, MTK_LOCAL_STATE_OFF,
+ MTK_LOCAL_STATE_OFF, MTK_PWR_LVL1, PSTATE_TYPE_POWERDOWN),
+#if PLAT_MAX_PWR_LVL > MTK_PWR_LVL1
+ /* State-id - 0x222 */
+ mtk_make_pwrstate_lvl2(MTK_LOCAL_STATE_OFF, MTK_LOCAL_STATE_OFF,
+ MTK_LOCAL_STATE_OFF, MTK_PWR_LVL2, PSTATE_TYPE_POWERDOWN),
+#endif
+ 0,
+};
+#endif
+
+#define CPU_IDX(cluster, cpu) ((cluster << 2) + cpu)
+#define ON true
+#define OFF false
+
+/* Pause MCDI when CPU hotplug */
+static bool HP_SSPM_PAUSE;
+/* CPU Hotplug by SSPM */
+static bool HP_SSPM_CTRL = true;
+/* Turn off cluster when CPU hotplug off */
+static bool HP_CLUSTER_OFF = true;
+/* Turn off cluster when CPU MCDI off */
+static bool MCDI_C2 = true;
+/* Enable MCDI */
+static bool MCDI_SSPM = true;
+
+static uintptr_t secure_entrypoint;
+
+static void mp1_L2_desel_config(void)
+{
+ mmio_write_64(MCUCFG_BASE + 0x2200, 0x2092c820);
+
+ dsb();
+}
+
+static bool clst_single_pwr(int cluster, int cpu)
+{
+ uint32_t cpu_mask[2] = {0x00001e00, 0x000f0000};
+ uint32_t cpu_pwr_bit[] = {9, 10, 11, 12, 16, 17, 18, 19};
+ int my_idx = (cluster << 2) + cpu;
+ uint32_t pwr_stat = mmio_read_32(0x10006180);
+
+ return !(pwr_stat & (cpu_mask[cluster] & ~BIT(cpu_pwr_bit[my_idx])));
+}
+
+static bool clst_single_on(int cluster, int cpu)
+{
+ uint32_t cpu_mask[2] = {0x0f, 0xf0};
+ int my_idx = (cluster << 2) + cpu;
+ uint32_t on_stat = mcdi_avail_cpu_mask_read();
+
+ return !(on_stat & (cpu_mask[cluster] & ~BIT(my_idx)));
+}
+
+static void plat_cpu_pwrdwn_common(void)
+{
+ /* Prevent interrupts from spuriously waking up this cpu */
+ mt_gic_rdistif_save();
+ mt_gic_cpuif_disable();
+}
+
+static void plat_cpu_pwron_common(void)
+{
+ /* Enable the gic cpu interface */
+ mt_gic_cpuif_enable();
+ mt_gic_rdistif_init();
+ mt_gic_rdistif_restore();
+}
+
+static void plat_cluster_pwrdwn_common(uint64_t mpidr, int cluster)
+{
+ if (cluster > 0)
+ mt_gic_sync_dcm_enable();
+
+ /* Disable coherency */
+ plat_mtk_cci_disable();
+ disable_scu(mpidr);
+}
+
+static void plat_cluster_pwron_common(uint64_t mpidr, int cluster)
+{
+ if (cluster > 0) {
+ l2c_parity_check_setup();
+ circular_buffer_setup();
+ mp1_L2_desel_config();
+ mt_gic_sync_dcm_disable();
+ }
+
+ /* Enable coherency */
+ enable_scu(mpidr);
+ plat_mtk_cci_enable();
+ /* Enable big core dcm */
+ plat_dcm_restore_cluster_on(mpidr);
+ /* Enable rgu dcm */
+ plat_dcm_rgu_enable();
+}
+
+static void plat_cpu_standby(plat_local_state_t cpu_state)
+{
+ u_register_t scr;
+
+ scr = read_scr_el3();
+ write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
+
+ isb();
+ dsb();
+ wfi();
+
+ write_scr_el3(scr);
+}
+
+static void mcdi_ctrl_before_hotplug_on(int cluster, int cpu)
+{
+ if (!HP_SSPM_CTRL && HP_SSPM_PAUSE && MCDI_SSPM) {
+ mcdi_pause_clr(cluster, CPU_IDX(cluster, cpu), OFF);
+ mcdi_pause_set(cluster, CPU_IDX(cluster, cpu), ON);
+ }
+}
+
+static void mcdi_ctrl_before_hotplug_off(int cluster, int cpu, bool cluster_off)
+{
+ if (!HP_SSPM_CTRL && HP_SSPM_PAUSE && MCDI_SSPM)
+ mcdi_pause_set(cluster_off ? cluster : -1,
+ CPU_IDX(cluster, cpu), OFF);
+}
+
+static void mcdi_ctrl_cluster_cpu_off(int cluster, int cpu, bool cluster_off)
+{
+ if (MCDI_SSPM) {
+ sspm_set_bootaddr(secure_entrypoint);
+
+ sspm_standbywfi_irq_enable(CPU_IDX(cluster, cpu));
+
+ if (cluster_off)
+ sspm_cluster_pwr_off_notify(cluster);
+ else
+ sspm_cluster_pwr_on_notify(cluster);
+ }
+}
+
+static void mcdi_ctrl_suspend(void)
+{
+ if (MCDI_SSPM)
+ mcdi_pause();
+}
+
+static void mcdi_ctrl_resume(void)
+{
+ if (MCDI_SSPM)
+ mcdi_unpause();
+}
+
+static void hotplug_ctrl_cluster_on(int cluster, int cpu)
+{
+ if (HP_SSPM_CTRL && MCDI_SSPM) {
+ mcdi_hotplug_clr(cluster, CPU_IDX(cluster, cpu), OFF);
+ mcdi_hotplug_set(cluster, -1, ON);
+ mcdi_hotplug_wait_ack(cluster, -1, ON);
+ } else {
+ /* power on cluster */
+ if (!spm_get_cluster_powerstate(cluster))
+ spm_poweron_cluster(cluster);
+ }
+}
+
+static void hotplug_ctrl_cpu_on(int cluster, int cpu)
+{
+ if (HP_SSPM_CTRL && MCDI_SSPM)
+ mcdi_hotplug_set(cluster, CPU_IDX(cluster, cpu), ON);
+ else
+ spm_poweron_cpu(cluster, cpu);
+}
+
+static void hotplug_ctrl_cpu_on_finish(int cluster, int cpu)
+{
+ spm_disable_cpu_auto_off(cluster, cpu);
+
+ if (HP_SSPM_CTRL && MCDI_SSPM)
+ mcdi_hotplug_clr(cluster, CPU_IDX(cluster, cpu), ON);
+ else if (HP_SSPM_PAUSE && MCDI_SSPM)
+ mcdi_pause_clr(cluster, CPU_IDX(cluster, cpu), ON);
+
+ mcdi_avail_cpu_mask_set(BIT(CPU_IDX(cluster, cpu)));
+}
+
+static void hotplug_ctrl_cluster_cpu_off(int cluster, int cpu, bool cluster_off)
+{
+ mcdi_avail_cpu_mask_clr(BIT(CPU_IDX(cluster, cpu)));
+
+ if (HP_SSPM_CTRL && MCDI_SSPM) {
+ mcdi_hotplug_set(cluster_off ? cluster : -1,
+ CPU_IDX(cluster, cpu), OFF);
+ } else {
+ spm_enable_cpu_auto_off(cluster, cpu);
+
+ if (cluster_off)
+ spm_enable_cluster_auto_off(cluster);
+
+ spm_set_cpu_power_off(cluster, cpu);
+ }
+}
+
+static int plat_mtk_power_domain_on(unsigned long mpidr)
+{
+ int cpu = MPIDR_AFFLVL0_VAL(mpidr);
+ int cluster = MPIDR_AFFLVL1_VAL(mpidr);
+ int clst_pwr = spm_get_cluster_powerstate(cluster);
+ unsigned int i;
+
+ mcdi_ctrl_before_hotplug_on(cluster, cpu);
+ hotplug_ctrl_cluster_on(cluster, cpu);
+
+ if (clst_pwr == 0) {
+ /* init cpu reset arch as AARCH64 of cluster */
+ for (i = 0; i < PLATFORM_MAX_CPUS_PER_CLUSTER; i++) {
+ mcucfg_init_archstate(cluster, i, 1);
+ mcucfg_set_bootaddr(cluster, i, secure_entrypoint);
+ }
+ }
+
+ hotplug_ctrl_cpu_on(cluster, cpu);
+
+ return PSCI_E_SUCCESS;
+}
+
+static void plat_mtk_power_domain_off(const psci_power_state_t *state)
+{
+ uint64_t mpidr = read_mpidr();
+ int cpu = MPIDR_AFFLVL0_VAL(mpidr);
+ int cluster = MPIDR_AFFLVL1_VAL(mpidr);
+ const plat_local_state_t *pds = state->pwr_domain_state;
+ bool afflvl1 = (pds[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF);
+ bool cluster_off = (HP_CLUSTER_OFF && afflvl1 &&
+ clst_single_on(cluster, cpu));
+
+ plat_cpu_pwrdwn_common();
+
+ if (cluster_off)
+ plat_cluster_pwrdwn_common(mpidr, cluster);
+
+ mcdi_ctrl_before_hotplug_off(cluster, cpu, cluster_off);
+ hotplug_ctrl_cluster_cpu_off(cluster, cpu, cluster_off);
+}
+
+static void plat_mtk_power_domain_on_finish(const psci_power_state_t *state)
+{
+ uint64_t mpidr = read_mpidr();
+ int cpu = MPIDR_AFFLVL0_VAL(mpidr);
+ int cluster = MPIDR_AFFLVL1_VAL(mpidr);
+ const plat_local_state_t *pds = state->pwr_domain_state;
+ bool afflvl1 = (pds[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF);
+
+ if (afflvl1)
+ plat_cluster_pwron_common(mpidr, cluster);
+
+ plat_cpu_pwron_common();
+
+ hotplug_ctrl_cpu_on_finish(cluster, cpu);
+}
+
+static void plat_mtk_power_domain_suspend(const psci_power_state_t *state)
+{
+ uint64_t mpidr = read_mpidr();
+ int cpu = MPIDR_AFFLVL0_VAL(mpidr);
+ int cluster = MPIDR_AFFLVL1_VAL(mpidr);
+ const plat_local_state_t *pds = state->pwr_domain_state;
+ bool afflvl1 = (pds[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF);
+ bool afflvl2 = (pds[MPIDR_AFFLVL2] == MTK_LOCAL_STATE_OFF);
+ bool cluster_off = MCDI_C2 && afflvl1 && clst_single_pwr(cluster, cpu);
+
+ plat_cpu_pwrdwn_common();
+
+ plat_dcm_mcsi_a_backup();
+
+ if (cluster_off || afflvl2)
+ plat_cluster_pwrdwn_common(mpidr, cluster);
+
+ if (afflvl2) {
+ spm_data_t spm_d = { .cmd = SPM_SUSPEND };
+ uint32_t *d = (uint32_t *)&spm_d;
+ uint32_t l = sizeof(spm_d) / sizeof(uint32_t);
+
+ mcdi_ctrl_suspend();
+
+ spm_set_bootaddr(secure_entrypoint);
+
+ if (MCDI_SSPM)
+ sspm_ipi_send_non_blocking(IPI_ID_SUSPEND, d);
+
+ spm_system_suspend();
+
+ if (MCDI_SSPM)
+ while (sspm_ipi_recv_non_blocking(IPI_ID_SUSPEND, d, l))
+ ;
+
+ mt_gic_distif_save();
+ } else {
+ mcdi_ctrl_cluster_cpu_off(cluster, cpu, cluster_off);
+ }
+}
+
+static void plat_mtk_power_domain_suspend_finish(const psci_power_state_t *state)
+{
+ uint64_t mpidr = read_mpidr();
+ int cluster = MPIDR_AFFLVL1_VAL(mpidr);
+ const plat_local_state_t *pds = state->pwr_domain_state;
+ bool afflvl2 = (pds[MPIDR_AFFLVL2] == MTK_LOCAL_STATE_OFF);
+
+ if (afflvl2) {
+ spm_data_t spm_d = { .cmd = SPM_RESUME };
+ uint32_t *d = (uint32_t *)&spm_d;
+ uint32_t l = sizeof(spm_d) / sizeof(uint32_t);
+
+ mt_gic_init();
+ mt_gic_distif_restore();
+ mt_gic_rdistif_restore();
+
+ mmio_write_32(EMI_WFIFO, 0xf);
+
+ if (MCDI_SSPM)
+ sspm_ipi_send_non_blocking(IPI_ID_SUSPEND, d);
+
+ spm_system_suspend_finish();
+
+ if (MCDI_SSPM)
+ while (sspm_ipi_recv_non_blocking(IPI_ID_SUSPEND, d, l))
+ ;
+
+ mcdi_ctrl_resume();
+ } else {
+ plat_cpu_pwron_common();
+ }
+
+ plat_cluster_pwron_common(mpidr, cluster);
+
+ plat_dcm_mcsi_a_restore();
+}
+
+#if PSCI_EXTENDED_STATE_ID
+
+static int plat_mtk_validate_power_state(unsigned int power_state,
+ psci_power_state_t *req_state)
+{
+ unsigned int state_id;
+ int i;
+
+ assert(req_state);
+
+ if (!MCDI_SSPM)
+ return PSCI_E_INVALID_PARAMS;
+
+ /*
+ * Currently we are using a linear search for finding the matching
+ * entry in the idle power state array. This can be made a binary
+ * search if the number of entries justify the additional complexity.
+ */
+ for (i = 0; !!mtk_pm_idle_states[i]; i++) {
+ if (power_state == mtk_pm_idle_states[i])
+ break;
+ }
+
+ /* Return error if entry not found in the idle state array */
+ if (!mtk_pm_idle_states[i])
+ return PSCI_E_INVALID_PARAMS;
+
+ i = 0;
+ state_id = psci_get_pstate_id(power_state);
+
+ /* Parse the State ID and populate the state info parameter */
+ while (state_id) {
+ req_state->pwr_domain_state[i++] = state_id &
+ MTK_LOCAL_PSTATE_MASK;
+ state_id >>= MTK_LOCAL_PSTATE_WIDTH;
+ }
+
+ return PSCI_E_SUCCESS;
+}
+
+#else /* if !PSCI_EXTENDED_STATE_ID */
+
+static int plat_mtk_validate_power_state(unsigned int power_state,
+ psci_power_state_t *req_state)
+{
+ int pstate = psci_get_pstate_type(power_state);
+ int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
+ int i;
+
+ assert(req_state);
+
+ if (pwr_lvl > PLAT_MAX_PWR_LVL)
+ return PSCI_E_INVALID_PARAMS;
+
+ /* Sanity check the requested state */
+ if (pstate == PSTATE_TYPE_STANDBY) {
+ /*
+ * It's possible to enter standby only on power level 0
+ * Ignore any other power level.
+ */
+ if (pwr_lvl != 0)
+ return PSCI_E_INVALID_PARAMS;
+
+ req_state->pwr_domain_state[MTK_PWR_LVL0] = MTK_LOCAL_STATE_RET;
+ } else if (!MCDI_SSPM) {
+ return PSCI_E_INVALID_PARAMS;
+ } else {
+ for (i = 0; i <= pwr_lvl; i++)
+ req_state->pwr_domain_state[i] = MTK_LOCAL_STATE_OFF;
+ }
+
+ return PSCI_E_SUCCESS;
+}
+
+#endif /* PSCI_EXTENDED_STATE_ID */
+
+/*******************************************************************************
+ * MTK handlers to shutdown/reboot the system
+ ******************************************************************************/
+static void __dead2 plat_mtk_system_off(void)
+{
+ INFO("MTK System Off\n");
+
+ rtc_power_off_sequence();
+ wk_pmic_enable_sdn_delay();
+ pmic_power_off();
+
+ wfi();
+ ERROR("MTK System Off: operation not handled.\n");
+ panic();
+}
+
+static void __dead2 plat_mtk_system_reset(void)
+{
+ struct bl_aux_gpio_info *gpio_reset = plat_get_mtk_gpio_reset();
+
+ INFO("MTK System Reset\n");
+
+ mt_set_gpio_out(gpio_reset->index, gpio_reset->polarity);
+
+ wfi();
+ ERROR("MTK System Reset: operation not handled.\n");
+ panic();
+}
+
+static void plat_mtk_get_sys_suspend_power_state(psci_power_state_t *req_state)
+{
+ assert(PLAT_MAX_PWR_LVL >= 2);
+
+ for (int i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++)
+ req_state->pwr_domain_state[i] = MTK_LOCAL_STATE_OFF;
+}
+
+/*******************************************************************************
+ * MTK_platform handler called when an affinity instance is about to be turned
+ * on. The level and mpidr determine the affinity instance.
+ ******************************************************************************/
+static const plat_psci_ops_t plat_plat_pm_ops = {
+ .cpu_standby = plat_cpu_standby,
+ .pwr_domain_on = plat_mtk_power_domain_on,
+ .pwr_domain_on_finish = plat_mtk_power_domain_on_finish,
+ .pwr_domain_off = plat_mtk_power_domain_off,
+ .pwr_domain_suspend = plat_mtk_power_domain_suspend,
+ .pwr_domain_suspend_finish = plat_mtk_power_domain_suspend_finish,
+ .system_off = plat_mtk_system_off,
+ .system_reset = plat_mtk_system_reset,
+ .validate_power_state = plat_mtk_validate_power_state,
+ .get_sys_suspend_power_state = plat_mtk_get_sys_suspend_power_state
+};
+
+int plat_setup_psci_ops(uintptr_t sec_entrypoint,
+ const plat_psci_ops_t **psci_ops)
+{
+ unsigned int i;
+
+ *psci_ops = &plat_plat_pm_ops;
+ secure_entrypoint = sec_entrypoint;
+
+ /* Init cpu reset arch as AARCH64 of cluster 0 */
+ for (i = 0; i < PLATFORM_MAX_CPUS_PER_CLUSTER; i++) {
+ mcucfg_init_archstate(0, i, 1);
+ mcucfg_set_bootaddr(0, i, secure_entrypoint);
+ }
+
+ if (!check_mcdi_ctl_stat()) {
+ HP_SSPM_CTRL = false;
+ MCDI_SSPM = false;
+ }
+
+ return 0;
+}
diff --git a/plat/mediatek/mt8183/plat_topology.c b/plat/mediatek/mt8183/plat_topology.c
new file mode 100644
index 0000000..7b1dd03
--- /dev/null
+++ b/plat/mediatek/mt8183/plat_topology.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <platform_def.h>
+#include <lib/psci/psci.h>
+
+const unsigned char mtk_power_domain_tree_desc[] = {
+ /* Number of root nodes */
+ PLATFORM_SYSTEM_COUNT,
+ /* Number of children for the root node */
+ PLATFORM_CLUSTER_COUNT,
+ /* Number of children for the first cluster node */
+ PLATFORM_CLUSTER0_CORE_COUNT,
+ /* Number of children for the second cluster node */
+ PLATFORM_CLUSTER1_CORE_COUNT
+};
+
+/*******************************************************************************
+ * This function returns the MT8173 default topology tree information.
+ ******************************************************************************/
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+ return mtk_power_domain_tree_desc;
+}
+
+/*******************************************************************************
+ * This function implements a part of the critical interface between the psci
+ * generic layer and the platform that allows the former to query the platform
+ * to convert an MPIDR to a unique linear index. An error code (-1) is returned
+ * in case the MPIDR is invalid.
+ ******************************************************************************/
+int plat_core_pos_by_mpidr(u_register_t mpidr)
+{
+ unsigned int cluster_id, cpu_id;
+
+ mpidr &= MPIDR_AFFINITY_MASK;
+
+ if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK))
+ return -1;
+
+ cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
+ cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
+
+ if (cluster_id >= PLATFORM_CLUSTER_COUNT)
+ return -1;
+
+ /*
+ * Validate cpu_id by checking whether it represents a CPU in
+ * one of the two clusters present on the platform.
+ */
+ if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
+ return -1;
+
+ return (cpu_id + (cluster_id * 4));
+}
diff --git a/plat/mediatek/mt8183/platform.mk b/plat/mediatek/mt8183/platform.mk
new file mode 100644
index 0000000..a737d24
--- /dev/null
+++ b/plat/mediatek/mt8183/platform.mk
@@ -0,0 +1,90 @@
+#
+# Copyright (c) 2019-2022, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+MTK_PLAT := plat/mediatek
+MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
+
+PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
+ -I${MTK_PLAT}/drivers/uart/ \
+ -I${MTK_PLAT}/include/ \
+ -I${MTK_PLAT_SOC}/drivers/ \
+ -I${MTK_PLAT_SOC}/drivers/emi_mpu/ \
+ -I${MTK_PLAT_SOC}/drivers/devapc/ \
+ -I${MTK_PLAT_SOC}/drivers/mcdi/ \
+ -I${MTK_PLAT_SOC}/drivers/spmc/ \
+ -I${MTK_PLAT_SOC}/drivers/gpio/ \
+ -I${MTK_PLAT_SOC}/drivers/timer/ \
+ -I${MTK_PLAT_SOC}/drivers/pmic/ \
+ -I${MTK_PLAT_SOC}/drivers/spm/ \
+ -I${MTK_PLAT_SOC}/drivers/sspm/ \
+ -I${MTK_PLAT_SOC}/drivers/rtc/ \
+ -I${MTK_PLAT_SOC}/include/
+
+PLAT_BL_COMMON_SOURCES := lib/xlat_tables/aarch64/xlat_tables.c \
+ lib/xlat_tables/xlat_tables_common.c \
+ plat/common/plat_psci_common.c \
+ plat/common/aarch64/crash_console_helpers.S
+
+# Include GICv3 driver files
+include drivers/arm/gic/v3/gicv3.mk
+
+BL31_SOURCES += common/desc_image_load.c \
+ drivers/arm/cci/cci.c \
+ ${GICV3_SOURCES} \
+ drivers/delay_timer/delay_timer.c \
+ drivers/delay_timer/generic_delay_timer.c \
+ drivers/gpio/gpio.c \
+ drivers/ti/uart/aarch64/16550_console.S \
+ lib/bl_aux_params/bl_aux_params.c \
+ lib/cpus/aarch64/aem_generic.S \
+ lib/cpus/aarch64/cortex_a53.S \
+ lib/cpus/aarch64/cortex_a73.S \
+ plat/common/plat_gicv3.c \
+ ${MTK_PLAT}/common/mtk_plat_common.c \
+ ${MTK_PLAT}/common/params_setup.c \
+ ${MTK_PLAT}/drivers/pmic_wrap/pmic_wrap_init.c \
+ ${MTK_PLAT}/drivers/rtc/rtc_common.c \
+ ${MTK_PLAT}/drivers/uart/uart.c \
+ ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \
+ ${MTK_PLAT_SOC}/aarch64/platform_common.c \
+ ${MTK_PLAT_SOC}/drivers/devapc/devapc.c \
+ ${MTK_PLAT_SOC}/drivers/mcsi/mcsi.c \
+ ${MTK_PLAT_SOC}/drivers/pmic/pmic.c \
+ ${MTK_PLAT_SOC}/drivers/rtc/rtc.c \
+ ${MTK_PLAT_SOC}/drivers/mcdi/mtk_mcdi.c \
+ ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c \
+ ${MTK_PLAT_SOC}/drivers/spm/spm.c \
+ ${MTK_PLAT_SOC}/drivers/spm/spm_pmic_wrap.c \
+ ${MTK_PLAT_SOC}/drivers/spm/spm_suspend.c \
+ ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
+ ${MTK_PLAT_SOC}/drivers/timer/mt_timer.c \
+ ${MTK_PLAT_SOC}/drivers/emi_mpu/emi_mpu.c \
+ ${MTK_PLAT_SOC}/plat_pm.c \
+ ${MTK_PLAT_SOC}/plat_topology.c \
+ ${MTK_PLAT_SOC}/plat_mt_gic.c \
+ ${MTK_PLAT_SOC}/plat_dcm.c \
+ ${MTK_PLAT_SOC}/bl31_plat_setup.c \
+ ${MTK_PLAT_SOC}/plat_debug.c \
+ ${MTK_PLAT_SOC}/scu.c \
+ ${MTK_PLAT_SOC}/drivers/sspm/sspm.c
+
+# Enable workarounds for selected Cortex-A53 erratas.
+ERRATA_A53_826319 := 0
+ERRATA_A53_836870 := 1
+ERRATA_A53_855873 := 1
+
+# indicate the reset vector address can be programmed
+PROGRAMMABLE_RESET_ADDRESS := 1
+
+COLD_BOOT_SINGLE_CPU := 1
+
+MULTI_CONSOLE_API := 1
+
+MACH_MT8183 := 1
+$(eval $(call add_define,MACH_MT8183))
+
+include lib/coreboot/coreboot.mk
+
diff --git a/plat/mediatek/mt8183/scu.c b/plat/mediatek/mt8183/scu.c
new file mode 100644
index 0000000..c4f1c3f
--- /dev/null
+++ b/plat/mediatek/mt8183/scu.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <assert.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <mcucfg.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+void disable_scu(u_register_t mpidr)
+{
+ uintptr_t axi_config = 0;
+ uint32_t axi_value;
+
+ switch (mpidr & MPIDR_CLUSTER_MASK) {
+ case 0x000:
+ axi_config = (uintptr_t)&mt8183_mcucfg->mp0_axi_config;
+ axi_value = MP0_ACINACTM;
+ break;
+ case 0x100:
+ axi_config = (uintptr_t)&mt8183_mcucfg->mp2_axi_config;
+ axi_value = MP2_ACINACTM;
+ break;
+ default:
+ ERROR("%s: mpidr does not exist\n", __func__);
+ panic();
+ }
+ mmio_setbits_32(axi_config, axi_value);
+}
+
+void enable_scu(u_register_t mpidr)
+{
+ uintptr_t axi_config = 0;
+ uint32_t axi_value;
+
+ switch (mpidr & MPIDR_CLUSTER_MASK) {
+ case 0x000:
+ axi_config = (uintptr_t)&mt8183_mcucfg->mp0_axi_config;
+ axi_value = MP0_ACINACTM;
+ break;
+ case 0x100:
+ axi_config = (uintptr_t)&mt8183_mcucfg->mp2_axi_config;
+ axi_value = MP2_ACINACTM;
+ break;
+ default:
+ ERROR("%s: mpidr does not exist\n", __func__);
+ panic();
+ }
+ mmio_clrbits_32(axi_config, axi_value);
+}