diff options
Diffstat (limited to '')
| -rw-r--r-- | drivers/nxp/ddr/phy-gen2/csr.h | 151 | ||||
| -rw-r--r-- | drivers/nxp/ddr/phy-gen2/ddr4fw.h | 2897 | ||||
| -rw-r--r-- | drivers/nxp/ddr/phy-gen2/ddrphy.mk | 20 | ||||
| -rw-r--r-- | drivers/nxp/ddr/phy-gen2/input.h | 106 | ||||
| -rw-r--r-- | drivers/nxp/ddr/phy-gen2/messages.h | 2909 | ||||
| -rw-r--r-- | drivers/nxp/ddr/phy-gen2/phy.c | 2678 | ||||
| -rw-r--r-- | drivers/nxp/ddr/phy-gen2/phy.h | 334 | ||||
| -rw-r--r-- | drivers/nxp/ddr/phy-gen2/pie.h | 632 |
8 files changed, 9727 insertions, 0 deletions
diff --git a/drivers/nxp/ddr/phy-gen2/csr.h b/drivers/nxp/ddr/phy-gen2/csr.h new file mode 100644 index 0000000..ee7b4d8 --- /dev/null +++ b/drivers/nxp/ddr/phy-gen2/csr.h @@ -0,0 +1,151 @@ +/* + * Copyright 2021 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef CSR_H +#define CSR_H + +#define t_anib 0 +#define t_dbyte 0x10000 +#define t_master 0x20000 +#define t_acsm 0x40000 +#define t_initeng 0x90000 +#define t_drtub 0xc0000 +#define t_apbonly 0xd0000 +#define csr_dbyte_misc_mode_addr 0x00 +#define csr_micro_cont_mux_sel_addr 0x00 +#define csr_uct_shadow_regs 0x04 +#define csr_cal_uclk_info_addr 0x08 +#define csr_seq0bdly0_addr 0x0b +#define csr_seq0bdly1_addr 0x0c +#define csr_seq0bdly2_addr 0x0d +#define csr_seq0bdly3_addr 0x0e +#define csr_seq0bdisable_flag0_addr 0x0c +#define csr_seq0bdisable_flag1_addr 0x0d +#define csr_seq0bdisable_flag2_addr 0x0e +#define csr_seq0bdisable_flag3_addr 0x0f +#define csr_seq0bdisable_flag4_addr 0x10 +#define csr_seq0bdisable_flag5_addr 0x11 +#define csr_seq0bdisable_flag6_addr 0x12 +#define csr_seq0bdisable_flag7_addr 0x13 +#define csr_dfi_mode_addr 0x18 +#define csr_tristate_mode_ca_addr 0x19 +#define csr_dfiphyupd_addr 0x21 +#define csr_dqs_preamble_control_addr 0x24 +#define csr_master_x4config_addr 0x25 +#define csr_enable_cs_multicast_addr 0x27 +#define csr_acx4_anib_dis_addr 0x2c +#define csr_dmipin_present_addr 0x2d +#define csr_ard_ptr_init_val_addr 0x2e +#define csr_dct_write_prot 0x31 +#define csr_uct_write_only_shadow 0x32 +#define csr_uct_write_prot 0x33 +#define csr_uct_dat_write_only_shadow 0x34 +#define csr_dbyte_dll_mode_cntrl_addr 0x3a +#define csr_atx_impedance_addr 0x43 +#define csr_dq_dqs_rcv_cntrl_addr 0x43 +#define csr_cal_offsets_addr 0x45 +#define csr_tx_impedance_ctrl1_addr 0x49 +#define csr_dq_dqs_rcv_cntrl1_addr 0x4a +#define csr_tx_odt_drv_stren_addr 0x4d +#define csr_cal_drv_str0_addr 0x50 +#define csr_atx_slew_rate_addr 0x55 +#define csr_proc_odt_time_ctl_addr 0x56 +#define csr_mem_alert_control_addr 0x5b +#define csr_mem_alert_control2_addr 0x5c +#define csr_tx_slew_rate_addr 0x5f +#define csr_mem_reset_l_addr 0x60 +#define csr_dfi_camode_addr 0x75 +#define csr_dll_gain_ctl_addr 0x7c +#define csr_dll_lockparam_addr 0x7d +#define csr_ucclk_hclk_enables_addr 0x80 +#define csr_acsm_playback0x0_addr 0x80 +#define csr_acsm_playback1x0_addr 0x81 +#define csr_cal_rate_addr 0x88 +#define csr_cal_zap_addr 0x89 +#define csr_cal_misc2_addr 0x98 +#define csr_micro_reset_addr 0x99 +#define csr_dfi_rd_data_cs_dest_map_addr 0xb0 +#define csr_vref_in_global_addr 0xb2 +#define csr_dfi_wr_data_cs_dest_map_addr 0xb4 +#define csr_pll_pwr_dn_addr 0xc3 +#define csr_pll_ctrl2_addr 0xc5 +#define csr_pll_ctrl1_addr 0xc7 +#define csr_pll_test_mode_addr 0xca +#define csr_pll_ctrl4_addr 0xcc +#define csr_dfi_freq_xlat0_addr 0xf0 +#define csr_acsm_ctrl0_addr 0xf0 +#define csr_dfi_freq_ratio_addr 0xfa +#define csr_acsm_ctrl13_addr 0xfd +#define csr_tx_pre_drv_mode_lsb 8 +#define csr_tx_pre_n_lsb 4 +#define csr_tx_pre_p_lsb 0 +#define csr_atx_pre_drv_mode_lsb 8 +#define csr_atx_pre_n_lsb 4 +#define csr_atx_pre_p_lsb 0 +#define csr_wdqsextension_lsb 8 +#define csr_lp4sttc_pre_bridge_rx_en_lsb 7 +#define csr_lp4postamble_ext_lsb 6 +#define csr_lp4tgl_two_tck_tx_dqs_pre_lsb 5 +#define csr_position_dfe_init_lsb 2 +#define csr_two_tck_tx_dqs_pre_lsb 1 +#define csr_two_tck_rx_dqs_pre_lsb 0 +#define csr_dll_rx_preamble_mode_lsb 1 +#define csr_odtstren_n_lsb 6 +#define csr_drv_stren_fsdq_n_lsb 6 +#define csr_drv_stren_fsdq_p_lsb 0 +#define csr_adrv_stren_n_lsb 5 +#define csr_adrv_stren_p_lsb 0 +#define csr_cal_drv_str_pu50_lsb 4 +#define csr_cal_once_lsb 5 +#define csr_cal_interval_lsb 0 +#define csr_cal_run_lsb 4 +#define csr_global_vref_in_dac_lsb 3 +#define csr_gain_curr_adj_lsb 7 +#define csr_major_mode_dbyte_lsb 4 +#define csr_dfe_ctrl_lsb 2 +#define csr_ext_vref_range_lsb 1 +#define csr_sel_analog_vref_lsb 0 +#define csr_malertsync_bypass_lsb 0 +#define csr_ck_dis_val_lsb 2 +#define csr_ddr2tmode_lsb 1 +#define csr_dis_dyn_adr_tri_lsb 0 +#define csr_dbyte_disable_lsb 2 +#define csr_power_down_rcvr_lsb 0 +#define csr_power_down_rcvr_dqs_lsb 9 +#define csr_rx_pad_standby_en_lsb 10 +#define csr_rx_pad_standby_en_mask 0x400 +#define csr_x4tg_lsb 0 +#define csr_reset_to_micro_mask 0x8 +#define csr_protect_mem_reset_mask 0x2 +#define csr_stall_to_micro_mask 0x1 +#define uct_write_prot_shadow_mask 0x1 +#define csr_acsm_par_mode_mask 0x4000 +#define csr_acsm_cke_enb_lsb 0 +#define csr_dfiphyupd_threshold_lsb 8 +#define csr_dfiphyupd_threshold_msb 11 +#define csr_dfiphyupd_threshold_mask 0xf00 +#define csr_dfi_rd_destm0_lsb 0 +#define csr_dfi_rd_destm1_lsb 2 +#define csr_dfi_rd_destm2_lsb 4 +#define csr_dfi_rd_destm3_lsb 6 +#define csr_dfi_wr_destm0_lsb 0 +#define csr_dfi_wr_destm1_lsb 2 +#define csr_dfi_wr_destm2_lsb 4 +#define csr_dfi_wr_destm3_lsb 6 +#define csr_acsm_2t_mode_mask 0x40 +#define csr_cal_misc2_err_dis 13 +#define csr_cal_offset_pdc_lsb 6 +#define csr_cal_offset_pdc_msb 9 +#define csr_cal_offset_pdc_mask 0xe0 +#define csr_cal_drv_pdth_mask 0x3c0 + + +struct impedance_mapping { + int ohm; + int code; +}; + +#endif diff --git a/drivers/nxp/ddr/phy-gen2/ddr4fw.h b/drivers/nxp/ddr/phy-gen2/ddr4fw.h new file mode 100644 index 0000000..f17f2e7 --- /dev/null +++ b/drivers/nxp/ddr/phy-gen2/ddr4fw.h @@ -0,0 +1,2897 @@ +/* + * Copyright 2021 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef DDR4FW +#define DDR4FW + +#define PHY_GEN2_MAX_IMAGE_SIZE 32768 +#define PHY_GEN2_IMEM_ADDR 0x50000 +#define PHY_GEN2_DMEM_ADDR 0x54000 + +struct ddr4u1d { + uint8_t reserved00; + uint8_t msg_misc; + uint16_t pmu_revision; + uint8_t pstate; + uint8_t pll_bypass_en; + uint16_t dramfreq; + uint8_t dfi_freq_ratio; + uint8_t bpznres_val; + uint8_t phy_odt_impedance; + uint8_t phy_drv_impedance; + uint8_t phy_vref; + uint8_t dram_type; + uint8_t disabled_dbyte; + uint8_t enabled_dqs; + uint8_t cs_present; + uint8_t cs_present_d0; + uint8_t cs_present_d1; + uint8_t addr_mirror; + uint8_t cs_test_fail; + uint8_t phy_cfg; + uint16_t sequence_ctrl; + uint8_t hdt_ctrl; + uint8_t reserved19[0x1B - 0x19]; + uint8_t share2dvref_result; + uint8_t reserved1c[0x22 - 0x1c]; + uint16_t phy_config_override; + uint8_t dfimrlmargin; + int8_t cdd_rr_3_2; + int8_t cdd_rr_3_1; + int8_t cdd_rr_3_0; + int8_t cdd_rr_2_3; + int8_t cdd_rr_2_1; + int8_t cdd_rr_2_0; + int8_t cdd_rr_1_3; + int8_t cdd_rr_1_2; + int8_t cdd_rr_1_0; + int8_t cdd_rr_0_3; + int8_t cdd_rr_0_2; + int8_t cdd_rr_0_1; + int8_t cdd_ww_3_2; + int8_t cdd_ww_3_1; + int8_t cdd_ww_3_0; + int8_t cdd_ww_2_3; + int8_t cdd_ww_2_1; + int8_t cdd_ww_2_0; + int8_t cdd_ww_1_3; + int8_t cdd_ww_1_2; + int8_t cdd_ww_1_0; + int8_t cdd_ww_0_3; + int8_t cdd_ww_0_2; + int8_t cdd_ww_0_1; + int8_t cdd_rw_3_3; + int8_t cdd_rw_3_2; + int8_t cdd_rw_3_1; + int8_t cdd_rw_3_0; + int8_t cdd_rw_2_3; + int8_t cdd_rw_2_2; + int8_t cdd_rw_2_1; + int8_t cdd_rw_2_0; + int8_t cdd_rw_1_3; + int8_t cdd_rw_1_2; + int8_t cdd_rw_1_1; + int8_t cdd_rw_1_0; + int8_t cdd_rw_0_3; + int8_t cdd_rw_0_2; + int8_t cdd_rw_0_1; + int8_t cdd_rw_0_0; + int8_t cdd_wr_3_3; + int8_t cdd_wr_3_2; + int8_t cdd_wr_3_1; + int8_t cdd_wr_3_0; + int8_t cdd_wr_2_3; + int8_t cdd_wr_2_2; + int8_t cdd_wr_2_1; + int8_t cdd_wr_2_0; + int8_t cdd_wr_1_3; + int8_t cdd_wr_1_2; + int8_t cdd_wr_1_1; + int8_t cdd_wr_1_0; + int8_t cdd_wr_0_3; + int8_t cdd_wr_0_2; + int8_t cdd_wr_0_1; + int8_t cdd_wr_0_0; + uint8_t reserved5d; + uint16_t mr0; + uint16_t mr1; + uint16_t mr2; + uint16_t mr3; + uint16_t mr4; + uint16_t mr5; + uint16_t mr6; + uint8_t x16present; + uint8_t cs_setup_gddec; + uint16_t rtt_nom_wr_park0; + uint16_t rtt_nom_wr_park1; + uint16_t rtt_nom_wr_park2; + uint16_t rtt_nom_wr_park3; + uint16_t rtt_nom_wr_park4; + uint16_t rtt_nom_wr_park5; + uint16_t rtt_nom_wr_park6; + uint16_t rtt_nom_wr_park7; + uint8_t acsm_odt_ctrl0; + uint8_t acsm_odt_ctrl1; + uint8_t acsm_odt_ctrl2; + uint8_t acsm_odt_ctrl3; + uint8_t acsm_odt_ctrl4; + uint8_t acsm_odt_ctrl5; + uint8_t acsm_odt_ctrl6; + uint8_t acsm_odt_ctrl7; + uint8_t vref_dq_r0nib0; + uint8_t vref_dq_r0nib1; + uint8_t vref_dq_r0nib2; + uint8_t vref_dq_r0nib3; + uint8_t vref_dq_r0nib4; + uint8_t vref_dq_r0nib5; + uint8_t vref_dq_r0nib6; + uint8_t vref_dq_r0nib7; + uint8_t vref_dq_r0nib8; + uint8_t vref_dq_r0nib9; + uint8_t vref_dq_r0nib10; + uint8_t vref_dq_r0nib11; + uint8_t vref_dq_r0nib12; + uint8_t vref_dq_r0nib13; + uint8_t vref_dq_r0nib14; + uint8_t vref_dq_r0nib15; + uint8_t vref_dq_r0nib16; + uint8_t vref_dq_r0nib17; + uint8_t vref_dq_r0nib18; + uint8_t vref_dq_r0nib19; + uint8_t vref_dq_r1nib0; + uint8_t vref_dq_r1nib1; + uint8_t vref_dq_r1nib2; + uint8_t vref_dq_r1nib3; + uint8_t vref_dq_r1nib4; + uint8_t vref_dq_r1nib5; + uint8_t vref_dq_r1nib6; + uint8_t vref_dq_r1nib7; + uint8_t vref_dq_r1nib8; + uint8_t vref_dq_r1nib9; + uint8_t vref_dq_r1nib10; + uint8_t vref_dq_r1nib11; + uint8_t vref_dq_r1nib12; + uint8_t vref_dq_r1nib13; + uint8_t vref_dq_r1nib14; + uint8_t vref_dq_r1nib15; + uint8_t vref_dq_r1nib16; + uint8_t vref_dq_r1nib17; + uint8_t vref_dq_r1nib18; + uint8_t vref_dq_r1nib19; + uint8_t vref_dq_r2nib0; + uint8_t vref_dq_r2nib1; + uint8_t vref_dq_r2nib2; + uint8_t vref_dq_r2nib3; + uint8_t vref_dq_r2nib4; + uint8_t vref_dq_r2nib5; + uint8_t vref_dq_r2nib6; + uint8_t vref_dq_r2nib7; + uint8_t vref_dq_r2nib8; + uint8_t vref_dq_r2nib9; + uint8_t vref_dq_r2nib10; + uint8_t vref_dq_r2nib11; + uint8_t vref_dq_r2nib12; + uint8_t vref_dq_r2nib13; + uint8_t vref_dq_r2nib14; + uint8_t vref_dq_r2nib15; + uint8_t vref_dq_r2nib16; + uint8_t vref_dq_r2nib17; + uint8_t vref_dq_r2nib18; + uint8_t vref_dq_r2nib19; + uint8_t vref_dq_r3nib0; + uint8_t vref_dq_r3nib1; + uint8_t vref_dq_r3nib2; + uint8_t vref_dq_r3nib3; + uint8_t vref_dq_r3nib4; + uint8_t vref_dq_r3nib5; + uint8_t vref_dq_r3nib6; + uint8_t vref_dq_r3nib7; + uint8_t vref_dq_r3nib8; + uint8_t vref_dq_r3nib9; + uint8_t vref_dq_r3nib10; + uint8_t vref_dq_r3nib11; + uint8_t vref_dq_r3nib12; + uint8_t vref_dq_r3nib13; + uint8_t vref_dq_r3nib14; + uint8_t vref_dq_r3nib15; + uint8_t vref_dq_r3nib16; + uint8_t vref_dq_r3nib17; + uint8_t vref_dq_r3nib18; + uint8_t vref_dq_r3nib19; + uint8_t reserved_d6[0x3f6 - 0xd6]; + uint16_t alt_cas_l; + uint8_t alt_wcas_l; + uint8_t d4misc; +} __packed; + +struct ddr4u2d { + uint8_t reserved00; + uint8_t msg_misc; + uint16_t pmu_revision; + uint8_t pstate; + uint8_t pll_bypass_en; + uint16_t dramfreq; + uint8_t dfi_freq_ratio; + uint8_t bpznres_val; + uint8_t phy_odt_impedance; + uint8_t phy_drv_impedance; + uint8_t phy_vref; + uint8_t dram_type; + uint8_t disabled_dbyte; + uint8_t enabled_dqs; + uint8_t cs_present; + uint8_t cs_present_d0; + uint8_t cs_present_d1; + uint8_t addr_mirror; + uint8_t cs_test_fail; + uint8_t phy_cfg; + uint16_t sequence_ctrl; + uint8_t hdt_ctrl; + uint8_t rx2d_train_opt; + uint8_t tx2d_train_opt; + uint8_t share2dvref_result; + uint8_t delay_weight2d; + uint8_t voltage_weight2d; + uint8_t reserved1e[0x22 - 0x1e]; + uint16_t phy_config_override; + uint8_t dfimrlmargin; + uint8_t r0_rx_clk_dly_margin; + uint8_t r0_vref_dac_margin; + uint8_t r0_tx_dq_dly_margin; + uint8_t r0_device_vref_margin; + uint8_t reserved29[0x33 - 0x29]; + uint8_t r1_rx_clk_dly_margin; + uint8_t r1_vref_dac_margin; + uint8_t r1_tx_dq_dly_margin; + uint8_t r1_device_vref_margin; + uint8_t reserved37[0x41 - 0x37]; + uint8_t r2_rx_clk_dly_margin; + uint8_t r2_vref_dac_margin; + uint8_t r2_tx_dq_dly_margin; + uint8_t r2_device_vref_margin; + uint8_t reserved45[0x4f - 0x45]; + uint8_t r3_rx_clk_dly_margin; + uint8_t r3_vref_dac_margin; + uint8_t r3_tx_dq_dly_margin; + uint8_t r3_device_vref_margin; + uint8_t reserved53[0x5e - 0x53]; + uint16_t mr0; + uint16_t mr1; + uint16_t mr2; + uint16_t mr3; + uint16_t mr4; + uint16_t mr5; + uint16_t mr6; + uint8_t x16present; + uint8_t cs_setup_gddec; + uint16_t rtt_nom_wr_park0; + uint16_t rtt_nom_wr_park1; + uint16_t rtt_nom_wr_park2; + uint16_t rtt_nom_wr_park3; + uint16_t rtt_nom_wr_park4; + uint16_t rtt_nom_wr_park5; + uint16_t rtt_nom_wr_park6; + uint16_t rtt_nom_wr_park7; + uint8_t acsm_odt_ctrl0; + uint8_t acsm_odt_ctrl1; + uint8_t acsm_odt_ctrl2; + uint8_t acsm_odt_ctrl3; + uint8_t acsm_odt_ctrl4; + uint8_t acsm_odt_ctrl5; + uint8_t acsm_odt_ctrl6; + uint8_t acsm_odt_ctrl7; + uint8_t vref_dq_r0nib0; + uint8_t vref_dq_r0nib1; + uint8_t vref_dq_r0nib2; + uint8_t vref_dq_r0nib3; + uint8_t vref_dq_r0nib4; + uint8_t vref_dq_r0nib5; + uint8_t vref_dq_r0nib6; + uint8_t vref_dq_r0nib7; + uint8_t vref_dq_r0nib8; + uint8_t vref_dq_r0nib9; + uint8_t vref_dq_r0nib10; + uint8_t vref_dq_r0nib11; + uint8_t vref_dq_r0nib12; + uint8_t vref_dq_r0nib13; + uint8_t vref_dq_r0nib14; + uint8_t vref_dq_r0nib15; + uint8_t vref_dq_r0nib16; + uint8_t vref_dq_r0nib17; + uint8_t vref_dq_r0nib18; + uint8_t vref_dq_r0nib19; + uint8_t vref_dq_r1nib0; + uint8_t vref_dq_r1nib1; + uint8_t vref_dq_r1nib2; + uint8_t vref_dq_r1nib3; + uint8_t vref_dq_r1nib4; + uint8_t vref_dq_r1nib5; + uint8_t vref_dq_r1nib6; + uint8_t vref_dq_r1nib7; + uint8_t vref_dq_r1nib8; + uint8_t vref_dq_r1nib9; + uint8_t vref_dq_r1nib10; + uint8_t vref_dq_r1nib11; + uint8_t vref_dq_r1nib12; + uint8_t vref_dq_r1nib13; + uint8_t vref_dq_r1nib14; + uint8_t vref_dq_r1nib15; + uint8_t vref_dq_r1nib16; + uint8_t vref_dq_r1nib17; + uint8_t vref_dq_r1nib18; + uint8_t vref_dq_r1nib19; + uint8_t vref_dq_r2nib0; + uint8_t vref_dq_r2nib1; + uint8_t vref_dq_r2nib2; + uint8_t vref_dq_r2nib3; + uint8_t vref_dq_r2nib4; + uint8_t vref_dq_r2nib5; + uint8_t vref_dq_r2nib6; + uint8_t vref_dq_r2nib7; + uint8_t vref_dq_r2nib8; + uint8_t vref_dq_r2nib9; + uint8_t vref_dq_r2nib10; + uint8_t vref_dq_r2nib11; + uint8_t vref_dq_r2nib12; + uint8_t vref_dq_r2nib13; + uint8_t vref_dq_r2nib14; + uint8_t vref_dq_r2nib15; + uint8_t vref_dq_r2nib16; + uint8_t vref_dq_r2nib17; + uint8_t vref_dq_r2nib18; + uint8_t vref_dq_r2nib19; + uint8_t vref_dq_r3nib0; + uint8_t vref_dq_r3nib1; + uint8_t vref_dq_r3nib2; + uint8_t vref_dq_r3nib3; + uint8_t vref_dq_r3nib4; + uint8_t vref_dq_r3nib5; + uint8_t vref_dq_r3nib6; + uint8_t vref_dq_r3nib7; + uint8_t vref_dq_r3nib8; + uint8_t vref_dq_r3nib9; + uint8_t vref_dq_r3nib10; + uint8_t vref_dq_r3nib11; + uint8_t vref_dq_r3nib12; + uint8_t vref_dq_r3nib13; + uint8_t vref_dq_r3nib14; + uint8_t vref_dq_r3nib15; + uint8_t vref_dq_r3nib16; + uint8_t vref_dq_r3nib17; + uint8_t vref_dq_r3nib18; + uint8_t vref_dq_r3nib19; + uint8_t reserved_d6[0x3f6 - 0xd6]; + uint16_t alt_cas_l; + uint8_t alt_wcas_l; + uint8_t d4misc; +} __packed; + +struct ddr4r1d { + uint8_t reserved00; + uint8_t msg_misc; + uint16_t pmu_revision; + uint8_t pstate; + uint8_t pll_bypass_en; + uint16_t dramfreq; + uint8_t dfi_freq_ratio; + uint8_t bpznres_val; + uint8_t phy_odt_impedance; + uint8_t phy_drv_impedance; + uint8_t phy_vref; + uint8_t dram_type; + uint8_t disabled_dbyte; + uint8_t enabled_dqs; + uint8_t cs_present; + uint8_t cs_present_d0; + uint8_t cs_present_d1; + uint8_t addr_mirror; + uint8_t cs_test_fail; + uint8_t phy_cfg; + uint16_t sequence_ctrl; + uint8_t hdt_ctrl; + uint8_t reserved19[0x22 - 0x19]; + uint16_t phy_config_override; + uint8_t dfimrlmargin; + int8_t cdd_rr_3_2; + int8_t cdd_rr_3_1; + int8_t cdd_rr_3_0; + int8_t cdd_rr_2_3; + int8_t cdd_rr_2_1; + int8_t cdd_rr_2_0; + int8_t cdd_rr_1_3; + int8_t cdd_rr_1_2; + int8_t cdd_rr_1_0; + int8_t cdd_rr_0_3; + int8_t cdd_rr_0_2; + int8_t cdd_rr_0_1; + int8_t cdd_ww_3_2; + int8_t cdd_ww_3_1; + int8_t cdd_ww_3_0; + int8_t cdd_ww_2_3; + int8_t cdd_ww_2_1; + int8_t cdd_ww_2_0; + int8_t cdd_ww_1_3; + int8_t cdd_ww_1_2; + int8_t cdd_ww_1_0; + int8_t cdd_ww_0_3; + int8_t cdd_ww_0_2; + int8_t cdd_ww_0_1; + int8_t cdd_rw_3_3; + int8_t cdd_rw_3_2; + int8_t cdd_rw_3_1; + int8_t cdd_rw_3_0; + int8_t cdd_rw_2_3; + int8_t cdd_rw_2_2; + int8_t cdd_rw_2_1; + int8_t cdd_rw_2_0; + int8_t cdd_rw_1_3; + int8_t cdd_rw_1_2; + int8_t cdd_rw_1_1; + int8_t cdd_rw_1_0; + int8_t cdd_rw_0_3; + int8_t cdd_rw_0_2; + int8_t cdd_rw_0_1; + int8_t cdd_rw_0_0; + int8_t cdd_wr_3_3; + int8_t cdd_wr_3_2; + int8_t cdd_wr_3_1; + int8_t cdd_wr_3_0; + int8_t cdd_wr_2_3; + int8_t cdd_wr_2_2; + int8_t cdd_wr_2_1; + int8_t cdd_wr_2_0; + int8_t cdd_wr_1_3; + int8_t cdd_wr_1_2; + int8_t cdd_wr_1_1; + int8_t cdd_wr_1_0; + int8_t cdd_wr_0_3; + int8_t cdd_wr_0_2; + int8_t cdd_wr_0_1; + int8_t cdd_wr_0_0; + uint8_t reserved5d; + uint16_t mr0; + uint16_t mr1; + uint16_t mr2; + uint16_t mr3; + uint16_t mr4; + uint16_t mr5; + uint16_t mr6; + uint8_t x16present; + uint8_t cs_setup_gddec; + uint16_t rtt_nom_wr_park0; + uint16_t rtt_nom_wr_park1; + uint16_t rtt_nom_wr_park2; + uint16_t rtt_nom_wr_park3; + uint16_t rtt_nom_wr_park4; + uint16_t rtt_nom_wr_park5; + uint16_t rtt_nom_wr_park6; + uint16_t rtt_nom_wr_park7; + uint8_t acsm_odt_ctrl0; + uint8_t acsm_odt_ctrl1; + uint8_t acsm_odt_ctrl2; + uint8_t acsm_odt_ctrl3; + uint8_t acsm_odt_ctrl4; + uint8_t acsm_odt_ctrl5; + uint8_t acsm_odt_ctrl6; + uint8_t acsm_odt_ctrl7; + uint8_t vref_dq_r0nib0; + uint8_t vref_dq_r0nib1; + uint8_t vref_dq_r0nib2; + uint8_t vref_dq_r0nib3; + uint8_t vref_dq_r0nib4; + uint8_t vref_dq_r0nib5; + uint8_t vref_dq_r0nib6; + uint8_t vref_dq_r0nib7; + uint8_t vref_dq_r0nib8; + uint8_t vref_dq_r0nib9; + uint8_t vref_dq_r0nib10; + uint8_t vref_dq_r0nib11; + uint8_t vref_dq_r0nib12; + uint8_t vref_dq_r0nib13; + uint8_t vref_dq_r0nib14; + uint8_t vref_dq_r0nib15; + uint8_t vref_dq_r0nib16; + uint8_t vref_dq_r0nib17; + uint8_t vref_dq_r0nib18; + uint8_t vref_dq_r0nib19; + uint8_t vref_dq_r1nib0; + uint8_t vref_dq_r1nib1; + uint8_t vref_dq_r1nib2; + uint8_t vref_dq_r1nib3; + uint8_t vref_dq_r1nib4; + uint8_t vref_dq_r1nib5; + uint8_t vref_dq_r1nib6; + uint8_t vref_dq_r1nib7; + uint8_t vref_dq_r1nib8; + uint8_t vref_dq_r1nib9; + uint8_t vref_dq_r1nib10; + uint8_t vref_dq_r1nib11; + uint8_t vref_dq_r1nib12; + uint8_t vref_dq_r1nib13; + uint8_t vref_dq_r1nib14; + uint8_t vref_dq_r1nib15; + uint8_t vref_dq_r1nib16; + uint8_t vref_dq_r1nib17; + uint8_t vref_dq_r1nib18; + uint8_t vref_dq_r1nib19; + uint8_t vref_dq_r2nib0; + uint8_t vref_dq_r2nib1; + uint8_t vref_dq_r2nib2; + uint8_t vref_dq_r2nib3; + uint8_t vref_dq_r2nib4; + uint8_t vref_dq_r2nib5; + uint8_t vref_dq_r2nib6; + uint8_t vref_dq_r2nib7; + uint8_t vref_dq_r2nib8; + uint8_t vref_dq_r2nib9; + uint8_t vref_dq_r2nib10; + uint8_t vref_dq_r2nib11; + uint8_t vref_dq_r2nib12; + uint8_t vref_dq_r2nib13; + uint8_t vref_dq_r2nib14; + uint8_t vref_dq_r2nib15; + uint8_t vref_dq_r2nib16; + uint8_t vref_dq_r2nib17; + uint8_t vref_dq_r2nib18; + uint8_t vref_dq_r2nib19; + uint8_t vref_dq_r3nib0; + uint8_t vref_dq_r3nib1; + uint8_t vref_dq_r3nib2; + uint8_t vref_dq_r3nib3; + uint8_t vref_dq_r3nib4; + uint8_t vref_dq_r3nib5; + uint8_t vref_dq_r3nib6; + uint8_t vref_dq_r3nib7; + uint8_t vref_dq_r3nib8; + uint8_t vref_dq_r3nib9; + uint8_t vref_dq_r3nib10; + uint8_t vref_dq_r3nib11; + uint8_t vref_dq_r3nib12; + uint8_t vref_dq_r3nib13; + uint8_t vref_dq_r3nib14; + uint8_t vref_dq_r3nib15; + uint8_t vref_dq_r3nib16; + uint8_t vref_dq_r3nib17; + uint8_t vref_dq_r3nib18; + uint8_t vref_dq_r3nib19; + uint8_t f0rc00_d0; + uint8_t f0rc01_d0; + uint8_t f0rc02_d0; + uint8_t f0rc03_d0; + uint8_t f0rc04_d0; + uint8_t f0rc05_d0; + uint8_t f0rc06_d0; + uint8_t f0rc07_d0; + uint8_t f0rc08_d0; + uint8_t f0rc09_d0; + uint8_t f0rc0a_d0; + uint8_t f0rc0b_d0; + uint8_t f0rc0c_d0; + uint8_t f0rc0d_d0; + uint8_t f0rc0e_d0; + uint8_t f0rc0f_d0; + uint8_t f0rc1x_d0; + uint8_t f0rc2x_d0; + uint8_t f0rc3x_d0; + uint8_t f0rc4x_d0; + uint8_t f0rc5x_d0; + uint8_t f0rc6x_d0; + uint8_t f0rc7x_d0; + uint8_t f0rc8x_d0; + uint8_t f0rc9x_d0; + uint8_t f0rcax_d0; + uint8_t f0rcbx_d0; + uint8_t f1rc00_d0; + uint8_t f1rc01_d0; + uint8_t f1rc02_d0; + uint8_t f1rc03_d0; + uint8_t f1rc04_d0; + uint8_t f1rc05_d0; + uint8_t f1rc06_d0; + uint8_t f1rc07_d0; + uint8_t f1rc08_d0; + uint8_t f1rc09_d0; + uint8_t f1rc0a_d0; + uint8_t f1rc0b_d0; + uint8_t f1rc0c_d0; + uint8_t f1rc0d_d0; + uint8_t f1rc0e_d0; + uint8_t f1rc0f_d0; + uint8_t f1rc1x_d0; + uint8_t f1rc2x_d0; + uint8_t f1rc3x_d0; + uint8_t f1rc4x_d0; + uint8_t f1rc5x_d0; + uint8_t f1rc6x_d0; + uint8_t f1rc7x_d0; + uint8_t f1rc8x_d0; + uint8_t f1rc9x_d0; + uint8_t f1rcax_d0; + uint8_t f1rcbx_d0; + uint8_t f0rc00_d1; + uint8_t f0rc01_d1; + uint8_t f0rc02_d1; + uint8_t f0rc03_d1; + uint8_t f0rc04_d1; + uint8_t f0rc05_d1; + uint8_t f0rc06_d1; + uint8_t f0rc07_d1; + uint8_t f0rc08_d1; + uint8_t f0rc09_d1; + uint8_t f0rc0a_d1; + uint8_t f0rc0b_d1; + uint8_t f0rc0c_d1; + uint8_t f0rc0d_d1; + uint8_t f0rc0e_d1; + uint8_t f0rc0f_d1; + uint8_t f0rc1x_d1; + uint8_t f0rc2x_d1; + uint8_t f0rc3x_d1; + uint8_t f0rc4x_d1; + uint8_t f0rc5x_d1; + uint8_t f0rc6x_d1; + uint8_t f0rc7x_d1; + uint8_t f0rc8x_d1; + uint8_t f0rc9x_d1; + uint8_t f0rcax_d1; + uint8_t f0rcbx_d1; + uint8_t f1rc00_d1; + uint8_t f1rc01_d1; + uint8_t f1rc02_d1; + uint8_t f1rc03_d1; + uint8_t f1rc04_d1; + uint8_t f1rc05_d1; + uint8_t f1rc06_d1; + uint8_t f1rc07_d1; + uint8_t f1rc08_d1; + uint8_t f1rc09_d1; + uint8_t f1rc0a_d1; + uint8_t f1rc0b_d1; + uint8_t f1rc0c_d1; + uint8_t f1rc0d_d1; + uint8_t f1rc0e_d1; + uint8_t f1rc0f_d1; + uint8_t f1rc1x_d1; + uint8_t f1rc2x_d1; + uint8_t f1rc3x_d1; + uint8_t f1rc4x_d1; + uint8_t f1rc5x_d1; + uint8_t f1rc6x_d1; + uint8_t f1rc7x_d1; + uint8_t f1rc8x_d1; + uint8_t f1rc9x_d1; + uint8_t f1rcax_d1; + uint8_t f1rcbx_d1; + uint8_t reserved142[0x3f6 - 0x142]; + uint16_t alt_cas_l; + uint8_t alt_wcas_l; + uint8_t d4misc; +} __packed; + +struct ddr4r2d { + uint8_t reserved00; + uint8_t msg_misc; + uint16_t pmu_revision; + uint8_t pstate; + uint8_t pll_bypass_en; + uint16_t dramfreq; + uint8_t dfi_freq_ratio; + uint8_t bpznres_val; + uint8_t phy_odt_impedance; + uint8_t phy_drv_impedance; + uint8_t phy_vref; + uint8_t dram_type; + uint8_t disabled_dbyte; + uint8_t enabled_dqs; + uint8_t cs_present; + uint8_t cs_present_d0; + uint8_t cs_present_d1; + uint8_t addr_mirror; + uint8_t cs_test_fail; + uint8_t phy_cfg; + uint16_t sequence_ctrl; + uint8_t hdt_ctrl; + uint8_t rx2d_train_opt; + uint8_t tx2d_train_opt; + uint8_t share2dvref_result; + uint8_t delay_weight2d; + uint8_t voltage_weight2d; + uint8_t reserved1e[0x22-0x1e]; + uint16_t phy_config_override; + uint8_t dfimrlmargin; + uint8_t r0_rx_clk_dly_margin; + uint8_t r0_vref_dac_margin; + uint8_t r0_tx_dq_dly_margin; + uint8_t r0_device_vref_margin; + uint8_t reserved29[0x33-0x29]; + uint8_t r1_rx_clk_dly_margin; + uint8_t r1_vref_dac_margin; + uint8_t r1_tx_dq_dly_margin; + uint8_t r1_device_vref_margin; + uint8_t reserved37[0x41-0x37]; + uint8_t r2_rx_clk_dly_margin; + uint8_t r2_vref_dac_margin; + uint8_t r2_tx_dq_dly_margin; + uint8_t r2_device_vref_margin; + uint8_t reserved45[0x4f - 0x45]; + uint8_t r3_rx_clk_dly_margin; + uint8_t r3_vref_dac_margin; + uint8_t r3_tx_dq_dly_margin; + uint8_t r3_device_vref_margin; + uint8_t reserved53[0x5e - 0x53]; + uint16_t mr0; + uint16_t mr1; + uint16_t mr2; + uint16_t mr3; + uint16_t mr4; + uint16_t mr5; + uint16_t mr6; + uint8_t x16present; + uint8_t cs_setup_gddec; + uint16_t rtt_nom_wr_park0; + uint16_t rtt_nom_wr_park1; + uint16_t rtt_nom_wr_park2; + uint16_t rtt_nom_wr_park3; + uint16_t rtt_nom_wr_park4; + uint16_t rtt_nom_wr_park5; + uint16_t rtt_nom_wr_park6; + uint16_t rtt_nom_wr_park7; + uint8_t acsm_odt_ctrl0; + uint8_t acsm_odt_ctrl1; + uint8_t acsm_odt_ctrl2; + uint8_t acsm_odt_ctrl3; + uint8_t acsm_odt_ctrl4; + uint8_t acsm_odt_ctrl5; + uint8_t acsm_odt_ctrl6; + uint8_t acsm_odt_ctrl7; + uint8_t vref_dq_r0nib0; + uint8_t vref_dq_r0nib1; + uint8_t vref_dq_r0nib2; + uint8_t vref_dq_r0nib3; + uint8_t vref_dq_r0nib4; + uint8_t vref_dq_r0nib5; + uint8_t vref_dq_r0nib6; + uint8_t vref_dq_r0nib7; + uint8_t vref_dq_r0nib8; + uint8_t vref_dq_r0nib9; + uint8_t vref_dq_r0nib10; + uint8_t vref_dq_r0nib11; + uint8_t vref_dq_r0nib12; + uint8_t vref_dq_r0nib13; + uint8_t vref_dq_r0nib14; + uint8_t vref_dq_r0nib15; + uint8_t vref_dq_r0nib16; + uint8_t vref_dq_r0nib17; + uint8_t vref_dq_r0nib18; + uint8_t vref_dq_r0nib19; + uint8_t vref_dq_r1nib0; + uint8_t vref_dq_r1nib1; + uint8_t vref_dq_r1nib2; + uint8_t vref_dq_r1nib3; + uint8_t vref_dq_r1nib4; + uint8_t vref_dq_r1nib5; + uint8_t vref_dq_r1nib6; + uint8_t vref_dq_r1nib7; + uint8_t vref_dq_r1nib8; + uint8_t vref_dq_r1nib9; + uint8_t vref_dq_r1nib10; + uint8_t vref_dq_r1nib11; + uint8_t vref_dq_r1nib12; + uint8_t vref_dq_r1nib13; + uint8_t vref_dq_r1nib14; + uint8_t vref_dq_r1nib15; + uint8_t vref_dq_r1nib16; + uint8_t vref_dq_r1nib17; + uint8_t vref_dq_r1nib18; + uint8_t vref_dq_r1nib19; + uint8_t vref_dq_r2nib0; + uint8_t vref_dq_r2nib1; + uint8_t vref_dq_r2nib2; + uint8_t vref_dq_r2nib3; + uint8_t vref_dq_r2nib4; + uint8_t vref_dq_r2nib5; + uint8_t vref_dq_r2nib6; + uint8_t vref_dq_r2nib7; + uint8_t vref_dq_r2nib8; + uint8_t vref_dq_r2nib9; + uint8_t vref_dq_r2nib10; + uint8_t vref_dq_r2nib11; + uint8_t vref_dq_r2nib12; + uint8_t vref_dq_r2nib13; + uint8_t vref_dq_r2nib14; + uint8_t vref_dq_r2nib15; + uint8_t vref_dq_r2nib16; + uint8_t vref_dq_r2nib17; + uint8_t vref_dq_r2nib18; + uint8_t vref_dq_r2nib19; + uint8_t vref_dq_r3nib0; + uint8_t vref_dq_r3nib1; + uint8_t vref_dq_r3nib2; + uint8_t vref_dq_r3nib3; + uint8_t vref_dq_r3nib4; + uint8_t vref_dq_r3nib5; + uint8_t vref_dq_r3nib6; + uint8_t vref_dq_r3nib7; + uint8_t vref_dq_r3nib8; + uint8_t vref_dq_r3nib9; + uint8_t vref_dq_r3nib10; + uint8_t vref_dq_r3nib11; + uint8_t vref_dq_r3nib12; + uint8_t vref_dq_r3nib13; + uint8_t vref_dq_r3nib14; + uint8_t vref_dq_r3nib15; + uint8_t vref_dq_r3nib16; + uint8_t vref_dq_r3nib17; + uint8_t vref_dq_r3nib18; + uint8_t vref_dq_r3nib19; + uint8_t f0rc00_d0; + uint8_t f0rc01_d0; + uint8_t f0rc02_d0; + uint8_t f0rc03_d0; + uint8_t f0rc04_d0; + uint8_t f0rc05_d0; + uint8_t f0rc06_d0; + uint8_t f0rc07_d0; + uint8_t f0rc08_d0; + uint8_t f0rc09_d0; + uint8_t f0rc0a_d0; + uint8_t f0rc0b_d0; + uint8_t f0rc0c_d0; + uint8_t f0rc0d_d0; + uint8_t f0rc0e_d0; + uint8_t f0rc0f_d0; + uint8_t f0rc1x_d0; + uint8_t f0rc2x_d0; + uint8_t f0rc3x_d0; + uint8_t f0rc4x_d0; + uint8_t f0rc5x_d0; + uint8_t f0rc6x_d0; + uint8_t f0rc7x_d0; + uint8_t f0rc8x_d0; + uint8_t f0rc9x_d0; + uint8_t f0rcax_d0; + uint8_t f0rcbx_d0; + uint8_t f1rc00_d0; + uint8_t f1rc01_d0; + uint8_t f1rc02_d0; + uint8_t f1rc03_d0; + uint8_t f1rc04_d0; + uint8_t f1rc05_d0; + uint8_t f1rc06_d0; + uint8_t f1rc07_d0; + uint8_t f1rc08_d0; + uint8_t f1rc09_d0; + uint8_t f1rc0a_d0; + uint8_t f1rc0b_d0; + uint8_t f1rc0c_d0; + uint8_t f1rc0d_d0; + uint8_t f1rc0e_d0; + uint8_t f1rc0f_d0; + uint8_t f1rc1x_d0; + uint8_t f1rc2x_d0; + uint8_t f1rc3x_d0; + uint8_t f1rc4x_d0; + uint8_t f1rc5x_d0; + uint8_t f1rc6x_d0; + uint8_t f1rc7x_d0; + uint8_t f1rc8x_d0; + uint8_t f1rc9x_d0; + uint8_t f1rcax_d0; + uint8_t f1rcbx_d0; + uint8_t f0rc00_d1; + uint8_t f0rc01_d1; + uint8_t f0rc02_d1; + uint8_t f0rc03_d1; + uint8_t f0rc04_d1; + uint8_t f0rc05_d1; + uint8_t f0rc06_d1; + uint8_t f0rc07_d1; + uint8_t f0rc08_d1; + uint8_t f0rc09_d1; + uint8_t f0rc0a_d1; + uint8_t f0rc0b_d1; + uint8_t f0rc0c_d1; + uint8_t f0rc0d_d1; + uint8_t f0rc0e_d1; + uint8_t f0rc0f_d1; + uint8_t f0rc1x_d1; + uint8_t f0rc2x_d1; + uint8_t f0rc3x_d1; + uint8_t f0rc4x_d1; + uint8_t f0rc5x_d1; + uint8_t f0rc6x_d1; + uint8_t f0rc7x_d1; + uint8_t f0rc8x_d1; + uint8_t f0rc9x_d1; + uint8_t f0rcax_d1; + uint8_t f0rcbx_d1; + uint8_t f1rc00_d1; + uint8_t f1rc01_d1; + uint8_t f1rc02_d1; + uint8_t f1rc03_d1; + uint8_t f1rc04_d1; + uint8_t f1rc05_d1; + uint8_t f1rc06_d1; + uint8_t f1rc07_d1; + uint8_t f1rc08_d1; + uint8_t f1rc09_d1; + uint8_t f1rc0a_d1; + uint8_t f1rc0b_d1; + uint8_t f1rc0c_d1; + uint8_t f1rc0d_d1; + uint8_t f1rc0e_d1; + uint8_t f1rc0f_d1; + uint8_t f1rc1x_d1; + uint8_t f1rc2x_d1; + uint8_t f1rc3x_d1; + uint8_t f1rc4x_d1; + uint8_t f1rc5x_d1; + uint8_t f1rc6x_d1; + uint8_t f1rc7x_d1; + uint8_t f1rc8x_d1; + uint8_t f1rc9x_d1; + uint8_t f1rcax_d1; + uint8_t f1rcbx_d1; + uint8_t reserved142[0x3f6 - 0x142]; + uint16_t alt_cas_l; + uint8_t alt_wcas_l; + uint8_t d4misc; +} __packed; + +struct ddr4lr1d { + uint8_t reserved00; + uint8_t msg_misc; + uint16_t pmu_revision; + uint8_t pstate; + uint8_t pll_bypass_en; + uint16_t dramfreq; + uint8_t dfi_freq_ratio; + uint8_t bpznres_val; + uint8_t phy_odt_impedance; + uint8_t phy_drv_impedance; + uint8_t phy_vref; + uint8_t dram_type; + uint8_t disabled_dbyte; + uint8_t enabled_dqs; + uint8_t cs_present; + uint8_t cs_present_d0; + uint8_t cs_present_d1; + uint8_t addr_mirror; + uint8_t cs_test_fail; + uint8_t phy_cfg; + uint16_t sequence_ctrl; + uint8_t hdt_ctrl; + uint8_t reserved19[0x22 - 0x19]; + uint16_t phy_config_override; + uint8_t dfimrlmargin; + int8_t cdd_rr_3_2; + int8_t cdd_rr_3_1; + int8_t cdd_rr_3_0; + int8_t cdd_rr_2_3; + int8_t cdd_rr_2_1; + int8_t cdd_rr_2_0; + int8_t cdd_rr_1_3; + int8_t cdd_rr_1_2; + int8_t cdd_rr_1_0; + int8_t cdd_rr_0_3; + int8_t cdd_rr_0_2; + int8_t cdd_rr_0_1; + int8_t cdd_ww_3_2; + int8_t cdd_ww_3_1; + int8_t cdd_ww_3_0; + int8_t cdd_ww_2_3; + int8_t cdd_ww_2_1; + int8_t cdd_ww_2_0; + int8_t cdd_ww_1_3; + int8_t cdd_ww_1_2; + int8_t cdd_ww_1_0; + int8_t cdd_ww_0_3; + int8_t cdd_ww_0_2; + int8_t cdd_ww_0_1; + int8_t cdd_rw_3_3; + int8_t cdd_rw_3_2; + int8_t cdd_rw_3_1; + int8_t cdd_rw_3_0; + int8_t cdd_rw_2_3; + int8_t cdd_rw_2_2; + int8_t cdd_rw_2_1; + int8_t cdd_rw_2_0; + int8_t cdd_rw_1_3; + int8_t cdd_rw_1_2; + int8_t cdd_rw_1_1; + int8_t cdd_rw_1_0; + int8_t cdd_rw_0_3; + int8_t cdd_rw_0_2; + int8_t cdd_rw_0_1; + int8_t cdd_rw_0_0; + int8_t cdd_wr_3_3; + int8_t cdd_wr_3_2; + int8_t cdd_wr_3_1; + int8_t cdd_wr_3_0; + int8_t cdd_wr_2_3; + int8_t cdd_wr_2_2; + int8_t cdd_wr_2_1; + int8_t cdd_wr_2_0; + int8_t cdd_wr_1_3; + int8_t cdd_wr_1_2; + int8_t cdd_wr_1_1; + int8_t cdd_wr_1_0; + int8_t cdd_wr_0_3; + int8_t cdd_wr_0_2; + int8_t cdd_wr_0_1; + int8_t cdd_wr_0_0; + uint8_t reserved5d; + uint16_t mr0; + uint16_t mr1; + uint16_t mr2; + uint16_t mr3; + uint16_t mr4; + uint16_t mr5; + uint16_t mr6; + uint8_t x16present; + uint8_t cs_setup_gddec; + uint16_t rtt_nom_wr_park0; + uint16_t rtt_nom_wr_park1; + uint16_t rtt_nom_wr_park2; + uint16_t rtt_nom_wr_park3; + uint16_t rtt_nom_wr_park4; + uint16_t rtt_nom_wr_park5; + uint16_t rtt_nom_wr_park6; + uint16_t rtt_nom_wr_park7; + uint8_t acsm_odt_ctrl0; + uint8_t acsm_odt_ctrl1; + uint8_t acsm_odt_ctrl2; + uint8_t acsm_odt_ctrl3; + uint8_t acsm_odt_ctrl4; + uint8_t acsm_odt_ctrl5; + uint8_t acsm_odt_ctrl6; + uint8_t acsm_odt_ctrl7; + uint8_t vref_dq_r0nib0; + uint8_t vref_dq_r0nib1; + uint8_t vref_dq_r0nib2; + uint8_t vref_dq_r0nib3; + uint8_t vref_dq_r0nib4; + uint8_t vref_dq_r0nib5; + uint8_t vref_dq_r0nib6; + uint8_t vref_dq_r0nib7; + uint8_t vref_dq_r0nib8; + uint8_t vref_dq_r0nib9; + uint8_t vref_dq_r0nib10; + uint8_t vref_dq_r0nib11; + uint8_t vref_dq_r0nib12; + uint8_t vref_dq_r0nib13; + uint8_t vref_dq_r0nib14; + uint8_t vref_dq_r0nib15; + uint8_t vref_dq_r0nib16; + uint8_t vref_dq_r0nib17; + uint8_t vref_dq_r0nib18; + uint8_t vref_dq_r0nib19; + uint8_t vref_dq_r1nib0; + uint8_t vref_dq_r1nib1; + uint8_t vref_dq_r1nib2; + uint8_t vref_dq_r1nib3; + uint8_t vref_dq_r1nib4; + uint8_t vref_dq_r1nib5; + uint8_t vref_dq_r1nib6; + uint8_t vref_dq_r1nib7; + uint8_t vref_dq_r1nib8; + uint8_t vref_dq_r1nib9; + uint8_t vref_dq_r1nib10; + uint8_t vref_dq_r1nib11; + uint8_t vref_dq_r1nib12; + uint8_t vref_dq_r1nib13; + uint8_t vref_dq_r1nib14; + uint8_t vref_dq_r1nib15; + uint8_t vref_dq_r1nib16; + uint8_t vref_dq_r1nib17; + uint8_t vref_dq_r1nib18; + uint8_t vref_dq_r1nib19; + uint8_t vref_dq_r2nib0; + uint8_t vref_dq_r2nib1; + uint8_t vref_dq_r2nib2; + uint8_t vref_dq_r2nib3; + uint8_t vref_dq_r2nib4; + uint8_t vref_dq_r2nib5; + uint8_t vref_dq_r2nib6; + uint8_t vref_dq_r2nib7; + uint8_t vref_dq_r2nib8; + uint8_t vref_dq_r2nib9; + uint8_t vref_dq_r2nib10; + uint8_t vref_dq_r2nib11; + uint8_t vref_dq_r2nib12; + uint8_t vref_dq_r2nib13; + uint8_t vref_dq_r2nib14; + uint8_t vref_dq_r2nib15; + uint8_t vref_dq_r2nib16; + uint8_t vref_dq_r2nib17; + uint8_t vref_dq_r2nib18; + uint8_t vref_dq_r2nib19; + uint8_t vref_dq_r3nib0; + uint8_t vref_dq_r3nib1; + uint8_t vref_dq_r3nib2; + uint8_t vref_dq_r3nib3; + uint8_t vref_dq_r3nib4; + uint8_t vref_dq_r3nib5; + uint8_t vref_dq_r3nib6; + uint8_t vref_dq_r3nib7; + uint8_t vref_dq_r3nib8; + uint8_t vref_dq_r3nib9; + uint8_t vref_dq_r3nib10; + uint8_t vref_dq_r3nib11; + uint8_t vref_dq_r3nib12; + uint8_t vref_dq_r3nib13; + uint8_t vref_dq_r3nib14; + uint8_t vref_dq_r3nib15; + uint8_t vref_dq_r3nib16; + uint8_t vref_dq_r3nib17; + uint8_t vref_dq_r3nib18; + uint8_t vref_dq_r3nib19; + uint8_t f0rc00_d0; + uint8_t f0rc01_d0; + uint8_t f0rc02_d0; + uint8_t f0rc03_d0; + uint8_t f0rc04_d0; + uint8_t f0rc05_d0; + uint8_t f0rc06_d0; + uint8_t f0rc07_d0; + uint8_t f0rc08_d0; + uint8_t f0rc09_d0; + uint8_t f0rc0a_d0; + uint8_t f0rc0b_d0; + uint8_t f0rc0c_d0; + uint8_t f0rc0d_d0; + uint8_t f0rc0e_d0; + uint8_t f0rc0f_d0; + uint8_t f0rc1x_d0; + uint8_t f0rc2x_d0; + uint8_t f0rc3x_d0; + uint8_t f0rc4x_d0; + uint8_t f0rc5x_d0; + uint8_t f0rc6x_d0; + uint8_t f0rc7x_d0; + uint8_t f0rc8x_d0; + uint8_t f0rc9x_d0; + uint8_t f0rcax_d0; + uint8_t f0rcbx_d0; + uint8_t f1rc00_d0; + uint8_t f1rc01_d0; + uint8_t f1rc02_d0; + uint8_t f1rc03_d0; + uint8_t f1rc04_d0; + uint8_t f1rc05_d0; + uint8_t f1rc06_d0; + uint8_t f1rc07_d0; + uint8_t f1rc08_d0; + uint8_t f1rc09_d0; + uint8_t f1rc0a_d0; + uint8_t f1rc0b_d0; + uint8_t f1rc0c_d0; + uint8_t f1rc0d_d0; + uint8_t f1rc0e_d0; + uint8_t f1rc0f_d0; + uint8_t f1rc1x_d0; + uint8_t f1rc2x_d0; + uint8_t f1rc3x_d0; + uint8_t f1rc4x_d0; + uint8_t f1rc5x_d0; + uint8_t f1rc6x_d0; + uint8_t f1rc7x_d0; + uint8_t f1rc8x_d0; + uint8_t f1rc9x_d0; + uint8_t f1rcax_d0; + uint8_t f1rcbx_d0; + uint8_t f0rc00_d1; + uint8_t f0rc01_d1; + uint8_t f0rc02_d1; + uint8_t f0rc03_d1; + uint8_t f0rc04_d1; + uint8_t f0rc05_d1; + uint8_t f0rc06_d1; + uint8_t f0rc07_d1; + uint8_t f0rc08_d1; + uint8_t f0rc09_d1; + uint8_t f0rc0a_d1; + uint8_t f0rc0b_d1; + uint8_t f0rc0c_d1; + uint8_t f0rc0d_d1; + uint8_t f0rc0e_d1; + uint8_t f0rc0f_d1; + uint8_t f0rc1x_d1; + uint8_t f0rc2x_d1; + uint8_t f0rc3x_d1; + uint8_t f0rc4x_d1; + uint8_t f0rc5x_d1; + uint8_t f0rc6x_d1; + uint8_t f0rc7x_d1; + uint8_t f0rc8x_d1; + uint8_t f0rc9x_d1; + uint8_t f0rcax_d1; + uint8_t f0rcbx_d1; + uint8_t f1rc00_d1; + uint8_t f1rc01_d1; + uint8_t f1rc02_d1; + uint8_t f1rc03_d1; + uint8_t f1rc04_d1; + uint8_t f1rc05_d1; + uint8_t f1rc06_d1; + uint8_t f1rc07_d1; + uint8_t f1rc08_d1; + uint8_t f1rc09_d1; + uint8_t f1rc0a_d1; + uint8_t f1rc0b_d1; + uint8_t f1rc0c_d1; + uint8_t f1rc0d_d1; + uint8_t f1rc0e_d1; + uint8_t f1rc0f_d1; + uint8_t f1rc1x_d1; + uint8_t f1rc2x_d1; + uint8_t f1rc3x_d1; + uint8_t f1rc4x_d1; + uint8_t f1rc5x_d1; + uint8_t f1rc6x_d1; + uint8_t f1rc7x_d1; + uint8_t f1rc8x_d1; + uint8_t f1rc9x_d1; + uint8_t f1rcax_d1; + uint8_t f1rcbx_d1; + uint8_t bc00_d0; + uint8_t bc01_d0; + uint8_t bc02_d0; + uint8_t bc03_d0; + uint8_t bc04_d0; + uint8_t bc05_d0; + uint8_t bc06_d0; + uint8_t bc07_d0; + uint8_t bc08_d0; + uint8_t bc09_d0; + uint8_t bc0a_d0; + uint8_t bc0b_d0; + uint8_t bc0c_d0; + uint8_t bc0d_d0; + uint8_t bc0e_d0; + uint8_t f0bc6x_d0; + uint8_t f0bccx_d0; + uint8_t f0bcdx_d0; + uint8_t f0bcex_d0; + uint8_t f0bcfx_d0; + uint8_t f1bccx_d0; + uint8_t f1bcdx_d0; + uint8_t f1bcex_d0; + uint8_t f1bcfx_d0; + uint8_t f0bc2x_b0_d0; + uint8_t f0bc3x_b0_d0; + uint8_t f0bc4x_b0_d0; + uint8_t f0bc5x_b0_d0; + uint8_t f0bc8x_b0_d0; + uint8_t f0bc9x_b0_d0; + uint8_t f0bcax_b0_d0; + uint8_t f0bcbx_b0_d0; + uint8_t f1bc2x_b0_d0; + uint8_t f1bc3x_b0_d0; + uint8_t f1bc4x_b0_d0; + uint8_t f1bc5x_b0_d0; + uint8_t f1bc8x_b0_d0; + uint8_t f1bc9x_b0_d0; + uint8_t f1bcax_b0_d0; + uint8_t f1bcbx_b0_d0; + uint8_t f2bc2x_b0_d0; + uint8_t f2bc3x_b0_d0; + uint8_t f2bc4x_b0_d0; + uint8_t f2bc5x_b0_d0; + uint8_t f2bc8x_b0_d0; + uint8_t f2bc9x_b0_d0; + uint8_t f2bcax_b0_d0; + uint8_t f2bcbx_b0_d0; + uint8_t f3bc2x_b0_d0; + uint8_t f3bc3x_b0_d0; + uint8_t f3bc4x_b0_d0; + uint8_t f3bc5x_b0_d0; + uint8_t f3bc8x_b0_d0; + uint8_t f3bc9x_b0_d0; + uint8_t f3bcax_b0_d0; + uint8_t f3bcbx_b0_d0; + uint8_t f0bc2x_b1_d0; + uint8_t f0bc3x_b1_d0; + uint8_t f0bc4x_b1_d0; + uint8_t f0bc5x_b1_d0; + uint8_t f0bc8x_b1_d0; + uint8_t f0bc9x_b1_d0; + uint8_t f0bcax_b1_d0; + uint8_t f0bcbx_b1_d0; + uint8_t f1bc2x_b1_d0; + uint8_t f1bc3x_b1_d0; + uint8_t f1bc4x_b1_d0; + uint8_t f1bc5x_b1_d0; + uint8_t f1bc8x_b1_d0; + uint8_t f1bc9x_b1_d0; + uint8_t f1bcax_b1_d0; + uint8_t f1bcbx_b1_d0; + uint8_t f2bc2x_b1_d0; + uint8_t f2bc3x_b1_d0; + uint8_t f2bc4x_b1_d0; + uint8_t f2bc5x_b1_d0; + uint8_t f2bc8x_b1_d0; + uint8_t f2bc9x_b1_d0; + uint8_t f2bcax_b1_d0; + uint8_t f2bcbx_b1_d0; + uint8_t f3bc2x_b1_d0; + uint8_t f3bc3x_b1_d0; + uint8_t f3bc4x_b1_d0; + uint8_t f3bc5x_b1_d0; + uint8_t f3bc8x_b1_d0; + uint8_t f3bc9x_b1_d0; + uint8_t f3bcax_b1_d0; + uint8_t f3bcbx_b1_d0; + uint8_t f0bc2x_b2_d0; + uint8_t f0bc3x_b2_d0; + uint8_t f0bc4x_b2_d0; + uint8_t f0bc5x_b2_d0; + uint8_t f0bc8x_b2_d0; + uint8_t f0bc9x_b2_d0; + uint8_t f0bcax_b2_d0; + uint8_t f0bcbx_b2_d0; + uint8_t f1bc2x_b2_d0; + uint8_t f1bc3x_b2_d0; + uint8_t f1bc4x_b2_d0; + uint8_t f1bc5x_b2_d0; + uint8_t f1bc8x_b2_d0; + uint8_t f1bc9x_b2_d0; + uint8_t f1bcax_b2_d0; + uint8_t f1bcbx_b2_d0; + uint8_t f2bc2x_b2_d0; + uint8_t f2bc3x_b2_d0; + uint8_t f2bc4x_b2_d0; + uint8_t f2bc5x_b2_d0; + uint8_t f2bc8x_b2_d0; + uint8_t f2bc9x_b2_d0; + uint8_t f2bcax_b2_d0; + uint8_t f2bcbx_b2_d0; + uint8_t f3bc2x_b2_d0; + uint8_t f3bc3x_b2_d0; + uint8_t f3bc4x_b2_d0; + uint8_t f3bc5x_b2_d0; + uint8_t f3bc8x_b2_d0; + uint8_t f3bc9x_b2_d0; + uint8_t f3bcax_b2_d0; + uint8_t f3bcbx_b2_d0; + uint8_t f0bc2x_b3_d0; + uint8_t f0bc3x_b3_d0; + uint8_t f0bc4x_b3_d0; + uint8_t f0bc5x_b3_d0; + uint8_t f0bc8x_b3_d0; + uint8_t f0bc9x_b3_d0; + uint8_t f0bcax_b3_d0; + uint8_t f0bcbx_b3_d0; + uint8_t f1bc2x_b3_d0; + uint8_t f1bc3x_b3_d0; + uint8_t f1bc4x_b3_d0; + uint8_t f1bc5x_b3_d0; + uint8_t f1bc8x_b3_d0; + uint8_t f1bc9x_b3_d0; + uint8_t f1bcax_b3_d0; + uint8_t f1bcbx_b3_d0; + uint8_t f2bc2x_b3_d0; + uint8_t f2bc3x_b3_d0; + uint8_t f2bc4x_b3_d0; + uint8_t f2bc5x_b3_d0; + uint8_t f2bc8x_b3_d0; + uint8_t f2bc9x_b3_d0; + uint8_t f2bcax_b3_d0; + uint8_t f2bcbx_b3_d0; + uint8_t f3bc2x_b3_d0; + uint8_t f3bc3x_b3_d0; + uint8_t f3bc4x_b3_d0; + uint8_t f3bc5x_b3_d0; + uint8_t f3bc8x_b3_d0; + uint8_t f3bc9x_b3_d0; + uint8_t f3bcax_b3_d0; + uint8_t f3bcbx_b3_d0; + uint8_t f0bc2x_b4_d0; + uint8_t f0bc3x_b4_d0; + uint8_t f0bc4x_b4_d0; + uint8_t f0bc5x_b4_d0; + uint8_t f0bc8x_b4_d0; + uint8_t f0bc9x_b4_d0; + uint8_t f0bcax_b4_d0; + uint8_t f0bcbx_b4_d0; + uint8_t f1bc2x_b4_d0; + uint8_t f1bc3x_b4_d0; + uint8_t f1bc4x_b4_d0; + uint8_t f1bc5x_b4_d0; + uint8_t f1bc8x_b4_d0; + uint8_t f1bc9x_b4_d0; + uint8_t f1bcax_b4_d0; + uint8_t f1bcbx_b4_d0; + uint8_t f2bc2x_b4_d0; + uint8_t f2bc3x_b4_d0; + uint8_t f2bc4x_b4_d0; + uint8_t f2bc5x_b4_d0; + uint8_t f2bc8x_b4_d0; + uint8_t f2bc9x_b4_d0; + uint8_t f2bcax_b4_d0; + uint8_t f2bcbx_b4_d0; + uint8_t f3bc2x_b4_d0; + uint8_t f3bc3x_b4_d0; + uint8_t f3bc4x_b4_d0; + uint8_t f3bc5x_b4_d0; + uint8_t f3bc8x_b4_d0; + uint8_t f3bc9x_b4_d0; + uint8_t f3bcax_b4_d0; + uint8_t f3bcbx_b4_d0; + uint8_t f0bc2x_b5_d0; + uint8_t f0bc3x_b5_d0; + uint8_t f0bc4x_b5_d0; + uint8_t f0bc5x_b5_d0; + uint8_t f0bc8x_b5_d0; + uint8_t f0bc9x_b5_d0; + uint8_t f0bcax_b5_d0; + uint8_t f0bcbx_b5_d0; + uint8_t f1bc2x_b5_d0; + uint8_t f1bc3x_b5_d0; + uint8_t f1bc4x_b5_d0; + uint8_t f1bc5x_b5_d0; + uint8_t f1bc8x_b5_d0; + uint8_t f1bc9x_b5_d0; + uint8_t f1bcax_b5_d0; + uint8_t f1bcbx_b5_d0; + uint8_t f2bc2x_b5_d0; + uint8_t f2bc3x_b5_d0; + uint8_t f2bc4x_b5_d0; + uint8_t f2bc5x_b5_d0; + uint8_t f2bc8x_b5_d0; + uint8_t f2bc9x_b5_d0; + uint8_t f2bcax_b5_d0; + uint8_t f2bcbx_b5_d0; + uint8_t f3bc2x_b5_d0; + uint8_t f3bc3x_b5_d0; + uint8_t f3bc4x_b5_d0; + uint8_t f3bc5x_b5_d0; + uint8_t f3bc8x_b5_d0; + uint8_t f3bc9x_b5_d0; + uint8_t f3bcax_b5_d0; + uint8_t f3bcbx_b5_d0; + uint8_t f0bc2x_b6_d0; + uint8_t f0bc3x_b6_d0; + uint8_t f0bc4x_b6_d0; + uint8_t f0bc5x_b6_d0; + uint8_t f0bc8x_b6_d0; + uint8_t f0bc9x_b6_d0; + uint8_t f0bcax_b6_d0; + uint8_t f0bcbx_b6_d0; + uint8_t f1bc2x_b6_d0; + uint8_t f1bc3x_b6_d0; + uint8_t f1bc4x_b6_d0; + uint8_t f1bc5x_b6_d0; + uint8_t f1bc8x_b6_d0; + uint8_t f1bc9x_b6_d0; + uint8_t f1bcax_b6_d0; + uint8_t f1bcbx_b6_d0; + uint8_t f2bc2x_b6_d0; + uint8_t f2bc3x_b6_d0; + uint8_t f2bc4x_b6_d0; + uint8_t f2bc5x_b6_d0; + uint8_t f2bc8x_b6_d0; + uint8_t f2bc9x_b6_d0; + uint8_t f2bcax_b6_d0; + uint8_t f2bcbx_b6_d0; + uint8_t f3bc2x_b6_d0; + uint8_t f3bc3x_b6_d0; + uint8_t f3bc4x_b6_d0; + uint8_t f3bc5x_b6_d0; + uint8_t f3bc8x_b6_d0; + uint8_t f3bc9x_b6_d0; + uint8_t f3bcax_b6_d0; + uint8_t f3bcbx_b6_d0; + uint8_t f0bc2x_b7_d0; + uint8_t f0bc3x_b7_d0; + uint8_t f0bc4x_b7_d0; + uint8_t f0bc5x_b7_d0; + uint8_t f0bc8x_b7_d0; + uint8_t f0bc9x_b7_d0; + uint8_t f0bcax_b7_d0; + uint8_t f0bcbx_b7_d0; + uint8_t f1bc2x_b7_d0; + uint8_t f1bc3x_b7_d0; + uint8_t f1bc4x_b7_d0; + uint8_t f1bc5x_b7_d0; + uint8_t f1bc8x_b7_d0; + uint8_t f1bc9x_b7_d0; + uint8_t f1bcax_b7_d0; + uint8_t f1bcbx_b7_d0; + uint8_t f2bc2x_b7_d0; + uint8_t f2bc3x_b7_d0; + uint8_t f2bc4x_b7_d0; + uint8_t f2bc5x_b7_d0; + uint8_t f2bc8x_b7_d0; + uint8_t f2bc9x_b7_d0; + uint8_t f2bcax_b7_d0; + uint8_t f2bcbx_b7_d0; + uint8_t f3bc2x_b7_d0; + uint8_t f3bc3x_b7_d0; + uint8_t f3bc4x_b7_d0; + uint8_t f3bc5x_b7_d0; + uint8_t f3bc8x_b7_d0; + uint8_t f3bc9x_b7_d0; + uint8_t f3bcax_b7_d0; + uint8_t f3bcbx_b7_d0; + uint8_t f0bc2x_b8_d0; + uint8_t f0bc3x_b8_d0; + uint8_t f0bc4x_b8_d0; + uint8_t f0bc5x_b8_d0; + uint8_t f0bc8x_b8_d0; + uint8_t f0bc9x_b8_d0; + uint8_t f0bcax_b8_d0; + uint8_t f0bcbx_b8_d0; + uint8_t f1bc2x_b8_d0; + uint8_t f1bc3x_b8_d0; + uint8_t f1bc4x_b8_d0; + uint8_t f1bc5x_b8_d0; + uint8_t f1bc8x_b8_d0; + uint8_t f1bc9x_b8_d0; + uint8_t f1bcax_b8_d0; + uint8_t f1bcbx_b8_d0; + uint8_t f2bc2x_b8_d0; + uint8_t f2bc3x_b8_d0; + uint8_t f2bc4x_b8_d0; + uint8_t f2bc5x_b8_d0; + uint8_t f2bc8x_b8_d0; + uint8_t f2bc9x_b8_d0; + uint8_t f2bcax_b8_d0; + uint8_t f2bcbx_b8_d0; + uint8_t f3bc2x_b8_d0; + uint8_t f3bc3x_b8_d0; + uint8_t f3bc4x_b8_d0; + uint8_t f3bc5x_b8_d0; + uint8_t f3bc8x_b8_d0; + uint8_t f3bc9x_b8_d0; + uint8_t f3bcax_b8_d0; + uint8_t f3bcbx_b8_d0; + uint8_t f5bc5x_d0; + uint8_t f5bc6x_d0; + uint8_t f4bc8x_d0; + uint8_t f4bc9x_d0; + uint8_t f4bcax_d0; + uint8_t f4bcbx_d0; + uint8_t f4bccx_d0; + uint8_t f4bcdx_d0; + uint8_t f4bcex_d0; + uint8_t f4bcfx_d0; + uint8_t f5bc8x_d0; + uint8_t f5bc9x_d0; + uint8_t f5bcax_d0; + uint8_t f5bcbx_d0; + uint8_t f5bccx_d0; + uint8_t f5bcdx_d0; + uint8_t f5bcex_d0; + uint8_t f5bcfx_d0; + uint8_t f6bc8x_d0; + uint8_t f6bc9x_d0; + uint8_t f6bcax_d0; + uint8_t f6bcbx_d0; + uint8_t f6bccx_d0; + uint8_t f6bcdx_d0; + uint8_t f6bcex_d0; + uint8_t f6bcfx_d0; + uint8_t f7bc8x_d0; + uint8_t f7bc9x_d0; + uint8_t f7bcax_d0; + uint8_t f7bcbx_d0; + uint8_t f7bccx_d0; + uint8_t f7bcdx_d0; + uint8_t f7bcex_d0; + uint8_t f7bcfx_d0; + uint8_t bc00_d1; + uint8_t bc01_d1; + uint8_t bc02_d1; + uint8_t bc03_d1; + uint8_t bc04_d1; + uint8_t bc05_d1; + uint8_t bc06_d1; + uint8_t bc07_d1; + uint8_t bc08_d1; + uint8_t bc09_d1; + uint8_t bc0a_d1; + uint8_t bc0b_d1; + uint8_t bc0c_d1; + uint8_t bc0d_d1; + uint8_t bc0e_d1; + uint8_t f0bc6x_d1; + uint8_t f0bccx_d1; + uint8_t f0bcdx_d1; + uint8_t f0bcex_d1; + uint8_t f0bcfx_d1; + uint8_t f1bccx_d1; + uint8_t f1bcdx_d1; + uint8_t f1bcex_d1; + uint8_t f1bcfx_d1; + uint8_t f0bc2x_b0_d1; + uint8_t f0bc3x_b0_d1; + uint8_t f0bc4x_b0_d1; + uint8_t f0bc5x_b0_d1; + uint8_t f0bc8x_b0_d1; + uint8_t f0bc9x_b0_d1; + uint8_t f0bcax_b0_d1; + uint8_t f0bcbx_b0_d1; + uint8_t f1bc2x_b0_d1; + uint8_t f1bc3x_b0_d1; + uint8_t f1bc4x_b0_d1; + uint8_t f1bc5x_b0_d1; + uint8_t f1bc8x_b0_d1; + uint8_t f1bc9x_b0_d1; + uint8_t f1bcax_b0_d1; + uint8_t f1bcbx_b0_d1; + uint8_t f2bc2x_b0_d1; + uint8_t f2bc3x_b0_d1; + uint8_t f2bc4x_b0_d1; + uint8_t f2bc5x_b0_d1; + uint8_t f2bc8x_b0_d1; + uint8_t f2bc9x_b0_d1; + uint8_t f2bcax_b0_d1; + uint8_t f2bcbx_b0_d1; + uint8_t f3bc2x_b0_d1; + uint8_t f3bc3x_b0_d1; + uint8_t f3bc4x_b0_d1; + uint8_t f3bc5x_b0_d1; + uint8_t f3bc8x_b0_d1; + uint8_t f3bc9x_b0_d1; + uint8_t f3bcax_b0_d1; + uint8_t f3bcbx_b0_d1; + uint8_t f0bc2x_b1_d1; + uint8_t f0bc3x_b1_d1; + uint8_t f0bc4x_b1_d1; + uint8_t f0bc5x_b1_d1; + uint8_t f0bc8x_b1_d1; + uint8_t f0bc9x_b1_d1; + uint8_t f0bcax_b1_d1; + uint8_t f0bcbx_b1_d1; + uint8_t f1bc2x_b1_d1; + uint8_t f1bc3x_b1_d1; + uint8_t f1bc4x_b1_d1; + uint8_t f1bc5x_b1_d1; + uint8_t f1bc8x_b1_d1; + uint8_t f1bc9x_b1_d1; + uint8_t f1bcax_b1_d1; + uint8_t f1bcbx_b1_d1; + uint8_t f2bc2x_b1_d1; + uint8_t f2bc3x_b1_d1; + uint8_t f2bc4x_b1_d1; + uint8_t f2bc5x_b1_d1; + uint8_t f2bc8x_b1_d1; + uint8_t f2bc9x_b1_d1; + uint8_t f2bcax_b1_d1; + uint8_t f2bcbx_b1_d1; + uint8_t f3bc2x_b1_d1; + uint8_t f3bc3x_b1_d1; + uint8_t f3bc4x_b1_d1; + uint8_t f3bc5x_b1_d1; + uint8_t f3bc8x_b1_d1; + uint8_t f3bc9x_b1_d1; + uint8_t f3bcax_b1_d1; + uint8_t f3bcbx_b1_d1; + uint8_t f0bc2x_b2_d1; + uint8_t f0bc3x_b2_d1; + uint8_t f0bc4x_b2_d1; + uint8_t f0bc5x_b2_d1; + uint8_t f0bc8x_b2_d1; + uint8_t f0bc9x_b2_d1; + uint8_t f0bcax_b2_d1; + uint8_t f0bcbx_b2_d1; + uint8_t f1bc2x_b2_d1; + uint8_t f1bc3x_b2_d1; + uint8_t f1bc4x_b2_d1; + uint8_t f1bc5x_b2_d1; + uint8_t f1bc8x_b2_d1; + uint8_t f1bc9x_b2_d1; + uint8_t f1bcax_b2_d1; + uint8_t f1bcbx_b2_d1; + uint8_t f2bc2x_b2_d1; + uint8_t f2bc3x_b2_d1; + uint8_t f2bc4x_b2_d1; + uint8_t f2bc5x_b2_d1; + uint8_t f2bc8x_b2_d1; + uint8_t f2bc9x_b2_d1; + uint8_t f2bcax_b2_d1; + uint8_t f2bcbx_b2_d1; + uint8_t f3bc2x_b2_d1; + uint8_t f3bc3x_b2_d1; + uint8_t f3bc4x_b2_d1; + uint8_t f3bc5x_b2_d1; + uint8_t f3bc8x_b2_d1; + uint8_t f3bc9x_b2_d1; + uint8_t f3bcax_b2_d1; + uint8_t f3bcbx_b2_d1; + uint8_t f0bc2x_b3_d1; + uint8_t f0bc3x_b3_d1; + uint8_t f0bc4x_b3_d1; + uint8_t f0bc5x_b3_d1; + uint8_t f0bc8x_b3_d1; + uint8_t f0bc9x_b3_d1; + uint8_t f0bcax_b3_d1; + uint8_t f0bcbx_b3_d1; + uint8_t f1bc2x_b3_d1; + uint8_t f1bc3x_b3_d1; + uint8_t f1bc4x_b3_d1; + uint8_t f1bc5x_b3_d1; + uint8_t f1bc8x_b3_d1; + uint8_t f1bc9x_b3_d1; + uint8_t f1bcax_b3_d1; + uint8_t f1bcbx_b3_d1; + uint8_t f2bc2x_b3_d1; + uint8_t f2bc3x_b3_d1; + uint8_t f2bc4x_b3_d1; + uint8_t f2bc5x_b3_d1; + uint8_t f2bc8x_b3_d1; + uint8_t f2bc9x_b3_d1; + uint8_t f2bcax_b3_d1; + uint8_t f2bcbx_b3_d1; + uint8_t f3bc2x_b3_d1; + uint8_t f3bc3x_b3_d1; + uint8_t f3bc4x_b3_d1; + uint8_t f3bc5x_b3_d1; + uint8_t f3bc8x_b3_d1; + uint8_t f3bc9x_b3_d1; + uint8_t f3bcax_b3_d1; + uint8_t f3bcbx_b3_d1; + uint8_t f0bc2x_b4_d1; + uint8_t f0bc3x_b4_d1; + uint8_t f0bc4x_b4_d1; + uint8_t f0bc5x_b4_d1; + uint8_t f0bc8x_b4_d1; + uint8_t f0bc9x_b4_d1; + uint8_t f0bcax_b4_d1; + uint8_t f0bcbx_b4_d1; + uint8_t f1bc2x_b4_d1; + uint8_t f1bc3x_b4_d1; + uint8_t f1bc4x_b4_d1; + uint8_t f1bc5x_b4_d1; + uint8_t f1bc8x_b4_d1; + uint8_t f1bc9x_b4_d1; + uint8_t f1bcax_b4_d1; + uint8_t f1bcbx_b4_d1; + uint8_t f2bc2x_b4_d1; + uint8_t f2bc3x_b4_d1; + uint8_t f2bc4x_b4_d1; + uint8_t f2bc5x_b4_d1; + uint8_t f2bc8x_b4_d1; + uint8_t f2bc9x_b4_d1; + uint8_t f2bcax_b4_d1; + uint8_t f2bcbx_b4_d1; + uint8_t f3bc2x_b4_d1; + uint8_t f3bc3x_b4_d1; + uint8_t f3bc4x_b4_d1; + uint8_t f3bc5x_b4_d1; + uint8_t f3bc8x_b4_d1; + uint8_t f3bc9x_b4_d1; + uint8_t f3bcax_b4_d1; + uint8_t f3bcbx_b4_d1; + uint8_t f0bc2x_b5_d1; + uint8_t f0bc3x_b5_d1; + uint8_t f0bc4x_b5_d1; + uint8_t f0bc5x_b5_d1; + uint8_t f0bc8x_b5_d1; + uint8_t f0bc9x_b5_d1; + uint8_t f0bcax_b5_d1; + uint8_t f0bcbx_b5_d1; + uint8_t f1bc2x_b5_d1; + uint8_t f1bc3x_b5_d1; + uint8_t f1bc4x_b5_d1; + uint8_t f1bc5x_b5_d1; + uint8_t f1bc8x_b5_d1; + uint8_t f1bc9x_b5_d1; + uint8_t f1bcax_b5_d1; + uint8_t f1bcbx_b5_d1; + uint8_t f2bc2x_b5_d1; + uint8_t f2bc3x_b5_d1; + uint8_t f2bc4x_b5_d1; + uint8_t f2bc5x_b5_d1; + uint8_t f2bc8x_b5_d1; + uint8_t f2bc9x_b5_d1; + uint8_t f2bcax_b5_d1; + uint8_t f2bcbx_b5_d1; + uint8_t f3bc2x_b5_d1; + uint8_t f3bc3x_b5_d1; + uint8_t f3bc4x_b5_d1; + uint8_t f3bc5x_b5_d1; + uint8_t f3bc8x_b5_d1; + uint8_t f3bc9x_b5_d1; + uint8_t f3bcax_b5_d1; + uint8_t f3bcbx_b5_d1; + uint8_t f0bc2x_b6_d1; + uint8_t f0bc3x_b6_d1; + uint8_t f0bc4x_b6_d1; + uint8_t f0bc5x_b6_d1; + uint8_t f0bc8x_b6_d1; + uint8_t f0bc9x_b6_d1; + uint8_t f0bcax_b6_d1; + uint8_t f0bcbx_b6_d1; + uint8_t f1bc2x_b6_d1; + uint8_t f1bc3x_b6_d1; + uint8_t f1bc4x_b6_d1; + uint8_t f1bc5x_b6_d1; + uint8_t f1bc8x_b6_d1; + uint8_t f1bc9x_b6_d1; + uint8_t f1bcax_b6_d1; + uint8_t f1bcbx_b6_d1; + uint8_t f2bc2x_b6_d1; + uint8_t f2bc3x_b6_d1; + uint8_t f2bc4x_b6_d1; + uint8_t f2bc5x_b6_d1; + uint8_t f2bc8x_b6_d1; + uint8_t f2bc9x_b6_d1; + uint8_t f2bcax_b6_d1; + uint8_t f2bcbx_b6_d1; + uint8_t f3bc2x_b6_d1; + uint8_t f3bc3x_b6_d1; + uint8_t f3bc4x_b6_d1; + uint8_t f3bc5x_b6_d1; + uint8_t f3bc8x_b6_d1; + uint8_t f3bc9x_b6_d1; + uint8_t f3bcax_b6_d1; + uint8_t f3bcbx_b6_d1; + uint8_t f0bc2x_b7_d1; + uint8_t f0bc3x_b7_d1; + uint8_t f0bc4x_b7_d1; + uint8_t f0bc5x_b7_d1; + uint8_t f0bc8x_b7_d1; + uint8_t f0bc9x_b7_d1; + uint8_t f0bcax_b7_d1; + uint8_t f0bcbx_b7_d1; + uint8_t f1bc2x_b7_d1; + uint8_t f1bc3x_b7_d1; + uint8_t f1bc4x_b7_d1; + uint8_t f1bc5x_b7_d1; + uint8_t f1bc8x_b7_d1; + uint8_t f1bc9x_b7_d1; + uint8_t f1bcax_b7_d1; + uint8_t f1bcbx_b7_d1; + uint8_t f2bc2x_b7_d1; + uint8_t f2bc3x_b7_d1; + uint8_t f2bc4x_b7_d1; + uint8_t f2bc5x_b7_d1; + uint8_t f2bc8x_b7_d1; + uint8_t f2bc9x_b7_d1; + uint8_t f2bcax_b7_d1; + uint8_t f2bcbx_b7_d1; + uint8_t f3bc2x_b7_d1; + uint8_t f3bc3x_b7_d1; + uint8_t f3bc4x_b7_d1; + uint8_t f3bc5x_b7_d1; + uint8_t f3bc8x_b7_d1; + uint8_t f3bc9x_b7_d1; + uint8_t f3bcax_b7_d1; + uint8_t f3bcbx_b7_d1; + uint8_t f0bc2x_b8_d1; + uint8_t f0bc3x_b8_d1; + uint8_t f0bc4x_b8_d1; + uint8_t f0bc5x_b8_d1; + uint8_t f0bc8x_b8_d1; + uint8_t f0bc9x_b8_d1; + uint8_t f0bcax_b8_d1; + uint8_t f0bcbx_b8_d1; + uint8_t f1bc2x_b8_d1; + uint8_t f1bc3x_b8_d1; + uint8_t f1bc4x_b8_d1; + uint8_t f1bc5x_b8_d1; + uint8_t f1bc8x_b8_d1; + uint8_t f1bc9x_b8_d1; + uint8_t f1bcax_b8_d1; + uint8_t f1bcbx_b8_d1; + uint8_t f2bc2x_b8_d1; + uint8_t f2bc3x_b8_d1; + uint8_t f2bc4x_b8_d1; + uint8_t f2bc5x_b8_d1; + uint8_t f2bc8x_b8_d1; + uint8_t f2bc9x_b8_d1; + uint8_t f2bcax_b8_d1; + uint8_t f2bcbx_b8_d1; + uint8_t f3bc2x_b8_d1; + uint8_t f3bc3x_b8_d1; + uint8_t f3bc4x_b8_d1; + uint8_t f3bc5x_b8_d1; + uint8_t f3bc8x_b8_d1; + uint8_t f3bc9x_b8_d1; + uint8_t f3bcax_b8_d1; + uint8_t f3bcbx_b8_d1; + uint8_t f5bc5x_d1; + uint8_t f5bc6x_d1; + uint8_t f4bc8x_d1; + uint8_t f4bc9x_d1; + uint8_t f4bcax_d1; + uint8_t f4bcbx_d1; + uint8_t f4bccx_d1; + uint8_t f4bcdx_d1; + uint8_t f4bcex_d1; + uint8_t f4bcfx_d1; + uint8_t f5bc8x_d1; + uint8_t f5bc9x_d1; + uint8_t f5bcax_d1; + uint8_t f5bcbx_d1; + uint8_t f5bccx_d1; + uint8_t f5bcdx_d1; + uint8_t f5bcex_d1; + uint8_t f5bcfx_d1; + uint8_t f6bc8x_d1; + uint8_t f6bc9x_d1; + uint8_t f6bcax_d1; + uint8_t f6bcbx_d1; + uint8_t f6bccx_d1; + uint8_t f6bcdx_d1; + uint8_t f6bcex_d1; + uint8_t f6bcfx_d1; + uint8_t f7bc8x_d1; + uint8_t f7bc9x_d1; + uint8_t f7bcax_d1; + uint8_t f7bcbx_d1; + uint8_t f7bccx_d1; + uint8_t f7bcdx_d1; + uint8_t f7bcex_d1; + uint8_t f7bcfx_d1; + uint16_t alt_cas_l; + uint8_t alt_wcas_l; + uint8_t d4misc; +} __packed; + +struct ddr4lr2d { + uint8_t reserved00; + uint8_t msg_misc; + uint16_t pmu_revision; + uint8_t pstate; + uint8_t pll_bypass_en; + uint16_t dramfreq; + uint8_t dfi_freq_ratio; + uint8_t bpznres_val; + uint8_t phy_odt_impedance; + uint8_t phy_drv_impedance; + uint8_t phy_vref; + uint8_t dram_type; + uint8_t disabled_dbyte; + uint8_t enabled_dqs; + uint8_t cs_present; + uint8_t cs_present_d0; + uint8_t cs_present_d1; + uint8_t addr_mirror; + uint8_t cs_test_fail; + uint8_t phy_cfg; + uint16_t sequence_ctrl; + uint8_t hdt_ctrl; + uint8_t rx2d_train_opt; + uint8_t tx2d_train_opt; + uint8_t share2dvref_result; + uint8_t delay_weight2d; + uint8_t voltage_weight2d; + uint8_t reserved1e[0x22 - 0x1e]; + uint16_t phy_config_override; + uint8_t dfimrlmargin; + uint8_t r0_rx_clk_dly_margin; + uint8_t r0_vref_dac_margin; + uint8_t r0_tx_dq_dly_margin; + uint8_t r0_device_vref_margin; + uint8_t reserved29[0x33 - 0x29]; + uint8_t r1_rx_clk_dly_margin; + uint8_t r1_vref_dac_margin; + uint8_t r1_tx_dq_dly_margin; + uint8_t r1_device_vref_margin; + uint8_t reserved37[0x41 - 0x37]; + uint8_t r2_rx_clk_dly_margin; + uint8_t r2_vref_dac_margin; + uint8_t r2_tx_dq_dly_margin; + uint8_t r2_device_vref_margin; + uint8_t reserved45[0x4f - 0x45]; + uint8_t r3_rx_clk_dly_margin; + uint8_t r3_vref_dac_margin; + uint8_t r3_tx_dq_dly_margin; + uint8_t r3_device_vref_margin; + uint8_t reserved53[0x5e - 0x53]; + uint16_t mr0; + uint16_t mr1; + uint16_t mr2; + uint16_t mr3; + uint16_t mr4; + uint16_t mr5; + uint16_t mr6; + uint8_t x16present; + uint8_t cs_setup_gddec; + uint16_t rtt_nom_wr_park0; + uint16_t rtt_nom_wr_park1; + uint16_t rtt_nom_wr_park2; + uint16_t rtt_nom_wr_park3; + uint16_t rtt_nom_wr_park4; + uint16_t rtt_nom_wr_park5; + uint16_t rtt_nom_wr_park6; + uint16_t rtt_nom_wr_park7; + uint8_t acsm_odt_ctrl0; + uint8_t acsm_odt_ctrl1; + uint8_t acsm_odt_ctrl2; + uint8_t acsm_odt_ctrl3; + uint8_t acsm_odt_ctrl4; + uint8_t acsm_odt_ctrl5; + uint8_t acsm_odt_ctrl6; + uint8_t acsm_odt_ctrl7; + uint8_t vref_dq_r0nib0; + uint8_t vref_dq_r0nib1; + uint8_t vref_dq_r0nib2; + uint8_t vref_dq_r0nib3; + uint8_t vref_dq_r0nib4; + uint8_t vref_dq_r0nib5; + uint8_t vref_dq_r0nib6; + uint8_t vref_dq_r0nib7; + uint8_t vref_dq_r0nib8; + uint8_t vref_dq_r0nib9; + uint8_t vref_dq_r0nib10; + uint8_t vref_dq_r0nib11; + uint8_t vref_dq_r0nib12; + uint8_t vref_dq_r0nib13; + uint8_t vref_dq_r0nib14; + uint8_t vref_dq_r0nib15; + uint8_t vref_dq_r0nib16; + uint8_t vref_dq_r0nib17; + uint8_t vref_dq_r0nib18; + uint8_t vref_dq_r0nib19; + uint8_t vref_dq_r1nib0; + uint8_t vref_dq_r1nib1; + uint8_t vref_dq_r1nib2; + uint8_t vref_dq_r1nib3; + uint8_t vref_dq_r1nib4; + uint8_t vref_dq_r1nib5; + uint8_t vref_dq_r1nib6; + uint8_t vref_dq_r1nib7; + uint8_t vref_dq_r1nib8; + uint8_t vref_dq_r1nib9; + uint8_t vref_dq_r1nib10; + uint8_t vref_dq_r1nib11; + uint8_t vref_dq_r1nib12; + uint8_t vref_dq_r1nib13; + uint8_t vref_dq_r1nib14; + uint8_t vref_dq_r1nib15; + uint8_t vref_dq_r1nib16; + uint8_t vref_dq_r1nib17; + uint8_t vref_dq_r1nib18; + uint8_t vref_dq_r1nib19; + uint8_t vref_dq_r2nib0; + uint8_t vref_dq_r2nib1; + uint8_t vref_dq_r2nib2; + uint8_t vref_dq_r2nib3; + uint8_t vref_dq_r2nib4; + uint8_t vref_dq_r2nib5; + uint8_t vref_dq_r2nib6; + uint8_t vref_dq_r2nib7; + uint8_t vref_dq_r2nib8; + uint8_t vref_dq_r2nib9; + uint8_t vref_dq_r2nib10; + uint8_t vref_dq_r2nib11; + uint8_t vref_dq_r2nib12; + uint8_t vref_dq_r2nib13; + uint8_t vref_dq_r2nib14; + uint8_t vref_dq_r2nib15; + uint8_t vref_dq_r2nib16; + uint8_t vref_dq_r2nib17; + uint8_t vref_dq_r2nib18; + uint8_t vref_dq_r2nib19; + uint8_t vref_dq_r3nib0; + uint8_t vref_dq_r3nib1; + uint8_t vref_dq_r3nib2; + uint8_t vref_dq_r3nib3; + uint8_t vref_dq_r3nib4; + uint8_t vref_dq_r3nib5; + uint8_t vref_dq_r3nib6; + uint8_t vref_dq_r3nib7; + uint8_t vref_dq_r3nib8; + uint8_t vref_dq_r3nib9; + uint8_t vref_dq_r3nib10; + uint8_t vref_dq_r3nib11; + uint8_t vref_dq_r3nib12; + uint8_t vref_dq_r3nib13; + uint8_t vref_dq_r3nib14; + uint8_t vref_dq_r3nib15; + uint8_t vref_dq_r3nib16; + uint8_t vref_dq_r3nib17; + uint8_t vref_dq_r3nib18; + uint8_t vref_dq_r3nib19; + uint8_t f0rc00_d0; + uint8_t f0rc01_d0; + uint8_t f0rc02_d0; + uint8_t f0rc03_d0; + uint8_t f0rc04_d0; + uint8_t f0rc05_d0; + uint8_t f0rc06_d0; + uint8_t f0rc07_d0; + uint8_t f0rc08_d0; + uint8_t f0rc09_d0; + uint8_t f0rc0a_d0; + uint8_t f0rc0b_d0; + uint8_t f0rc0c_d0; + uint8_t f0rc0d_d0; + uint8_t f0rc0e_d0; + uint8_t f0rc0f_d0; + uint8_t f0rc1x_d0; + uint8_t f0rc2x_d0; + uint8_t f0rc3x_d0; + uint8_t f0rc4x_d0; + uint8_t f0rc5x_d0; + uint8_t f0rc6x_d0; + uint8_t f0rc7x_d0; + uint8_t f0rc8x_d0; + uint8_t f0rc9x_d0; + uint8_t f0rcax_d0; + uint8_t f0rcbx_d0; + uint8_t f1rc00_d0; + uint8_t f1rc01_d0; + uint8_t f1rc02_d0; + uint8_t f1rc03_d0; + uint8_t f1rc04_d0; + uint8_t f1rc05_d0; + uint8_t f1rc06_d0; + uint8_t f1rc07_d0; + uint8_t f1rc08_d0; + uint8_t f1rc09_d0; + uint8_t f1rc0a_d0; + uint8_t f1rc0b_d0; + uint8_t f1rc0c_d0; + uint8_t f1rc0d_d0; + uint8_t f1rc0e_d0; + uint8_t f1rc0f_d0; + uint8_t f1rc1x_d0; + uint8_t f1rc2x_d0; + uint8_t f1rc3x_d0; + uint8_t f1rc4x_d0; + uint8_t f1rc5x_d0; + uint8_t f1rc6x_d0; + uint8_t f1rc7x_d0; + uint8_t f1rc8x_d0; + uint8_t f1rc9x_d0; + uint8_t f1rcax_d0; + uint8_t f1rcbx_d0; + uint8_t f0rc00_d1; + uint8_t f0rc01_d1; + uint8_t f0rc02_d1; + uint8_t f0rc03_d1; + uint8_t f0rc04_d1; + uint8_t f0rc05_d1; + uint8_t f0rc06_d1; + uint8_t f0rc07_d1; + uint8_t f0rc08_d1; + uint8_t f0rc09_d1; + uint8_t f0rc0a_d1; + uint8_t f0rc0b_d1; + uint8_t f0rc0c_d1; + uint8_t f0rc0d_d1; + uint8_t f0rc0e_d1; + uint8_t f0rc0f_d1; + uint8_t f0rc1x_d1; + uint8_t f0rc2x_d1; + uint8_t f0rc3x_d1; + uint8_t f0rc4x_d1; + uint8_t f0rc5x_d1; + uint8_t f0rc6x_d1; + uint8_t f0rc7x_d1; + uint8_t f0rc8x_d1; + uint8_t f0rc9x_d1; + uint8_t f0rcax_d1; + uint8_t f0rcbx_d1; + uint8_t f1rc00_d1; + uint8_t f1rc01_d1; + uint8_t f1rc02_d1; + uint8_t f1rc03_d1; + uint8_t f1rc04_d1; + uint8_t f1rc05_d1; + uint8_t f1rc06_d1; + uint8_t f1rc07_d1; + uint8_t f1rc08_d1; + uint8_t f1rc09_d1; + uint8_t f1rc0a_d1; + uint8_t f1rc0b_d1; + uint8_t f1rc0c_d1; + uint8_t f1rc0d_d1; + uint8_t f1rc0e_d1; + uint8_t f1rc0f_d1; + uint8_t f1rc1x_d1; + uint8_t f1rc2x_d1; + uint8_t f1rc3x_d1; + uint8_t f1rc4x_d1; + uint8_t f1rc5x_d1; + uint8_t f1rc6x_d1; + uint8_t f1rc7x_d1; + uint8_t f1rc8x_d1; + uint8_t f1rc9x_d1; + uint8_t f1rcax_d1; + uint8_t f1rcbx_d1; + uint8_t bc00_d0; + uint8_t bc01_d0; + uint8_t bc02_d0; + uint8_t bc03_d0; + uint8_t bc04_d0; + uint8_t bc05_d0; + uint8_t bc06_d0; + uint8_t bc07_d0; + uint8_t bc08_d0; + uint8_t bc09_d0; + uint8_t bc0a_d0; + uint8_t bc0b_d0; + uint8_t bc0c_d0; + uint8_t bc0d_d0; + uint8_t bc0e_d0; + uint8_t f0bc6x_d0; + uint8_t f0bccx_d0; + uint8_t f0bcdx_d0; + uint8_t f0bcex_d0; + uint8_t f0bcfx_d0; + uint8_t f1bccx_d0; + uint8_t f1bcdx_d0; + uint8_t f1bcex_d0; + uint8_t f1bcfx_d0; + uint8_t f0bc2x_b0_d0; + uint8_t f0bc3x_b0_d0; + uint8_t f0bc4x_b0_d0; + uint8_t f0bc5x_b0_d0; + uint8_t f0bc8x_b0_d0; + uint8_t f0bc9x_b0_d0; + uint8_t f0bcax_b0_d0; + uint8_t f0bcbx_b0_d0; + uint8_t f1bc2x_b0_d0; + uint8_t f1bc3x_b0_d0; + uint8_t f1bc4x_b0_d0; + uint8_t f1bc5x_b0_d0; + uint8_t f1bc8x_b0_d0; + uint8_t f1bc9x_b0_d0; + uint8_t f1bcax_b0_d0; + uint8_t f1bcbx_b0_d0; + uint8_t f2bc2x_b0_d0; + uint8_t f2bc3x_b0_d0; + uint8_t f2bc4x_b0_d0; + uint8_t f2bc5x_b0_d0; + uint8_t f2bc8x_b0_d0; + uint8_t f2bc9x_b0_d0; + uint8_t f2bcax_b0_d0; + uint8_t f2bcbx_b0_d0; + uint8_t f3bc2x_b0_d0; + uint8_t f3bc3x_b0_d0; + uint8_t f3bc4x_b0_d0; + uint8_t f3bc5x_b0_d0; + uint8_t f3bc8x_b0_d0; + uint8_t f3bc9x_b0_d0; + uint8_t f3bcax_b0_d0; + uint8_t f3bcbx_b0_d0; + uint8_t f0bc2x_b1_d0; + uint8_t f0bc3x_b1_d0; + uint8_t f0bc4x_b1_d0; + uint8_t f0bc5x_b1_d0; + uint8_t f0bc8x_b1_d0; + uint8_t f0bc9x_b1_d0; + uint8_t f0bcax_b1_d0; + uint8_t f0bcbx_b1_d0; + uint8_t f1bc2x_b1_d0; + uint8_t f1bc3x_b1_d0; + uint8_t f1bc4x_b1_d0; + uint8_t f1bc5x_b1_d0; + uint8_t f1bc8x_b1_d0; + uint8_t f1bc9x_b1_d0; + uint8_t f1bcax_b1_d0; + uint8_t f1bcbx_b1_d0; + uint8_t f2bc2x_b1_d0; + uint8_t f2bc3x_b1_d0; + uint8_t f2bc4x_b1_d0; + uint8_t f2bc5x_b1_d0; + uint8_t f2bc8x_b1_d0; + uint8_t f2bc9x_b1_d0; + uint8_t f2bcax_b1_d0; + uint8_t f2bcbx_b1_d0; + uint8_t f3bc2x_b1_d0; + uint8_t f3bc3x_b1_d0; + uint8_t f3bc4x_b1_d0; + uint8_t f3bc5x_b1_d0; + uint8_t f3bc8x_b1_d0; + uint8_t f3bc9x_b1_d0; + uint8_t f3bcax_b1_d0; + uint8_t f3bcbx_b1_d0; + uint8_t f0bc2x_b2_d0; + uint8_t f0bc3x_b2_d0; + uint8_t f0bc4x_b2_d0; + uint8_t f0bc5x_b2_d0; + uint8_t f0bc8x_b2_d0; + uint8_t f0bc9x_b2_d0; + uint8_t f0bcax_b2_d0; + uint8_t f0bcbx_b2_d0; + uint8_t f1bc2x_b2_d0; + uint8_t f1bc3x_b2_d0; + uint8_t f1bc4x_b2_d0; + uint8_t f1bc5x_b2_d0; + uint8_t f1bc8x_b2_d0; + uint8_t f1bc9x_b2_d0; + uint8_t f1bcax_b2_d0; + uint8_t f1bcbx_b2_d0; + uint8_t f2bc2x_b2_d0; + uint8_t f2bc3x_b2_d0; + uint8_t f2bc4x_b2_d0; + uint8_t f2bc5x_b2_d0; + uint8_t f2bc8x_b2_d0; + uint8_t f2bc9x_b2_d0; + uint8_t f2bcax_b2_d0; + uint8_t f2bcbx_b2_d0; + uint8_t f3bc2x_b2_d0; + uint8_t f3bc3x_b2_d0; + uint8_t f3bc4x_b2_d0; + uint8_t f3bc5x_b2_d0; + uint8_t f3bc8x_b2_d0; + uint8_t f3bc9x_b2_d0; + uint8_t f3bcax_b2_d0; + uint8_t f3bcbx_b2_d0; + uint8_t f0bc2x_b3_d0; + uint8_t f0bc3x_b3_d0; + uint8_t f0bc4x_b3_d0; + uint8_t f0bc5x_b3_d0; + uint8_t f0bc8x_b3_d0; + uint8_t f0bc9x_b3_d0; + uint8_t f0bcax_b3_d0; + uint8_t f0bcbx_b3_d0; + uint8_t f1bc2x_b3_d0; + uint8_t f1bc3x_b3_d0; + uint8_t f1bc4x_b3_d0; + uint8_t f1bc5x_b3_d0; + uint8_t f1bc8x_b3_d0; + uint8_t f1bc9x_b3_d0; + uint8_t f1bcax_b3_d0; + uint8_t f1bcbx_b3_d0; + uint8_t f2bc2x_b3_d0; + uint8_t f2bc3x_b3_d0; + uint8_t f2bc4x_b3_d0; + uint8_t f2bc5x_b3_d0; + uint8_t f2bc8x_b3_d0; + uint8_t f2bc9x_b3_d0; + uint8_t f2bcax_b3_d0; + uint8_t f2bcbx_b3_d0; + uint8_t f3bc2x_b3_d0; + uint8_t f3bc3x_b3_d0; + uint8_t f3bc4x_b3_d0; + uint8_t f3bc5x_b3_d0; + uint8_t f3bc8x_b3_d0; + uint8_t f3bc9x_b3_d0; + uint8_t f3bcax_b3_d0; + uint8_t f3bcbx_b3_d0; + uint8_t f0bc2x_b4_d0; + uint8_t f0bc3x_b4_d0; + uint8_t f0bc4x_b4_d0; + uint8_t f0bc5x_b4_d0; + uint8_t f0bc8x_b4_d0; + uint8_t f0bc9x_b4_d0; + uint8_t f0bcax_b4_d0; + uint8_t f0bcbx_b4_d0; + uint8_t f1bc2x_b4_d0; + uint8_t f1bc3x_b4_d0; + uint8_t f1bc4x_b4_d0; + uint8_t f1bc5x_b4_d0; + uint8_t f1bc8x_b4_d0; + uint8_t f1bc9x_b4_d0; + uint8_t f1bcax_b4_d0; + uint8_t f1bcbx_b4_d0; + uint8_t f2bc2x_b4_d0; + uint8_t f2bc3x_b4_d0; + uint8_t f2bc4x_b4_d0; + uint8_t f2bc5x_b4_d0; + uint8_t f2bc8x_b4_d0; + uint8_t f2bc9x_b4_d0; + uint8_t f2bcax_b4_d0; + uint8_t f2bcbx_b4_d0; + uint8_t f3bc2x_b4_d0; + uint8_t f3bc3x_b4_d0; + uint8_t f3bc4x_b4_d0; + uint8_t f3bc5x_b4_d0; + uint8_t f3bc8x_b4_d0; + uint8_t f3bc9x_b4_d0; + uint8_t f3bcax_b4_d0; + uint8_t f3bcbx_b4_d0; + uint8_t f0bc2x_b5_d0; + uint8_t f0bc3x_b5_d0; + uint8_t f0bc4x_b5_d0; + uint8_t f0bc5x_b5_d0; + uint8_t f0bc8x_b5_d0; + uint8_t f0bc9x_b5_d0; + uint8_t f0bcax_b5_d0; + uint8_t f0bcbx_b5_d0; + uint8_t f1bc2x_b5_d0; + uint8_t f1bc3x_b5_d0; + uint8_t f1bc4x_b5_d0; + uint8_t f1bc5x_b5_d0; + uint8_t f1bc8x_b5_d0; + uint8_t f1bc9x_b5_d0; + uint8_t f1bcax_b5_d0; + uint8_t f1bcbx_b5_d0; + uint8_t f2bc2x_b5_d0; + uint8_t f2bc3x_b5_d0; + uint8_t f2bc4x_b5_d0; + uint8_t f2bc5x_b5_d0; + uint8_t f2bc8x_b5_d0; + uint8_t f2bc9x_b5_d0; + uint8_t f2bcax_b5_d0; + uint8_t f2bcbx_b5_d0; + uint8_t f3bc2x_b5_d0; + uint8_t f3bc3x_b5_d0; + uint8_t f3bc4x_b5_d0; + uint8_t f3bc5x_b5_d0; + uint8_t f3bc8x_b5_d0; + uint8_t f3bc9x_b5_d0; + uint8_t f3bcax_b5_d0; + uint8_t f3bcbx_b5_d0; + uint8_t f0bc2x_b6_d0; + uint8_t f0bc3x_b6_d0; + uint8_t f0bc4x_b6_d0; + uint8_t f0bc5x_b6_d0; + uint8_t f0bc8x_b6_d0; + uint8_t f0bc9x_b6_d0; + uint8_t f0bcax_b6_d0; + uint8_t f0bcbx_b6_d0; + uint8_t f1bc2x_b6_d0; + uint8_t f1bc3x_b6_d0; + uint8_t f1bc4x_b6_d0; + uint8_t f1bc5x_b6_d0; + uint8_t f1bc8x_b6_d0; + uint8_t f1bc9x_b6_d0; + uint8_t f1bcax_b6_d0; + uint8_t f1bcbx_b6_d0; + uint8_t f2bc2x_b6_d0; + uint8_t f2bc3x_b6_d0; + uint8_t f2bc4x_b6_d0; + uint8_t f2bc5x_b6_d0; + uint8_t f2bc8x_b6_d0; + uint8_t f2bc9x_b6_d0; + uint8_t f2bcax_b6_d0; + uint8_t f2bcbx_b6_d0; + uint8_t f3bc2x_b6_d0; + uint8_t f3bc3x_b6_d0; + uint8_t f3bc4x_b6_d0; + uint8_t f3bc5x_b6_d0; + uint8_t f3bc8x_b6_d0; + uint8_t f3bc9x_b6_d0; + uint8_t f3bcax_b6_d0; + uint8_t f3bcbx_b6_d0; + uint8_t f0bc2x_b7_d0; + uint8_t f0bc3x_b7_d0; + uint8_t f0bc4x_b7_d0; + uint8_t f0bc5x_b7_d0; + uint8_t f0bc8x_b7_d0; + uint8_t f0bc9x_b7_d0; + uint8_t f0bcax_b7_d0; + uint8_t f0bcbx_b7_d0; + uint8_t f1bc2x_b7_d0; + uint8_t f1bc3x_b7_d0; + uint8_t f1bc4x_b7_d0; + uint8_t f1bc5x_b7_d0; + uint8_t f1bc8x_b7_d0; + uint8_t f1bc9x_b7_d0; + uint8_t f1bcax_b7_d0; + uint8_t f1bcbx_b7_d0; + uint8_t f2bc2x_b7_d0; + uint8_t f2bc3x_b7_d0; + uint8_t f2bc4x_b7_d0; + uint8_t f2bc5x_b7_d0; + uint8_t f2bc8x_b7_d0; + uint8_t f2bc9x_b7_d0; + uint8_t f2bcax_b7_d0; + uint8_t f2bcbx_b7_d0; + uint8_t f3bc2x_b7_d0; + uint8_t f3bc3x_b7_d0; + uint8_t f3bc4x_b7_d0; + uint8_t f3bc5x_b7_d0; + uint8_t f3bc8x_b7_d0; + uint8_t f3bc9x_b7_d0; + uint8_t f3bcax_b7_d0; + uint8_t f3bcbx_b7_d0; + uint8_t f0bc2x_b8_d0; + uint8_t f0bc3x_b8_d0; + uint8_t f0bc4x_b8_d0; + uint8_t f0bc5x_b8_d0; + uint8_t f0bc8x_b8_d0; + uint8_t f0bc9x_b8_d0; + uint8_t f0bcax_b8_d0; + uint8_t f0bcbx_b8_d0; + uint8_t f1bc2x_b8_d0; + uint8_t f1bc3x_b8_d0; + uint8_t f1bc4x_b8_d0; + uint8_t f1bc5x_b8_d0; + uint8_t f1bc8x_b8_d0; + uint8_t f1bc9x_b8_d0; + uint8_t f1bcax_b8_d0; + uint8_t f1bcbx_b8_d0; + uint8_t f2bc2x_b8_d0; + uint8_t f2bc3x_b8_d0; + uint8_t f2bc4x_b8_d0; + uint8_t f2bc5x_b8_d0; + uint8_t f2bc8x_b8_d0; + uint8_t f2bc9x_b8_d0; + uint8_t f2bcax_b8_d0; + uint8_t f2bcbx_b8_d0; + uint8_t f3bc2x_b8_d0; + uint8_t f3bc3x_b8_d0; + uint8_t f3bc4x_b8_d0; + uint8_t f3bc5x_b8_d0; + uint8_t f3bc8x_b8_d0; + uint8_t f3bc9x_b8_d0; + uint8_t f3bcax_b8_d0; + uint8_t f3bcbx_b8_d0; + uint8_t f5bc5x_d0; + uint8_t f5bc6x_d0; + uint8_t f4bc8x_d0; + uint8_t f4bc9x_d0; + uint8_t f4bcax_d0; + uint8_t f4bcbx_d0; + uint8_t f4bccx_d0; + uint8_t f4bcdx_d0; + uint8_t f4bcex_d0; + uint8_t f4bcfx_d0; + uint8_t f5bc8x_d0; + uint8_t f5bc9x_d0; + uint8_t f5bcax_d0; + uint8_t f5bcbx_d0; + uint8_t f5bccx_d0; + uint8_t f5bcdx_d0; + uint8_t f5bcex_d0; + uint8_t f5bcfx_d0; + uint8_t f6bc8x_d0; + uint8_t f6bc9x_d0; + uint8_t f6bcax_d0; + uint8_t f6bcbx_d0; + uint8_t f6bccx_d0; + uint8_t f6bcdx_d0; + uint8_t f6bcex_d0; + uint8_t f6bcfx_d0; + uint8_t f7bc8x_d0; + uint8_t f7bc9x_d0; + uint8_t f7bcax_d0; + uint8_t f7bcbx_d0; + uint8_t f7bccx_d0; + uint8_t f7bcdx_d0; + uint8_t f7bcex_d0; + uint8_t f7bcfx_d0; + uint8_t bc00_d1; + uint8_t bc01_d1; + uint8_t bc02_d1; + uint8_t bc03_d1; + uint8_t bc04_d1; + uint8_t bc05_d1; + uint8_t bc06_d1; + uint8_t bc07_d1; + uint8_t bc08_d1; + uint8_t bc09_d1; + uint8_t bc0a_d1; + uint8_t bc0b_d1; + uint8_t bc0c_d1; + uint8_t bc0d_d1; + uint8_t bc0e_d1; + uint8_t f0bc6x_d1; + uint8_t f0bccx_d1; + uint8_t f0bcdx_d1; + uint8_t f0bcex_d1; + uint8_t f0bcfx_d1; + uint8_t f1bccx_d1; + uint8_t f1bcdx_d1; + uint8_t f1bcex_d1; + uint8_t f1bcfx_d1; + uint8_t f0bc2x_b0_d1; + uint8_t f0bc3x_b0_d1; + uint8_t f0bc4x_b0_d1; + uint8_t f0bc5x_b0_d1; + uint8_t f0bc8x_b0_d1; + uint8_t f0bc9x_b0_d1; + uint8_t f0bcax_b0_d1; + uint8_t f0bcbx_b0_d1; + uint8_t f1bc2x_b0_d1; + uint8_t f1bc3x_b0_d1; + uint8_t f1bc4x_b0_d1; + uint8_t f1bc5x_b0_d1; + uint8_t f1bc8x_b0_d1; + uint8_t f1bc9x_b0_d1; + uint8_t f1bcax_b0_d1; + uint8_t f1bcbx_b0_d1; + uint8_t f2bc2x_b0_d1; + uint8_t f2bc3x_b0_d1; + uint8_t f2bc4x_b0_d1; + uint8_t f2bc5x_b0_d1; + uint8_t f2bc8x_b0_d1; + uint8_t f2bc9x_b0_d1; + uint8_t f2bcax_b0_d1; + uint8_t f2bcbx_b0_d1; + uint8_t f3bc2x_b0_d1; + uint8_t f3bc3x_b0_d1; + uint8_t f3bc4x_b0_d1; + uint8_t f3bc5x_b0_d1; + uint8_t f3bc8x_b0_d1; + uint8_t f3bc9x_b0_d1; + uint8_t f3bcax_b0_d1; + uint8_t f3bcbx_b0_d1; + uint8_t f0bc2x_b1_d1; + uint8_t f0bc3x_b1_d1; + uint8_t f0bc4x_b1_d1; + uint8_t f0bc5x_b1_d1; + uint8_t f0bc8x_b1_d1; + uint8_t f0bc9x_b1_d1; + uint8_t f0bcax_b1_d1; + uint8_t f0bcbx_b1_d1; + uint8_t f1bc2x_b1_d1; + uint8_t f1bc3x_b1_d1; + uint8_t f1bc4x_b1_d1; + uint8_t f1bc5x_b1_d1; + uint8_t f1bc8x_b1_d1; + uint8_t f1bc9x_b1_d1; + uint8_t f1bcax_b1_d1; + uint8_t f1bcbx_b1_d1; + uint8_t f2bc2x_b1_d1; + uint8_t f2bc3x_b1_d1; + uint8_t f2bc4x_b1_d1; + uint8_t f2bc5x_b1_d1; + uint8_t f2bc8x_b1_d1; + uint8_t f2bc9x_b1_d1; + uint8_t f2bcax_b1_d1; + uint8_t f2bcbx_b1_d1; + uint8_t f3bc2x_b1_d1; + uint8_t f3bc3x_b1_d1; + uint8_t f3bc4x_b1_d1; + uint8_t f3bc5x_b1_d1; + uint8_t f3bc8x_b1_d1; + uint8_t f3bc9x_b1_d1; + uint8_t f3bcax_b1_d1; + uint8_t f3bcbx_b1_d1; + uint8_t f0bc2x_b2_d1; + uint8_t f0bc3x_b2_d1; + uint8_t f0bc4x_b2_d1; + uint8_t f0bc5x_b2_d1; + uint8_t f0bc8x_b2_d1; + uint8_t f0bc9x_b2_d1; + uint8_t f0bcax_b2_d1; + uint8_t f0bcbx_b2_d1; + uint8_t f1bc2x_b2_d1; + uint8_t f1bc3x_b2_d1; + uint8_t f1bc4x_b2_d1; + uint8_t f1bc5x_b2_d1; + uint8_t f1bc8x_b2_d1; + uint8_t f1bc9x_b2_d1; + uint8_t f1bcax_b2_d1; + uint8_t f1bcbx_b2_d1; + uint8_t f2bc2x_b2_d1; + uint8_t f2bc3x_b2_d1; + uint8_t f2bc4x_b2_d1; + uint8_t f2bc5x_b2_d1; + uint8_t f2bc8x_b2_d1; + uint8_t f2bc9x_b2_d1; + uint8_t f2bcax_b2_d1; + uint8_t f2bcbx_b2_d1; + uint8_t f3bc2x_b2_d1; + uint8_t f3bc3x_b2_d1; + uint8_t f3bc4x_b2_d1; + uint8_t f3bc5x_b2_d1; + uint8_t f3bc8x_b2_d1; + uint8_t f3bc9x_b2_d1; + uint8_t f3bcax_b2_d1; + uint8_t f3bcbx_b2_d1; + uint8_t f0bc2x_b3_d1; + uint8_t f0bc3x_b3_d1; + uint8_t f0bc4x_b3_d1; + uint8_t f0bc5x_b3_d1; + uint8_t f0bc8x_b3_d1; + uint8_t f0bc9x_b3_d1; + uint8_t f0bcax_b3_d1; + uint8_t f0bcbx_b3_d1; + uint8_t f1bc2x_b3_d1; + uint8_t f1bc3x_b3_d1; + uint8_t f1bc4x_b3_d1; + uint8_t f1bc5x_b3_d1; + uint8_t f1bc8x_b3_d1; + uint8_t f1bc9x_b3_d1; + uint8_t f1bcax_b3_d1; + uint8_t f1bcbx_b3_d1; + uint8_t f2bc2x_b3_d1; + uint8_t f2bc3x_b3_d1; + uint8_t f2bc4x_b3_d1; + uint8_t f2bc5x_b3_d1; + uint8_t f2bc8x_b3_d1; + uint8_t f2bc9x_b3_d1; + uint8_t f2bcax_b3_d1; + uint8_t f2bcbx_b3_d1; + uint8_t f3bc2x_b3_d1; + uint8_t f3bc3x_b3_d1; + uint8_t f3bc4x_b3_d1; + uint8_t f3bc5x_b3_d1; + uint8_t f3bc8x_b3_d1; + uint8_t f3bc9x_b3_d1; + uint8_t f3bcax_b3_d1; + uint8_t f3bcbx_b3_d1; + uint8_t f0bc2x_b4_d1; + uint8_t f0bc3x_b4_d1; + uint8_t f0bc4x_b4_d1; + uint8_t f0bc5x_b4_d1; + uint8_t f0bc8x_b4_d1; + uint8_t f0bc9x_b4_d1; + uint8_t f0bcax_b4_d1; + uint8_t f0bcbx_b4_d1; + uint8_t f1bc2x_b4_d1; + uint8_t f1bc3x_b4_d1; + uint8_t f1bc4x_b4_d1; + uint8_t f1bc5x_b4_d1; + uint8_t f1bc8x_b4_d1; + uint8_t f1bc9x_b4_d1; + uint8_t f1bcax_b4_d1; + uint8_t f1bcbx_b4_d1; + uint8_t f2bc2x_b4_d1; + uint8_t f2bc3x_b4_d1; + uint8_t f2bc4x_b4_d1; + uint8_t f2bc5x_b4_d1; + uint8_t f2bc8x_b4_d1; + uint8_t f2bc9x_b4_d1; + uint8_t f2bcax_b4_d1; + uint8_t f2bcbx_b4_d1; + uint8_t f3bc2x_b4_d1; + uint8_t f3bc3x_b4_d1; + uint8_t f3bc4x_b4_d1; + uint8_t f3bc5x_b4_d1; + uint8_t f3bc8x_b4_d1; + uint8_t f3bc9x_b4_d1; + uint8_t f3bcax_b4_d1; + uint8_t f3bcbx_b4_d1; + uint8_t f0bc2x_b5_d1; + uint8_t f0bc3x_b5_d1; + uint8_t f0bc4x_b5_d1; + uint8_t f0bc5x_b5_d1; + uint8_t f0bc8x_b5_d1; + uint8_t f0bc9x_b5_d1; + uint8_t f0bcax_b5_d1; + uint8_t f0bcbx_b5_d1; + uint8_t f1bc2x_b5_d1; + uint8_t f1bc3x_b5_d1; + uint8_t f1bc4x_b5_d1; + uint8_t f1bc5x_b5_d1; + uint8_t f1bc8x_b5_d1; + uint8_t f1bc9x_b5_d1; + uint8_t f1bcax_b5_d1; + uint8_t f1bcbx_b5_d1; + uint8_t f2bc2x_b5_d1; + uint8_t f2bc3x_b5_d1; + uint8_t f2bc4x_b5_d1; + uint8_t f2bc5x_b5_d1; + uint8_t f2bc8x_b5_d1; + uint8_t f2bc9x_b5_d1; + uint8_t f2bcax_b5_d1; + uint8_t f2bcbx_b5_d1; + uint8_t f3bc2x_b5_d1; + uint8_t f3bc3x_b5_d1; + uint8_t f3bc4x_b5_d1; + uint8_t f3bc5x_b5_d1; + uint8_t f3bc8x_b5_d1; + uint8_t f3bc9x_b5_d1; + uint8_t f3bcax_b5_d1; + uint8_t f3bcbx_b5_d1; + uint8_t f0bc2x_b6_d1; + uint8_t f0bc3x_b6_d1; + uint8_t f0bc4x_b6_d1; + uint8_t f0bc5x_b6_d1; + uint8_t f0bc8x_b6_d1; + uint8_t f0bc9x_b6_d1; + uint8_t f0bcax_b6_d1; + uint8_t f0bcbx_b6_d1; + uint8_t f1bc2x_b6_d1; + uint8_t f1bc3x_b6_d1; + uint8_t f1bc4x_b6_d1; + uint8_t f1bc5x_b6_d1; + uint8_t f1bc8x_b6_d1; + uint8_t f1bc9x_b6_d1; + uint8_t f1bcax_b6_d1; + uint8_t f1bcbx_b6_d1; + uint8_t f2bc2x_b6_d1; + uint8_t f2bc3x_b6_d1; + uint8_t f2bc4x_b6_d1; + uint8_t f2bc5x_b6_d1; + uint8_t f2bc8x_b6_d1; + uint8_t f2bc9x_b6_d1; + uint8_t f2bcax_b6_d1; + uint8_t f2bcbx_b6_d1; + uint8_t f3bc2x_b6_d1; + uint8_t f3bc3x_b6_d1; + uint8_t f3bc4x_b6_d1; + uint8_t f3bc5x_b6_d1; + uint8_t f3bc8x_b6_d1; + uint8_t f3bc9x_b6_d1; + uint8_t f3bcax_b6_d1; + uint8_t f3bcbx_b6_d1; + uint8_t f0bc2x_b7_d1; + uint8_t f0bc3x_b7_d1; + uint8_t f0bc4x_b7_d1; + uint8_t f0bc5x_b7_d1; + uint8_t f0bc8x_b7_d1; + uint8_t f0bc9x_b7_d1; + uint8_t f0bcax_b7_d1; + uint8_t f0bcbx_b7_d1; + uint8_t f1bc2x_b7_d1; + uint8_t f1bc3x_b7_d1; + uint8_t f1bc4x_b7_d1; + uint8_t f1bc5x_b7_d1; + uint8_t f1bc8x_b7_d1; + uint8_t f1bc9x_b7_d1; + uint8_t f1bcax_b7_d1; + uint8_t f1bcbx_b7_d1; + uint8_t f2bc2x_b7_d1; + uint8_t f2bc3x_b7_d1; + uint8_t f2bc4x_b7_d1; + uint8_t f2bc5x_b7_d1; + uint8_t f2bc8x_b7_d1; + uint8_t f2bc9x_b7_d1; + uint8_t f2bcax_b7_d1; + uint8_t f2bcbx_b7_d1; + uint8_t f3bc2x_b7_d1; + uint8_t f3bc3x_b7_d1; + uint8_t f3bc4x_b7_d1; + uint8_t f3bc5x_b7_d1; + uint8_t f3bc8x_b7_d1; + uint8_t f3bc9x_b7_d1; + uint8_t f3bcax_b7_d1; + uint8_t f3bcbx_b7_d1; + uint8_t f0bc2x_b8_d1; + uint8_t f0bc3x_b8_d1; + uint8_t f0bc4x_b8_d1; + uint8_t f0bc5x_b8_d1; + uint8_t f0bc8x_b8_d1; + uint8_t f0bc9x_b8_d1; + uint8_t f0bcax_b8_d1; + uint8_t f0bcbx_b8_d1; + uint8_t f1bc2x_b8_d1; + uint8_t f1bc3x_b8_d1; + uint8_t f1bc4x_b8_d1; + uint8_t f1bc5x_b8_d1; + uint8_t f1bc8x_b8_d1; + uint8_t f1bc9x_b8_d1; + uint8_t f1bcax_b8_d1; + uint8_t f1bcbx_b8_d1; + uint8_t f2bc2x_b8_d1; + uint8_t f2bc3x_b8_d1; + uint8_t f2bc4x_b8_d1; + uint8_t f2bc5x_b8_d1; + uint8_t f2bc8x_b8_d1; + uint8_t f2bc9x_b8_d1; + uint8_t f2bcax_b8_d1; + uint8_t f2bcbx_b8_d1; + uint8_t f3bc2x_b8_d1; + uint8_t f3bc3x_b8_d1; + uint8_t f3bc4x_b8_d1; + uint8_t f3bc5x_b8_d1; + uint8_t f3bc8x_b8_d1; + uint8_t f3bc9x_b8_d1; + uint8_t f3bcax_b8_d1; + uint8_t f3bcbx_b8_d1; + uint8_t f5bc5x_d1; + uint8_t f5bc6x_d1; + uint8_t f4bc8x_d1; + uint8_t f4bc9x_d1; + uint8_t f4bcax_d1; + uint8_t f4bcbx_d1; + uint8_t f4bccx_d1; + uint8_t f4bcdx_d1; + uint8_t f4bcex_d1; + uint8_t f4bcfx_d1; + uint8_t f5bc8x_d1; + uint8_t f5bc9x_d1; + uint8_t f5bcax_d1; + uint8_t f5bcbx_d1; + uint8_t f5bccx_d1; + uint8_t f5bcdx_d1; + uint8_t f5bcex_d1; + uint8_t f5bcfx_d1; + uint8_t f6bc8x_d1; + uint8_t f6bc9x_d1; + uint8_t f6bcax_d1; + uint8_t f6bcbx_d1; + uint8_t f6bccx_d1; + uint8_t f6bcdx_d1; + uint8_t f6bcex_d1; + uint8_t f6bcfx_d1; + uint8_t f7bc8x_d1; + uint8_t f7bc9x_d1; + uint8_t f7bcax_d1; + uint8_t f7bcbx_d1; + uint8_t f7bccx_d1; + uint8_t f7bcdx_d1; + uint8_t f7bcex_d1; + uint8_t f7bcfx_d1; + uint16_t alt_cas_l; + uint8_t alt_wcas_l; + uint8_t d4misc; +} __packed; +#endif diff --git a/drivers/nxp/ddr/phy-gen2/ddrphy.mk b/drivers/nxp/ddr/phy-gen2/ddrphy.mk new file mode 100644 index 0000000..ba5c774 --- /dev/null +++ b/drivers/nxp/ddr/phy-gen2/ddrphy.mk @@ -0,0 +1,20 @@ +# +# Copyright 2021 NXP +# +# SPDX-License-Identifier: BSD-3-Clause +# +# +#----------------------------------------------------------------------------- + +# SNPS ddr phy driver files + +DDR_PHY_C = +DDR_PHY_H = + +$(DDR_PHY_C): $(DDR_PHY_H) $(COMMON_HDRS) src + @cp -r "$(DDR_PHY_PATH)/$@" "$(SRC_DIR)/$@" + +$(DDR_PHY_H): src + @cp -r "$(DDR_PHY_PATH)/$@" "$(SRC_DIR)/$@" + +#------------------------------------------------ diff --git a/drivers/nxp/ddr/phy-gen2/input.h b/drivers/nxp/ddr/phy-gen2/input.h new file mode 100644 index 0000000..dbcd1ae --- /dev/null +++ b/drivers/nxp/ddr/phy-gen2/input.h @@ -0,0 +1,106 @@ +/* + * Copyright 2021 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _INPUT_H_ +#define _INPUT_H_ + +enum dram_types { + DDR4, + DDR3, + LPDDR4, + LPDDR3, + LPDDR2, + DDR5, +}; + +enum dimm_types { + UDIMM, + SODIMM, + RDIMM, + LRDIMM, + NODIMM, +}; + +struct input_basic { + enum dram_types dram_type; + enum dimm_types dimm_type; + int lp4x_mode; /* 0x1 = lpddr4x mode, when dram_type is lpddr4 + */ + /* not used for protocols other than lpddr4 */ + int num_dbyte; /* number of dbytes physically instantiated */ + int num_active_dbyte_dfi0; /* number of active dbytes to be + * controlled by dfi0 + */ + int num_active_dbyte_dfi1; /* number of active dbytes to be + * controlled by dfi1. Not used for + * protocols other than lpddr3 and + * lpddr4 + */ + int num_anib; /* number of anibs physically instantiated */ + int num_rank_dfi0; /* number of ranks in dfi0 channel */ + int num_rank_dfi1; /* number of ranks in dfi1 channel */ + int dram_data_width; /* 4,8,16 or 32 depending on protocol and dram + * type + */ + int num_pstates; + int frequency; /* memclk frequency in mhz -- round up */ + int pll_bypass; /* pll bypass enable */ + int dfi_freq_ratio; /* selected dfi frequency ratio */ + int dfi1exists; /* whether they phy config has dfi1 channel */ + int train2d; + int hard_macro_ver; + int read_dbienable; + int dfi_mode; /* no longer used */ +}; + +struct input_advanced { + int d4rx_preamble_length; + int d4tx_preamble_length; + int ext_cal_res_val; /* external pull-down resistor */ + int is2ttiming; + int odtimpedance; + int tx_impedance; + int atx_impedance; + int mem_alert_en; + int mem_alert_puimp; + int mem_alert_vref_level; + int mem_alert_sync_bypass; + int dis_dyn_adr_tri; + int phy_mstr_train_interval; + int phy_mstr_max_req_to_ack; + int wdqsext; + int cal_interval; + int cal_once; + int dram_byte_swap; + int rx_en_back_off; + int train_sequence_ctrl; + int phy_gen2_umctl_opt; + int phy_gen2_umctl_f0rc5x; + int tx_slew_rise_dq; + int tx_slew_fall_dq; + int tx_slew_rise_ac; + int tx_slew_fall_ac; + int enable_high_clk_skew_fix; + int disable_unused_addr_lns; + int phy_init_sequence_num; + int cs_mode; /* rdimm */ + int cast_cs_to_cid; /* rdimm */ +}; + +struct input { + struct input_basic basic; + struct input_advanced adv; + unsigned int mr[7]; + unsigned int cs_d0; + unsigned int cs_d1; + unsigned int mirror; + unsigned int odt[4]; + unsigned int rcw[16]; + unsigned int rcw3x; + unsigned int vref; +}; + +#endif diff --git a/drivers/nxp/ddr/phy-gen2/messages.h b/drivers/nxp/ddr/phy-gen2/messages.h new file mode 100644 index 0000000..7dec7df --- /dev/null +++ b/drivers/nxp/ddr/phy-gen2/messages.h @@ -0,0 +1,2909 @@ +/* + * Copyright 2021 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef MESSAGE_H +#define MESSAGE_H + +#ifdef DEBUG +struct phy_msg { + uint32_t index; + const char *msg; +}; + +const static struct phy_msg messages_1d[] = { + {0x00000001, + "PMU1:prbsGenCtl:%x\n" + }, + {0x00010000, + "PMU1: loading 2D acsm sequence\n" + }, + {0x00020000, + "PMU1: loading 1D acsm sequence\n" + }, + {0x00030002, + "PMU3: %d memclocks @ %d to get half of 300ns\n" + }, + {0x00040000, + "PMU: Error: User requested MPR read pattern for read DQS training in DDR3 Mode\n" + }, + {0x00050000, + "PMU3: Running 1D search for left eye edge\n" + }, + {0x00060001, + "PMU1: In Phase Left Edge Search cs %d\n" + }, + {0x00070001, + "PMU1: Out of Phase Left Edge Search cs %d\n" + }, + {0x00080000, + "PMU3: Running 1D search for right eye edge\n" + }, + {0x00090001, + "PMU1: In Phase Right Edge Search cs %d\n" + }, + {0x000a0001, + "PMU1: Out of Phase Right Edge Search cs %d\n" + }, + {0x000b0001, + "PMU1: mxRdLat training pstate %d\n" + }, + {0x000c0001, + "PMU1: mxRdLat search for cs %d\n" + }, + {0x000d0001, + "PMU0: MaxRdLat non consistent DtsmLoThldXingInd 0x%03x\n" + }, + {0x000e0003, + "PMU4: CS %d Dbyte %d worked with DFIMRL = %d DFICLKs\n" + }, + {0x000f0004, + "PMU3: MaxRdLat Read Lane err mask for csn %d, DFIMRL %2d DFIClks, dbyte %d = 0x%03x\n" + }, + {0x00100003, + "PMU3: MaxRdLat Read Lane err mask for csn %d DFIMRL %2d, All dbytes = 0x%03x\n" + }, + {0x00110001, + "PMU: Error: CS%d failed to find a DFIMRL setting that worked for all bytes during MaxRdLat training\n" + }, + {0x00120002, + "PMU3: Smallest passing DFIMRL for all dbytes in CS%d = %d DFIClks\n" + }, + {0x00130000, + "PMU: Error: No passing DFIMRL value found for any chip select during MaxRdLat training\n" + }, + {0x00140003, + "PMU: Error: Dbyte %d lane %d txDqDly passing region is too small (width = %d)\n" + }, + {0x00150006, + "PMU10: Adjusting rxclkdly db %d nib %d from %d+%d=%d->%d\n" + }, + {0x00160000, + "PMU4: TxDqDly Passing Regions (EyeLeft EyeRight -> EyeCenter) Units=1/32 UI\n" + }, + {0x00170005, + "PMU4: DB %d Lane %d: %3d %3d -> %3d\n" + }, + {0x00180002, + "PMU2: TXDQ delayLeft[%2d] = %3d (DISCONNECTED)\n" + }, + {0x00190004, + "PMU2: TXDQ delayLeft[%2d] = %3d oopScaled = %3d selectOop %d\n" + }, + {0x001a0002, + "PMU2: TXDQ delayRight[%2d] = %3d (DISCONNECTED)\n" + }, + {0x001b0004, + "PMU2: TXDQ delayRight[%2d] = %3d oopScaled = %3d selectOop %d\n" + }, + {0x001c0003, + "PMU: Error: Dbyte %d lane %d txDqDly passing region is too small (width = %d)\n" + }, + {0x001d0000, + "PMU4: TxDqDly Passing Regions (EyeLeft EyeRight -> EyeCenter) Units=1/32 UI\n" + }, + {0x001e0002, + "PMU4: DB %d Lane %d: (DISCONNECTED)\n" + }, + {0x001f0005, + "PMU4: DB %d Lane %d: %3d %3d -> %3d\n" + }, + {0x00200002, + "PMU3: Running 1D search csn %d for DM Right/NotLeft(%d) eye edge\n" + }, + {0x00210002, + "PMU3: WrDq DM byte%2d with Errcnt %d\n" + }, + {0x00220002, + "PMU3: WrDq DM byte%2d avgDly 0x%04x\n" + }, + {0x00230002, + "PMU1: WrDq DM byte%2d with Errcnt %d\n" + }, + {0x00240001, + "PMU: Error: Dbyte %d txDqDly DM training did not start inside the eye\n" + }, + {0x00250000, + "PMU4: DM TxDqDly Passing Regions (EyeLeft EyeRight -> EyeCenter) Units=1/32 UI\n" + }, + {0x00260002, + "PMU4: DB %d Lane %d: (DISCONNECTED)\n" + }, + {0x00270005, + "PMU4: DB %d Lane %d: %3d %3d -> %3d\n" + }, + {0x00280003, + "PMU: Error: Dbyte %d lane %d txDqDly DM passing region is too small (width = %d)\n" + }, + {0x00290004, + "PMU3: Errcnt for MRD/MWD search nib %2d delay = (%d, 0x%02x) = %d\n" + }, + {0x002a0000, + "PMU3: Precharge all open banks\n" + }, + {0x002b0002, + "PMU: Error: Dbyte %d nibble %d found mutliple working coarse delay setting for MRD/MWD\n" + }, + {0x002c0000, + "PMU4: MRD Passing Regions (coarseVal, fineLeft fineRight -> fineCenter)\n" + }, + {0x002d0000, + "PMU4: MWD Passing Regions (coarseVal, fineLeft fineRight -> fineCenter)\n" + }, + {0x002e0004, + "PMU10: Warning: DB %d nibble %d has multiple working coarse delays, %d and %d, choosing the smaller delay\n" + }, + {0x002f0003, + "PMU: Error: Dbyte %d nibble %d MRD/MWD passing region is too small (width = %d)\n" + }, + {0x00300006, + "PMU4: DB %d nibble %d: %3d, %3d %3d -> %3d\n" + }, + {0x00310002, + "PMU1: Start MRD/nMWD %d for csn %d\n" + }, + {0x00320002, + "PMU2: RXDQS delayLeft[%2d] = %3d (DISCONNECTED)\n" + }, + {0x00330006, + "PMU2: RXDQS delayLeft[%2d] = %3d delayOop[%2d] = %3d OopScaled %4d, selectOop %d\n" + }, + {0x00340002, + "PMU2: RXDQS delayRight[%2d] = %3d (DISCONNECTED)\n" + }, + {0x00350006, + "PMU2: RXDQS delayRight[%2d] = %3d delayOop[%2d] = %4d OopScaled %4d, selectOop %d\n" + }, + {0x00360000, + "PMU4: RxClkDly Passing Regions (EyeLeft EyeRight -> EyeCenter)\n" + }, + {0x00370002, + "PMU4: DB %d nibble %d: (DISCONNECTED)\n" + }, + {0x00380005, + "PMU4: DB %d nibble %d: %3d %3d -> %3d\n" + }, + {0x00390003, + "PMU: Error: Dbyte %d nibble %d rxClkDly passing region is too small (width = %d)\n" + }, + {0x003a0002, + "PMU0: goodbar = %d for RDWR_BLEN %d\n" + }, + {0x003b0001, + "PMU3: RxClkDly = %d\n" + }, + {0x003c0005, + "PMU0: db %d l %d absLane %d -> bottom %d top %d\n" + }, + {0x003d0009, + "PMU3: BYTE %d - %3d %3d %3d %3d %3d %3d %3d %3d\n" + }, + {0x003e0002, + "PMU: Error: dbyte %d lane %d's per-lane vrefDAC's had no passing region\n" + }, + {0x003f0004, + "PMU0: db%d l%d - %d %d\n" + }, + {0x00400002, + "PMU0: goodbar = %d for RDWR_BLEN %d\n" + }, + {0x00410004, + "PMU3: db%d l%d saw %d issues at rxClkDly %d\n" + }, + {0x00420003, + "PMU3: db%d l%d first saw a pass->fail edge at rxClkDly %d\n" + }, + {0x00430002, + "PMU3: lane %d PBD = %d\n" + }, + {0x00440003, + "PMU3: db%d l%d first saw a DBI pass->fail edge at rxClkDly %d\n" + }, + {0x00450003, + "PMU2: db%d l%d already passed rxPBD = %d\n" + }, + {0x00460003, + "PMU0: db%d l%d, PBD = %d\n" + }, + {0x00470002, + "PMU: Error: dbyte %d lane %d failed read deskew\n" + }, + {0x00480003, + "PMU0: db%d l%d, inc PBD = %d\n" + }, + {0x00490003, + "PMU1: Running lane deskew on pstate %d csn %d rdDBIEn %d\n" + }, + {0x004a0000, + "PMU: Error: Read deskew training has been requested, but csrMajorModeDbyte[2] is set\n" + }, + {0x004b0002, + "PMU1: AcsmCsMapCtrl%02d 0x%04x\n" + }, + {0x004c0002, + "PMU1: AcsmCsMapCtrl%02d 0x%04x\n" + }, + {0x004d0001, + "PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D3U Type\n" + }, + {0x004e0001, + "PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D3R Type\n" + }, + {0x004f0001, + "PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D4U Type\n" + }, + {0x00500001, + "PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D4R Type\n" + }, + {0x00510001, + "PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D4LR Type\n" + }, + {0x00520000, + "PMU: Error: Both 2t timing mode and ddr4 geardown mode specified in the messageblock's PhyCfg and MR3 fields. Only one can be enabled\n" + }, + {0x00530003, + "PMU10: PHY TOTALS - NUM_DBYTES %d NUM_NIBBLES %d NUM_ANIBS %d\n" + }, + {0x00540006, + "PMU10: CSA=0x%02x, CSB=0x%02x, TSTAGES=0x%04x, HDTOUT=%d, MMISC=%d DRAMFreq=%dMT DramType=LPDDR3\n" + }, + {0x00550006, + "PMU10: CSA=0x%02x, CSB=0x%02x, TSTAGES=0x%04x, HDTOUT=%d, MMISC=%d DRAMFreq=%dMT DramType=LPDDR4\n" + }, + {0x00560008, + "PMU10: CS=0x%02x, TSTAGES=0x%04x, HDTOUT=%d, 2T=%d, MMISC=%d AddrMirror=%d DRAMFreq=%dMT DramType=%d\n" + }, + {0x00570004, + "PMU10: Pstate%d MR0=0x%04x MR1=0x%04x MR2=0x%04x\n" + }, + {0x00580008, + "PMU10: Pstate%d MRS MR0=0x%04x MR1=0x%04x MR2=0x%04x MR3=0x%04x MR4=0x%04x MR5=0x%04x MR6=0x%04x\n" + }, + {0x00590005, + "PMU10: Pstate%d MRS MR1_A0=0x%04x MR2_A0=0x%04x MR3_A0=0x%04x MR11_A0=0x%04x\n" + }, + {0x005a0000, + "PMU10: UseBroadcastMR set. All ranks and channels use MRXX_A0 for MR settings.\n" + }, + {0x005b0005, + "PMU10: Pstate%d MRS MR01_A0=0x%02x MR02_A0=0x%02x MR03_A0=0x%02x MR11_A0=0x%02x\n" + }, + {0x005c0005, + "PMU10: Pstate%d MRS MR12_A0=0x%02x MR13_A0=0x%02x MR14_A0=0x%02x MR22_A0=0x%02x\n" + }, + {0x005d0005, + "PMU10: Pstate%d MRS MR01_A1=0x%02x MR02_A1=0x%02x MR03_A1=0x%02x MR11_A1=0x%02x\n" + }, + {0x005e0005, + "PMU10: Pstate%d MRS MR12_A1=0x%02x MR13_A1=0x%02x MR14_A1=0x%02x MR22_A1=0x%02x\n" + }, + {0x005f0005, + "PMU10: Pstate%d MRS MR01_B0=0x%02x MR02_B0=0x%02x MR03_B0=0x%02x MR11_B0=0x%02x\n" + }, + {0x00600005, + "PMU10: Pstate%d MRS MR12_B0=0x%02x MR13_B0=0x%02x MR14_B0=0x%02x MR22_B0=0x%02x\n" + }, + {0x00610005, + "PMU10: Pstate%d MRS MR01_B1=0x%02x MR02_B1=0x%02x MR03_B1=0x%02x MR11_B1=0x%02x\n" + }, + {0x00620005, + "PMU10: Pstate%d MRS MR12_B1=0x%02x MR13_B1=0x%02x MR14_B1=0x%02x MR22_B1=0x%02x\n" + }, + {0x00630002, + "PMU1: AcsmOdtCtrl%02d 0x%02x\n" + }, + {0x00640002, + "PMU1: AcsmCsMapCtrl%02d 0x%04x\n" + }, + {0x00650002, + "PMU1: AcsmCsMapCtrl%02d 0x%04x\n" + }, + {0x00660000, + "PMU1: HwtCAMode set\n" + }, + {0x00670001, + "PMU3: DDR4 infinite preamble enter/exit mode %d\n" + }, + {0x00680002, + "PMU1: In rxenb_train() csn=%d pstate=%d\n" + }, + {0x00690000, + "PMU3: Finding DQS falling edge\n" + }, + {0x006a0000, + "PMU3: Searching for DDR3/LPDDR3/LPDDR4 read preamble\n" + }, + {0x006b0009, + "PMU3: dtsm fails Even Nibbles : %2x %2x %2x %2x %2x %2x %2x %2x %2x\n" + }, + {0x006c0009, + "PMU3: dtsm fails Odd Nibbles : %2x %2x %2x %2x %2x %2x %2x %2x %2x\n" + }, + {0x006d0002, + "PMU3: Preamble search pass=%d anyfail=%d\n" + }, + {0x006e0000, + "PMU: Error: RxEn training preamble not found\n" + }, + {0x006f0000, + "PMU3: Found DQS pre-amble\n" + }, + {0x00700001, + "PMU: Error: Dbyte %d couldn't find the rising edge of DQS during RxEn Training\n" + }, + {0x00710000, + "PMU3: RxEn aligning to first rising edge of burst\n" + }, + {0x00720001, + "PMU3: Decreasing RxEn delay by %d fine step to allow full capture of reads\n" + }, + {0x00730001, + "PMU3: MREP Delay = %d\n" + }, + {0x00740003, + "PMU3: Errcnt for MREP nib %2d delay = %2d is %d\n" + }, + {0x00750002, + "PMU3: MREP nibble %d sampled a 1 at data buffer delay %d\n" + }, + {0x00760002, + "PMU3: MREP nibble %d saw a 0 to 1 transition at data buffer delay %d\n" + }, + {0x00770000, + "PMU2: MREP did not find a 0 to 1 transition for all nibbles. Failing nibbles assumed to have rising edge close to fine delay 63\n" + }, + {0x00780002, + "PMU2: Rising edge found in alias window, setting rxDly for nibble %d = %d\n" + }, + {0x00790002, + "PMU: Error: Failed MREP for nib %d with %d one\n" + }, + {0x007a0003, + "PMU2: Rising edge not found in alias window with %d one, leaving rxDly for nibble %d = %d\n" + }, + {0x007b0002, + "PMU3: Training DIMM %d CSn %d\n" + }, + {0x007c0001, + "PMU3: exitCAtrain_lp3 cs 0x%x\n" + }, + {0x007d0001, + "PMU3: enterCAtrain_lp3 cs 0x%x\n" + }, + {0x007e0001, + "PMU3: CAtrain_switchmsb_lp3 cs 0x%x\n" + }, + {0x007f0001, + "PMU3: CATrain_rdwr_lp3 looking for pattern %x\n" + }, + {0x00800000, + "PMU3: exitCAtrain_lp4\n" + }, + {0x00810001, + "PMU3: DEBUG enterCAtrain_lp4 1: cs 0x%x\n" + }, + {0x00820001, + "PMU3: DEBUG enterCAtrain_lp4 3: Put dbyte %d in async mode\n" + }, + {0x00830000, + "PMU3: DEBUG enterCAtrain_lp4 5: Send MR13 to turn on CA training\n" + }, + {0x00840003, + "PMU3: DEBUG enterCAtrain_lp4 7: idx = %d vref = %x mr12 = %x\n" + }, + {0x00850001, + "PMU3: CATrain_rdwr_lp4 looking for pattern %x\n" + }, + {0x00860004, + "PMU3: Phase %d CAreadbackA db:%d %x xo:%x\n" + }, + {0x00870005, + "PMU3: DEBUG lp4SetCatrVref 1: cs=%d chan=%d mr12=%x vref=%d.%d%%\n" + }, + {0x00880003, + "PMU3: DEBUG lp4SetCatrVref 3: mr12 = %x send vref= %x to db=%d\n" + }, + {0x00890000, + "PMU10:Optimizing vref\n" + }, + {0x008a0004, + "PMU4:mr12:%2x cs:%d chan %d r:%4x\n" + }, + {0x008b0005, + "PMU3: i:%2d bstr:%2d bsto:%2d st:%d r:%d\n" + }, + {0x008c0002, + "Failed to find sufficient CA Vref Passing Region for CS %d ch. %d\n" + }, + {0x008d0005, + "PMU3:Found %d.%d%% MR12:%x for cs:%d chan %d\n" + }, + {0x008e0002, + "PMU3:Calculated %d for AtxImpedence from acx %d.\n" + }, + {0x008f0000, + "PMU3:CA Odt impedence ==0. Use default vref.\n" + }, + {0x00900003, + "PMU3:Calculated %d.%d%% for Vref MR12=0x%x.\n" + }, + {0x00910000, + "PMU3: CAtrain_lp\n" + }, + {0x00920000, + "PMU3: CAtrain Begins.\n" + }, + {0x00930001, + "PMU3: CAtrain_lp testing dly %d\n" + }, + {0x00940001, + "PMU5: CA bitmap dump for cs %x\n" + }, + {0x00950001, + "PMU5: CAA%d " + }, + {0x00960001, "%02x" + }, + {0x00970000, "\n" + }, + {0x00980001, + "PMU5: CAB%d " + }, + {0x00990001, "%02x" + }, + {0x009a0000, "\n" + }, + {0x009b0003, + "PMU3: anibi=%d, anibichan[anibi]=%d ,chan=%d\n" + }, + {0x009c0001, "%02x" + }, + {0x009d0001, "\nPMU3:Raw CA setting :%x" + }, + {0x009e0002, "\nPMU3:ATxDly setting:%x margin:%d\n" + }, + {0x009f0002, "\nPMU3:InvClk ATxDly setting:%x margin:%d\n" + }, + {0x00a00000, "\nPMU3:No Range found!\n" + }, + {0x00a10003, + "PMU3: 2 anibi=%d, anibichan[anibi]=%d ,chan=%d" + }, + {0x00a20002, "\nPMU3: no neg clock => CA setting anib=%d, :%d\n" + }, + {0x00a30001, + "PMU3:Normal margin:%d\n" + }, + {0x00a40001, + "PMU3:Inverted margin:%d\n" + }, + {0x00a50000, + "PMU3:Using Inverted clock\n" + }, + {0x00a60000, + "PMU3:Using normal clk\n" + }, + {0x00a70003, + "PMU3: 3 anibi=%d, anibichan[anibi]=%d ,chan=%d\n" + }, + {0x00a80002, + "PMU3: Setting ATxDly for anib %x to %x\n" + }, + {0x00a90000, + "PMU: Error: CA Training Failed.\n" + }, + {0x00aa0000, + "PMU1: Writing MRs\n" + }, + {0x00ab0000, + "PMU4:Using MR12 values from 1D CA VREF training.\n" + }, + {0x00ac0000, + "PMU3:Writing all MRs to fsp 1\n" + }, + {0x00ad0000, + "PMU10:Lp4Quickboot mode.\n" + }, + {0x00ae0000, + "PMU3: Writing MRs\n" + }, + {0x00af0001, + "PMU10: Setting boot clock divider to %d\n" + }, + {0x00b00000, + "PMU3: Resetting DRAM\n" + }, + {0x00b10000, + "PMU3: setup for RCD initalization\n" + }, + {0x00b20000, + "PMU3: pmu_exit_SR from dev_init()\n" + }, + {0x00b30000, + "PMU3: initializing RCD\n" + }, + {0x00b40000, + "PMU10: **** Executing 2D Image ****\n" + }, + {0x00b50001, + "PMU10: **** Start DDR4 Training. PMU Firmware Revision 0x%04x ****\n" + }, + {0x00b60001, + "PMU10: **** Start DDR3 Training. PMU Firmware Revision 0x%04x ****\n" + }, + {0x00b70001, + "PMU10: **** Start LPDDR3 Training. PMU Firmware Revision 0x%04x ****\n" + }, + {0x00b80001, + "PMU10: **** Start LPDDR4 Training. PMU Firmware Revision 0x%04x ****\n" + }, + {0x00b90000, + "PMU: Error: Mismatched internal revision between DCCM and ICCM images\n" + }, + {0x00ba0001, + "PMU10: **** Testchip %d Specific Firmware ****\n" + }, + {0x00bb0000, + "PMU1: LRDIMM with EncodedCS mode, one DIMM\n" + }, + {0x00bc0000, + "PMU1: LRDIMM with EncodedCS mode, two DIMMs\n" + }, + {0x00bd0000, + "PMU1: RDIMM with EncodedCS mode, one DIMM\n" + }, + {0x00be0000, + "PMU2: Starting LRDIMM MREP training for all ranks\n" + }, + {0x00bf0000, + "PMU199: LRDIMM MREP training for all ranks completed\n" + }, + {0x00c00000, + "PMU2: Starting LRDIMM DWL training for all ranks\n" + }, + {0x00c10000, + "PMU199: LRDIMM DWL training for all ranks completed\n" + }, + {0x00c20000, + "PMU2: Starting LRDIMM MRD training for all ranks\n" + }, + {0x00c30000, + "PMU199: LRDIMM MRD training for all ranks completed\n" + }, + {0x00c40000, + "PMU2: Starting RXEN training for all ranks\n" + }, + {0x00c50000, + "PMU2: Starting write leveling fine delay training for all ranks\n" + }, + {0x00c60000, + "PMU2: Starting LRDIMM MWD training for all ranks\n" + }, + {0x00c70000, + "PMU199: LRDIMM MWD training for all ranks completed\n" + }, + {0x00c80000, + "PMU2: Starting write leveling fine delay training for all ranks\n" + }, + {0x00c90000, + "PMU2: Starting read deskew training\n" + }, + {0x00ca0000, + "PMU2: Starting SI friendly 1d RdDqs training for all ranks\n" + }, + {0x00cb0000, + "PMU2: Starting write leveling coarse delay training for all ranks\n" + }, + {0x00cc0000, + "PMU2: Starting 1d WrDq training for all ranks\n" + }, + {0x00cd0000, + "PMU2: Running DQS2DQ Oscillator for all ranks\n" + }, + {0x00ce0000, + "PMU2: Starting again read deskew training but with PRBS\n" + }, + {0x00cf0000, + "PMU2: Starting 1d RdDqs training for all ranks\n" + }, + {0x00d00000, + "PMU2: Starting again 1d WrDq training for all ranks\n" + }, + {0x00d10000, + "PMU2: Starting MaxRdLat training\n" + }, + {0x00d20000, + "PMU2: Starting 2d WrDq training for all ranks\n" + }, + {0x00d30000, + "PMU2: Starting 2d RdDqs training for all ranks\n" + }, + {0x00d40002, + "PMU3:read_fifo %x %x\n" + }, + {0x00d50001, + "PMU: Error: Invalid PhyDrvImpedance of 0x%x specified in message block.\n" + }, + {0x00d60001, + "PMU: Error: Invalid PhyOdtImpedance of 0x%x specified in message block.\n" + }, + {0x00d70001, + "PMU: Error: Invalid BPZNResVal of 0x%x specified in message block.\n" + }, + {0x00d80005, + "PMU3: fixRxEnBackOff csn:%d db:%d dn:%d bo:%d dly:%x\n" + }, + {0x00d90001, + "PMU3: fixRxEnBackOff dly:%x\n" + }, + {0x00da0000, + "PMU3: Entering setupPpt\n" + }, + {0x00db0000, + "PMU3: Start lp4PopulateHighLowBytes\n" + }, + {0x00dc0002, + "PMU3:Dbyte Detect: db%d received %x\n" + }, + {0x00dd0002, + "PMU3:getDqs2Dq read %x from dbyte %d\n" + }, + {0x00de0002, + "PMU3:getDqs2Dq(2) read %x from dbyte %d\n" + }, + {0x00df0001, + "PMU: Error: Dbyte %d read 0 from the DQS oscillator it is connected to\n" + }, + {0x00e00002, + "PMU4: Dbyte %d dqs2dq = %d/32 UI\n" + }, + {0x00e10003, + "PMU3:getDqs2Dq set dqs2dq:%d/32 ui (%d ps) from dbyte %d\n" + }, + {0x00e20003, + "PMU3: Setting coarse delay in AtxDly chiplet %d from 0x%02x to 0x%02x\n" + }, + {0x00e30003, + "PMU3: Clearing coarse delay in AtxDly chiplet %d from 0x%02x to 0x%02x\n" + }, + {0x00e40000, + "PMU3: Performing DDR4 geardown sync sequence\n" + }, + {0x00e50000, + "PMU1: Enter self refresh\n" + }, + {0x00e60000, + "PMU1: Exit self refresh\n" + }, + {0x00e70000, + "PMU: Error: No dbiEnable with lp4\n" + }, + {0x00e80000, + "PMU: Error: No dbiDisable with lp4\n" + }, + {0x00e90001, + "PMU1: DDR4 update Rx DBI Setting disable %d\n" + }, + {0x00ea0001, + "PMU1: DDR4 update 2nCk WPre Setting disable %d\n" + }, + {0x00eb0005, + "PMU1: read_delay: db%d lane%d delays[%2d] = 0x%02x (max 0x%02x)\n" + }, + {0x00ec0004, + "PMU1: write_delay: db%d lane%d delays[%2d] = 0x%04x\n" + }, + {0x00ed0001, + "PMU5: ID=%d -- db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 --\n" + }, + {0x00ee000b, + "PMU5: [%d]:0x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n" + }, + {0x00ef0003, + "PMU2: dump delays - pstate=%d dimm=%d csn=%d\n" + }, + {0x00f00000, + "PMU3: Printing Mid-Training Delay Information\n" + }, + {0x00f10001, + "PMU5: CS%d <<KEY>> 0 TrainingCntr <<KEY>> coarse(15:10) fine(9:0)\n" + }, + {0x00f20001, + "PMU5: CS%d <<KEY>> 0 RxEnDly, 1 RxClkDly <<KEY>> coarse(10:6) fine(5:0)\n" + }, + {0x00f30001, + "PMU5: CS%d <<KEY>> 0 TxDqsDly, 1 TxDqDly <<KEY>> coarse(9:6) fine(5:0)\n" + }, + {0x00f40001, + "PMU5: CS%d <<KEY>> 0 RxPBDly <<KEY>> 1 Delay Unit ~= 7ps\n" + }, + {0x00f50000, + "PMU5: all CS <<KEY>> 0 DFIMRL <<KEY>> Units = DFI clocks\n" + }, + {0x00f60000, + "PMU5: all CS <<KEY>> VrefDACs <<KEY>> DAC(6:0)\n" + }, + {0x00f70000, + "PMU1: Set DMD in MR13 and wrDBI in MR3 for training\n" + }, + {0x00f80000, + "PMU: Error: getMaxRxen() failed to find largest rxen nibble delay\n" + }, + {0x00f90003, + "PMU2: getMaxRxen(): maxDly %d maxTg %d maxNib %d\n" + }, + {0x00fa0003, + "PMU2: getRankMaxRxen(): maxDly %d Tg %d maxNib %d\n" + }, + {0x00fb0000, + "PMU1: skipping CDD calculation in 2D image\n" + }, + {0x00fc0001, + "PMU3: Calculating CDDs for pstate %d\n" + }, + {0x00fd0003, + "PMU3: rxFromDly[%d][%d] = %d\n" + }, + {0x00fe0003, + "PMU3: rxToDly [%d][%d] = %d\n" + }, + {0x00ff0003, + "PMU3: rxDly [%d][%d] = %d\n" + }, + {0x01000003, + "PMU3: txDly [%d][%d] = %d\n" + }, + {0x01010003, + "PMU3: allFine CDD_RR_%d_%d = %d\n" + }, + {0x01020003, + "PMU3: allFine CDD_WW_%d_%d = %d\n" + }, + {0x01030003, + "PMU3: CDD_RR_%d_%d = %d\n" + }, + {0x01040003, + "PMU3: CDD_WW_%d_%d = %d\n" + }, + {0x01050003, + "PMU3: allFine CDD_RW_%d_%d = %d\n" + }, + {0x01060003, + "PMU3: allFine CDD_WR_%d_%d = %d\n" + }, + {0x01070003, + "PMU3: CDD_RW_%d_%d = %d\n" + }, + {0x01080003, + "PMU3: CDD_WR_%d_%d = %d\n" + }, + {0x01090004, + "PMU3: F%dBC2x_B%d_D%d = 0x%02x\n" + }, + {0x010a0004, + "PMU3: F%dBC3x_B%d_D%d = 0x%02x\n" + }, + {0x010b0004, + "PMU3: F%dBC4x_B%d_D%d = 0x%02x\n" + }, + {0x010c0004, + "PMU3: F%dBC5x_B%d_D%d = 0x%02x\n" + }, + {0x010d0004, + "PMU3: F%dBC8x_B%d_D%d = 0x%02x\n" + }, + {0x010e0004, + "PMU3: F%dBC9x_B%d_D%d = 0x%02x\n" + }, + {0x010f0004, + "PMU3: F%dBCAx_B%d_D%d = 0x%02x\n" + }, + {0x01100004, + "PMU3: F%dBCBx_B%d_D%d = 0x%02x\n" + }, + {0x01110000, + "PMU10: Entering context_switch_postamble\n" + }, + {0x01120003, + "PMU10: context_switch_postamble is enabled for DIMM %d, RC0A=0x%x, RC3x=0x%x\n" + }, + {0x01130000, + "PMU10: Setting bcw fspace 0\n" + }, + {0x01140001, + "PMU10: Sending BC0A = 0x%x\n" + }, + {0x01150001, + "PMU10: Sending BC6x = 0x%x\n" + }, + {0x01160001, + "PMU10: Sending RC0A = 0x%x\n" + }, + {0x01170001, + "PMU10: Sending RC3x = 0x%x\n" + }, + {0x01180001, + "PMU10: Sending RC0A = 0x%x\n" + }, + {0x01190001, + "PMU1: enter_lp3: DEBUG: pstate = %d\n" + }, + {0x011a0001, + "PMU1: enter_lp3: DEBUG: dfifreqxlat_pstate = %d\n" + }, + {0x011b0001, + "PMU1: enter_lp3: DEBUG: pllbypass = %d\n" + }, + {0x011c0001, + "PMU1: enter_lp3: DEBUG: forcecal = %d\n" + }, + {0x011d0001, + "PMU1: enter_lp3: DEBUG: pllmaxrange = 0x%x\n" + }, + {0x011e0001, + "PMU1: enter_lp3: DEBUG: dacval_out = 0x%x\n" + }, + {0x011f0001, + "PMU1: enter_lp3: DEBUG: pllctrl3 = 0x%x\n" + }, + {0x01200000, + "PMU3: Loading DRAM with BIOS supplied MR values and entering self refresh prior to exiting PMU code.\n" + }, + {0x01210002, + "PMU3: Setting DataBuffer function space of dimmcs 0x%02x to %d\n" + }, + {0x01220002, + "PMU4: Setting RCW FxRC%Xx = 0x%02x\n" + }, + {0x01230002, + "PMU4: Setting RCW FxRC%02x = 0x%02x\n" + }, + {0x01240001, + "PMU1: DDR4 update Rd Pre Setting disable %d\n" + }, + {0x01250002, + "PMU2: Setting BCW FxBC%Xx = 0x%02x\n" + }, + {0x01260002, + "PMU2: Setting BCW BC%02x = 0x%02x\n" + }, + {0x01270002, + "PMU2: Setting BCW PBA mode FxBC%Xx = 0x%02x\n" + }, + {0x01280002, + "PMU2: Setting BCW PBA mode BC%02x = 0x%02x\n" + }, + {0x01290003, + "PMU4: BCW value for dimm %d, fspace %d, addr 0x%04x\n" + }, + {0x012a0002, + "PMU4: DB %d, value 0x%02x\n" + }, + {0x012b0000, + "PMU6: WARNING MREP underflow, set to min value -2 coarse, 0 fine\n" + }, + {0x012c0004, + "PMU6: LRDIMM Writing final data buffer fine delay value nib %2d, trainDly %3d, fineDly code %2d, new MREP fine %2d\n" + }, + {0x012d0003, + "PMU6: LRDIMM Writing final data buffer fine delay value nib %2d, trainDly %3d, fineDly code %2d\n" + }, + {0x012e0003, + "PMU6: LRDIMM Writing data buffer fine delay type %d nib %2d, code %2d\n" + }, + {0x012f0002, + "PMU6: Writing final data buffer coarse delay value dbyte %2d, coarse = 0x%02x\n" + }, + {0x01300003, + "PMU4: data 0x%04x at MB addr 0x%08x saved at CSR addr 0x%08x\n" + }, + {0x01310003, + "PMU4: data 0x%04x at MB addr 0x%08x restored from CSR addr 0x%08x\n" + }, + {0x01320003, + "PMU4: data 0x%04x at MB addr 0x%08x saved at CSR addr 0x%08x\n" + }, + {0x01330003, + "PMU4: data 0x%04x at MB addr 0x%08x restored from CSR addr 0x%08x\n" + }, + {0x01340001, + "PMU3: Update BC00, BC01, BC02 for rank-dimm 0x%02x\n" + }, + {0x01350000, + "PMU3: Writing D4 RDIMM RCD Control words F0RC00 -> F0RC0F\n" + }, + {0x01360000, + "PMU3: Disable parity in F0RC0E\n" + }, + {0x01370000, + "PMU3: Writing D4 RDIMM RCD Control words F1RC00 -> F1RC05\n" + }, + {0x01380000, + "PMU3: Writing D4 RDIMM RCD Control words F1RC1x -> F1RC9x\n" + }, + {0x01390000, + "PMU3: Writing D4 Data buffer Control words BC00 -> BC0E\n" + }, + {0x013a0002, + "PMU1: setAltCL Sending MR0 0x%x cl=%d\n" + }, + {0x013b0002, + "PMU1: restoreFromAltCL Sending MR0 0x%x cl=%d\n" + }, + {0x013c0002, + "PMU1: restoreAcsmFromAltCL Sending MR0 0x%x cl=%d\n" + }, + {0x013d0002, + "PMU2: Setting D3R RC%d = 0x%01x\n" + }, + {0x013e0000, + "PMU3: Writing D3 RDIMM RCD Control words RC0 -> RC11\n" + }, + {0x013f0002, + "PMU0: VrefDAC0/1 vddqStart %d dacToVddq %d\n" + }, + {0x01400001, + "PMU: Error: Messageblock phyVref=0x%x is above the limit for TSMC28's attenuated LPDDR4 receivers. Please see the pub databook\n" + }, + {0x01410001, + "PMU: Error: Messageblock phyVref=0x%x is above the limit for TSMC28's attenuated DDR4 receivers. Please see the pub databook\n" + }, + {0x01420001, + "PMU0: PHY VREF @ (%d/1000) VDDQ\n" + }, + {0x01430002, + "PMU0: initalizing phy vrefDacs to %d ExtVrefRange %x\n" + }, + {0x01440002, + "PMU0: initalizing global vref to %d range %d\n" + }, + {0x01450002, + "PMU4: Setting initial device vrefDQ for CS%d to MR6 = 0x%04x\n" + }, + {0x01460003, + "PMU1: In write_level_fine() csn=%d dimm=%d pstate=%d\n" + }, + {0x01470000, + "PMU3: Fine write leveling hardware search increasing TxDqsDly until full bursts are seen\n" + }, + {0x01480000, + "PMU4: WL normalized pos : ........................|........................\n" + }, + {0x01490007, + "PMU4: WL margin for nib %2d: %08x%08x%08x%08x%08x%08x\n" + }, + {0x014a0000, + "PMU4: WL normalized pos : ........................|........................\n" + }, + {0x014b0000, + "PMU3: Exiting write leveling mode\n" + }, + {0x014c0001, + "PMU3: got %d for cl in load_wrlvl_acsm\n" + }, + {0x014d0003, + "PMU1: In write_level_coarse() csn=%d dimm=%d pstate=%d\n" + }, + {0x014e0003, + "PMU3: left eye edge search db:%d ln:%d dly:0x%x\n" + }, + {0x014f0003, + "PMU3: right eye edge search db:%d ln:%d dly:0x%x\n" + }, + {0x01500004, + "PMU3: eye center db:%d ln:%d dly:0x%x (maxdq:%x)\n" + }, + {0x01510003, + "PMU3: Wrote to TxDqDly db:%d ln:%d dly:0x%x\n" + }, + {0x01520003, + "PMU3: Wrote to TxDqDly db:%d ln:%d dly:0x%x\n" + }, + {0x01530002, + "PMU3: Coarse write leveling dbyte%2d is still failing for TxDqsDly=0x%04x\n" + }, + {0x01540002, + "PMU4: Coarse write leveling iteration %d saw %d data miscompares across the entire phy\n" + }, + {0x01550000, + "PMU: Error: Failed write leveling coarse\n" + }, + {0x01560001, + "PMU3: got %d for cl in load_wrlvl_acsm\n" + }, + {0x01570003, + "PMU3: In write_level_coarse() csn=%d dimm=%d pstate=%d\n" + }, + {0x01580003, + "PMU3: left eye edge search db:%d ln:%d dly:0x%x\n" + }, + {0x01590003, + "PMU3: right eye edge search db: %d ln: %d dly: 0x%x\n" + }, + {0x015a0004, + "PMU3: eye center db: %d ln: %d dly: 0x%x (maxdq: 0x%x)\n" + }, + {0x015b0003, + "PMU3: Wrote to TxDqDly db: %d ln: %d dly: 0x%x\n" + }, + {0x015c0003, + "PMU3: Wrote to TxDqDly db: %d ln: %d dly: 0x%x\n" + }, + {0x015d0002, + "PMU3: Coarse write leveling nibble%2d is still failing for TxDqsDly=0x%04x\n" + }, + {0x015e0002, + "PMU4: Coarse write leveling iteration %d saw %d data miscompares across the entire phy\n" + }, + {0x015f0000, + "PMU: Error: Failed write leveling coarse\n" + }, + {0x01600000, + "PMU4: WL normalized pos : ................................|................................\n" + }, + {0x01610009, + "PMU4: WL margin for nib %2d: %08x%08x%08x%08x%08x%08x%08x%08x\n" + }, + {0x01620000, + "PMU4: WL normalized pos : ................................|................................\n" + }, + {0x01630001, + "PMU8: Adjust margin after WL coarse to be larger than %d\n" + }, + {0x01640001, + "PMU: Error: All margin after write leveling coarse are smaller than minMargin %d\n" + }, + {0x01650002, + "PMU8: Decrement nib %d TxDqsDly by %d fine step\n" + }, + {0x01660003, + "PMU3: In write_level_coarse() csn=%d dimm=%d pstate=%d\n" + }, + {0x01670005, + "PMU2: Write level: dbyte %d nib%d dq/dmbi %2d dqsfine 0x%04x dqDly 0x%04x\n" + }, + {0x01680002, + "PMU3: Coarse write leveling nibble%2d is still failing for TxDqsDly=0x%04x\n" + }, + {0x01690002, + "PMU4: Coarse write leveling iteration %d saw %d data miscompares across the entire phy\n" + }, + {0x016a0000, + "PMU: Error: Failed write leveling coarse\n" + }, + {0x016b0001, + "PMU3: DWL delay = %d\n" + }, + {0x016c0003, + "PMU3: Errcnt for DWL nib %2d delay = %2d is %d\n" + }, + {0x016d0002, + "PMU3: DWL nibble %d sampled a 1 at delay %d\n" + }, + {0x016e0003, + "PMU3: DWL nibble %d passed at delay %d. Rising edge was at %d\n" + }, + {0x016f0000, + "PMU2: DWL did nto find a rising edge of memclk for all nibbles. Failing nibbles assumed to have rising edge close to fine delay 63\n" + }, + {0x01700002, + "PMU2: Rising edge found in alias window, setting wrlvlDly for nibble %d = %d\n" + }, + {0x01710002, + "PMU: Error: Failed DWL for nib %d with %d one\n" + }, + {0x01720003, + "PMU2: Rising edge not found in alias window with %d one, leaving wrlvlDly for nibble %d = %d\n" + }, + {0x04000000, + "PMU: Error:Mailbox Buffer Overflowed.\n" + }, + {0x04010000, + "PMU: Error:Mailbox Buffer Overflowed.\n" + }, + {0x04020000, + "PMU: ***** Assertion Error - terminating *****\n" + }, + {0x04030002, + "PMU1: swapByte db %d by %d\n" + }, + {0x04040003, + "PMU3: get_cmd_dly max(%d ps, %d memclk) = %d\n" + }, + {0x04050002, + "PMU0: Write CSR 0x%06x 0x%04x\n" + }, + {0x04060002, + "PMU0: hwt_init_ppgc_prbs(): Polynomial: %x, Deg: %d\n" + }, + {0x04070001, + "PMU: Error: acsm_set_cmd to non existent instruction address %d\n" + }, + {0x04080001, + "PMU: Error: acsm_set_cmd with unknown ddr cmd 0x%x\n" + }, + {0x0409000c, + "PMU1: acsm_addr %02x, acsm_flgs %04x, ddr_cmd %02x, cmd_dly %02x, ddr_addr %04x, ddr_bnk %02x, ddr_cs %02x, cmd_rcnt %02x, AcsmSeq0/1/2/3 %04x %04x %04x %04x\n" + }, + {0x040a0000, + "PMU: Error: Polling on ACSM done failed to complete in acsm_poll_done()...\n" + }, + {0x040b0000, + "PMU1: acsm RUN\n" + }, + {0x040c0000, + "PMU1: acsm STOPPED\n" + }, + {0x040d0002, + "PMU1: acsm_init: acsm_mode %04x mxrdlat %04x\n" + }, + {0x040e0002, + "PMU: Error: setAcsmCLCWL: cl and cwl must be each >= 2 and 5, resp. CL=%d CWL=%d\n" + }, + {0x040f0002, + "PMU: Error: setAcsmCLCWL: cl and cwl must be each >= 5. CL=%d CWL=%d\n" + }, + {0x04100002, + "PMU1: setAcsmCLCWL: CASL %04d WCASL %04d\n" + }, + {0x04110001, + "PMU: Error: Reserved value of register F0RC0F found in message block: 0x%04x\n" + }, + {0x04120001, + "PMU3: Written MRS to CS=0x%02x\n" + }, + {0x04130001, + "PMU3: Written MRS to CS=0x%02x\n" + }, + {0x04140000, + "PMU3: Entering Boot Freq Mode.\n" + }, + {0x04150001, + "PMU: Error: Boot clock divider setting of %d is too small\n" + }, + {0x04160000, + "PMU3: Exiting Boot Freq Mode.\n" + }, + {0x04170002, + "PMU3: Writing MR%d OP=%x\n" + }, + {0x04180000, + "PMU: Error: Delay too large in slomo\n" + }, + {0x04190001, + "PMU3: Written MRS to CS=0x%02x\n" + }, + {0x041a0000, + "PMU3: Enable Channel A\n" + }, + {0x041b0000, + "PMU3: Enable Channel B\n" + }, + {0x041c0000, + "PMU3: Enable All Channels\n" + }, + {0x041d0002, + "PMU2: Use PDA mode to set MR%d with value 0x%02x\n" + }, + {0x041e0001, + "PMU3: Written Vref with PDA to CS=0x%02x\n" + }, + {0x041f0000, + "PMU1: start_cal: DEBUG: setting CalRun to 1\n" + }, + {0x04200000, + "PMU1: start_cal: DEBUG: setting CalRun to 0\n" + }, + {0x04210001, + "PMU1: lock_pll_dll: DEBUG: pstate = %d\n" + }, + {0x04220001, + "PMU1: lock_pll_dll: DEBUG: dfifreqxlat_pstate = %d\n" + }, + {0x04230001, + "PMU1: lock_pll_dll: DEBUG: pllbypass = %d\n" + }, + {0x04240001, + "PMU3: SaveLcdlSeed: Saving seed %d\n" + }, + {0x04250000, + "PMU1: in phy_defaults()\n" + }, + {0x04260003, + "PMU3: ACXConf:%d MaxNumDbytes:%d NumDfi:%d\n" + }, + {0x04270005, + "PMU1: setAltAcsmCLCWL setting cl=%d cwl=%d\n" + }, +}; + +const static struct phy_msg messages_2d[] = { + {0x00000001, + "PMU0: Converting %d into an MR\n" + }, + {0x00010003, + "PMU DEBUG: vref_idx %d -= %d, range_idx = %d\n" + }, + {0x00020002, + "PMU0: vrefIdx. Passing range %d, remaining vrefidx = %d\n" + }, + {0x00030002, + "PMU0: VrefIdx %d -> MR[6:0] 0x%02x\n" + }, + {0x00040001, + "PMU0: Converting MR 0x%04x to vrefIdx\n" + }, + {0x00050002, + "PMU0: DAC %d Range %d\n" + }, + {0x00060003, + "PMU0: Range %d, Range_idx %d, vref_idx offset %d\n" + }, + {0x00070002, + "PMU0: MR 0x%04x -> VrefIdx %d\n" + }, + {0x00080001, + "PMU: Error: Illegal timing group number ,%d, in getPtrVrefDq\n" + }, + {0x00090003, + "PMU1: VrefDqR%dNib%d = %d\n" + }, + {0x000a0003, + "PMU0: VrefDqR%dNib%d = %d\n" + }, + {0x000b0000, + "PMU0: ----------------MARGINS-------\n" + }, + {0x000c0002, + "PMU0: R%d_RxClkDly_Margin = %d\n" + }, + {0x000d0002, + "PMU0: R%d_VrefDac_Margin = %d\n" + }, + {0x000e0002, + "PMU0: R%d_TxDqDly_Margin = %d\n" + }, + {0x000f0002, + "PMU0: R%d_DeviceVref_Margin = %d\n" + }, + {0x00100000, + "PMU0: -----------------------\n" + }, + {0x00110003, + "PMU0: eye %d's for all TG's is [%d ... %d]\n" + }, + {0x00120000, + "PMU0: ------- settingWeight -----\n" + }, + {0x00130002, + "PMU0: Weight %d @ Setting %d\n" + }, + {0x0014001f, + "PMU4: %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d >%3d< %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d\n" + }, + {0x00150002, + "PMU3: Voltage Range = [%d, %d]\n" + }, + {0x00160004, + "PMU4: -- DB%d L%d -- centers: delay = %d, voltage = %d\n" + }, + {0x00170001, + "PMU5: <<KEY>> 0 TxDqDlyTg%d <<KEY>> coarse(6:6) fine(5:0)\n" + }, + {0x00180001, + "PMU5: <<KEY>> 0 messageBlock VrefDqR%d <<KEY>> MR6(6:0)\n" + }, + {0x00190001, + "PMU5: <<KEY>> 0 RxClkDlyTg%d <<KEY>> fine(5:0)\n" + }, + {0x001a0003, + "PMU0: tgToCsn: tg %d + 0x%04x -> csn %d\n" + }, + {0x001b0002, + "PMU: Error: LP4 rank %d cannot be mapped on tg %d\n" + }, + {0x001c0002, + "PMU3: Sending vref %d, Mr = 0X%05x, to all devices\n" + }, + {0x001d0004, + "PMU4: -------- %dD Write Scanning TG %d (CS 0x%x) Lanes 0x%03x --------\n" + }, + {0x001e0002, + "PMU0: training lanes 0x%03x using lanes 0x%03x\n" + }, + {0x001f0003, + "PMU4: ------- 2D-DFE Read Scanning TG %d (CS 0x%x) Lanes 0x%03x -------\n" + }, + {0x00200004, + "PMU4: ------- %dD Read Scanning TG %d (CS 0x%x) Lanes 0x%03x -------\n" + }, + {0x00210003, + "PMU4: TG%d MR1[13,6,5]=0x%x MR6[13,9,8]=0x%x\n" + }, + {0x00220002, + "PMU0: training lanes 0x%03x using lanes 0x%03x\n" + }, + {0x00230003, + "PMU4: ------- 2D-DFE Read Scanning TG %d (CS 0x%x) Lanes 0x%03x -------\n" + }, + {0x00240004, + "PMU4: ------- %dD Read Scanning TG %d (CS 0x%x) Lanes 0x%03x -------\n" + }, + {0x00250002, + "PMU0: training lanes 0x%03x using lanes 0x%03x\n" + }, + {0x00260002, + "PMU3: Sending vref %d, Mr = 0X%05x, to all devices\n" + }, + {0x00270004, + "PMU4: -------- %dD Write Scanning TG %d (CS 0x%x) Lanes 0x%03x --------\n" + }, + {0x00280001, + "PMU0: input %d\n" + }, + {0x00290002, + "PMU4: Programmed Voltage Search Range [%d, %d]\n" + }, + {0x002a0002, + "PMU3: Delay Stepsize = %d Fine, Voltage Stepsize = %d DAC\n" + }, + {0x002b0002, + "PMU4: Delay Weight = %d, Voltage Weight = %d\n" + }, + {0x002c0003, + "PMU0: raw 0x%x allFine %d incDec %d" + }, + {0x002d0008, + "PMU0: db%d l%d, voltage 0x%x (u_r %d) delay 0x%x (u_r %d) - lcdl %d mask 0x%x\n" + }, + {0x002e0005, + "PMU0: DB%d L%d, Eye %d, Seed = (0x%x, 0x%x)\n" + }, + {0x002f0002, + "PMU3: 2D Enables : %d, 1, %d\n" + }, + {0x00300006, + "PMU3: 2D Delay Ranges: OOPL[0x%04x,0x%04x], IP[0x%04x,0x%04x], OOPR[0x%04x,0x%04x]\n" + }, + {0x00310002, + "PMU3: 2D Voltage Search Range : [%d, %d]\n" + }, + {0x00320002, + "PMU4: Found Voltage Search Range [%d, %d]\n" + }, + {0x00330002, + "PMU0: User Weight = %d, Voltage Weight = %d\n" + }, + {0x00340005, + "PMU0: D(%d,%d) V(%d,%d | %d)\n" + }, + {0x00350002, + "PMU0: Norm Weight = %d, Voltage Weight = %d\n" + }, + {0x00360002, + "PMU0: seed 0 = (%d,%d) (center)\n" + }, + {0x00370003, + "PMU0: seed 1 = (%d,%d).min edge at idx %d\n" + }, + {0x00380003, + "PMU0: seed 2 = (%d,%d) max edge at idx %d\n" + }, + {0x00390003, + "PMU0: Search point %d = (%d,%d)\n" + }, + {0x003a0005, + "PMU0: YMARGIN: ^ %d, - %d, v %d. rate %d = %d\n" + }, + {0x003b0003, + "PMU0: XMARGIN: center %d, edge %d. = %d\n" + }, + {0x003c0002, + "PMU0: ----------- weighting (%d,%d) ----------------\n" + }, + {0x003d0003, + "PMU0: X margin - L %d R %d - Min %d\n" + }, + {0x003e0003, + "PMU0: Y margin - L %d R %d - Min %d\n" + }, + {0x003f0003, + "PMU0: center (%d,%d) weight = %d\n" + }, + {0x00400003, + "PMU4: Eye argest blob area %d from %d to %d\n" + }, + {0x00410002, + "PMU0: Compute centroid min_x %d max_x %d\n" + }, + {0x00420003, + "PMU0: Compute centroid sumLnDlyWidth %d sumLnVrefWidth %d sumLnWidht %d\n" + }, + {0x00430000, + "PMU: Error: No passing region found for 1 or more lanes. Set hdtCtrl=4 to see passing regions\n" + }, + {0x00440003, + "PMU0: Centroid ( %d, %d ) found with sumLnWidht %d\n" + }, + {0x00450003, + "PMU0: Optimal allFine Center ( %d + %d ,%d )\n" + }, + {0x00460003, + "PMU3: point %d starting at (%d,%d)\n" + }, + {0x00470002, + "PMU0: picking left (%d > %d)\n" + }, + {0x00480002, + "PMU0: picking right (%d > %d)\n" + }, + {0x00490002, + "PMU0: picking down (%d > %d)\n" + }, + {0x004a0002, + "PMU0: picking up (%d > %d)\n" + }, + {0x004b0009, + "PMU3: new center @ (%3d, %3d). Moved (%2i, %2i) -- L %d, R %d, C %d, U %d, D %d\n" + }, + {0x004c0003, + "PMU3: cordNum %d imporved %d to %d\n" + }, + {0x004d0000, + "PMU: Error: No passing region found for 1 or more lanes. Set hdtCtrl=4 to see passing regions\n" + }, + {0x004e0004, + "PMU0: Optimal allFine Center ( %d + %d ,%d ), found with weight %d.\n" + }, + {0x004f0003, + "PMU0: merging lanes=%d..%d, centerMerge_t %d\n" + }, + {0x00500001, + "PMU0: laneVal %d is disable\n" + }, + {0x00510002, + "PMU0: checking common center %d against current center %d\n" + }, + {0x00520001, + "PMU: Error: getCompoundEye Called on lane%d eye with non-compatible centers\n" + }, + {0x00530001, + "PMU0: laneItr %d is disable\n" + }, + {0x00540005, + "PMU0: lane %d, data_idx %d, offset_idx %d, = [%d..%d]\n" + }, + {0x00550003, + "PMU0: lane %d, data_idx %d, offset_idx %d, offset_idx out of range!\n" + }, + {0x00560003, + "PMU0: mergeData[%d] = max_v_low %d, min_v_high %d\n" + }, + {0x00570005, + "PMU1: writing merged center (%d,%d) back to dataBlock[%d]. doDelay %d, doVoltage %d\n" + }, + {0x00580005, + "PMU0: applying relative (%i,%i) back to dataBlock[%d]. doDelay %d, doVoltage %d\n" + }, + {0x00590002, + "PMU0: drvstren %x is idx %d in the table\n" + }, + {0x005a0000, + "PMU4: truncating FFE drive strength search range. Out of drive strengths to check.\n" + }, + {0x005b0002, + "PMU5: Weak 1 changed to pull-up %5d ohms, pull-down %5d ohms\n" + }, + {0x005c0002, + "PMU5: Weak 0 changed to pull-up %5d ohms, pull-down %5d ohms\n" + }, + {0x005d0003, + "PMU0: dlyMargin L %02d R %02d, min %02d\n" + }, + {0x005e0003, + "PMU0: vrefMargin T %02d B %02d, min %02d\n" + }, + {0x005f0002, + "PMU3: new minimum VrefMargin (%d < %d) recorded\n" + }, + {0x00600002, + "PMU3: new minimum DlyMargin (%d < %d) recorded\n" + }, + {0x00610000, + "PMU0: RX finding the per-nibble, per-tg rxClkDly values\n" + }, + {0x00620003, + "PMU0: Merging collected eyes [%d..%d) and analyzing for nibble %d's optimal rxClkDly\n" + }, + {0x00630002, + "PMU0: -- centers: delay = %d, voltage = %d\n" + }, + {0x00640003, + "PMU0: dumping optimized eye -- centers: delay = %d (%d), voltage = %d\n" + }, + {0x00650000, + "PMU0: TX optimizing txDqDelays\n" + }, + {0x00660001, + "PMU3: Analyzing collected eye %d for a lane's optimal TxDqDly\n" + }, + {0x00670001, + "PMU0: eye-lane %d is disable\n" + }, + {0x00680000, + "PMU0: TX optimizing device voltages\n" + }, + {0x00690002, + "PMU0: Merging collected eyes [%d..%d) and analyzing for optimal device txVref\n" + }, + {0x006a0002, + "PMU0: -- centers: delay = %d, voltage = %d\n" + }, + {0x006b0003, + "PMU0: dumping optimized eye -- centers: delay = %d (%d), voltage = %d\n" + }, + {0x006c0000, + "PMU4: VrefDac (compound all TG) Bottom Top -> Center\n" + }, + {0x006d0005, + "PMU4: DB%d L%d %3d %3d -> %3d (DISCONNECTED)\n" + }, + {0x006e0005, + "PMU4: DB%d L%d %3d %3d -> %3d\n" + }, + {0x006f0005, + "PMU0: writing rxClkDelay for tg%d db%1d nib%1d to 0x%02x from eye[%02d] (DISCONNECTED)\n" + }, + {0x00700003, + "PMU: Error: Dbyte %d nibble %d's optimal rxClkDly of 0x%x is out of bounds\n" + }, + {0x00710005, + "PMU0: writing rxClkDelay for tg%d db%1d nib%1d to 0x%02x from eye[%02d]\n" + }, + {0x00720005, + "PMU0: tx voltage for tg%2d nib%2d to %3d (%d) from eye[%02d]\n" + }, + {0x00730001, + "PMU0: vref Sum = %d\n" + }, + {0x00740004, + "PMU0: tx voltage total is %d/%d -> %d -> %d\n" + }, + {0x00750007, + "PMU0: writing txDqDelay for tg%1d db%1d ln%1d to 0x%02x (%d coarse, %d fine) from eye[%02d] (DISCONNECTED)\n" + }, + {0x00760003, + "PMU: Error: Dbyte %d lane %d's optimal txDqDly of 0x%x is out of bounds\n" + }, + {0x00770007, + "PMU0: writing txDqDelay for tg%1d db%1d l%1d to 0x%02x (%d coarse, %d fine) from eye[%02d]\n" + }, + {0x00780002, + "PMU0: %d (0=tx, 1=rx) TgMask for this simulation: %x\n" + }, + {0x00790001, + "PMU0: eye-byte %d is disable\n" + }, + {0x007a0001, + "PMU0: eye-lane %d is disable\n" + }, + {0x007b0003, + "PMU10: Start d4_2d_lrdimm_rx_dfe dimm %d nbTap %d biasStepMode %d\n" + }, + {0x007c0001, + "PMU10: DB DFE feature not fully supported, F2BCEx value is 0x%02x\n" + }, + {0x007d0001, + "PMU10: DB DFE feature fully supported, F2BCEx value is 0x%02x\n" + }, + {0x007e0002, + "PMU8: Start d4_2d_lrdimm_rx_dfe for tap %d biasStepInc %d\n" + }, + {0x007f0001, + "PMU7: Start d4_2d_lrdimm_rx_dfe tapCoff 0x%0x\n" + }, + {0x00800003, + "PMU6: d4_2d_lrdimm_rx_dfe db %d lane %d area %d\n" + }, + {0x00810004, + "PMU7: d4_2d_lrdimm_rx_dfe db %d lane %d max area %d best bias 0x%0x\n" + }, + {0x00820001, + "PMU0: eye-lane %d is disable\n" + }, + {0x00830003, + "PMU5: Setting 0x%x improved rank weight (%4d < %4d)\n" + }, + {0x00840001, + "PMU4: Setting 0x%x still optimal\n" + }, + {0x00850002, + "PMU5: ---- Training CS%d MR%d DRAM Equalization ----\n" + }, + {0x00860001, + "PMU0: eye-lane %d is disable\n" + }, + {0x00870003, + "PMU0: eye %d weight %d allTgWeight %d\n" + }, + {0x00880002, + "PMU5: FFE figure of merit improved from %d to %d\n" + }, + {0x00890002, + "PMU: Error: LP4 rank %d cannot be mapped on tg %d\n" + }, + {0x008a0000, + "PMU4: Adjusting vrefDac0 for just 1->x transitions\n" + }, + {0x008b0000, + "PMU4: Adjusting vrefDac1 for just 0->x transitions\n" + }, + {0x008c0001, + "PMU5: Strong 1, pull-up %d ohms\n" + }, + {0x008d0001, + "PMU5: Strong 0, pull-down %d ohms\n" + }, + {0x008e0000, + "PMU4: Enabling weak drive strengths (FFE)\n" + }, + {0x008f0000, + "PMU5: Changing all weak driver strengths\n" + }, + {0x00900000, + "PMU5: Finalizing weak drive strengths\n" + }, + {0x00910000, + "PMU4: retraining with optimal drive strength settings\n" + }, + {0x00920002, + "PMU0: targeting CsX = %d and CsY = %d\n" + }, + {0x00930001, + "PMU1:prbsGenCtl:%x\n" + }, + {0x00940000, + "PMU1: loading 2D acsm sequence\n" + }, + {0x00950000, + "PMU1: loading 1D acsm sequence\n" + }, + {0x00960002, + "PMU3: %d memclocks @ %d to get half of 300ns\n" + }, + {0x00970000, + "PMU: Error: User requested MPR read pattern for read DQS training in DDR3 Mode\n" + }, + {0x00980000, + "PMU3: Running 1D search for left eye edge\n" + }, + {0x00990001, + "PMU1: In Phase Left Edge Search cs %d\n" + }, + {0x009a0001, + "PMU1: Out of Phase Left Edge Search cs %d\n" + }, + {0x009b0000, + "PMU3: Running 1D search for right eye edge\n" + }, + {0x009c0001, + "PMU1: In Phase Right Edge Search cs %d\n" + }, + {0x009d0001, + "PMU1: Out of Phase Right Edge Search cs %d\n" + }, + {0x009e0001, + "PMU1: mxRdLat training pstate %d\n" + }, + {0x009f0001, + "PMU1: mxRdLat search for cs %d\n" + }, + {0x00a00001, + "PMU0: MaxRdLat non consistent DtsmLoThldXingInd 0x%03x\n" + }, + {0x00a10003, + "PMU4: CS %d Dbyte %d worked with DFIMRL = %d DFICLKs\n" + }, + {0x00a20004, + "PMU3: MaxRdLat Read Lane err mask for csn %d, DFIMRL %2d DFIClks, dbyte %d = 0x%03x\n" + }, + {0x00a30003, + "PMU3: MaxRdLat Read Lane err mask for csn %d DFIMRL %2d, All dbytes = 0x%03x\n" + }, + {0x00a40001, + "PMU: Error: CS%d failed to find a DFIMRL setting that worked for all bytes during MaxRdLat training\n" + }, + {0x00a50002, + "PMU3: Smallest passing DFIMRL for all dbytes in CS%d = %d DFIClks\n" + }, + {0x00a60000, + "PMU: Error: No passing DFIMRL value found for any chip select during MaxRdLat training\n" + }, + {0x00a70003, + "PMU: Error: Dbyte %d lane %d txDqDly passing region is too small (width = %d)\n" + }, + {0x00a80006, + "PMU10: Adjusting rxclkdly db %d nib %d from %d+%d=%d->%d\n" + }, + {0x00a90000, + "PMU4: TxDqDly Passing Regions (EyeLeft EyeRight -> EyeCenter) Units=1/32 UI\n" + }, + {0x00aa0005, + "PMU4: DB %d Lane %d: %3d %3d -> %3d\n" + }, + {0x00ab0002, + "PMU2: TXDQ delayLeft[%2d] = %3d (DISCONNECTED)\n" + }, + {0x00ac0004, + "PMU2: TXDQ delayLeft[%2d] = %3d oopScaled = %3d selectOop %d\n" + }, + {0x00ad0002, + "PMU2: TXDQ delayRight[%2d] = %3d (DISCONNECTED)\n" + }, + {0x00ae0004, + "PMU2: TXDQ delayRight[%2d] = %3d oopScaled = %3d selectOop %d\n" + }, + {0x00af0003, + "PMU: Error: Dbyte %d lane %d txDqDly passing region is too small (width = %d)\n" + }, + {0x00b00000, + "PMU4: TxDqDly Passing Regions (EyeLeft EyeRight -> EyeCenter) Units=1/32 UI\n" + }, + {0x00b10002, + "PMU4: DB %d Lane %d: (DISCONNECTED)\n" + }, + {0x00b20005, + "PMU4: DB %d Lane %d: %3d %3d -> %3d\n" + }, + {0x00b30002, + "PMU3: Running 1D search csn %d for DM Right/NotLeft(%d) eye edge\n" + }, + {0x00b40002, + "PMU3: WrDq DM byte%2d with Errcnt %d\n" + }, + {0x00b50002, + "PMU3: WrDq DM byte%2d avgDly 0x%04x\n" + }, + {0x00b60002, + "PMU1: WrDq DM byte%2d with Errcnt %d\n" + }, + {0x00b70001, + "PMU: Error: Dbyte %d txDqDly DM training did not start inside the eye\n" + }, + {0x00b80000, + "PMU4: DM TxDqDly Passing Regions (EyeLeft EyeRight -> EyeCenter) Units=1/32 UI\n" + }, + {0x00b90002, + "PMU4: DB %d Lane %d: (DISCONNECTED)\n" + }, + {0x00ba0005, + "PMU4: DB %d Lane %d: %3d %3d -> %3d\n" + }, + {0x00bb0003, + "PMU: Error: Dbyte %d lane %d txDqDly DM passing region is too small (width = %d)\n" + }, + {0x00bc0004, + "PMU3: Errcnt for MRD/MWD search nib %2d delay = (%d, 0x%02x) = %d\n" + }, + {0x00bd0000, + "PMU3: Precharge all open banks\n" + }, + {0x00be0002, + "PMU: Error: Dbyte %d nibble %d found mutliple working coarse delay setting for MRD/MWD\n" + }, + {0x00bf0000, + "PMU4: MRD Passing Regions (coarseVal, fineLeft fineRight -> fineCenter)\n" + }, + {0x00c00000, + "PMU4: MWD Passing Regions (coarseVal, fineLeft fineRight -> fineCenter)\n" + }, + {0x00c10004, + "PMU10: Warning: DB %d nibble %d has multiple working coarse delays, %d and %d, choosing the smaller delay\n" + }, + {0x00c20003, + "PMU: Error: Dbyte %d nibble %d MRD/MWD passing region is too small (width = %d)\n" + }, + {0x00c30006, + "PMU4: DB %d nibble %d: %3d, %3d %3d -> %3d\n" + }, + {0x00c40002, + "PMU1: Start MRD/nMWD %d for csn %d\n" + }, + {0x00c50002, + "PMU2: RXDQS delayLeft[%2d] = %3d (DISCONNECTED)\n" + }, + {0x00c60006, + "PMU2: RXDQS delayLeft[%2d] = %3d delayOop[%2d] = %3d OopScaled %4d, selectOop %d\n" + }, + {0x00c70002, + "PMU2: RXDQS delayRight[%2d] = %3d (DISCONNECTED)\n" + }, + {0x00c80006, + "PMU2: RXDQS delayRight[%2d] = %3d delayOop[%2d] = %4d OopScaled %4d, selectOop %d\n" + }, + {0x00c90000, + "PMU4: RxClkDly Passing Regions (EyeLeft EyeRight -> EyeCenter)\n" + }, + {0x00ca0002, + "PMU4: DB %d nibble %d: (DISCONNECTED)\n" + }, + {0x00cb0005, + "PMU4: DB %d nibble %d: %3d %3d -> %3d\n" + }, + {0x00cc0003, + "PMU: Error: Dbyte %d nibble %d rxClkDly passing region is too small (width = %d)\n" + }, + {0x00cd0002, + "PMU0: goodbar = %d for RDWR_BLEN %d\n" + }, + {0x00ce0001, + "PMU3: RxClkDly = %d\n" + }, + {0x00cf0005, + "PMU0: db %d l %d absLane %d -> bottom %d top %d\n" + }, + {0x00d00009, + "PMU3: BYTE %d - %3d %3d %3d %3d %3d %3d %3d %3d\n" + }, + {0x00d10002, + "PMU: Error: dbyte %d lane %d's per-lane vrefDAC's had no passing region\n" + }, + {0x00d20004, + "PMU0: db%d l%d - %d %d\n" + }, + {0x00d30002, + "PMU0: goodbar = %d for RDWR_BLEN %d\n" + }, + {0x00d40004, + "PMU3: db%d l%d saw %d issues at rxClkDly %d\n" + }, + {0x00d50003, + "PMU3: db%d l%d first saw a pass->fail edge at rxClkDly %d\n" + }, + {0x00d60002, + "PMU3: lane %d PBD = %d\n" + }, + {0x00d70003, + "PMU3: db%d l%d first saw a DBI pass->fail edge at rxClkDly %d\n" + }, + {0x00d80003, + "PMU2: db%d l%d already passed rxPBD = %d\n" + }, + {0x00d90003, + "PMU0: db%d l%d, PBD = %d\n" + }, + {0x00da0002, + "PMU: Error: dbyte %d lane %d failed read deskew\n" + }, + {0x00db0003, + "PMU0: db%d l%d, inc PBD = %d\n" + }, + {0x00dc0003, + "PMU1: Running lane deskew on pstate %d csn %d rdDBIEn %d\n" + }, + {0x00dd0000, + "PMU: Error: Read deskew training has been requested, but csrMajorModeDbyte[2] is set\n" + }, + {0x00de0002, + "PMU1: AcsmCsMapCtrl%02d 0x%04x\n" + }, + {0x00df0002, + "PMU1: AcsmCsMapCtrl%02d 0x%04x\n" + }, + {0x00e00001, + "PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D3U Type\n" + }, + {0x00e10001, + "PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D3R Type\n" + }, + {0x00e20001, + "PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D4U Type\n" + }, + {0x00e30001, + "PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D4R Type\n" + }, + {0x00e40001, + "PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D4LR Type\n" + }, + {0x00e50000, + "PMU: Error: Both 2t timing mode and ddr4 geardown mode specified in the messageblock's PhyCfg and MR3 fields. Only one can be enabled\n" + }, + {0x00e60003, + "PMU10: PHY TOTALS - NUM_DBYTES %d NUM_NIBBLES %d NUM_ANIBS %d\n" + }, + {0x00e70006, + "PMU10: CSA=0x%02x, CSB=0x%02x, TSTAGES=0x%04x, HDTOUT=%d, MMISC=%d DRAMFreq=%dMT DramType=LPDDR3\n" + }, + {0x00e80006, + "PMU10: CSA=0x%02x, CSB=0x%02x, TSTAGES=0x%04x, HDTOUT=%d, MMISC=%d DRAMFreq=%dMT DramType=LPDDR4\n" + }, + {0x00e90008, + "PMU10: CS=0x%02x, TSTAGES=0x%04x, HDTOUT=%d, 2T=%d, MMISC=%d AddrMirror=%d DRAMFreq=%dMT DramType=%d\n" + }, + {0x00ea0004, + "PMU10: Pstate%d MR0=0x%04x MR1=0x%04x MR2=0x%04x\n" + }, + {0x00eb0008, + "PMU10: Pstate%d MRS MR0=0x%04x MR1=0x%04x MR2=0x%04x MR3=0x%04x MR4=0x%04x MR5=0x%04x MR6=0x%04x\n" + }, + {0x00ec0005, + "PMU10: Pstate%d MRS MR1_A0=0x%04x MR2_A0=0x%04x MR3_A0=0x%04x MR11_A0=0x%04x\n" + }, + {0x00ed0000, + "PMU10: UseBroadcastMR set. All ranks and channels use MRXX_A0 for MR settings.\n" + }, + {0x00ee0005, + "PMU10: Pstate%d MRS MR01_A0=0x%02x MR02_A0=0x%02x MR03_A0=0x%02x MR11_A0=0x%02x\n" + }, + {0x00ef0005, + "PMU10: Pstate%d MRS MR12_A0=0x%02x MR13_A0=0x%02x MR14_A0=0x%02x MR22_A0=0x%02x\n" + }, + {0x00f00005, + "PMU10: Pstate%d MRS MR01_A1=0x%02x MR02_A1=0x%02x MR03_A1=0x%02x MR11_A1=0x%02x\n" + }, + {0x00f10005, + "PMU10: Pstate%d MRS MR12_A1=0x%02x MR13_A1=0x%02x MR14_A1=0x%02x MR22_A1=0x%02x\n" + }, + {0x00f20005, + "PMU10: Pstate%d MRS MR01_B0=0x%02x MR02_B0=0x%02x MR03_B0=0x%02x MR11_B0=0x%02x\n" + }, + {0x00f30005, + "PMU10: Pstate%d MRS MR12_B0=0x%02x MR13_B0=0x%02x MR14_B0=0x%02x MR22_B0=0x%02x\n" + }, + {0x00f40005, + "PMU10: Pstate%d MRS MR01_B1=0x%02x MR02_B1=0x%02x MR03_B1=0x%02x MR11_B1=0x%02x\n" + }, + {0x00f50005, + "PMU10: Pstate%d MRS MR12_B1=0x%02x MR13_B1=0x%02x MR14_B1=0x%02x MR22_B1=0x%02x\n" + }, + {0x00f60002, + "PMU1: AcsmOdtCtrl%02d 0x%02x\n" + }, + {0x00f70002, + "PMU1: AcsmCsMapCtrl%02d 0x%04x\n" + }, + {0x00f80002, + "PMU1: AcsmCsMapCtrl%02d 0x%04x\n" + }, + {0x00f90000, + "PMU1: HwtCAMode set\n" + }, + {0x00fa0001, + "PMU3: DDR4 infinite preamble enter/exit mode %d\n" + }, + {0x00fb0002, + "PMU1: In rxenb_train() csn=%d pstate=%d\n" + }, + {0x00fc0000, + "PMU3: Finding DQS falling edge\n" + }, + {0x00fd0000, + "PMU3: Searching for DDR3/LPDDR3/LPDDR4 read preamble\n" + }, + {0x00fe0009, + "PMU3: dtsm fails Even Nibbles : %2x %2x %2x %2x %2x %2x %2x %2x %2x\n" + }, + {0x00ff0009, + "PMU3: dtsm fails Odd Nibbles : %2x %2x %2x %2x %2x %2x %2x %2x %2x\n" + }, + {0x01000002, + "PMU3: Preamble search pass=%d anyfail=%d\n" + }, + {0x01010000, + "PMU: Error: RxEn training preamble not found\n" + }, + {0x01020000, + "PMU3: Found DQS pre-amble\n" + }, + {0x01030001, + "PMU: Error: Dbyte %d couldn't find the rising edge of DQS during RxEn Training\n" + }, + {0x01040000, + "PMU3: RxEn aligning to first rising edge of burst\n" + }, + {0x01050001, + "PMU3: Decreasing RxEn delay by %d fine step to allow full capture of reads\n" + }, + {0x01060001, + "PMU3: MREP Delay = %d\n" + }, + {0x01070003, + "PMU3: Errcnt for MREP nib %2d delay = %2d is %d\n" + }, + {0x01080002, + "PMU3: MREP nibble %d sampled a 1 at data buffer delay %d\n" + }, + {0x01090002, + "PMU3: MREP nibble %d saw a 0 to 1 transition at data buffer delay %d\n" + }, + {0x010a0000, + "PMU2: MREP did not find a 0 to 1 transition for all nibbles. Failing nibbles assumed to have rising edge close to fine delay 63\n" + }, + {0x010b0002, + "PMU2: Rising edge found in alias window, setting rxDly for nibble %d = %d\n" + }, + {0x010c0002, + "PMU: Error: Failed MREP for nib %d with %d one\n" + }, + {0x010d0003, + "PMU2: Rising edge not found in alias window with %d one, leaving rxDly for nibble %d = %d\n" + }, + {0x010e0002, + "PMU3: Training DIMM %d CSn %d\n" + }, + {0x010f0001, + "PMU3: exitCAtrain_lp3 cs 0x%x\n" + }, + {0x01100001, + "PMU3: enterCAtrain_lp3 cs 0x%x\n" + }, + {0x01110001, + "PMU3: CAtrain_switchmsb_lp3 cs 0x%x\n" + }, + {0x01120001, + "PMU3: CATrain_rdwr_lp3 looking for pattern %x\n" + }, + {0x01130000, + "PMU3: exitCAtrain_lp4\n" + }, + {0x01140001, + "PMU3: DEBUG enterCAtrain_lp4 1: cs 0x%x\n" + }, + {0x01150001, + "PMU3: DEBUG enterCAtrain_lp4 3: Put dbyte %d in async mode\n" + }, + {0x01160000, + "PMU3: DEBUG enterCAtrain_lp4 5: Send MR13 to turn on CA training\n" + }, + {0x01170003, + "PMU3: DEBUG enterCAtrain_lp4 7: idx = %d vref = %x mr12 = %x\n" + }, + {0x01180001, + "PMU3: CATrain_rdwr_lp4 looking for pattern %x\n" + }, + {0x01190004, + "PMU3: Phase %d CAreadbackA db:%d %x xo:%x\n" + }, + {0x011a0005, + "PMU3: DEBUG lp4SetCatrVref 1: cs=%d chan=%d mr12=%x vref=%d.%d%%\n" + }, + {0x011b0003, + "PMU3: DEBUG lp4SetCatrVref 3: mr12 = %x send vref= %x to db=%d\n" + }, + {0x011c0000, + "PMU10:Optimizing vref\n" + }, + {0x011d0004, + "PMU4:mr12:%2x cs:%d chan %d r:%4x\n" + }, + {0x011e0005, + "PMU3: i:%2d bstr:%2d bsto:%2d st:%d r:%d\n" + }, + {0x011f0002, + "Failed to find sufficient CA Vref Passing Region for CS %d ch. %d\n" + }, + {0x01200005, + "PMU3:Found %d.%d%% MR12:%x for cs:%d chan %d\n" + }, + {0x01210002, + "PMU3:Calculated %d for AtxImpedence from acx %d.\n" + }, + {0x01220000, + "PMU3:CA Odt impedence ==0. Use default vref.\n" + }, + {0x01230003, + "PMU3:Calculated %d.%d%% for Vref MR12=0x%x.\n" + }, + {0x01240000, + "PMU3: CAtrain_lp\n" + }, + {0x01250000, + "PMU3: CAtrain Begins.\n" + }, + {0x01260001, + "PMU3: CAtrain_lp testing dly %d\n" + }, + {0x01270001, + "PMU5: CA bitmap dump for cs %x\n" + }, + {0x01280001, + "PMU5: CAA%d " + }, + {0x01290001, "%02x" + }, + {0x012a0000, "\n" + }, + {0x012b0001, + "PMU5: CAB%d " + }, + {0x012c0001, "%02x" + }, + {0x012d0000, "\n" + }, + {0x012e0003, + "PMU3: anibi=%d, anibichan[anibi]=%d ,chan=%d\n" + }, + {0x012f0001, "%02x" + }, + {0x01300001, "\nPMU3:Raw CA setting :%x" + }, + {0x01310002, "\nPMU3:ATxDly setting:%x margin:%d\n" + }, + {0x01320002, "\nPMU3:InvClk ATxDly setting:%x margin:%d\n" + }, + {0x01330000, "\nPMU3:No Range found!\n" + }, + {0x01340003, + "PMU3: 2 anibi=%d, anibichan[anibi]=%d ,chan=%d" + }, + {0x01350002, "\nPMU3: no neg clock => CA setting anib=%d, :%d\n" + }, + {0x01360001, + "PMU3:Normal margin:%d\n" + }, + {0x01370001, + "PMU3:Inverted margin:%d\n" + }, + {0x01380000, + "PMU3:Using Inverted clock\n" + }, + {0x01390000, + "PMU3:Using normal clk\n" + }, + {0x013a0003, + "PMU3: 3 anibi=%d, anibichan[anibi]=%d ,chan=%d\n" + }, + {0x013b0002, + "PMU3: Setting ATxDly for anib %x to %x\n" + }, + {0x013c0000, + "PMU: Error: CA Training Failed.\n" + }, + {0x013d0000, + "PMU1: Writing MRs\n" + }, + {0x013e0000, + "PMU4:Using MR12 values from 1D CA VREF training.\n" + }, + {0x013f0000, + "PMU3:Writing all MRs to fsp 1\n" + }, + {0x01400000, + "PMU10:Lp4Quickboot mode.\n" + }, + {0x01410000, + "PMU3: Writing MRs\n" + }, + {0x01420001, + "PMU10: Setting boot clock divider to %d\n" + }, + {0x01430000, + "PMU3: Resetting DRAM\n" + }, + {0x01440000, + "PMU3: setup for RCD initalization\n" + }, + {0x01450000, + "PMU3: pmu_exit_SR from dev_init()\n" + }, + {0x01460000, + "PMU3: initializing RCD\n" + }, + {0x01470000, + "PMU10: **** Executing 2D Image ****\n" + }, + {0x01480001, + "PMU10: **** Start DDR4 Training. PMU Firmware Revision 0x%04x ****\n" + }, + {0x01490001, + "PMU10: **** Start DDR3 Training. PMU Firmware Revision 0x%04x ****\n" + }, + {0x014a0001, + "PMU10: **** Start LPDDR3 Training. PMU Firmware Revision 0x%04x ****\n" + }, + {0x014b0001, + "PMU10: **** Start LPDDR4 Training. PMU Firmware Revision 0x%04x ****\n" + }, + {0x014c0000, + "PMU: Error: Mismatched internal revision between DCCM and ICCM images\n" + }, + {0x014d0001, + "PMU10: **** Testchip %d Specific Firmware ****\n" + }, + {0x014e0000, + "PMU1: LRDIMM with EncodedCS mode, one DIMM\n" + }, + {0x014f0000, + "PMU1: LRDIMM with EncodedCS mode, two DIMMs\n" + }, + {0x01500000, + "PMU1: RDIMM with EncodedCS mode, one DIMM\n" + }, + {0x01510000, + "PMU2: Starting LRDIMM MREP training for all ranks\n" + }, + {0x01520000, + "PMU199: LRDIMM MREP training for all ranks completed\n" + }, + {0x01530000, + "PMU2: Starting LRDIMM DWL training for all ranks\n" + }, + {0x01540000, + "PMU199: LRDIMM DWL training for all ranks completed\n" + }, + {0x01550000, + "PMU2: Starting LRDIMM MRD training for all ranks\n" + }, + {0x01560000, + "PMU199: LRDIMM MRD training for all ranks completed\n" + }, + {0x01570000, + "PMU2: Starting RXEN training for all ranks\n" + }, + {0x01580000, + "PMU2: Starting write leveling fine delay training for all ranks\n" + }, + {0x01590000, + "PMU2: Starting LRDIMM MWD training for all ranks\n" + }, + {0x015a0000, + "PMU199: LRDIMM MWD training for all ranks completed\n" + }, + {0x015b0000, + "PMU2: Starting write leveling fine delay training for all ranks\n" + }, + {0x015c0000, + "PMU2: Starting read deskew training\n" + }, + {0x015d0000, + "PMU2: Starting SI friendly 1d RdDqs training for all ranks\n" + }, + {0x015e0000, + "PMU2: Starting write leveling coarse delay training for all ranks\n" + }, + {0x015f0000, + "PMU2: Starting 1d WrDq training for all ranks\n" + }, + {0x01600000, + "PMU2: Running DQS2DQ Oscillator for all ranks\n" + }, + {0x01610000, + "PMU2: Starting again read deskew training but with PRBS\n" + }, + {0x01620000, + "PMU2: Starting 1d RdDqs training for all ranks\n" + }, + {0x01630000, + "PMU2: Starting again 1d WrDq training for all ranks\n" + }, + {0x01640000, + "PMU2: Starting MaxRdLat training\n" + }, + {0x01650000, + "PMU2: Starting 2d WrDq training for all ranks\n" + }, + {0x01660000, + "PMU2: Starting 2d RdDqs training for all ranks\n" + }, + {0x01670002, + "PMU3:read_fifo %x %x\n" + }, + {0x01680001, + "PMU: Error: Invalid PhyDrvImpedance of 0x%x specified in message block.\n" + }, + {0x01690001, + "PMU: Error: Invalid PhyOdtImpedance of 0x%x specified in message block.\n" + }, + {0x016a0001, + "PMU: Error: Invalid BPZNResVal of 0x%x specified in message block.\n" + }, + {0x016b0005, + "PMU3: fixRxEnBackOff csn:%d db:%d dn:%d bo:%d dly:%x\n" + }, + {0x016c0001, + "PMU3: fixRxEnBackOff dly:%x\n" + }, + {0x016d0000, + "PMU3: Entering setupPpt\n" + }, + {0x016e0000, + "PMU3: Start lp4PopulateHighLowBytes\n" + }, + {0x016f0002, + "PMU3:Dbyte Detect: db%d received %x\n" + }, + {0x01700002, + "PMU3:getDqs2Dq read %x from dbyte %d\n" + }, + {0x01710002, + "PMU3:getDqs2Dq(2) read %x from dbyte %d\n" + }, + {0x01720001, + "PMU: Error: Dbyte %d read 0 from the DQS oscillator it is connected to\n" + }, + {0x01730002, + "PMU4: Dbyte %d dqs2dq = %d/32 UI\n" + }, + {0x01740003, + "PMU3:getDqs2Dq set dqs2dq:%d/32 ui (%d ps) from dbyte %d\n" + }, + {0x01750003, + "PMU3: Setting coarse delay in AtxDly chiplet %d from 0x%02x to 0x%02x\n" + }, + {0x01760003, + "PMU3: Clearing coarse delay in AtxDly chiplet %d from 0x%02x to 0x%02x\n" + }, + {0x01770000, + "PMU3: Performing DDR4 geardown sync sequence\n" + }, + {0x01780000, + "PMU1: Enter self refresh\n" + }, + {0x01790000, + "PMU1: Exit self refresh\n" + }, + {0x017a0000, + "PMU: Error: No dbiEnable with lp4\n" + }, + {0x017b0000, + "PMU: Error: No dbiDisable with lp4\n" + }, + {0x017c0001, + "PMU1: DDR4 update Rx DBI Setting disable %d\n" + }, + {0x017d0001, + "PMU1: DDR4 update 2nCk WPre Setting disable %d\n" + }, + {0x017e0005, + "PMU1: read_delay: db%d lane%d delays[%2d] = 0x%02x (max 0x%02x)\n" + }, + {0x017f0004, + "PMU1: write_delay: db%d lane%d delays[%2d] = 0x%04x\n" + }, + {0x01800001, + "PMU5: ID=%d -- db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 --\n" + }, + {0x0181000b, + "PMU5: [%d]:0x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n" + }, + {0x01820003, + "PMU2: dump delays - pstate=%d dimm=%d csn=%d\n" + }, + {0x01830000, + "PMU3: Printing Mid-Training Delay Information\n" + }, + {0x01840001, + "PMU5: CS%d <<KEY>> 0 TrainingCntr <<KEY>> coarse(15:10) fine(9:0)\n" + }, + {0x01850001, + "PMU5: CS%d <<KEY>> 0 RxEnDly, 1 RxClkDly <<KEY>> coarse(10:6) fine(5:0)\n" + }, + {0x01860001, + "PMU5: CS%d <<KEY>> 0 TxDqsDly, 1 TxDqDly <<KEY>> coarse(9:6) fine(5:0)\n" + }, + {0x01870001, + "PMU5: CS%d <<KEY>> 0 RxPBDly <<KEY>> 1 Delay Unit ~= 7ps\n" + }, + {0x01880000, + "PMU5: all CS <<KEY>> 0 DFIMRL <<KEY>> Units = DFI clocks\n" + }, + {0x01890000, + "PMU5: all CS <<KEY>> VrefDACs <<KEY>> DAC(6:0)\n" + }, + {0x018a0000, + "PMU1: Set DMD in MR13 and wrDBI in MR3 for training\n" + }, + {0x018b0000, + "PMU: Error: getMaxRxen() failed to find largest rxen nibble delay\n" + }, + {0x018c0003, + "PMU2: getMaxRxen(): maxDly %d maxTg %d maxNib %d\n" + }, + {0x018d0003, + "PMU2: getRankMaxRxen(): maxDly %d Tg %d maxNib %d\n" + }, + {0x018e0000, + "PMU1: skipping CDD calculation in 2D image\n" + }, + {0x018f0001, + "PMU3: Calculating CDDs for pstate %d\n" + }, + {0x01900003, + "PMU3: rxFromDly[%d][%d] = %d\n" + }, + {0x01910003, + "PMU3: rxToDly [%d][%d] = %d\n" + }, + {0x01920003, + "PMU3: rxDly [%d][%d] = %d\n" + }, + {0x01930003, + "PMU3: txDly [%d][%d] = %d\n" + }, + {0x01940003, + "PMU3: allFine CDD_RR_%d_%d = %d\n" + }, + {0x01950003, + "PMU3: allFine CDD_WW_%d_%d = %d\n" + }, + {0x01960003, + "PMU3: CDD_RR_%d_%d = %d\n" + }, + {0x01970003, + "PMU3: CDD_WW_%d_%d = %d\n" + }, + {0x01980003, + "PMU3: allFine CDD_RW_%d_%d = %d\n" + }, + {0x01990003, + "PMU3: allFine CDD_WR_%d_%d = %d\n" + }, + {0x019a0003, + "PMU3: CDD_RW_%d_%d = %d\n" + }, + {0x019b0003, + "PMU3: CDD_WR_%d_%d = %d\n" + }, + {0x019c0004, + "PMU3: F%dBC2x_B%d_D%d = 0x%02x\n" + }, + {0x019d0004, + "PMU3: F%dBC3x_B%d_D%d = 0x%02x\n" + }, + {0x019e0004, + "PMU3: F%dBC4x_B%d_D%d = 0x%02x\n" + }, + {0x019f0004, + "PMU3: F%dBC5x_B%d_D%d = 0x%02x\n" + }, + {0x01a00004, + "PMU3: F%dBC8x_B%d_D%d = 0x%02x\n" + }, + {0x01a10004, + "PMU3: F%dBC9x_B%d_D%d = 0x%02x\n" + }, + {0x01a20004, + "PMU3: F%dBCAx_B%d_D%d = 0x%02x\n" + }, + {0x01a30004, + "PMU3: F%dBCBx_B%d_D%d = 0x%02x\n" + }, + {0x01a40000, + "PMU10: Entering context_switch_postamble\n" + }, + {0x01a50003, + "PMU10: context_switch_postamble is enabled for DIMM %d, RC0A=0x%x, RC3x=0x%x\n" + }, + {0x01a60000, + "PMU10: Setting bcw fspace 0\n" + }, + {0x01a70001, + "PMU10: Sending BC0A = 0x%x\n" + }, + {0x01a80001, + "PMU10: Sending BC6x = 0x%x\n" + }, + {0x01a90001, + "PMU10: Sending RC0A = 0x%x\n" + }, + {0x01aa0001, + "PMU10: Sending RC3x = 0x%x\n" + }, + {0x01ab0001, + "PMU10: Sending RC0A = 0x%x\n" + }, + {0x01ac0001, + "PMU1: enter_lp3: DEBUG: pstate = %d\n" + }, + {0x01ad0001, + "PMU1: enter_lp3: DEBUG: dfifreqxlat_pstate = %d\n" + }, + {0x01ae0001, + "PMU1: enter_lp3: DEBUG: pllbypass = %d\n" + }, + {0x01af0001, + "PMU1: enter_lp3: DEBUG: forcecal = %d\n" + }, + {0x01b00001, + "PMU1: enter_lp3: DEBUG: pllmaxrange = 0x%x\n" + }, + {0x01b10001, + "PMU1: enter_lp3: DEBUG: dacval_out = 0x%x\n" + }, + {0x01b20001, + "PMU1: enter_lp3: DEBUG: pllctrl3 = 0x%x\n" + }, + {0x01b30000, + "PMU3: Loading DRAM with BIOS supplied MR values and entering self refresh prior to exiting PMU code.\n" + }, + {0x01b40002, + "PMU3: Setting DataBuffer function space of dimmcs 0x%02x to %d\n" + }, + {0x01b50002, + "PMU4: Setting RCW FxRC%Xx = 0x%02x\n" + }, + {0x01b60002, + "PMU4: Setting RCW FxRC%02x = 0x%02x\n" + }, + {0x01b70001, + "PMU1: DDR4 update Rd Pre Setting disable %d\n" + }, + {0x01b80002, + "PMU2: Setting BCW FxBC%Xx = 0x%02x\n" + }, + {0x01b90002, + "PMU2: Setting BCW BC%02x = 0x%02x\n" + }, + {0x01ba0002, + "PMU2: Setting BCW PBA mode FxBC%Xx = 0x%02x\n" + }, + {0x01bb0002, + "PMU2: Setting BCW PBA mode BC%02x = 0x%02x\n" + }, + {0x01bc0003, + "PMU4: BCW value for dimm %d, fspace %d, addr 0x%04x\n" + }, + {0x01bd0002, + "PMU4: DB %d, value 0x%02x\n" + }, + {0x01be0000, + "PMU6: WARNING MREP underflow, set to min value -2 coarse, 0 fine\n" + }, + {0x01bf0004, + "PMU6: LRDIMM Writing final data buffer fine delay value nib %2d, trainDly %3d, fineDly code %2d, new MREP fine %2d\n" + }, + {0x01c00003, + "PMU6: LRDIMM Writing final data buffer fine delay value nib %2d, trainDly %3d, fineDly code %2d\n" + }, + {0x01c10003, + "PMU6: LRDIMM Writing data buffer fine delay type %d nib %2d, code %2d\n" + }, + {0x01c20002, + "PMU6: Writing final data buffer coarse delay value dbyte %2d, coarse = 0x%02x\n" + }, + {0x01c30003, + "PMU4: data 0x%04x at MB addr 0x%08x saved at CSR addr 0x%08x\n" + }, + {0x01c40003, + "PMU4: data 0x%04x at MB addr 0x%08x restored from CSR addr 0x%08x\n" + }, + {0x01c50003, + "PMU4: data 0x%04x at MB addr 0x%08x saved at CSR addr 0x%08x\n" + }, + {0x01c60003, + "PMU4: data 0x%04x at MB addr 0x%08x restored from CSR addr 0x%08x\n" + }, + {0x01c70001, + "PMU3: Update BC00, BC01, BC02 for rank-dimm 0x%02x\n" + }, + {0x01c80000, + "PMU3: Writing D4 RDIMM RCD Control words F0RC00 -> F0RC0F\n" + }, + {0x01c90000, + "PMU3: Disable parity in F0RC0E\n" + }, + {0x01ca0000, + "PMU3: Writing D4 RDIMM RCD Control words F1RC00 -> F1RC05\n" + }, + {0x01cb0000, + "PMU3: Writing D4 RDIMM RCD Control words F1RC1x -> F1RC9x\n" + }, + {0x01cc0000, + "PMU3: Writing D4 Data buffer Control words BC00 -> BC0E\n" + }, + {0x01cd0002, + "PMU1: setAltCL Sending MR0 0x%x cl=%d\n" + }, + {0x01ce0002, + "PMU1: restoreFromAltCL Sending MR0 0x%x cl=%d\n" + }, + {0x01cf0002, + "PMU1: restoreAcsmFromAltCL Sending MR0 0x%x cl=%d\n" + }, + {0x01d00002, + "PMU2: Setting D3R RC%d = 0x%01x\n" + }, + {0x01d10000, + "PMU3: Writing D3 RDIMM RCD Control words RC0 -> RC11\n" + }, + {0x01d20002, + "PMU0: VrefDAC0/1 vddqStart %d dacToVddq %d\n" + }, + {0x01d30001, + "PMU: Error: Messageblock phyVref=0x%x is above the limit for TSMC28's attenuated LPDDR4 receivers. Please see the pub databook\n" + }, + {0x01d40001, + "PMU: Error: Messageblock phyVref=0x%x is above the limit for TSMC28's attenuated DDR4 receivers. Please see the pub databook\n" + }, + {0x01d50001, + "PMU0: PHY VREF @ (%d/1000) VDDQ\n" + }, + {0x01d60002, + "PMU0: initalizing phy vrefDacs to %d ExtVrefRange %x\n" + }, + {0x01d70002, + "PMU0: initalizing global vref to %d range %d\n" + }, + {0x01d80002, + "PMU4: Setting initial device vrefDQ for CS%d to MR6 = 0x%04x\n" + }, + {0x01d90003, + "PMU1: In write_level_fine() csn=%d dimm=%d pstate=%d\n" + }, + {0x01da0000, + "PMU3: Fine write leveling hardware search increasing TxDqsDly until full bursts are seen\n" + }, + {0x01db0000, + "PMU4: WL normalized pos : ........................|........................\n" + }, + {0x01dc0007, + "PMU4: WL margin for nib %2d: %08x%08x%08x%08x%08x%08x\n" + }, + {0x01dd0000, + "PMU4: WL normalized pos : ........................|........................\n" + }, + {0x01de0000, + "PMU3: Exiting write leveling mode\n" + }, + {0x01df0001, + "PMU3: got %d for cl in load_wrlvl_acsm\n" + }, + {0x01e00003, + "PMU1: In write_level_coarse() csn=%d dimm=%d pstate=%d\n" + }, + {0x01e10003, + "PMU3: left eye edge search db:%d ln:%d dly:0x%x\n" + }, + {0x01e20003, + "PMU3: right eye edge search db:%d ln:%d dly:0x%x\n" + }, + {0x01e30004, + "PMU3: eye center db:%d ln:%d dly:0x%x (maxdq:%x)\n" + }, + {0x01e40003, + "PMU3: Wrote to TxDqDly db:%d ln:%d dly:0x%x\n" + }, + {0x01e50003, + "PMU3: Wrote to TxDqDly db:%d ln:%d dly:0x%x\n" + }, + {0x01e60002, + "PMU3: Coarse write leveling dbyte%2d is still failing for TxDqsDly=0x%04x\n" + }, + {0x01e70002, + "PMU4: Coarse write leveling iteration %d saw %d data miscompares across the entire phy\n" + }, + {0x01e80000, + "PMU: Error: Failed write leveling coarse\n" + }, + {0x01e90001, + "PMU3: got %d for cl in load_wrlvl_acsm\n" + }, + {0x01ea0003, + "PMU3: In write_level_coarse() csn=%d dimm=%d pstate=%d\n" + }, + {0x01eb0003, + "PMU3: left eye edge search db:%d ln:%d dly:0x%x\n" + }, + {0x01ec0003, + "PMU3: right eye edge search db: %d ln: %d dly: 0x%x\n" + }, + {0x01ed0004, + "PMU3: eye center db: %d ln: %d dly: 0x%x (maxdq: 0x%x)\n" + }, + {0x01ee0003, + "PMU3: Wrote to TxDqDly db: %d ln: %d dly: 0x%x\n" + }, + {0x01ef0003, + "PMU3: Wrote to TxDqDly db: %d ln: %d dly: 0x%x\n" + }, + {0x01f00002, + "PMU3: Coarse write leveling nibble%2d is still failing for TxDqsDly=0x%04x\n" + }, + {0x01f10002, + "PMU4: Coarse write leveling iteration %d saw %d data miscompares across the entire phy\n" + }, + {0x01f20000, + "PMU: Error: Failed write leveling coarse\n" + }, + {0x01f30000, + "PMU4: WL normalized pos : ................................|................................\n" + }, + {0x01f40009, + "PMU4: WL margin for nib %2d: %08x%08x%08x%08x%08x%08x%08x%08x\n" + }, + {0x01f50000, + "PMU4: WL normalized pos : ................................|................................\n" + }, + {0x01f60001, + "PMU8: Adjust margin after WL coarse to be larger than %d\n" + }, + {0x01f70001, + "PMU: Error: All margin after write leveling coarse are smaller than minMargin %d\n" + }, + {0x01f80002, + "PMU8: Decrement nib %d TxDqsDly by %d fine step\n" + }, + {0x01f90003, + "PMU3: In write_level_coarse() csn=%d dimm=%d pstate=%d\n" + }, + {0x01fa0005, + "PMU2: Write level: dbyte %d nib%d dq/dmbi %2d dqsfine 0x%04x dqDly 0x%04x\n" + }, + {0x01fb0002, + "PMU3: Coarse write leveling nibble%2d is still failing for TxDqsDly=0x%04x\n" + }, + {0x01fc0002, + "PMU4: Coarse write leveling iteration %d saw %d data miscompares across the entire phy\n" + }, + {0x01fd0000, + "PMU: Error: Failed write leveling coarse\n" + }, + {0x01fe0001, + "PMU3: DWL delay = %d\n" + }, + {0x01ff0003, + "PMU3: Errcnt for DWL nib %2d delay = %2d is %d\n" + }, + {0x02000002, + "PMU3: DWL nibble %d sampled a 1 at delay %d\n" + }, + {0x02010003, + "PMU3: DWL nibble %d passed at delay %d. Rising edge was at %d\n" + }, + {0x02020000, + "PMU2: DWL did nto find a rising edge of memclk for all nibbles. Failing nibbles assumed to have rising edge close to fine delay 63\n" + }, + {0x02030002, + "PMU2: Rising edge found in alias window, setting wrlvlDly for nibble %d = %d\n" + }, + {0x02040002, + "PMU: Error: Failed DWL for nib %d with %d one\n" + }, + {0x02050003, + "PMU2: Rising edge not found in alias window with %d one, leaving wrlvlDly for nibble %d = %d\n" + }, + {0x04000000, + "PMU: Error:Mailbox Buffer Overflowed.\n" + }, + {0x04010000, + "PMU: Error:Mailbox Buffer Overflowed.\n" + }, + {0x04020000, + "PMU: ***** Assertion Error - terminating *****\n" + }, + {0x04030002, + "PMU1: swapByte db %d by %d\n" + }, + {0x04040003, + "PMU3: get_cmd_dly max(%d ps, %d memclk) = %d\n" + }, + {0x04050002, + "PMU0: Write CSR 0x%06x 0x%04x\n" + }, + {0x04060002, + "PMU0: hwt_init_ppgc_prbs(): Polynomial: %x, Deg: %d\n" + }, + {0x04070001, + "PMU: Error: acsm_set_cmd to non existent instruction address %d\n" + }, + {0x04080001, + "PMU: Error: acsm_set_cmd with unknown ddr cmd 0x%x\n" + }, + {0x0409000c, + "PMU1: acsm_addr %02x, acsm_flgs %04x, ddr_cmd %02x, cmd_dly %02x, ddr_addr %04x, ddr_bnk %02x, ddr_cs %02x, cmd_rcnt %02x, AcsmSeq0/1/2/3 %04x %04x %04x %04x\n" + }, + {0x040a0000, + "PMU: Error: Polling on ACSM done failed to complete in acsm_poll_done()...\n" + }, + {0x040b0000, + "PMU1: acsm RUN\n" + }, + {0x040c0000, + "PMU1: acsm STOPPED\n" + }, + {0x040d0002, + "PMU1: acsm_init: acsm_mode %04x mxrdlat %04x\n" + }, + {0x040e0002, + "PMU: Error: setAcsmCLCWL: cl and cwl must be each >= 2 and 5, resp. CL=%d CWL=%d\n" + }, + {0x040f0002, + "PMU: Error: setAcsmCLCWL: cl and cwl must be each >= 5. CL=%d CWL=%d\n" + }, + {0x04100002, + "PMU1: setAcsmCLCWL: CASL %04d WCASL %04d\n" + }, + {0x04110001, + "PMU: Error: Reserved value of register F0RC0F found in message block: 0x%04x\n" + }, + {0x04120001, + "PMU3: Written MRS to CS=0x%02x\n" + }, + {0x04130001, + "PMU3: Written MRS to CS=0x%02x\n" + }, + {0x04140000, + "PMU3: Entering Boot Freq Mode.\n" + }, + {0x04150001, + "PMU: Error: Boot clock divider setting of %d is too small\n" + }, + {0x04160000, + "PMU3: Exiting Boot Freq Mode.\n" + }, + {0x04170002, + "PMU3: Writing MR%d OP=%x\n" + }, + {0x04180000, + "PMU: Error: Delay too large in slomo\n" + }, + {0x04190001, + "PMU3: Written MRS to CS=0x%02x\n" + }, + {0x041a0000, + "PMU3: Enable Channel A\n" + }, + {0x041b0000, + "PMU3: Enable Channel B\n" + }, + {0x041c0000, + "PMU3: Enable All Channels\n" + }, + {0x041d0002, + "PMU2: Use PDA mode to set MR%d with value 0x%02x\n" + }, + {0x041e0001, + "PMU3: Written Vref with PDA to CS=0x%02x\n" + }, + {0x041f0000, + "PMU1: start_cal: DEBUG: setting CalRun to 1\n" + }, + {0x04200000, + "PMU1: start_cal: DEBUG: setting CalRun to 0\n" + }, + {0x04210001, + "PMU1: lock_pll_dll: DEBUG: pstate = %d\n" + }, + {0x04220001, + "PMU1: lock_pll_dll: DEBUG: dfifreqxlat_pstate = %d\n" + }, + {0x04230001, + "PMU1: lock_pll_dll: DEBUG: pllbypass = %d\n" + }, + {0x04240001, + "PMU3: SaveLcdlSeed: Saving seed %d\n" + }, + {0x04250000, + "PMU1: in phy_defaults()\n" + }, + {0x04260003, + "PMU3: ACXConf:%d MaxNumDbytes:%d NumDfi:%d\n" + }, + {0x04270005, + "PMU1: setAltAcsmCLCWL setting cl=%d cwl=%d\n" + }, +}; +#endif /* DEBUG */ +#endif diff --git a/drivers/nxp/ddr/phy-gen2/phy.c b/drivers/nxp/ddr/phy-gen2/phy.c new file mode 100644 index 0000000..9e52145 --- /dev/null +++ b/drivers/nxp/ddr/phy-gen2/phy.c @@ -0,0 +1,2678 @@ +/* + * Copyright 2021-2022 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include <errno.h> +#include <stdint.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> + +#include <common/debug.h> +#include "csr.h" +#include <ddr.h> +#include "ddr4fw.h" +#include <drivers/delay_timer.h> +#ifdef NXP_WARM_BOOT +#include <fspi_api.h> +#endif +#include "input.h" +#include <lib/mmio.h> +#include <lib/utils.h> +#include <lib/xlat_tables/xlat_tables_v2.h> +#ifdef DDR_PHY_DEBUG +#include "messages.h" +#endif +#ifdef NXP_WARM_BOOT +#include "phy.h" +#endif +#include "pie.h" + +#define TIMEOUTDEFAULT 500 +#define MAP_PHY_ADDR(pstate, n, instance, offset, c) \ + ((((pstate * n) + instance + c) << 12) + offset) + +static uint32_t map_phy_addr_space(uint32_t addr) +{ + /* 23 bit addressing */ + uint32_t pstate = (addr & U(0x700000)) >> 20U; /* bit 22:20 */ + uint32_t block_type = (addr & U(0x0f0000)) >> 16U; /* bit 19:16 */ + uint32_t instance = (addr & U(0x00f000)) >> 12U; /* bit 15:12 */ + uint32_t offset = (addr & U(0x000fff)); /* bit 11:0 */ + + switch (block_type) { + case 0x0: /* 0x0 : ANIB */ + return MAP_PHY_ADDR(pstate, 12, instance, offset, 0); + case 0x1: /* 0x1 : DBYTE */ + return MAP_PHY_ADDR(pstate, 10, instance, offset, 0x30); + case 0x2: /* 0x2 : MASTER */ + return MAP_PHY_ADDR(pstate, 1, 0, offset, 0x58); + case 0x4: /* 0x4 : ACSM */ + return MAP_PHY_ADDR(pstate, 1, 0, offset, 0x5c); + case 0x5: /* 0x5 : μCTL Memory */ + return MAP_PHY_ADDR(pstate, 0, instance, offset, 0x60); + case 0x7: /* 0x7 : PPGC */ + return MAP_PHY_ADDR(pstate, 0, 0, offset, 0x68); + case 0x9: /* 0x9 : INITENG */ + return MAP_PHY_ADDR(pstate, 1, 0, offset, 0x69); + case 0xc: /* 0xC : DRTUB */ + return MAP_PHY_ADDR(pstate, 0, 0, offset, 0x6d); + case 0xd: /* 0xD : APB Only */ + return MAP_PHY_ADDR(pstate, 0, 0, offset, 0x6e); + default: + printf("ERR: Invalid block_type = 0x%x\n", block_type); + return 0; + } +} + +static inline uint16_t *phy_io_addr(void *phy, uint32_t addr) +{ + return phy + (map_phy_addr_space(addr) << 2); +} + +static inline void phy_io_write16(uint16_t *phy, uint32_t addr, uint16_t data) +{ + mmio_write_16((uintptr_t)phy_io_addr(phy, addr), data); +#ifdef DEBUG_PHY_IO + printf("0x%06x,0x%x\n", addr, data); +#endif +} + +static inline uint16_t phy_io_read16(uint16_t *phy, uint32_t addr) +{ + uint16_t reg = mmio_read_16((uintptr_t) phy_io_addr(phy, addr)); + +#ifdef DEBUG_PHY_IO + printf("R: 0x%06x,0x%x\n", addr, reg); +#endif + + return reg; +} + +#ifdef NXP_APPLY_MAX_CDD + +#define CDD_VAL_READ_ADDR (0x054012) +#define CDD_DATA_LEN (60) + +static void read_phy_reg(uint16_t *phy, uint32_t addr, + uint16_t *buf, uint32_t len) +{ + uint32_t i = 0U; + + for (i = 0U; i < len/2; i++) { + buf[i] = phy_io_read16(phy, (addr + i)); + } +} + +static uint32_t findrank(uint32_t cs_in_use) +{ + uint32_t val = 0U; + + switch (cs_in_use) { + case U(0xf): + val = 4U; + break; + case U(0x3): + val = 2U; + break; + case U(0x1): + val = 1U; + break; + default: + printf("Error - Invalid cs_in_use value\n"); + } + return val; +} + +static uint8_t findmax(uint8_t *buf, uint32_t len) +{ + uint8_t max = 0U; + uint32_t i = 0U; + + for (i = 0U; i < len; i++) { + if (buf[i] > max) { + max = buf[i]; + } + } + + return max; +} + +static void get_cdd_val(uint16_t **phy_ptr, uint32_t rank, uint32_t freq, + uint32_t *tcfg0, uint32_t *tcfg4) +{ + uint8_t cdd[CDD_DATA_LEN+4] = {0U}; + uint32_t i, val = 0U; + uint16_t *phy; + uint8_t buf[16] = {U(0x0)}; + uint8_t trr = 0U, tww = 0U, trw = 0U, twr = 0U; + uint8_t rrmax = 0U, wwmax = 0U, rwmax = 0U, wrmax = 0U; + uint8_t tmp = U(0x0); + uint8_t *c = NULL; + + for (i = 0U; i < NUM_OF_DDRC; i++) { + + phy = phy_ptr[i]; + if (phy == NULL) { + continue; + } + + phy_io_write16(phy, t_apbonly | + csr_micro_cont_mux_sel_addr, U(0x0)); + + read_phy_reg(phy, CDD_VAL_READ_ADDR, + (uint16_t *)&cdd, CDD_DATA_LEN); + + phy_io_write16(phy, t_apbonly | + csr_micro_cont_mux_sel_addr, U(0x1)); + + /* CDD values and address + * + * 0x054012 0x24 cdd[0] CDD[X][X] + * 0x054012 0x25 cdd[1] RR[3][2] + * 0x054013 0x26 cdd[2] RR[3][1] + * 0x054013 0x27 cdd[3] RR[3][0] + * 0x054014 0x28 cdd[4] RR[2][3] + * 0x054014 0x29 cdd[5] RR[2][1] + * 0x054015 0x2a cdd[6] RR[2][0] + * 0x054015 0x2b cdd[7] RR[1][3] + * 0x054016 0x2c cdd[8] RR[1][2] + * 0x054016 0x2d cdd[9] RR[1][0] + * 0x054017 0x2e cdd[10] RR[0][3] + * 0x054017 0x2f cdd[11] RR[0][2] + * 0x054018 0x30 cdd[12] RR[0][1] + + * 0x054018 0x31 cdd[13] WW[3][2] + * 0x054019 0x32 cdd[14] WW[3][1] + * 0x054019 0x33 cdd[15] WW[3][0] + * 0x05401a 0x34 cdd[16] WW[2][3] + * 0x05401a 0x35 cdd[17] WW[2][1] + * 0x05401b 0x36 cdd[18] WW[2][0] + * 0x05401b 0x37 cdd[19] WW[1][3] + * 0x05401c 0x38 cdd[20] WW[1][2] + * 0x05401c 0x39 cdd[21] WW[1][0] + * 0x05401d 0x3a cdd[22] WW[0][3] + * 0x05401d 0x3b cdd[23] WW[0][2] + * 0x05401e 0x3c cdd[24] WW[0][1] + + * 0x05401e 0x3d cdd[25] RW[3][3] + * 0x05401f 0x3e cdd[26] RW[3][2] + * 0x05401f 0x3f cdd[27] RW[3][1] + * 0x054020 0x40 cdd[28] RW[3][0] + * 0x054020 0x41 cdd[29] RW[2][3] + * 0x054021 0x42 cdd[30] RW[2][2] + * 0x054021 0x43 cdd[31] RW[2][1] + * 0x054022 0x44 cdd[32] RW[2][0] + * 0x054022 0x45 cdd[33] RW[1][3] + * 0x054023 0x46 cdd[34] RW[1][2] + * 0x054023 0x47 cdd[35] RW[1][1] + * 0x054024 0x48 cdd[36] RW[1][0] + * 0x054024 0x49 cdd[37] RW[0][3] + * 0x054025 0x4a cdd[38] RW[0][2] + * 0x054025 0x4b cdd[39] RW[0][1] + * 0x054026 0x4c cdd[40] RW[0][0] + + * 0x054026 0x4d cdd[41] WR[3][3] + * 0x054027 0x4e cdd[42] WR[3][2] + * 0x054027 0x4f cdd[43] WR[3][1] + * 0x054028 0x50 cdd[44] WR[3][0] + * 0x054028 0x51 cdd[45] WR[2][3] + * 0x054029 0x52 cdd[46] WR[2][2] + * 0x054029 0x53 cdd[47] WR[2][1] + * 0x05402a 0x54 cdd[48] WR[2][0] + * 0x05402a 0x55 cdd[49] WR[1][3] + * 0x05402b 0x56 cdd[50] WR[1][2] + * 0x05402b 0x57 cdd[51] WR[1][1] + * 0x05402c 0x58 cdd[52] WR[1][0] + * 0x05402c 0x59 cdd[53] WR[0][3] + * 0x05402d 0x5a cdd[54] WR[0][2] + * 0x05402d 0x5b cdd[55] WR[0][1] + * 0x05402e 0x5c cdd[56] WR[0][0] + * 0x05402e 0x5d cdd[57] CDD[Y][Y] + */ + + switch (rank) { + case 1U: + tmp = rwmax; + rwmax = cdd[40]; + if (tmp > rwmax) { + rwmax = tmp; + } + + tmp = wrmax; + wrmax = cdd[56]; + if (tmp > wrmax) { + wrmax = tmp; + } + + break; + + case 2U: + buf[0] = cdd[12]; + buf[1] = cdd[9]; + tmp = rrmax; + rrmax = findmax(buf, 2U); + if (tmp > rrmax) { + rrmax = tmp; + } + + buf[0] = cdd[24]; + buf[1] = cdd[21]; + tmp = wwmax; + wwmax = findmax(buf, 2U); + if (tmp > wwmax) { + wwmax = tmp; + } + + buf[0] = cdd[40]; + buf[1] = cdd[39]; + buf[2] = cdd[36]; + buf[3] = cdd[35]; + tmp = rwmax; + rwmax = findmax(buf, 4U); + if (tmp > rwmax) { + rwmax = tmp; + } + + buf[0] = cdd[56]; + buf[1] = cdd[55]; + buf[2] = cdd[52]; + buf[3] = cdd[51]; + tmp = wrmax; + wrmax = findmax(buf, 4U); + if (tmp > wrmax) { + wrmax = tmp; + } + + break; + + case 4U: + tmp = rrmax; + c = &cdd[1]; + rrmax = findmax(c, 12U); + if (tmp > rrmax) { + rrmax = tmp; + } + + tmp = wwmax; + c = &cdd[13]; + wwmax = findmax(c, 12U); + if (tmp > wwmax) { + wwmax = tmp; + } + + tmp = rwmax; + c = &cdd[25]; + rwmax = findmax(c, 16U); + if (tmp > rwmax) { + rwmax = tmp; + } + + tmp = wrmax; + c = &cdd[41]; + wrmax = findmax(c, 16U); + if (tmp > wrmax) { + wrmax = tmp; + } + + break; + + } + } + + rrmax += 3U; + wwmax += 4U; + + if (wwmax > 7U) { + wwmax = 7U; + } + + if (rrmax > 7U) { + rrmax = 7U; + } + + if (wrmax > U(0xf)) { + wrmax = 0U; + } + + if (rwmax > U(0x7)) { + rwmax = U(0x7); + } + + val = *tcfg0; + tww = (val >> 24U) & U(0x3); + trr = (val >> 26U) & U(0x3); + twr = (val >> 28U) & U(0x3); + trw = (val >> 30U) & U(0x3); + + val = *tcfg4; + tww = tww | (((val >> 8U) & U(0x1)) << 2U); + trr = trr | (((val >> 10U) & U(0x1)) << 2U); + twr = twr | (((val >> 12U) & U(0x1)) << 2U); + trw = trw | (((val >> 14U) & U(0x3)) << 2U); + + if (trr > rrmax) { + rrmax = trr; + } + + if (tww > wwmax) { + wwmax = tww; + } + + if (trw > rwmax) { + rwmax = trw; + } + + if (twr > wrmax) { + wrmax = twr; + } + + debug("CDD rrmax %x wwmax %x rwmax %x wrmax %x\n", + rrmax, wwmax, rwmax, wrmax); + + val = ((wwmax & U(0x3)) << 24U) + | ((rrmax & U(0x3)) << 26U) + | ((wrmax & U(0x3)) << 28U) + | ((rwmax & U(0x3)) << 30U); + + *tcfg0 = (*tcfg0 & U(0x00FFFFFF)) | (val); + + val = (((wwmax >> 2U) & U(0x1)) << 8U) + | (((rrmax >> 2U) & U(0x1)) << 10U) + | (((wrmax >> 2U) & U(0x1)) << 12U) + | (((rwmax >> 2U) & U(0x3)) << 14U); + + *tcfg4 = (*tcfg4 & U(0xffff00ff)) | val; +} +#endif + +#ifdef NXP_WARM_BOOT +int save_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_store, + uint32_t num_of_phy, int train2d) +{ + uint16_t *phy = NULL, value = 0x0; + uint32_t size = 1U, num_of_regs = 1U, phy_store = 0U; + int i = 0, j = 0, ret = -EINVAL; + + ret = xspi_sector_erase(address_to_store, PHY_ERASE_SIZE); + if (ret != 0) { + return -EINVAL; + } + + for (j = 0; j < num_of_phy; j++) { + /* Save training values of all PHYs */ + phy = phy_ptr[j]; + size = sizeof(training_1D_values); + num_of_regs = ARRAY_SIZE(training_1D_values); + + /* Enable access to the internal CSRs */ + phy_io_write16(phy, t_apbonly | + csr_micro_cont_mux_sel_addr, 0x0); + /* Enable clocks in case they were disabled. */ + phy_io_write16(phy, t_drtub | + csr_ucclk_hclk_enables_addr, 0x3); + if (train2d != 0) { + /* Address to store training values is + * to be appended for next PHY + */ + phy_store = address_to_store + (j * + (sizeof(training_1D_values) + + sizeof(training_2D_values))); + } else { + phy_store = address_to_store + (j * + (sizeof(training_1D_values))); + } + debug("Saving 1D Training reg val at: %d\n", phy_store); + for (i = 0; i < num_of_regs; i++) { + value = phy_io_read16(phy, training_1D_values[i].addr); +#ifdef DEBUG_WARM_RESET + debug("%d. Reg: %x, value: %x PHY: %p\n", i, + training_1D_values[i].addr, value, + phy_io_addr(phy, + training_1D_values[i].addr)); +#endif + training_1D_values[i].data = value; + } + /* Storing 1D training values on flash */ + ret = xspi_write(phy_store, (void *)training_1D_values, size); + if (train2d != 0) { + phy_store = phy_store+size; + size = sizeof(training_2D_values); + num_of_regs = ARRAY_SIZE(training_2D_values); + debug("Saving 2D Training reg val at:%d\n", phy_store); + for (i = 0; i < num_of_regs; i++) { + value = phy_io_read16(phy, + training_2D_values[i].addr); + training_2D_values[i].data = value; +#ifdef DEBUG_WARM_RESET + debug("%d.2D addr:0x%x,val:0x%x,PHY:0x%p\n", + i, training_2D_values[i].addr, + value, phy_io_addr(phy, + training_2D_values[i].addr)); +#endif + } + /* Storing 2D training values on flash */ + ret = xspi_write(phy_store, training_2D_values, + size); + } + /* Disable clocks in case they were disabled. */ + phy_io_write16(phy, t_drtub | + csr_ucclk_hclk_enables_addr, 0x0); + /* Disable access to the internal CSRs */ + phy_io_write16(phy, t_apbonly | + csr_micro_cont_mux_sel_addr, 0x1); + } + if (ret != 0) { + return -EINVAL; + } + + return 0; +} + +int restore_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_restore, + uint32_t num_of_phy, int train2d) +{ + uint16_t *phy = NULL; + uint32_t size = 1U, num_of_regs = 1U, phy_store = 0U; + int i = 0, j = 0, ret = -EINVAL; + + debug("Restoring Training register values\n"); + for (j = 0; j < num_of_phy; j++) { + phy = phy_ptr[j]; + size = sizeof(training_1D_values); + num_of_regs = ARRAY_SIZE(training_1D_values); + if (train2d != 0) { + /* The address to restore training values is + * to be appended for next PHY + */ + phy_store = address_to_restore + (j * + (sizeof(training_1D_values) + + sizeof(training_2D_values))); + } else { + phy_store = address_to_restore + (j * + (sizeof(training_1D_values))); + } + /* Enable access to the internal CSRs */ + phy_io_write16(phy, t_apbonly | + csr_micro_cont_mux_sel_addr, 0x0); + /* Enable clocks in case they were disabled. */ + phy_io_write16(phy, t_drtub | + csr_ucclk_hclk_enables_addr, 0x3); + + /* Reading 1D training values from flash*/ + ret = xspi_read(phy_store, (uint32_t *)training_1D_values, + size); + debug("Restoring 1D Training reg val at:%08x\n", phy_store); + for (i = 0; i < num_of_regs; i++) { + phy_io_write16(phy, training_1D_values[i].addr, + training_1D_values[i].data); +#ifdef DEBUG_WARM_RESET + debug("%d. Reg: %x, value: %x PHY: %p\n", i, + training_1D_values[i].addr, + training_1D_values[i].data, + phy_io_addr(phy, + training_1D_values[i].addr)); +#endif + } + if (train2d != 0) { + phy_store = phy_store + size; + size = sizeof(training_2D_values); + num_of_regs = ARRAY_SIZE(training_2D_values); + /* Reading 2D training values from flash */ + ret = xspi_read(phy_store, + (uint32_t *)training_2D_values, size); + debug("Restoring 2D Training reg val at:%08x\n", + phy_store); + for (i = 0; i < num_of_regs; i++) { + phy_io_write16(phy, training_2D_values[i].addr, + training_2D_values[i].data); +#ifdef DEBUG_WARM_RESET + debug("%d. Reg: %x, value: %x PHY: %p\n", i, + training_2D_values[i].addr, + training_2D_values[i].data, + phy_io_addr(phy, + training_1D_values[i].addr)); +#endif + } + } + /* Disable clocks in case they were disabled. */ + phy_io_write16(phy, t_drtub | + csr_ucclk_hclk_enables_addr, 0x0); + /* Disable access to the internal CSRs */ + phy_io_write16(phy, t_apbonly | + csr_micro_cont_mux_sel_addr, 0x1); + } + if (ret != 0) { + return -EINVAL; + } + return 0; +} +#endif + +static void load_pieimage(uint16_t *phy, + enum dimm_types dimm_type) +{ + int i; + int size; + const struct pie *image = NULL; + + switch (dimm_type) { + case UDIMM: + case SODIMM: + case NODIMM: + image = pie_udimm; + size = ARRAY_SIZE(pie_udimm); + break; + case RDIMM: + image = pie_rdimm; + size = ARRAY_SIZE(pie_rdimm); + break; + case LRDIMM: + image = pie_lrdimm; + size = ARRAY_SIZE(pie_lrdimm); + break; + default: + printf("Unsupported DIMM type\n"); + break; + } + + if (image != NULL) { + for (i = 0; i < size; i++) + phy_io_write16(phy, image[i].addr, image[i].data); + } +} + +static void prog_acsm_playback(uint16_t *phy, + const struct input *input, const void *msg) +{ + int vec; + const struct ddr4r1d *msg_blk; + uint16_t acsmplayback[2][3]; + uint32_t f0rc0a; + uint32_t f0rc3x; + uint32_t f0rc5x; + + if (input->basic.dimm_type != RDIMM) { + return; + } + + msg_blk = msg; + f0rc0a = (msg_blk->f0rc0a_d0 & U(0xf)) | U(0xa0); + f0rc3x = (msg_blk->f0rc3x_d0 & U(0xff)) | U(0x300); + f0rc5x = (input->adv.phy_gen2_umctl_f0rc5x & U(0xff)) | U(0x500); + + acsmplayback[0][0] = U(0x3ff) & f0rc0a; + acsmplayback[1][0] = (U(0x1c00) & f0rc0a) >> 10U; + acsmplayback[0][1] = U(0x3ff) & f0rc3x; + acsmplayback[1][1] = (U(0x1c00) & f0rc3x) >> 10U; + acsmplayback[0][2] = U(0x3ff) & f0rc5x; + acsmplayback[1][2] = (U(0x1c00) & f0rc5x) >> 10U; + for (vec = 0; vec < 3; vec++) { + phy_io_write16(phy, t_acsm | (csr_acsm_playback0x0_addr + + (vec << 1)), acsmplayback[0][vec]); + phy_io_write16(phy, t_acsm | (csr_acsm_playback1x0_addr + + (vec << 1)), acsmplayback[1][vec]); + } +} + +static void prog_acsm_ctr(uint16_t *phy, + const struct input *input) +{ + if (input->basic.dimm_type != RDIMM) { + return; + } + + phy_io_write16(phy, t_acsm | csr_acsm_ctrl13_addr, + 0xf << csr_acsm_cke_enb_lsb); + + phy_io_write16(phy, t_acsm | csr_acsm_ctrl0_addr, + csr_acsm_par_mode_mask | csr_acsm_2t_mode_mask); +} + +static void prog_cal_rate_run(uint16_t *phy, + const struct input *input) +{ + int cal_rate; + int cal_interval; + int cal_once; + uint32_t addr; + + cal_interval = input->adv.cal_interval; + cal_once = input->adv.cal_once; + cal_rate = 0x1 << csr_cal_run_lsb | + cal_once << csr_cal_once_lsb | + cal_interval << csr_cal_interval_lsb; + addr = t_master | csr_cal_rate_addr; + phy_io_write16(phy, addr, cal_rate); +} + +static void prog_seq0bdly0(uint16_t *phy, + const struct input *input) +{ + int ps_count[4]; + int frq; + uint32_t addr; + int lower_freq_opt = 0; + + __unused const soc_info_t *soc_info; + + frq = input->basic.frequency >> 1; + ps_count[0] = frq >> 3; /* 0.5 * frq / 4*/ + if (input->basic.frequency < 400) { + lower_freq_opt = (input->basic.dimm_type == RDIMM) ? 7 : 3; + } else if (input->basic.frequency < 533) { + lower_freq_opt = (input->basic.dimm_type == RDIMM) ? 14 : 11; + } + + /* 1.0 * frq / 4 - lower_freq */ + ps_count[1] = (frq >> 2) - lower_freq_opt; + ps_count[2] = (frq << 1) + (frq >> 1); /* 10.0 * frq / 4 */ + +#ifdef DDR_PLL_FIX + soc_info = get_soc_info(); + if (soc_info->svr_reg.bf.maj_ver == 1) { + ps_count[0] = 0x520; /* seq0bdly0 */ + ps_count[1] = 0xa41; /* seq0bdly1 */ + ps_count[2] = 0x668a; /* seq0bdly2 */ + } +#endif + if (frq > 266) { + ps_count[3] = 44; + } else if (frq > 200) { + ps_count[3] = 33; + } else { + ps_count[3] = 16; + } + + addr = t_master | csr_seq0bdly0_addr; + phy_io_write16(phy, addr, ps_count[0]); + + debug("seq0bdly0 = 0x%x\n", phy_io_read16(phy, addr)); + + addr = t_master | csr_seq0bdly1_addr; + phy_io_write16(phy, addr, ps_count[1]); + + debug("seq0bdly1 = 0x%x\n", phy_io_read16(phy, addr)); + + addr = t_master | csr_seq0bdly2_addr; + phy_io_write16(phy, addr, ps_count[2]); + + debug("seq0bdly2 = 0x%x\n", phy_io_read16(phy, addr)); + + addr = t_master | csr_seq0bdly3_addr; + phy_io_write16(phy, addr, ps_count[3]); + + debug("seq0bdly3 = 0x%x\n", phy_io_read16(phy, addr)); +} + +/* Only RDIMM requires msg_blk */ +static void i_load_pie(uint16_t **phy_ptr, + const struct input *input, + const void *msg) +{ + int i; + uint16_t *phy; + + for (i = 0; i < NUM_OF_DDRC; i++) { + phy = phy_ptr[i]; + if (phy == NULL) { + continue; + } + + phy_io_write16(phy, + t_apbonly | csr_micro_cont_mux_sel_addr, + 0U); + + load_pieimage(phy, input->basic.dimm_type); + + prog_seq0bdly0(phy, input); + phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag0_addr, + U(0x0000)); + phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag1_addr, + U(0x0173)); + phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag2_addr, + U(0x0060)); + phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag3_addr, + U(0x6110)); + phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag4_addr, + U(0x2152)); + phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag5_addr, + U(0xdfbd)); + phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag6_addr, + input->basic.dimm_type == RDIMM && + input->adv.phy_gen2_umctl_opt == 1U ? + U(0x6000) : U(0xffff)); + phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag7_addr, + U(0x6152)); + prog_acsm_playback(phy, input, msg); /* rdimm */ + prog_acsm_ctr(phy, input); /* rdimm */ + + phy_io_write16(phy, t_master | csr_cal_zap_addr, U(0x1)); + prog_cal_rate_run(phy, input); + + phy_io_write16(phy, t_drtub | csr_ucclk_hclk_enables_addr, + input->basic.dimm_type == RDIMM ? U(0x2) : 0U); + + phy_io_write16(phy, t_apbonly | csr_micro_cont_mux_sel_addr, 1U); + } +} + +static void phy_gen2_init_input(struct input *input) +{ + int i; + + input->adv.dram_byte_swap = 0; + input->adv.ext_cal_res_val = 0; + input->adv.tx_slew_rise_dq = 0xf; + input->adv.tx_slew_fall_dq = 0xf; + input->adv.tx_slew_rise_ac = 0xf; + input->adv.tx_slew_fall_ac = 0xf; + input->adv.mem_alert_en = 0; + input->adv.mem_alert_puimp = 5; + input->adv.mem_alert_vref_level = 0x29; + input->adv.mem_alert_sync_bypass = 0; + input->adv.cal_interval = 0x9; + input->adv.cal_once = 0; + input->adv.dis_dyn_adr_tri = 0; + input->adv.is2ttiming = 0; + input->adv.d4rx_preamble_length = 0; + input->adv.d4tx_preamble_length = 0; + + for (i = 0; i < 7; i++) { + debug("mr[%d] = 0x%x\n", i, input->mr[i]); + } + + debug("input->cs_d0 = 0x%x\n", input->cs_d0); + debug("input->cs_d1 = 0x%x\n", input->cs_d1); + debug("input->mirror = 0x%x\n", input->mirror); + debug("PHY ODT impedance = %d ohm\n", input->adv.odtimpedance); + debug("PHY DQ driver impedance = %d ohm\n", input->adv.tx_impedance); + debug("PHY Addr driver impedance = %d ohm\n", input->adv.atx_impedance); + + for (i = 0; i < 4; i++) { + debug("odt[%d] = 0x%x\n", i, input->odt[i]); + } + + if (input->basic.dimm_type == RDIMM) { + for (i = 0; i < 16; i++) { + debug("input->rcw[%d] = 0x%x\n", i, input->rcw[i]); + } + debug("input->rcw3x = 0x%x\n", input->rcw3x); + } +} + +/* + * All protocols share the same base structure of message block. + * RDIMM and LRDIMM have more entries defined than UDIMM. + * Create message blocks for 1D and 2D training. + * Update len with message block size. + */ +static int phy_gen2_msg_init(void *msg_1d, + void *msg_2d, + const struct input *input) +{ + struct ddr4u1d *msg_blk = msg_1d; + struct ddr4u2d *msg_blk_2d = msg_2d; + struct ddr4r1d *msg_blk_r; + struct ddr4lr1d *msg_blk_lr; + + switch (input->basic.dimm_type) { + case UDIMM: + case SODIMM: + case NODIMM: + msg_blk->dram_type = U(0x2); + break; + case RDIMM: + msg_blk->dram_type = U(0x4); + break; + case LRDIMM: + msg_blk->dram_type = U(0x5); + break; + default: + ERROR("Unsupported DIMM type\n"); + return -EINVAL; + } + msg_blk->pstate = 0U; + + /*Enable quickRd2D, a substage of read deskew, to 1D training.*/ + msg_blk->reserved00 = U(0x20); + + /*Enable High-Effort WrDQ1D.*/ + msg_blk->reserved00 |= U(0x40); + + /* Enable 1D extra effort training.*/ + msg_blk->reserved1c[3] = U(0x3); + + if (input->basic.dimm_type == LRDIMM) { + msg_blk->sequence_ctrl = U(0x3f1f); + } else { + msg_blk->sequence_ctrl = U(0x031f); + } + msg_blk->phy_config_override = 0U; +#ifdef DDR_PHY_DEBUG + msg_blk->hdt_ctrl = U(0x5); +#else + msg_blk->hdt_ctrl = U(0xc9); +#endif + msg_blk->msg_misc = U(0x0); + msg_blk->dfimrlmargin = U(0x1); + msg_blk->phy_vref = input->vref ? input->vref : U(0x61); + msg_blk->cs_present = input->cs_d0 | input->cs_d1; + msg_blk->cs_present_d0 = input->cs_d0; + msg_blk->cs_present_d1 = input->cs_d1; + if (input->mirror != 0) { + msg_blk->addr_mirror = U(0x0a); /* odd CS are mirrored */ + } + msg_blk->share2dvref_result = 1U; + + msg_blk->acsm_odt_ctrl0 = input->odt[0]; + msg_blk->acsm_odt_ctrl1 = input->odt[1]; + msg_blk->acsm_odt_ctrl2 = input->odt[2]; + msg_blk->acsm_odt_ctrl3 = input->odt[3]; + msg_blk->enabled_dqs = (input->basic.num_active_dbyte_dfi0 + + input->basic.num_active_dbyte_dfi1) * 8; + msg_blk->x16present = input->basic.dram_data_width == 0x10 ? + msg_blk->cs_present : 0; + msg_blk->d4misc = U(0x1); + msg_blk->cs_setup_gddec = U(0x1); + msg_blk->rtt_nom_wr_park0 = 0U; + msg_blk->rtt_nom_wr_park1 = 0U; + msg_blk->rtt_nom_wr_park2 = 0U; + msg_blk->rtt_nom_wr_park3 = 0U; + msg_blk->rtt_nom_wr_park4 = 0U; + msg_blk->rtt_nom_wr_park5 = 0U; + msg_blk->rtt_nom_wr_park6 = 0U; + msg_blk->rtt_nom_wr_park7 = 0U; + msg_blk->mr0 = input->mr[0]; + msg_blk->mr1 = input->mr[1]; + msg_blk->mr2 = input->mr[2]; + msg_blk->mr3 = input->mr[3]; + msg_blk->mr4 = input->mr[4]; + msg_blk->mr5 = input->mr[5]; + msg_blk->mr6 = input->mr[6]; + if ((msg_blk->mr4 & U(0x1c0)) != 0U) { + ERROR("Setting DRAM CAL mode is not supported\n"); + } + + msg_blk->alt_cas_l = 0U; + msg_blk->alt_wcas_l = 0U; + + msg_blk->dramfreq = input->basic.frequency * 2U; + msg_blk->pll_bypass_en = input->basic.pll_bypass; + msg_blk->dfi_freq_ratio = input->basic.dfi_freq_ratio == 0U ? 1U : + input->basic.dfi_freq_ratio == 1U ? 2U : + 4U; + msg_blk->bpznres_val = input->adv.ext_cal_res_val; + msg_blk->disabled_dbyte = 0U; + + debug("msg_blk->dram_type = 0x%x\n", msg_blk->dram_type); + debug("msg_blk->sequence_ctrl = 0x%x\n", msg_blk->sequence_ctrl); + debug("msg_blk->phy_cfg = 0x%x\n", msg_blk->phy_cfg); + debug("msg_blk->x16present = 0x%x\n", msg_blk->x16present); + debug("msg_blk->dramfreq = 0x%x\n", msg_blk->dramfreq); + debug("msg_blk->pll_bypass_en = 0x%x\n", msg_blk->pll_bypass_en); + debug("msg_blk->dfi_freq_ratio = 0x%x\n", msg_blk->dfi_freq_ratio); + debug("msg_blk->phy_odt_impedance = 0x%x\n", + msg_blk->phy_odt_impedance); + debug("msg_blk->phy_drv_impedance = 0x%x\n", + msg_blk->phy_drv_impedance); + debug("msg_blk->bpznres_val = 0x%x\n", msg_blk->bpznres_val); + debug("msg_blk->enabled_dqs = 0x%x\n", msg_blk->enabled_dqs); + debug("msg_blk->acsm_odt_ctrl0 = 0x%x\n", msg_blk->acsm_odt_ctrl0); + debug("msg_blk->acsm_odt_ctrl1 = 0x%x\n", msg_blk->acsm_odt_ctrl1); + debug("msg_blk->acsm_odt_ctrl2 = 0x%x\n", msg_blk->acsm_odt_ctrl2); + debug("msg_blk->acsm_odt_ctrl3 = 0x%x\n", msg_blk->acsm_odt_ctrl3); + + /* RDIMM only */ + if (input->basic.dimm_type == RDIMM || + input->basic.dimm_type == LRDIMM) { + msg_blk_r = (struct ddr4r1d *)msg_blk; + if (msg_blk_r->cs_present_d0 != 0U) { + msg_blk_r->f0rc00_d0 = input->rcw[0]; + msg_blk_r->f0rc01_d0 = input->rcw[1]; + msg_blk_r->f0rc02_d0 = input->rcw[2]; + msg_blk_r->f0rc03_d0 = input->rcw[3]; + msg_blk_r->f0rc04_d0 = input->rcw[4]; + msg_blk_r->f0rc05_d0 = input->rcw[5]; + msg_blk_r->f0rc06_d0 = input->rcw[6]; + msg_blk_r->f0rc07_d0 = input->rcw[7]; + msg_blk_r->f0rc08_d0 = input->rcw[8]; + msg_blk_r->f0rc09_d0 = input->rcw[9]; + msg_blk_r->f0rc0a_d0 = input->rcw[10]; + msg_blk_r->f0rc0b_d0 = input->rcw[11]; + msg_blk_r->f0rc0c_d0 = input->rcw[12]; + msg_blk_r->f0rc0d_d0 = input->rcw[13]; + msg_blk_r->f0rc0e_d0 = input->rcw[14]; + msg_blk_r->f0rc0f_d0 = input->rcw[15]; + msg_blk_r->f0rc3x_d0 = input->rcw3x; + } + if (msg_blk_r->cs_present_d1 != 0) { + msg_blk_r->f0rc00_d1 = input->rcw[0]; + msg_blk_r->f0rc01_d1 = input->rcw[1]; + msg_blk_r->f0rc02_d1 = input->rcw[2]; + msg_blk_r->f0rc03_d1 = input->rcw[3]; + msg_blk_r->f0rc04_d1 = input->rcw[4]; + msg_blk_r->f0rc05_d1 = input->rcw[5]; + msg_blk_r->f0rc06_d1 = input->rcw[6]; + msg_blk_r->f0rc07_d1 = input->rcw[7]; + msg_blk_r->f0rc08_d1 = input->rcw[8]; + msg_blk_r->f0rc09_d1 = input->rcw[9]; + msg_blk_r->f0rc0a_d1 = input->rcw[10]; + msg_blk_r->f0rc0b_d1 = input->rcw[11]; + msg_blk_r->f0rc0c_d1 = input->rcw[12]; + msg_blk_r->f0rc0d_d1 = input->rcw[13]; + msg_blk_r->f0rc0e_d1 = input->rcw[14]; + msg_blk_r->f0rc0f_d1 = input->rcw[15]; + msg_blk_r->f0rc3x_d1 = input->rcw3x; + } + if (input->basic.dimm_type == LRDIMM) { + msg_blk_lr = (struct ddr4lr1d *)msg_blk; + msg_blk_lr->bc0a_d0 = msg_blk_lr->f0rc0a_d0; + msg_blk_lr->bc0a_d1 = msg_blk_lr->f0rc0a_d1; + msg_blk_lr->f0bc6x_d0 = msg_blk_lr->f0rc3x_d0; + msg_blk_lr->f0bc6x_d1 = msg_blk_lr->f0rc3x_d1; + } + } + + /* below is different for 1D and 2D message block */ + if (input->basic.train2d != 0) { + memcpy(msg_blk_2d, msg_blk, sizeof(struct ddr4u1d)); + /*High-Effort WrDQ1D is applicable to 2D traning also*/ + msg_blk_2d->reserved00 |= U(0x40); + msg_blk_2d->sequence_ctrl = U(0x0061); + msg_blk_2d->rx2d_train_opt = 0U; + msg_blk_2d->tx2d_train_opt = 0U; + msg_blk_2d->share2dvref_result = 1U; + msg_blk_2d->delay_weight2d = U(0x20); + msg_blk_2d->voltage_weight2d = U(0x80); + debug("rx2d_train_opt %d, tx2d_train_opt %d\n", + msg_blk_2d->rx2d_train_opt, + msg_blk_2d->tx2d_train_opt); + } + + msg_blk->phy_cfg = (((msg_blk->mr3 & U(0x8)) != 0U) || + ((msg_blk_2d->mr3 & 0x8) != 0U)) ? 0U + : input->adv.is2ttiming; + + return 0; +} + +static void prog_tx_pre_drv_mode(uint16_t *phy, + const struct input *input) +{ + int lane, byte, b_addr, c_addr, p_addr; + int tx_slew_rate, tx_pre_p, tx_pre_n; + int tx_pre_drv_mode = 0x2; + uint32_t addr; + + /* Program TxPreDrvMode with 0x2 */ + /* FIXME: TxPreDrvMode depends on DramType? */ + tx_pre_p = input->adv.tx_slew_rise_dq; + tx_pre_n = input->adv.tx_slew_fall_dq; + tx_slew_rate = tx_pre_drv_mode << csr_tx_pre_drv_mode_lsb | + tx_pre_p << csr_tx_pre_p_lsb | + tx_pre_n << csr_tx_pre_n_lsb; + p_addr = 0; + for (byte = 0; byte < input->basic.num_dbyte; byte++) { + c_addr = byte << 12; + for (lane = 0; lane <= 1; lane++) { + b_addr = lane << 8; + addr = p_addr | t_dbyte | c_addr | b_addr | + csr_tx_slew_rate_addr; + phy_io_write16(phy, addr, tx_slew_rate); + } + } +} + +static void prog_atx_pre_drv_mode(uint16_t *phy, + const struct input *input) +{ + int anib, c_addr; + int atx_slew_rate, atx_pre_p, atx_pre_n, atx_pre_drv_mode, + ck_anib_inst[2]; + uint32_t addr; + + atx_pre_n = input->adv.tx_slew_fall_ac; + atx_pre_p = input->adv.tx_slew_rise_ac; + + if (input->basic.num_anib == 8) { + ck_anib_inst[0] = 1; + ck_anib_inst[1] = 1; + } else if (input->basic.num_anib == 10 || input->basic.num_anib == 12 || + input->basic.num_anib == 13) { + ck_anib_inst[0] = 4; + ck_anib_inst[1] = 5; + } else { + ERROR("Invalid number of aNIBs: %d\n", input->basic.num_anib); + return; + } + + for (anib = 0; anib < input->basic.num_anib; anib++) { + c_addr = anib << 12; + if (anib == ck_anib_inst[0] || anib == ck_anib_inst[1]) { + atx_pre_drv_mode = 0; + } else { + atx_pre_drv_mode = 3; + } + atx_slew_rate = atx_pre_drv_mode << csr_atx_pre_drv_mode_lsb | + atx_pre_n << csr_atx_pre_n_lsb | + atx_pre_p << csr_atx_pre_p_lsb; + addr = t_anib | c_addr | csr_atx_slew_rate_addr; + phy_io_write16(phy, addr, atx_slew_rate); + } +} + +static void prog_enable_cs_multicast(uint16_t *phy, + const struct input *input) +{ + uint32_t addr = t_master | csr_enable_cs_multicast_addr; + + if (input->basic.dimm_type != RDIMM && + input->basic.dimm_type != LRDIMM) { + return; + } + + phy_io_write16(phy, addr, input->adv.cast_cs_to_cid); +} + +static void prog_dfi_rd_data_cs_dest_map(uint16_t *phy, + unsigned int ip_rev, + const struct input *input, + const struct ddr4lr1d *msg) +{ + const struct ddr4lr1d *msg_blk; + uint16_t dfi_xxdestm0 = 0U; + uint16_t dfi_xxdestm1 = 0U; + uint16_t dfi_xxdestm2 = 0U; + uint16_t dfi_xxdestm3 = 0U; + uint16_t dfi_rd_data_cs_dest_map; + uint16_t dfi_wr_data_cs_dest_map; + __unused const soc_info_t *soc_info; + +#ifdef ERRATA_DDR_A011396 + /* Only apply to DDRC 5.05.00 */ + soc_info = get_soc_info(); + if ((soc_info->svr_reg.bf.maj_ver == 1U) && (ip_rev == U(0x50500))) { + phy_io_write16(phy, + t_master | csr_dfi_rd_data_cs_dest_map_addr, + 0U); + return; + } +#endif + + msg_blk = msg; + + switch (input->basic.dimm_type) { + case UDIMM: + case SODIMM: + case NODIMM: + if ((msg_blk->msg_misc & U(0x40)) != 0U) { + dfi_rd_data_cs_dest_map = U(0xa0); + dfi_wr_data_cs_dest_map = U(0xa0); + + phy_io_write16(phy, + t_master | csr_dfi_rd_data_cs_dest_map_addr, + dfi_rd_data_cs_dest_map); + phy_io_write16(phy, + t_master | csr_dfi_wr_data_cs_dest_map_addr, + dfi_wr_data_cs_dest_map); + } + break; + case LRDIMM: + if (msg->cs_present_d1 != 0U) { + dfi_xxdestm2 = 1U; + dfi_xxdestm3 = 1U; + } + + dfi_rd_data_cs_dest_map = + dfi_xxdestm0 << csr_dfi_rd_destm0_lsb | + dfi_xxdestm1 << csr_dfi_rd_destm1_lsb | + dfi_xxdestm2 << csr_dfi_rd_destm2_lsb | + dfi_xxdestm3 << csr_dfi_rd_destm3_lsb; + dfi_wr_data_cs_dest_map = + dfi_xxdestm0 << csr_dfi_wr_destm0_lsb | + dfi_xxdestm1 << csr_dfi_wr_destm1_lsb | + dfi_xxdestm2 << csr_dfi_wr_destm2_lsb | + dfi_xxdestm3 << csr_dfi_wr_destm3_lsb; + phy_io_write16(phy, t_master | csr_dfi_rd_data_cs_dest_map_addr, + dfi_rd_data_cs_dest_map); + phy_io_write16(phy, t_master | csr_dfi_wr_data_cs_dest_map_addr, + dfi_wr_data_cs_dest_map); + + break; + default: + break; + } +} + +static void prog_pll_ctrl(uint16_t *phy, + const struct input *input) +{ + uint32_t addr; + int pll_ctrl1 = 0x21; /* 000100001b */ + int pll_ctrl4 = 0x17f; /* 101111111b */ + int pll_test_mode = 0x24; /* 00100100b */ + + addr = t_master | csr_pll_ctrl1_addr; + phy_io_write16(phy, addr, pll_ctrl1); + + debug("pll_ctrl1 = 0x%x\n", phy_io_read16(phy, addr)); + + addr = t_master | csr_pll_test_mode_addr; + phy_io_write16(phy, addr, pll_test_mode); + + debug("pll_test_mode = 0x%x\n", phy_io_read16(phy, addr)); + + addr = t_master | csr_pll_ctrl4_addr; + phy_io_write16(phy, addr, pll_ctrl4); + + debug("pll_ctrl4 = 0x%x\n", phy_io_read16(phy, addr)); +} + +static void prog_pll_ctrl2(uint16_t *phy, + const struct input *input) +{ + int pll_ctrl2; + uint32_t addr = t_master | csr_pll_ctrl2_addr; + + if (input->basic.frequency / 2 < 235) { + pll_ctrl2 = 0x7; + } else if (input->basic.frequency / 2 < 313) { + pll_ctrl2 = 0x6; + } else if (input->basic.frequency / 2 < 469) { + pll_ctrl2 = 0xb; + } else if (input->basic.frequency / 2 < 625) { + pll_ctrl2 = 0xa; + } else if (input->basic.frequency / 2 < 938) { + pll_ctrl2 = 0x19; + } else if (input->basic.frequency / 2 < 1067) { + pll_ctrl2 = 0x18; + } else { + pll_ctrl2 = 0x19; + } + + phy_io_write16(phy, addr, pll_ctrl2); + + debug("pll_ctrl2 = 0x%x\n", phy_io_read16(phy, addr)); +} + +static void prog_dll_lck_param(uint16_t *phy, const struct input *input) +{ + uint32_t addr = t_master | csr_dll_lockparam_addr; + + phy_io_write16(phy, addr, U(0x212)); + debug("dll_lck_param = 0x%x\n", phy_io_read16(phy, addr)); +} + +static void prog_dll_gain_ctl(uint16_t *phy, const struct input *input) +{ + uint32_t addr = t_master | csr_dll_gain_ctl_addr; + + phy_io_write16(phy, addr, U(0x61)); + debug("dll_gain_ctl = 0x%x\n", phy_io_read16(phy, addr)); +} + +static void prog_pll_pwr_dn(uint16_t *phy, + const struct input *input) +{ + uint32_t addr; + + addr = t_master | csr_pll_pwr_dn_addr; + phy_io_write16(phy, addr, 0U); + + debug("pll_pwrdn = 0x%x\n", phy_io_read16(phy, addr)); +} + +static void prog_ard_ptr_init_val(uint16_t *phy, + const struct input *input) +{ + int ard_ptr_init_val; + uint32_t addr = t_master | csr_ard_ptr_init_val_addr; + + if (input->basic.frequency >= 933) { + ard_ptr_init_val = 0x2; + } else { + ard_ptr_init_val = 0x1; + } + + phy_io_write16(phy, addr, ard_ptr_init_val); +} + +static void prog_dqs_preamble_control(uint16_t *phy, + const struct input *input) +{ + int data; + uint32_t addr = t_master | csr_dqs_preamble_control_addr; + const int wdqsextension = 0; + const int lp4sttc_pre_bridge_rx_en = 0; + const int lp4postamble_ext = 0; + const int lp4tgl_two_tck_tx_dqs_pre = 0; + const int position_dfe_init = 2; + const int dll_rx_preamble_mode = 1; + int two_tck_tx_dqs_pre = input->adv.d4tx_preamble_length; + int two_tck_rx_dqs_pre = input->adv.d4rx_preamble_length; + + data = wdqsextension << csr_wdqsextension_lsb | + lp4sttc_pre_bridge_rx_en << csr_lp4sttc_pre_bridge_rx_en_lsb | + lp4postamble_ext << csr_lp4postamble_ext_lsb | + lp4tgl_two_tck_tx_dqs_pre << csr_lp4tgl_two_tck_tx_dqs_pre_lsb | + position_dfe_init << csr_position_dfe_init_lsb | + two_tck_tx_dqs_pre << csr_two_tck_tx_dqs_pre_lsb | + two_tck_rx_dqs_pre << csr_two_tck_rx_dqs_pre_lsb; + phy_io_write16(phy, addr, data); + + data = dll_rx_preamble_mode << csr_dll_rx_preamble_mode_lsb; + addr = t_master | csr_dbyte_dll_mode_cntrl_addr; + phy_io_write16(phy, addr, data); +} + +static void prog_proc_odt_time_ctl(uint16_t *phy, + const struct input *input) +{ + int proc_odt_time_ctl; + uint32_t addr = t_master | csr_proc_odt_time_ctl_addr; + + if (input->adv.wdqsext != 0) { + proc_odt_time_ctl = 0x3; + } else if (input->basic.frequency <= 933) { + proc_odt_time_ctl = 0xa; + } else if (input->basic.frequency <= 1200) { + if (input->adv.d4rx_preamble_length == 1) { + proc_odt_time_ctl = 0x2; + } else { + proc_odt_time_ctl = 0x6; + } + } else { + if (input->adv.d4rx_preamble_length == 1) { + proc_odt_time_ctl = 0x3; + } else { + proc_odt_time_ctl = 0x7; + } + } + phy_io_write16(phy, addr, proc_odt_time_ctl); +} + +static const struct impedance_mapping map[] = { + { 29, 0x3f }, + { 31, 0x3e }, + { 33, 0x3b }, + { 36, 0x3a }, + { 39, 0x39 }, + { 42, 0x38 }, + { 46, 0x1b }, + { 51, 0x1a }, + { 57, 0x19 }, + { 64, 0x18 }, + { 74, 0x0b }, + { 88, 0x0a }, + { 108, 0x09 }, + { 140, 0x08 }, + { 200, 0x03 }, + { 360, 0x02 }, + { 481, 0x01 }, + {} +}; + +static int map_impedance(int strength) +{ + const struct impedance_mapping *tbl = map; + int val = 0; + + if (strength == 0) { + return 0; + } + + while (tbl->ohm != 0U) { + if (strength < tbl->ohm) { + val = tbl->code; + break; + } + tbl++; + } + + return val; +} + +static int map_odtstren_p(int strength, int hard_macro_ver) +{ + int val = -1; + + if (hard_macro_ver == 4) { + if (strength == 0) { + val = 0; + } else if (strength == 120) { + val = 0x8; + } else if (strength == 60) { + val = 0x18; + } else if (strength == 40) { + val = 0x38; + } else { + printf("error: unsupported ODTStrenP %d\n", strength); + } + } else { + val = map_impedance(strength); + } + + return val; +} + +static void prog_tx_odt_drv_stren(uint16_t *phy, + const struct input *input) +{ + int lane, byte, b_addr, c_addr; + int tx_odt_drv_stren; + int odtstren_p, odtstren_n; + uint32_t addr; + + odtstren_p = map_odtstren_p(input->adv.odtimpedance, + input->basic.hard_macro_ver); + if (odtstren_p < 0) { + return; + } + + odtstren_n = 0; /* always high-z */ + tx_odt_drv_stren = odtstren_n << csr_odtstren_n_lsb | odtstren_p; + for (byte = 0; byte < input->basic.num_dbyte; byte++) { + c_addr = byte << 12; + for (lane = 0; lane <= 1; lane++) { + b_addr = lane << 8; + addr = t_dbyte | c_addr | b_addr | + csr_tx_odt_drv_stren_addr; + phy_io_write16(phy, addr, tx_odt_drv_stren); + } + } +} + +static int map_drvstren_fsdq_p(int strength, int hard_macro_ver) +{ + int val = -1; + + if (hard_macro_ver == 4) { + if (strength == 0) { + val = 0x07; + } else if (strength == 120) { + val = 0x0F; + } else if (strength == 60) { + val = 0x1F; + } else if (strength == 40) { + val = 0x3F; + } else { + printf("error: unsupported drv_stren_fSDq_p %d\n", + strength); + } + } else { + val = map_impedance(strength); + } + + return val; +} + +static int map_drvstren_fsdq_n(int strength, int hard_macro_ver) +{ + int val = -1; + + if (hard_macro_ver == 4) { + if (strength == 0) { + val = 0x00; + } else if (strength == 120) { + val = 0x08; + } else if (strength == 60) { + val = 0x18; + } else if (strength == 40) { + val = 0x38; + } else { + printf("error: unsupported drvStrenFSDqN %d\n", + strength); + } + } else { + val = map_impedance(strength); + } + + return val; +} + +static void prog_tx_impedance_ctrl1(uint16_t *phy, + const struct input *input) +{ + int lane, byte, b_addr, c_addr; + int tx_impedance_ctrl1; + int drv_stren_fsdq_p, drv_stren_fsdq_n; + uint32_t addr; + + drv_stren_fsdq_p = map_drvstren_fsdq_p(input->adv.tx_impedance, + input->basic.hard_macro_ver); + drv_stren_fsdq_n = map_drvstren_fsdq_n(input->adv.tx_impedance, + input->basic.hard_macro_ver); + tx_impedance_ctrl1 = drv_stren_fsdq_n << csr_drv_stren_fsdq_n_lsb | + drv_stren_fsdq_p << csr_drv_stren_fsdq_p_lsb; + + for (byte = 0; byte < input->basic.num_dbyte; byte++) { + c_addr = byte << 12; + for (lane = 0; lane <= 1; lane++) { + b_addr = lane << 8; + addr = t_dbyte | c_addr | b_addr | + csr_tx_impedance_ctrl1_addr; + phy_io_write16(phy, addr, tx_impedance_ctrl1); + } + } +} + +static int map_adrv_stren_p(int strength, int hard_macro_ver) +{ + int val = -1; + + if (hard_macro_ver == 4) { + if (strength == 120) { + val = 0x1c; + } else if (strength == 60) { + val = 0x1d; + } else if (strength == 40) { + val = 0x1f; + } else { + printf("error: unsupported aDrv_stren_p %d\n", + strength); + } + } else { + if (strength == 120) { + val = 0x00; + } else if (strength == 60) { + val = 0x01; + } else if (strength == 40) { + val = 0x03; + } else if (strength == 30) { + val = 0x07; + } else if (strength == 24) { + val = 0x0f; + } else if (strength == 20) { + val = 0x1f; + } else { + printf("error: unsupported aDrv_stren_p %d\n", + strength); + } + } + + return val; +} + +static int map_adrv_stren_n(int strength, int hard_macro_ver) +{ + int val = -1; + + if (hard_macro_ver == 4) { + if (strength == 120) { + val = 0x00; + } else if (strength == 60) { + val = 0x01; + } else if (strength == 40) { + val = 0x03; + } else { + printf("Error: unsupported ADrvStrenP %d\n", strength); + } + } else { + if (strength == 120) { + val = 0x00; + } else if (strength == 60) { + val = 0x01; + } else if (strength == 40) { + val = 0x03; + } else if (strength == 30) { + val = 0x07; + } else if (strength == 24) { + val = 0x0f; + } else if (strength == 20) { + val = 0x1f; + } else { + printf("Error: unsupported ADrvStrenP %d\n", strength); + } + } + + return val; +} + +static void prog_atx_impedance(uint16_t *phy, + const struct input *input) +{ + int anib, c_addr; + int atx_impedance; + int adrv_stren_p; + int adrv_stren_n; + uint32_t addr; + + if (input->basic.hard_macro_ver == 4 && + input->adv.atx_impedance == 20) { + printf("Error:ATxImpedance has to be 40 for HardMacroVer 4\n"); + return; + } + + adrv_stren_p = map_adrv_stren_p(input->adv.atx_impedance, + input->basic.hard_macro_ver); + adrv_stren_n = map_adrv_stren_n(input->adv.atx_impedance, + input->basic.hard_macro_ver); + atx_impedance = adrv_stren_n << csr_adrv_stren_n_lsb | + adrv_stren_p << csr_adrv_stren_p_lsb; + for (anib = 0; anib < input->basic.num_anib; anib++) { + c_addr = anib << 12; + addr = t_anib | c_addr | csr_atx_impedance_addr; + phy_io_write16(phy, addr, atx_impedance); + } +} + +static void prog_dfi_mode(uint16_t *phy, + const struct input *input) +{ + int dfi_mode; + uint32_t addr; + + if (input->basic.dfi1exists == 1) { + dfi_mode = 0x5; /* DFI1 exists but disabled */ + } else { + dfi_mode = 0x1; /* DFI1 does not physically exists */ + } + addr = t_master | csr_dfi_mode_addr; + phy_io_write16(phy, addr, dfi_mode); +} + +static void prog_acx4_anib_dis(uint16_t *phy, const struct input *input) +{ + uint32_t addr; + + addr = t_master | csr_acx4_anib_dis_addr; + phy_io_write16(phy, addr, 0x0); + debug("%s 0x%x\n", __func__, phy_io_read16(phy, addr)); +} + +static void prog_dfi_camode(uint16_t *phy, + const struct input *input) +{ + int dfi_camode = 2; + uint32_t addr = t_master | csr_dfi_camode_addr; + + phy_io_write16(phy, addr, dfi_camode); +} + +static void prog_cal_drv_str0(uint16_t *phy, + const struct input *input) +{ + int cal_drv_str0; + int cal_drv_str_pd50; + int cal_drv_str_pu50; + uint32_t addr; + + cal_drv_str_pu50 = input->adv.ext_cal_res_val; + cal_drv_str_pd50 = cal_drv_str_pu50; + cal_drv_str0 = cal_drv_str_pu50 << csr_cal_drv_str_pu50_lsb | + cal_drv_str_pd50; + addr = t_master | csr_cal_drv_str0_addr; + phy_io_write16(phy, addr, cal_drv_str0); +} + +static void prog_cal_uclk_info(uint16_t *phy, + const struct input *input) +{ + int cal_uclk_ticks_per1u_s; + uint32_t addr; + + cal_uclk_ticks_per1u_s = input->basic.frequency >> 1; + if (cal_uclk_ticks_per1u_s < 24) { + cal_uclk_ticks_per1u_s = 24; + } + + addr = t_master | csr_cal_uclk_info_addr; + phy_io_write16(phy, addr, cal_uclk_ticks_per1u_s); +} + +static void prog_cal_rate(uint16_t *phy, + const struct input *input) +{ + int cal_rate; + int cal_interval; + int cal_once; + uint32_t addr; + + cal_interval = input->adv.cal_interval; + cal_once = input->adv.cal_once; + cal_rate = cal_once << csr_cal_once_lsb | + cal_interval << csr_cal_interval_lsb; + addr = t_master | csr_cal_rate_addr; + phy_io_write16(phy, addr, cal_rate); +} + +static void prog_vref_in_global(uint16_t *phy, + const struct input *input, + const struct ddr4u1d *msg) +{ + int vref_in_global; + int global_vref_in_dac = 0; + int global_vref_in_sel = 0; + uint32_t addr; + + /* + * phy_vref_prcnt = msg->phy_vref / 128.0 + * global_vref_in_dac = (phy_vref_prcnt - 0.345) / 0.005; + */ + global_vref_in_dac = (msg->phy_vref * 1000 - 345 * 128 + 320) / + (5 * 128); + + vref_in_global = global_vref_in_dac << csr_global_vref_in_dac_lsb | + global_vref_in_sel; + addr = t_master | csr_vref_in_global_addr; + phy_io_write16(phy, addr, vref_in_global); +} + +static void prog_dq_dqs_rcv_cntrl(uint16_t *phy, + const struct input *input) +{ + int lane, byte, b_addr, c_addr; + int dq_dqs_rcv_cntrl; + int gain_curr_adj_defval = 0xb; + int major_mode_dbyte = 3; + int dfe_ctrl_defval = 0; + int ext_vref_range_defval = 0; + int sel_analog_vref = 1; + uint32_t addr; + +#ifdef ERRATA_DDR_A050958 + gain_curr_adj_defval = 0x1f; +#endif + + dq_dqs_rcv_cntrl = gain_curr_adj_defval << csr_gain_curr_adj_lsb | + major_mode_dbyte << csr_major_mode_dbyte_lsb | + dfe_ctrl_defval << csr_dfe_ctrl_lsb | + ext_vref_range_defval << csr_ext_vref_range_lsb | + sel_analog_vref << csr_sel_analog_vref_lsb; + for (byte = 0; byte < input->basic.num_dbyte; byte++) { + c_addr = byte << 12; + for (lane = 0; lane <= 1; lane++) { + b_addr = lane << 8; + addr = t_dbyte | c_addr | b_addr | + csr_dq_dqs_rcv_cntrl_addr; + phy_io_write16(phy, addr, dq_dqs_rcv_cntrl); + } + } +} + +static void prog_mem_alert_control(uint16_t *phy, + const struct input *input) +{ + int mem_alert_control; + int mem_alert_control2; + int malertpu_en; + int malertrx_en; + int malertvref_level; + int malertpu_stren; + int malertsync_bypass; + int malertdisable_val_defval = 1; + uint32_t addr; + + if (input->basic.dram_type == DDR4 && input->adv.mem_alert_en == 1) { + malertpu_en = 1; + malertrx_en = 1; + malertpu_stren = input->adv.mem_alert_puimp; + malertvref_level = input->adv.mem_alert_vref_level; + malertsync_bypass = input->adv.mem_alert_sync_bypass; + mem_alert_control = malertdisable_val_defval << 14 | + malertrx_en << 13 | + malertpu_en << 12 | + malertpu_stren << 8 | + malertvref_level; + mem_alert_control2 = malertsync_bypass << + csr_malertsync_bypass_lsb; + addr = t_master | csr_mem_alert_control_addr; + phy_io_write16(phy, addr, mem_alert_control); + addr = t_master | csr_mem_alert_control2_addr; + phy_io_write16(phy, addr, mem_alert_control2); + } +} + +static void prog_dfi_freq_ratio(uint16_t *phy, + const struct input *input) +{ + int dfi_freq_ratio; + uint32_t addr = t_master | csr_dfi_freq_ratio_addr; + + dfi_freq_ratio = input->basic.dfi_freq_ratio; + phy_io_write16(phy, addr, dfi_freq_ratio); +} + +static void prog_tristate_mode_ca(uint16_t *phy, + const struct input *input) +{ + int tristate_mode_ca; + int dis_dyn_adr_tri; + int ddr2tmode; + int ck_dis_val_def = 1; + uint32_t addr = t_master | csr_tristate_mode_ca_addr; + + dis_dyn_adr_tri = input->adv.dis_dyn_adr_tri; + ddr2tmode = input->adv.is2ttiming; + tristate_mode_ca = ck_dis_val_def << csr_ck_dis_val_lsb | + ddr2tmode << csr_ddr2tmode_lsb | + dis_dyn_adr_tri << csr_dis_dyn_adr_tri_lsb; + phy_io_write16(phy, addr, tristate_mode_ca); +} + +static void prog_dfi_xlat(uint16_t *phy, + const struct input *input) +{ + uint16_t loop_vector; + int dfifreqxlat_dat; + int pllbypass_dat; + uint32_t addr; + + /* fIXME: Shall unused P1, P2, P3 be bypassed? */ + pllbypass_dat = input->basic.pll_bypass; /* only [0] is used */ + for (loop_vector = 0; loop_vector < 8; loop_vector++) { + if (loop_vector == 0) { + dfifreqxlat_dat = pllbypass_dat + 0x5555; + } else if (loop_vector == 7) { + dfifreqxlat_dat = 0xf000; + } else { + dfifreqxlat_dat = 0x5555; + } + addr = t_master | (csr_dfi_freq_xlat0_addr + loop_vector); + phy_io_write16(phy, addr, dfifreqxlat_dat); + } +} + +static void prog_dbyte_misc_mode(uint16_t *phy, + const struct input *input, + const struct ddr4u1d *msg) +{ + int dbyte_misc_mode; + int dq_dqs_rcv_cntrl1; + int dq_dqs_rcv_cntrl1_1; + int byte, c_addr; + uint32_t addr; + + dbyte_misc_mode = 0x1 << csr_dbyte_disable_lsb; + dq_dqs_rcv_cntrl1 = 0x1ff << csr_power_down_rcvr_lsb | + 0x1 << csr_power_down_rcvr_dqs_lsb | + 0x1 << csr_rx_pad_standby_en_lsb; + dq_dqs_rcv_cntrl1_1 = (0x100 << csr_power_down_rcvr_lsb | + csr_rx_pad_standby_en_mask); + for (byte = 0; byte < input->basic.num_dbyte; byte++) { + c_addr = byte << 12; + if (byte <= input->basic.num_active_dbyte_dfi0 - 1) { + /* disable RDBI lane if not used. */ + if ((input->basic.dram_data_width != 4) && + (((msg->mr5 >> 12) & 0x1) == 0)) { + addr = t_dbyte + | c_addr + | csr_dq_dqs_rcv_cntrl1_addr; + phy_io_write16(phy, addr, dq_dqs_rcv_cntrl1_1); + } + } else { + addr = t_dbyte | c_addr | csr_dbyte_misc_mode_addr; + phy_io_write16(phy, addr, dbyte_misc_mode); + addr = t_dbyte | c_addr | csr_dq_dqs_rcv_cntrl1_addr; + phy_io_write16(phy, addr, dq_dqs_rcv_cntrl1); + } + } +} + +static void prog_master_x4config(uint16_t *phy, + const struct input *input) +{ + int master_x4config; + int x4tg; + uint32_t addr = t_master | csr_master_x4config_addr; + + x4tg = input->basic.dram_data_width == 4 ? 0xf : 0; + master_x4config = x4tg << csr_x4tg_lsb; + phy_io_write16(phy, addr, master_x4config); +} + +static void prog_dmipin_present(uint16_t *phy, + const struct input *input, + const struct ddr4u1d *msg) +{ + int dmipin_present; + uint32_t addr = t_master | csr_dmipin_present_addr; + + dmipin_present = (msg->mr5 >> 12) & 0x1; + phy_io_write16(phy, addr, dmipin_present); +} + +static void prog_dfi_phyupd(uint16_t *phy, + const struct input *input) +{ + int dfiphyupd_dat; + uint32_t addr; + + addr = t_master | (csr_dfiphyupd_addr); + dfiphyupd_dat = phy_io_read16(phy, addr) & + ~csr_dfiphyupd_threshold_mask; + + phy_io_write16(phy, addr, dfiphyupd_dat); +} + +static void prog_cal_misc2(uint16_t *phy, + const struct input *input) +{ + int cal_misc2_dat, cal_drv_pdth_data, cal_offsets_dat; + uint32_t addr; + + addr = t_master | (csr_cal_misc2_addr); + cal_misc2_dat = phy_io_read16(phy, addr) | + (1 << csr_cal_misc2_err_dis); + + phy_io_write16(phy, addr, cal_misc2_dat); + + addr = t_master | (csr_cal_offsets_addr); + + cal_drv_pdth_data = 0x9 << 6; + cal_offsets_dat = (phy_io_read16(phy, addr) & ~csr_cal_drv_pdth_mask) + | cal_drv_pdth_data; + + phy_io_write16(phy, addr, cal_offsets_dat); +} + +static int c_init_phy_config(uint16_t **phy_ptr, + unsigned int ip_rev, + const struct input *input, + const void *msg) +{ + int i; + uint16_t *phy; + __unused const soc_info_t *soc_info; + + for (i = 0; i < NUM_OF_DDRC; i++) { + phy = phy_ptr[i]; + if (phy == NULL) { + continue; + } + + debug("Initialize PHY %d config\n", i); + prog_dfi_phyupd(phy, input); + prog_cal_misc2(phy, input); + prog_tx_pre_drv_mode(phy, input); + prog_atx_pre_drv_mode(phy, input); + prog_enable_cs_multicast(phy, input); /* rdimm and lrdimm */ + prog_dfi_rd_data_cs_dest_map(phy, ip_rev, input, msg); + prog_pll_ctrl2(phy, input); +#ifdef DDR_PLL_FIX + soc_info = get_soc_info(); + debug("SOC_SI_REV = %x\n", soc_info->svr_reg.bf.maj_ver); + if (soc_info->svr_reg.bf.maj_ver == 1) { + prog_pll_pwr_dn(phy, input); + + /*Enable FFE aka TxEqualizationMode for rev1 SI*/ + phy_io_write16(phy, 0x010048, 0x1); + } +#endif + prog_ard_ptr_init_val(phy, input); + prog_dqs_preamble_control(phy, input); + prog_dll_lck_param(phy, input); + prog_dll_gain_ctl(phy, input); + prog_proc_odt_time_ctl(phy, input); + prog_tx_odt_drv_stren(phy, input); + prog_tx_impedance_ctrl1(phy, input); + prog_atx_impedance(phy, input); + prog_dfi_mode(phy, input); + prog_dfi_camode(phy, input); + prog_cal_drv_str0(phy, input); + prog_cal_uclk_info(phy, input); + prog_cal_rate(phy, input); + prog_vref_in_global(phy, input, msg); + prog_dq_dqs_rcv_cntrl(phy, input); + prog_mem_alert_control(phy, input); + prog_dfi_freq_ratio(phy, input); + prog_tristate_mode_ca(phy, input); + prog_dfi_xlat(phy, input); + prog_dbyte_misc_mode(phy, input, msg); + prog_master_x4config(phy, input); + prog_dmipin_present(phy, input, msg); + prog_acx4_anib_dis(phy, input); + } + + return 0; +} + +static uint32_t get_mail(uint16_t *phy, int stream) +{ + int timeout; + uint32_t mail = 0U; + + timeout = TIMEOUTDEFAULT; + while (((--timeout) != 0) && + ((phy_io_read16(phy, t_apbonly | csr_uct_shadow_regs) + & uct_write_prot_shadow_mask) != 0)) { + mdelay(10); + } + if (timeout == 0) { + ERROR("Timeout getting mail from PHY\n"); + return 0xFFFF; + } + + mail = phy_io_read16(phy, t_apbonly | + csr_uct_write_only_shadow); + if (stream != 0) { + mail |= phy_io_read16(phy, t_apbonly | + csr_uct_dat_write_only_shadow) << 16; + } + + /* Ack */ + phy_io_write16(phy, t_apbonly | csr_dct_write_prot, 0); + + timeout = TIMEOUTDEFAULT; + while (((--timeout) != 0) && + ((phy_io_read16(phy, t_apbonly | csr_uct_shadow_regs) + & uct_write_prot_shadow_mask) == 0)) { + mdelay(1); + } + if (timeout == 0) { + ERROR("Timeout ack PHY mail\n"); + } + + /* completed */ + phy_io_write16(phy, t_apbonly | csr_dct_write_prot, 1U); + + return mail; +} + +#ifdef DDR_PHY_DEBUG +static const char *lookup_msg(uint32_t index, int train2d) +{ + int i; + int size; + const struct phy_msg *messages; + const char *ptr = NULL; + + if (train2d != 0) { + messages = messages_2d; + size = ARRAY_SIZE(messages_2d); + } else { + messages = messages_1d; + size = ARRAY_SIZE(messages_1d); + } + for (i = 0; i < size; i++) { + if (messages[i].index == index) { + ptr = messages[i].msg; + break; + } + } + + return ptr; +} +#endif + +#define MAX_ARGS 32 +static void decode_stream_message(uint16_t *phy, int train2d) +{ + uint32_t index __unused; + + __unused const char *format; + __unused uint32_t args[MAX_ARGS]; + __unused int i; + +#ifdef DDR_PHY_DEBUG + index = get_mail(phy, 1); + if ((index & 0xffff) > MAX_ARGS) { /* up to MAX_ARGS args so far */ + printf("Program error in %s\n", __func__); + } + for (i = 0; i < (index & 0xffff) && i < MAX_ARGS; i++) { + args[i] = get_mail(phy, 1); + } + + format = lookup_msg(index, train2d); + if (format != NULL) { + printf("0x%08x: ", index); + printf(format, args[0], args[1], args[2], args[3], args[4], + args[5], args[6], args[7], args[8], args[9], args[10], + args[11], args[12], args[13], args[14], args[15], + args[16], args[17], args[18], args[19], args[20], + args[21], args[22], args[23], args[24], args[25], + args[26], args[27], args[28], args[29], args[30], + args[31]); + } +#endif +} + +static int wait_fw_done(uint16_t *phy, int train2d) +{ + uint32_t mail = 0U; + + while (mail == U(0x0)) { + mail = get_mail(phy, 0); + switch (mail) { + case U(0x7): + debug("%s Training completed\n", train2d ? "2D" : "1D"); + break; + case U(0xff): + debug("%s Training failure\n", train2d ? "2D" : "1D"); + break; + case U(0x0): + debug("End of initialization\n"); + mail = 0U; + break; + case U(0x1): + debug("End of fine write leveling\n"); + mail = 0U; + break; + case U(0x2): + debug("End of read enable training\n"); + mail = 0U; + break; + case U(0x3): + debug("End of read delay center optimization\n"); + mail = 0U; + break; + case U(0x4): + debug("End of write delay center optimization\n"); + mail = 0U; + break; + case U(0x5): + debug("End of 2D read delay/voltage center optimztn\n"); + mail = 0U; + break; + case U(0x6): + debug("End of 2D write delay/voltage center optmztn\n"); + mail = 0U; + break; + case U(0x8): + decode_stream_message(phy, train2d); + mail = 0U; + break; + case U(0x9): + debug("End of max read latency training\n"); + mail = 0U; + break; + case U(0xa): + debug("End of read dq deskew training\n"); + mail = 0U; + break; + case U(0xc): + debug("End of LRDIMM Specific training, including:\n"); + debug("/tDWL, MREP, MRD and MWD\n"); + mail = 0U; + break; + case U(0xd): + debug("End of CA training\n"); + mail = 0U; + break; + case U(0xfd): + debug("End of MPR read delay center optimization\n"); + mail = 0U; + break; + case U(0xfe): + debug("End of Write leveling coarse delay\n"); + mail = 0U; + break; + case U(0xffff): + debug("Timed out\n"); + break; + default: + mail = 0U; + break; + } + } + + if (mail == U(0x7)) { + return 0; + } else if (mail == U(0xff)) { + return -EIO; + } else if (mail == U(0xffff)) { + return -ETIMEDOUT; + } + + debug("PHY_GEN2 FW: Unxpected mail = 0x%x\n", mail); + + return -EINVAL; +} + +static int g_exec_fw(uint16_t **phy_ptr, int train2d, struct input *input) +{ + int ret = -EINVAL; + int i; + uint16_t *phy; + + for (i = 0; i < NUM_OF_DDRC; i++) { + phy = phy_ptr[i]; + if (phy == NULL) { + continue; + } + debug("Applying PLL optimal settings\n"); + prog_pll_ctrl2(phy, input); + prog_pll_ctrl(phy, input); + phy_io_write16(phy, + t_apbonly | csr_micro_cont_mux_sel_addr, + 0x1); + phy_io_write16(phy, + t_apbonly | csr_micro_reset_addr, + csr_reset_to_micro_mask | + csr_stall_to_micro_mask); + phy_io_write16(phy, + t_apbonly | csr_micro_reset_addr, + csr_stall_to_micro_mask); + phy_io_write16(phy, + t_apbonly | csr_micro_reset_addr, + 0); + + ret = wait_fw_done(phy, train2d); + if (ret == -ETIMEDOUT) { + ERROR("Wait timed out: Firmware execution on PHY %d\n", + i); + } + } + return ret; +} + +static inline int send_fw(uint16_t *phy, + uint32_t dst, + uint16_t *img, + uint32_t size) +{ + uint32_t i; + + if ((size % 2U) != 0U) { + ERROR("Wrong image size 0x%x\n", size); + return -EINVAL; + } + + for (i = 0U; i < size / 2; i++) { + phy_io_write16(phy, dst + i, *(img + i)); + } + + return 0; +} + +static int load_fw(uint16_t **phy_ptr, + struct input *input, + int train2d, + void *msg, + size_t len, + uintptr_t phy_gen2_fw_img_buf, + int (*img_loadr)(unsigned int, uintptr_t *, uint32_t *), + uint32_t warm_boot_flag) +{ + uint32_t imem_id, dmem_id; + uintptr_t image_buf; + uint32_t size; + int ret; + int i; + uint16_t *phy; + + switch (input->basic.dimm_type) { + case UDIMM: + case SODIMM: + case NODIMM: + imem_id = train2d ? DDR_IMEM_UDIMM_2D_IMAGE_ID : + DDR_IMEM_UDIMM_1D_IMAGE_ID; + dmem_id = train2d ? DDR_DMEM_UDIMM_2D_IMAGE_ID : + DDR_DMEM_UDIMM_1D_IMAGE_ID; + break; + case RDIMM: + imem_id = train2d ? DDR_IMEM_RDIMM_2D_IMAGE_ID : + DDR_IMEM_RDIMM_1D_IMAGE_ID; + dmem_id = train2d ? DDR_DMEM_RDIMM_2D_IMAGE_ID : + DDR_DMEM_RDIMM_1D_IMAGE_ID; + break; + default: + ERROR("Unsupported DIMM type\n"); + return -EINVAL; + } + + size = PHY_GEN2_MAX_IMAGE_SIZE; + image_buf = (uintptr_t)phy_gen2_fw_img_buf; + ret = img_loadr(imem_id, &image_buf, &size); + if (ret != 0) { + ERROR("Failed to load %d firmware.\n", imem_id); + return ret; + } + debug("Loaded Imaged id %d of size %x at address %lx\n", + imem_id, size, image_buf); + + for (i = 0; i < NUM_OF_DDRC; i++) { + phy = phy_ptr[i]; + if (phy == NULL) { + continue; + } + + if (warm_boot_flag != DDR_WARM_BOOT) { + if (train2d == 0) { + phy_io_write16(phy, t_master | + csr_mem_reset_l_addr, + csr_protect_mem_reset_mask); + } + } + /* Enable access to the internal CSRs */ + phy_io_write16(phy, t_apbonly | csr_micro_cont_mux_sel_addr, 0); + + ret = send_fw(phy, PHY_GEN2_IMEM_ADDR, + (uint16_t *)image_buf, size); + if (ret != 0) { + return ret; + } + } + + size = PHY_GEN2_MAX_IMAGE_SIZE; + image_buf = (uintptr_t)phy_gen2_fw_img_buf; + ret = img_loadr(dmem_id, &image_buf, &size); + if (ret != 0) { + ERROR("Failed to load %d firmware.\n", dmem_id); + return ret; + } + debug("Loaded Imaged id %d of size %x at address %lx\n", + dmem_id, size, image_buf); + image_buf += len; + size -= len; + + for (i = 0; i < NUM_OF_DDRC; i++) { + phy = phy_ptr[i]; + if (phy == NULL) { + continue; + } + + ret = send_fw(phy, PHY_GEN2_DMEM_ADDR, msg, len); + if (ret != 0) { + return ret; + } + + ret = send_fw(phy, PHY_GEN2_DMEM_ADDR + len / 2, + (uint16_t *)image_buf, size); + if (ret != 0) { + return ret; + } + } + + return ret; +} + +static void parse_odt(const unsigned int val, + const int read, + const int i, + const unsigned int cs_d0, + const unsigned int cs_d1, + unsigned int *odt) +{ + int shift = read ? 4 : 0; + int j; + + if (i < 0 || i > 3) { + printf("Error: invalid chip-select value\n"); + } + switch (val) { + case DDR_ODT_CS: + odt[i] |= (1 << i) << shift; + break; + case DDR_ODT_ALL_OTHER_CS: + for (j = 0; j < DDRC_NUM_CS; j++) { + if (i == j) { + continue; + } + if (((cs_d0 | cs_d1) & (1 << j)) == 0) { + continue; + } + odt[j] |= (1 << i) << shift; + } + break; + case DDR_ODT_CS_AND_OTHER_DIMM: + odt[i] |= (1 << i) << 4; + /* fallthrough */ + case DDR_ODT_OTHER_DIMM: + for (j = 0; j < DDRC_NUM_CS; j++) { + if ((((cs_d0 & (1 << i)) != 0) && + ((cs_d1 & (1 << j)) != 0)) || + (((cs_d1 & (1 << i)) != 0) && + ((cs_d0 & (1 << j)) != 0))) { + odt[j] |= (1 << i) << shift; + } + } + break; + case DDR_ODT_ALL: + for (j = 0; j < DDRC_NUM_CS; j++) { + if (((cs_d0 | cs_d1) & (1 << j)) == 0) { + continue; + } + odt[j] |= (1 << i) << shift; + } + break; + case DDR_ODT_SAME_DIMM: + for (j = 0; j < DDRC_NUM_CS; j++) { + if ((((cs_d0 & (1 << i)) != 0) && + ((cs_d0 & (1 << j)) != 0)) || + (((cs_d1 & (1 << i)) != 0) && + ((cs_d1 & (1 << j)) != 0))) { + odt[j] |= (1 << i) << shift; + } + } + break; + case DDR_ODT_OTHER_CS_ONSAMEDIMM: + for (j = 0; j < DDRC_NUM_CS; j++) { + if (i == j) { + continue; + } + if ((((cs_d0 & (1 << i)) != 0) && + ((cs_d0 & (1 << j)) != 0)) || + (((cs_d1 & (1 << i)) != 0) && + ((cs_d1 & (1 << j)) != 0))) { + odt[j] |= (1 << i) << shift; + } + } + break; + case DDR_ODT_NEVER: + break; + default: + break; + } +} + +#ifdef DEBUG_DDR_INPUT_CONFIG +char *dram_types_str[] = { + "DDR4", + "DDR3", + "LDDDR4", + "LPDDR3", + "LPDDR2", + "DDR5" +}; + +char *dimm_types_str[] = { + "UDIMM", + "SODIMM", + "RDIMM", + "LRDIMM", + "NODIMM", +}; + + +static void print_jason_format(struct input *input, + struct ddr4u1d *msg_1d, + struct ddr4u2d *msg_2d) +{ + + printf("\n{"); + printf("\n \"dram_type\": \"%s\",", dram_types_str[input->basic.dram_type]); + printf("\n \"dimm_type\": \"%s\",", dimm_types_str[input->basic.dimm_type]); + printf("\n \"hard_macro_ver\": \"%d\",", input->basic.hard_macro_ver); + printf("\n \"num_dbyte\": \"0x%04x\",", (unsigned int)input->basic.num_dbyte); + printf("\n \"num_active_dbyte_dfi0\": \"0x%04x\",", (unsigned int)input->basic.num_active_dbyte_dfi0); + printf("\n \"num_anib\": \"0x%04x\",", (unsigned int)input->basic.num_anib); + printf("\n \"num_rank_dfi0\": \"0x%04x\",", (unsigned int)input->basic.num_rank_dfi0); + printf("\n \"num_pstates\": \"0x%04x\",", (unsigned int)input->basic.num_pstates); + printf("\n \"frequency\": \"%d\",", input->basic.frequency); + printf("\n \"pll_bypass\": \"0x%04x\",", (unsigned int)input->basic.dfi_freq_ratio); + printf("\n \"dfi_freq_ratio\": \"0x%04x\",", (unsigned int)input->basic.dfi_freq_ratio); + printf("\n \"dfi1_exists\": \"0x%04x\",", (unsigned int)input->basic.dfi1exists); + printf("\n \"dram_data_width\": \"0x%04x\",", (unsigned int)input->basic.dram_data_width); + printf("\n \"dram_byte_swap\": \"0x%04x\",", (unsigned int)input->adv.dram_byte_swap); + printf("\n \"ext_cal_res_val\": \"0x%04x\",", (unsigned int)input->adv.ext_cal_res_val); + printf("\n \"tx_slew_rise_dq\": \"0x%04x\",", (unsigned int)input->adv.tx_slew_rise_dq); + printf("\n \"tx_slew_fall_dq\": \"0x%04x\",", (unsigned int)input->adv.tx_slew_fall_dq); + printf("\n \"tx_slew_rise_ac\": \"0x%04x\",", (unsigned int)input->adv.tx_slew_rise_ac); + printf("\n \"tx_slew_fall_ac\": \"0x%04x\",", (unsigned int)input->adv.tx_slew_fall_ac); + printf("\n \"odt_impedance\": \"%d\",", input->adv.odtimpedance); + printf("\n \"tx_impedance\": \"%d\",", input->adv.tx_impedance); + printf("\n \"atx_impedance\": \"%d\",", input->adv.atx_impedance); + printf("\n \"mem_alert_en\": \"0x%04x\",", (unsigned int)input->adv.mem_alert_en); + printf("\n \"mem_alert_pu_imp\": \"0x%04x\",", (unsigned int)input->adv.mem_alert_puimp); + printf("\n \"mem_alert_vref_level\": \"0x%04x\",", (unsigned int)input->adv.mem_alert_vref_level); + printf("\n \"mem_alert_sync_bypass\": \"0x%04x\",", (unsigned int)input->adv.mem_alert_sync_bypass); + printf("\n \"cal_interval\": \"0x%04x\",", (unsigned int)input->adv.cal_interval); + printf("\n \"cal_once\": \"0x%04x\",", (unsigned int)input->adv.cal_once); + printf("\n \"dis_dyn_adr_tri\": \"0x%04x\",", (unsigned int)input->adv.dis_dyn_adr_tri); + printf("\n \"is2t_timing\": \"0x%04x\",", (unsigned int)input->adv.is2ttiming); + printf("\n \"d4rx_preabmle_length\": \"0x%04x\",", (unsigned int)input->adv.d4rx_preamble_length); + printf("\n \"d4tx_preamble_length\": \"0x%04x\",", (unsigned int)input->adv.d4tx_preamble_length); + printf("\n \"msg_misc\": \"0x%02x\",", (unsigned int)msg_1d->msg_misc); + printf("\n \"reserved00\": \"0x%01x\",", (unsigned int)msg_1d->reserved00); + printf("\n \"hdt_ctrl\": \"0x%02x\",", (unsigned int)msg_1d->hdt_ctrl); + printf("\n \"cs_present\": \"0x%02x\",", (unsigned int)msg_1d->cs_present); + printf("\n \"phy_vref\": \"0x%02x\",", (unsigned int)msg_1d->phy_vref); + printf("\n \"dfi_mrl_margin\": \"0x%02x\",", (unsigned int)msg_1d->dfimrlmargin); + printf("\n \"addr_mirror\": \"0x%02x\",", (unsigned int)msg_1d->addr_mirror); + printf("\n \"wr_odt_pat_rank0\": \"0x%02x\",", (unsigned int)(msg_1d->acsm_odt_ctrl0 & 0x0f)); + printf("\n \"wr_odt_pat_rank1\": \"0x%02x\",", (unsigned int)(msg_1d->acsm_odt_ctrl1 & 0x0f)); + printf("\n \"wr_odt_pat_rank2\": \"0x%02x\",", (unsigned int)(msg_1d->acsm_odt_ctrl2 & 0x0f)); + printf("\n \"wr_odt_pat_rank3\": \"0x%02x\",", (unsigned int)(msg_1d->acsm_odt_ctrl3 & 0x0f)); + printf("\n \"rd_odt_pat_rank0\": \"0x%02x\",", (unsigned int)(msg_1d->acsm_odt_ctrl0 & 0xf0)); + printf("\n \"rd_odt_pat_rank1\": \"0x%02x\",", (unsigned int)(msg_1d->acsm_odt_ctrl1 & 0xf0)); + printf("\n \"rd_odt_pat_rank2\": \"0x%02x\",", (unsigned int)(msg_1d->acsm_odt_ctrl2 & 0xf0)); + printf("\n \"rd_odt_pat_rank3\": \"0x%02x\",", (unsigned int)(msg_1d->acsm_odt_ctrl3 & 0xf0)); + printf("\n \"d4_misc\": \"0x%01x\",", (unsigned int)msg_1d->d4misc); + printf("\n \"share_2d_vref_results\": \"0x%01x\",", (unsigned int)msg_1d->share2dvref_result); + printf("\n \"sequence_ctrl\": \"0x%04x\",", (unsigned int)msg_1d->sequence_ctrl); + printf("\n \"mr0\": \"0x%04x\",", (unsigned int)msg_1d->mr0); + printf("\n \"mr1\": \"0x%04x\",", (unsigned int)msg_1d->mr1); + printf("\n \"mr2\": \"0x%04x\",", (unsigned int)msg_1d->mr2); + printf("\n \"mr3\": \"0x%04x\",", (unsigned int)msg_1d->mr3); + printf("\n \"mr4\": \"0x%04x\",", (unsigned int)msg_1d->mr4); + printf("\n \"mr5\": \"0x%04x\",", (unsigned int)msg_1d->mr5); + printf("\n \"mr6\": \"0x%04x\",", (unsigned int)msg_1d->mr6); + printf("\n \"alt_cal_l\": \"0x%04x\",", (unsigned int)msg_1d->alt_cas_l); + printf("\n \"alt_wcal_l\": \"0x%04x\",", (unsigned int)msg_1d->alt_wcas_l); + printf("\n \"sequence_ctrl_2d\": \"0x%04x\",", (unsigned int)msg_2d->sequence_ctrl); + printf("\n \"rtt_nom_wr_park0\": \"0x%01x\",", (unsigned int)msg_1d->rtt_nom_wr_park0); + printf("\n \"rtt_nom_wr_park1\": \"0x%01x\",", (unsigned int)msg_1d->rtt_nom_wr_park1); + printf("\n \"rtt_nom_wr_park2\": \"0x%01x\",", (unsigned int)msg_1d->rtt_nom_wr_park2); + printf("\n \"rtt_nom_wr_park3\": \"0x%01x\",", (unsigned int)msg_1d->rtt_nom_wr_park3); + printf("\n \"rtt_nom_wr_park4\": \"0x%01x\",", (unsigned int)msg_1d->rtt_nom_wr_park4); + printf("\n \"rtt_nom_wr_park5\": \"0x%01x\",", (unsigned int)msg_1d->rtt_nom_wr_park5); + printf("\n \"rtt_nom_wr_park6\": \"0x%01x\",", (unsigned int)msg_1d->rtt_nom_wr_park6); + printf("\n \"rtt_nom_wr_park7\": \"0x%01x\"", (unsigned int)msg_1d->rtt_nom_wr_park7); + printf("\n}"); + printf("\n"); +} +#endif + +int compute_ddr_phy(struct ddr_info *priv) +{ + const unsigned long clk = priv->clk; + const struct memctl_opt *popts = &priv->opt; + const struct ddr_conf *conf = &priv->conf; + const struct dimm_params *dimm_param = &priv->dimm; + struct ddr_cfg_regs *regs = &priv->ddr_reg; + int ret; + static struct input input; + static struct ddr4u1d msg_1d; + static struct ddr4u2d msg_2d; + unsigned int i; + unsigned int odt_rd, odt_wr; + __unused const soc_info_t *soc_info; +#ifdef NXP_APPLY_MAX_CDD + unsigned int tcfg0, tcfg4, rank; +#endif + + if (dimm_param == NULL) { + ERROR("Empty DIMM parameters.\n"); + return -EINVAL; + } + + zeromem(&input, sizeof(input)); + zeromem(&msg_1d, sizeof(msg_1d)); + zeromem(&msg_2d, sizeof(msg_2d)); + + input.basic.dram_type = DDR4; + /* FIXME: Add condition for LRDIMM */ + input.basic.dimm_type = (dimm_param->rdimm != 0) ? RDIMM : UDIMM; + input.basic.num_dbyte = dimm_param->primary_sdram_width / 8 + + dimm_param->ec_sdram_width / 8; + input.basic.num_active_dbyte_dfi0 = input.basic.num_dbyte; + input.basic.num_rank_dfi0 = dimm_param->n_ranks; + input.basic.dram_data_width = dimm_param->device_width; + input.basic.hard_macro_ver = 0xa; + input.basic.num_pstates = 1; + input.basic.dfi_freq_ratio = 1; + input.basic.num_anib = 0xc; + input.basic.train2d = popts->skip2d ? 0 : 1; + input.basic.frequency = (int) (clk / 2000000ul); + debug("frequency = %dMHz\n", input.basic.frequency); + input.cs_d0 = conf->cs_on_dimm[0]; +#if DDRC_NUM_DIMM > 1 + input.cs_d1 = conf->cs_on_dimm[1]; +#endif + input.mirror = dimm_param->mirrored_dimm; + input.mr[0] = regs->sdram_mode[0] & U(0xffff); + input.mr[1] = regs->sdram_mode[0] >> 16U; + input.mr[2] = regs->sdram_mode[1] >> 16U; + input.mr[3] = regs->sdram_mode[1] & U(0xffff); + input.mr[4] = regs->sdram_mode[8] >> 16U; + input.mr[5] = regs->sdram_mode[8] & U(0xffff); + input.mr[6] = regs->sdram_mode[9] >> 16U; + input.vref = popts->vref_phy; + debug("Vref_phy = %d percent\n", (input.vref * 100U) >> 7U); + for (i = 0U; i < DDRC_NUM_CS; i++) { + if ((regs->cs[i].config & SDRAM_CS_CONFIG_EN) == 0U) { + continue; + } + odt_rd = (regs->cs[i].config >> 20U) & U(0x7); + odt_wr = (regs->cs[i].config >> 16U) & U(0x7); + parse_odt(odt_rd, true, i, input.cs_d0, input.cs_d1, + input.odt); + parse_odt(odt_wr, false, i, input.cs_d0, input.cs_d1, + input.odt); + } + + /* Do not set sdram_cfg[RD_EN] or sdram_cfg2[RCW_EN] for RDIMM */ + if (dimm_param->rdimm != 0U) { + regs->sdram_cfg[0] &= ~(1 << 28U); + regs->sdram_cfg[1] &= ~(1 << 2U); + input.rcw[0] = (regs->sdram_rcw[0] >> 28U) & U(0xf); + input.rcw[1] = (regs->sdram_rcw[0] >> 24U) & U(0xf); + input.rcw[2] = (regs->sdram_rcw[0] >> 20U) & U(0xf); + input.rcw[3] = (regs->sdram_rcw[0] >> 16U) & U(0xf); + input.rcw[4] = (regs->sdram_rcw[0] >> 12U) & U(0xf); + input.rcw[5] = (regs->sdram_rcw[0] >> 8U) & U(0xf); + input.rcw[6] = (regs->sdram_rcw[0] >> 4U) & U(0xf); + input.rcw[7] = (regs->sdram_rcw[0] >> 0U) & U(0xf); + input.rcw[8] = (regs->sdram_rcw[1] >> 28U) & U(0xf); + input.rcw[9] = (regs->sdram_rcw[1] >> 24U) & U(0xf); + input.rcw[10] = (regs->sdram_rcw[1] >> 20U) & U(0xf); + input.rcw[11] = (regs->sdram_rcw[1] >> 16U) & U(0xf); + input.rcw[12] = (regs->sdram_rcw[1] >> 12U) & U(0xf); + input.rcw[13] = (regs->sdram_rcw[1] >> 8U) & U(0xf); + input.rcw[14] = (regs->sdram_rcw[1] >> 4U) & U(0xf); + input.rcw[15] = (regs->sdram_rcw[1] >> 0U) & U(0xf); + input.rcw3x = (regs->sdram_rcw[2] >> 8U) & U(0xff); + } + + input.adv.odtimpedance = popts->odt ? popts->odt : 60; + input.adv.tx_impedance = popts->phy_tx_impedance ? + popts->phy_tx_impedance : 28; + input.adv.atx_impedance = popts->phy_atx_impedance ? + popts->phy_atx_impedance : 30; + + debug("Initializing input adv data structure\n"); + phy_gen2_init_input(&input); + + debug("Initializing message block\n"); + ret = phy_gen2_msg_init(&msg_1d, &msg_2d, &input); + if (ret != 0) { + ERROR("Init msg failed (error code %d)\n", ret); + return ret; + } + + ret = c_init_phy_config(priv->phy, priv->ip_rev, &input, &msg_1d); + if (ret != 0) { + ERROR("Init PHY failed (error code %d)\n", ret); + return ret; + } +#ifdef NXP_WARM_BOOT + debug("Warm boot flag value %0x\n", priv->warm_boot_flag); + if (priv->warm_boot_flag == DDR_WARM_BOOT) { + debug("Restoring the Phy training data\n"); + // Restore the training data + ret = restore_phy_training_values(priv->phy, + PHY_TRAINING_REGS_ON_FLASH, + priv->num_ctlrs, + input.basic.train2d); + if (ret != 0) { + ERROR("Restoring of training data failed %d\n", ret); + return ret; + } + } else { +#endif + /* Mapping IMG buffer firstly */ + ret = mmap_add_dynamic_region(priv->phy_gen2_fw_img_buf, + priv->phy_gen2_fw_img_buf, + PHY_GEN2_MAX_IMAGE_SIZE, + MT_MEMORY | MT_RW | MT_SECURE); + if (ret != 0) { + ERROR("Failed to add dynamic memory region.\n"); + return ret; + } + + debug("Load 1D firmware\n"); + ret = load_fw(priv->phy, &input, 0, &msg_1d, + sizeof(struct ddr4u1d), priv->phy_gen2_fw_img_buf, + priv->img_loadr, priv->warm_boot_flag); + if (ret != 0) { + ERROR("Loading firmware failed (error code %d)\n", ret); + return ret; + } + + debug("Execute firmware\n"); + ret = g_exec_fw(priv->phy, 0, &input); + if (ret != 0) { + ERROR("Execution FW failed (error code %d)\n", ret); + } + +#ifdef NXP_APPLY_MAX_CDD + soc_info = get_soc_info(); + if (soc_info->svr_reg.bf.maj_ver == 2) { + tcfg0 = regs->timing_cfg[0]; + tcfg4 = regs->timing_cfg[4]; + rank = findrank(conf->cs_in_use); + get_cdd_val(priv->phy, rank, input.basic.frequency, + &tcfg0, &tcfg4); + regs->timing_cfg[0] = tcfg0; + regs->timing_cfg[4] = tcfg4; + } +#endif + + if ((ret == 0) && (input.basic.train2d != 0)) { + /* 2D training starts here */ + debug("Load 2D firmware\n"); + ret = load_fw(priv->phy, &input, 1, &msg_2d, + sizeof(struct ddr4u2d), + priv->phy_gen2_fw_img_buf, + priv->img_loadr, + priv->warm_boot_flag); + if (ret != 0) { + ERROR("Loading fw failed (err code %d)\n", ret); + } else { + debug("Execute 2D firmware\n"); + ret = g_exec_fw(priv->phy, 1, &input); + if (ret != 0) { + ERROR("Execution FW failed (err %d)\n", + ret); + } + } + } +#ifdef NXP_WARM_BOOT + if (priv->warm_boot_flag != DDR_WRM_BOOT_NT_SUPPORTED && + ret == 0) { + debug("save the phy training data\n"); + //Save training data TBD + ret = save_phy_training_values(priv->phy, + PHY_TRAINING_REGS_ON_FLASH, + priv->num_ctlrs, + input.basic.train2d); + if (ret != 0) { + ERROR("Saving training data failed."); + ERROR("Warm boot will fail. Error=%d.\n", ret); + } + } + } /* else */ +#endif + + if (ret == 0) { + debug("Load PIE\n"); + i_load_pie(priv->phy, &input, &msg_1d); + + NOTICE("DDR4 %s with %d-rank %d-bit bus (x%d)\n", + input.basic.dimm_type == RDIMM ? "RDIMM" : + input.basic.dimm_type == LRDIMM ? "LRDIMM" : + "UDIMM", + dimm_param->n_ranks, + dimm_param->primary_sdram_width, + dimm_param->device_width); + } +#ifdef DEBUG_DDR_INPUT_CONFIG + print_jason_format(&input, &msg_1d, &msg_2d); +#endif + + return ret; +} diff --git a/drivers/nxp/ddr/phy-gen2/phy.h b/drivers/nxp/ddr/phy-gen2/phy.h new file mode 100644 index 0000000..15e80d1 --- /dev/null +++ b/drivers/nxp/ddr/phy-gen2/phy.h @@ -0,0 +1,334 @@ +/* + * Copyright 2021 NXP + * SPDX-License-Identifier: BSD-3-Clause + */ + +#if !defined(PHY_H) && defined(NXP_WARM_BOOT) +#define PHY_H + +#include <flash_info.h> + +/* To store sector size to be erase on flash*/ +#define PHY_ERASE_SIZE F_SECTOR_ERASE_SZ + +/*Structure to implement address-data map tuples to store PHY training values*/ +struct phy_training_values { + uint32_t addr; + uint16_t data; +}; +/* Saves PHY Training Register values after cold reset + *@param[in] phy_ptr array to store addresses of PHYs + *@param[in] address_to_store address to save PHY training register values + *on flash + *@param[in] num_of_phy the number of PHY for which training values are + *to be saved + *@param[in] train2d flag to store whether 2D training registers are to + *be saved or not + * + *PHY training values will be stored on flash at contigous memory in the order: + *1D training registers, 2D training registers + *for each PHY + * + *if train2d is false saving 2D training registers will be skipped + */ +int save_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_store, + uint32_t num_of_phy, int train2d); + +/*Restores PHY Training Register values after warm reset + *@param[in] phy_ptr array to store addresses of PHYs + *@param[in] address_to_store address to retrieve PHY training register + *values from flash + *@param[in] num_of_phy the number of PHY for which training values are + *to be restored + *@param[in] train2d flag to store whether 2D training registers are + *to be restored or not + * + *if train2d is false saving 2D training registers will be skipped + */ + +int restore_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_restore, + uint32_t num_of_phy, int train2d); + +/* + * Address data tuples to store the PHY 1D + */ + +struct phy_training_values training_1D_values[] = { + {0x200B2, 0}, {0x200CB, 0}, {0x10043, 0}, {0x11043, 0}, + {0x12043, 0}, {0x13043, 0}, {0x14043, 0}, {0x15043, 0}, + {0x16043, 0}, {0x17043, 0}, {0x18043, 0}, {0x10143, 0}, + {0x11143, 0}, {0x12143, 0}, {0x13143, 0}, {0x14143, 0}, + {0x15143, 0}, {0x16143, 0}, {0x17143, 0}, {0x18143, 0}, + {0x10080, 0}, {0x11080, 0}, {0x12080, 0}, {0x13080, 0}, + {0x14080, 0}, {0x15080, 0}, {0x16080, 0}, {0x17080, 0}, + {0x18080, 0}, {0x10180, 0}, {0x11180, 0}, {0x12180, 0}, + {0x13180, 0}, {0x14180, 0}, {0x15180, 0}, {0x16180, 0}, + {0x17180, 0}, {0x18180, 0}, {0x10081, 0}, {0x11081, 0}, + {0x12081, 0}, {0x13081, 0}, {0x14081, 0}, {0x15081, 0}, + {0x16081, 0}, {0x17081, 0}, {0x18081, 0}, {0x10181, 0}, + {0x11181, 0}, {0x12181, 0}, {0x13181, 0}, {0x14181, 0}, + {0x15181, 0}, {0x16181, 0}, {0x17181, 0}, {0x18181, 0}, + {0x10082, 0}, {0x11082, 0}, {0x12082, 0}, {0x13082, 0}, + {0x14082, 0}, {0x15082, 0}, {0x16082, 0}, {0x17082, 0}, + {0x18082, 0}, {0x10182, 0}, {0x11182, 0}, {0x12182, 0}, + {0x13182, 0}, {0x14182, 0}, {0x15182, 0}, {0x16182, 0}, + {0x17182, 0}, {0x18182, 0}, {0x10083, 0}, {0x11083, 0}, + {0x12083, 0}, {0x13083, 0}, {0x14083, 0}, {0x15083, 0}, + {0x16083, 0}, {0x17083, 0}, {0x18083, 0}, {0x10183, 0}, + {0x11183, 0}, {0x12183, 0}, {0x13183, 0}, {0x14183, 0}, + {0x15183, 0}, {0x16183, 0}, {0x17183, 0}, {0x18183, 0}, + {0x100D0, 0}, {0x110D0, 0}, {0x120D0, 0}, {0x130D0, 0}, + {0x140D0, 0}, {0x150D0, 0}, {0x160D0, 0}, {0x170D0, 0}, + {0x180D0, 0}, {0x101D0, 0}, {0x111D0, 0}, {0x121D0, 0}, + {0x131D0, 0}, {0x141D0, 0}, {0x151D0, 0}, {0x161D0, 0}, + {0x171D0, 0}, {0x181D0, 0}, {0x100D1, 0}, {0x110D1, 0}, + {0x120D1, 0}, {0x130D1, 0}, {0x140D1, 0}, {0x150D1, 0}, + {0x160D1, 0}, {0x170D1, 0}, {0x180D1, 0}, {0x101D1, 0}, + {0x111D1, 0}, {0x121D1, 0}, {0x131D1, 0}, {0x141D1, 0}, + {0x151D1, 0}, {0x161D1, 0}, {0x171D1, 0}, {0x181D1, 0}, + {0x100D2, 0}, {0x110D2, 0}, {0x120D2, 0}, {0x130D2, 0}, + {0x140D2, 0}, {0x150D2, 0}, {0x160D2, 0}, {0x170D2, 0}, + {0x180D2, 0}, {0x101D2, 0}, {0x111D2, 0}, {0x121D2, 0}, + {0x131D2, 0}, {0x141D2, 0}, {0x151D2, 0}, {0x161D2, 0}, + {0x171D2, 0}, {0x181D2, 0}, {0x100D3, 0}, {0x110D3, 0}, + {0x120D3, 0}, {0x130D3, 0}, {0x140D3, 0}, {0x150D3, 0}, + {0x160D3, 0}, {0x170D3, 0}, {0x180D3, 0}, {0x101D3, 0}, + {0x111D3, 0}, {0x121D3, 0}, {0x131D3, 0}, {0x141D3, 0}, + {0x151D3, 0}, {0x161D3, 0}, {0x171D3, 0}, {0x181D3, 0}, + {0x10068, 0}, {0x11068, 0}, {0x12068, 0}, {0x13068, 0}, + {0x14068, 0}, {0x15068, 0}, {0x16068, 0}, {0x17068, 0}, + {0x18068, 0}, {0x10168, 0}, {0x11168, 0}, {0x12168, 0}, + {0x13168, 0}, {0x14168, 0}, {0x15168, 0}, {0x16168, 0}, + {0x17168, 0}, {0x18168, 0}, {0x10268, 0}, {0x11268, 0}, + {0x12268, 0}, {0x13268, 0}, {0x14268, 0}, {0x15268, 0}, + {0x16268, 0}, {0x17268, 0}, {0x18268, 0}, {0x10368, 0}, + {0x11368, 0}, {0x12368, 0}, {0x13368, 0}, {0x14368, 0}, + {0x15368, 0}, {0x16368, 0}, {0x17368, 0}, {0x18368, 0}, + {0x10468, 0}, {0x11468, 0}, {0x12468, 0}, {0x13468, 0}, + {0x14468, 0}, {0x15468, 0}, {0x16468, 0}, {0x17468, 0}, + {0x18468, 0}, {0x10568, 0}, {0x11568, 0}, {0x12568, 0}, + {0x13568, 0}, {0x14568, 0}, {0x15568, 0}, {0x16568, 0}, + {0x17568, 0}, {0x18568, 0}, {0x10668, 0}, {0x11668, 0}, + {0x12668, 0}, {0x13668, 0}, {0x14668, 0}, {0x15668, 0}, + {0x16668, 0}, {0x17668, 0}, {0x18668, 0}, {0x10768, 0}, + {0x11768, 0}, {0x12768, 0}, {0x13768, 0}, {0x14768, 0}, + {0x15768, 0}, {0x16768, 0}, {0x17768, 0}, {0x18768, 0}, + {0x10868, 0}, {0x11868, 0}, {0x12868, 0}, {0x13868, 0}, + {0x14868, 0}, {0x15868, 0}, {0x16868, 0}, {0x17868, 0}, + {0x18868, 0}, {0x10069, 0}, {0x11069, 0}, {0x12069, 0}, + {0x13069, 0}, {0x14069, 0}, {0x15069, 0}, {0x16069, 0}, + {0x17069, 0}, {0x18069, 0}, {0x10169, 0}, {0x11169, 0}, + {0x12169, 0}, {0x13169, 0}, {0x14169, 0}, {0x15169, 0}, + {0x16169, 0}, {0x17169, 0}, {0x18169, 0}, {0x10269, 0}, + {0x11269, 0}, {0x12269, 0}, {0x13269, 0}, {0x14269, 0}, + {0x15269, 0}, {0x16269, 0}, {0x17269, 0}, {0x18269, 0}, + {0x10369, 0}, {0x11369, 0}, {0x12369, 0}, {0x13369, 0}, + {0x14369, 0}, {0x15369, 0}, {0x16369, 0}, {0x17369, 0}, + {0x18369, 0}, {0x10469, 0}, {0x11469, 0}, {0x12469, 0}, + {0x13469, 0}, {0x14469, 0}, {0x15469, 0}, {0x16469, 0}, + {0x17469, 0}, {0x18469, 0}, {0x10569, 0}, {0x11569, 0}, + {0x12569, 0}, {0x13569, 0}, {0x14569, 0}, {0x15569, 0}, + {0x16569, 0}, {0x17569, 0}, {0x18569, 0}, {0x10669, 0}, + {0x11669, 0}, {0x12669, 0}, {0x13669, 0}, {0x14669, 0}, + {0x15669, 0}, {0x16669, 0}, {0x17669, 0}, {0x18669, 0}, + {0x10769, 0}, {0x11769, 0}, {0x12769, 0}, {0x13769, 0}, + {0x14769, 0}, {0x15769, 0}, {0x16769, 0}, {0x17769, 0}, + {0x18769, 0}, {0x10869, 0}, {0x11869, 0}, {0x12869, 0}, + {0x13869, 0}, {0x14869, 0}, {0x15869, 0}, {0x16869, 0}, + {0x17869, 0}, {0x18869, 0}, {0x1006A, 0}, {0x1106A, 0}, + {0x1206A, 0}, {0x1306A, 0}, {0x1406A, 0}, {0x1506A, 0}, + {0x1606A, 0}, {0x1706A, 0}, {0x1806A, 0}, {0x1016A, 0}, + {0x1116A, 0}, {0x1216A, 0}, {0x1316A, 0}, {0x1416A, 0}, + {0x1516A, 0}, {0x1616A, 0}, {0x1716A, 0}, {0x1816A, 0}, + {0x1026A, 0}, {0x1126A, 0}, {0x1226A, 0}, {0x1326A, 0}, + {0x1426A, 0}, {0x1526A, 0}, {0x1626A, 0}, {0x1726A, 0}, + {0x1826A, 0}, {0x1036A, 0}, {0x1136A, 0}, {0x1236A, 0}, + {0x1336A, 0}, {0x1436A, 0}, {0x1536A, 0}, {0x1636A, 0}, + {0x1736A, 0}, {0x1836A, 0}, {0x1046A, 0}, {0x1146A, 0}, + {0x1246A, 0}, {0x1346A, 0}, {0x1446A, 0}, {0x1546A, 0}, + {0x1646A, 0}, {0x1746A, 0}, {0x1846A, 0}, {0x1056A, 0}, + {0x1156A, 0}, {0x1256A, 0}, {0x1356A, 0}, {0x1456A, 0}, + {0x1556A, 0}, {0x1656A, 0}, {0x1756A, 0}, {0x1856A, 0}, + {0x1066A, 0}, {0x1166A, 0}, {0x1266A, 0}, {0x1366A, 0}, + {0x1466A, 0}, {0x1566A, 0}, {0x1666A, 0}, {0x1766A, 0}, + {0x1866A, 0}, {0x1076A, 0}, {0x1176A, 0}, {0x1276A, 0}, + {0x1376A, 0}, {0x1476A, 0}, {0x1576A, 0}, {0x1676A, 0}, + {0x1776A, 0}, {0x1876A, 0}, {0x1086A, 0}, {0x1186A, 0}, + {0x1286A, 0}, {0x1386A, 0}, {0x1486A, 0}, {0x1586A, 0}, + {0x1686A, 0}, {0x1786A, 0}, {0x1886A, 0}, {0x1006B, 0}, + {0x1106B, 0}, {0x1206B, 0}, {0x1306B, 0}, {0x1406B, 0}, + {0x1506B, 0}, {0x1606B, 0}, {0x1706B, 0}, {0x1806B, 0}, + {0x1016B, 0}, {0x1116B, 0}, {0x1216B, 0}, {0x1316B, 0}, + {0x1416B, 0}, {0x1516B, 0}, {0x1616B, 0}, {0x1716B, 0}, + {0x1816B, 0}, {0x1026B, 0}, {0x1126B, 0}, {0x1226B, 0}, + {0x1326B, 0}, {0x1426B, 0}, {0x1526B, 0}, {0x1626B, 0}, + {0x1726B, 0}, {0x1826B, 0}, {0x1036B, 0}, {0x1136B, 0}, + {0x1236B, 0}, {0x1336B, 0}, {0x1436B, 0}, {0x1536B, 0}, + {0x1636B, 0}, {0x1736B, 0}, {0x1836B, 0}, {0x1046B, 0}, + {0x1146B, 0}, {0x1246B, 0}, {0x1346B, 0}, {0x1446B, 0}, + {0x1546B, 0}, {0x1646B, 0}, {0x1746B, 0}, {0x1846B, 0}, + {0x1056B, 0}, {0x1156B, 0}, {0x1256B, 0}, {0x1356B, 0}, + {0x1456B, 0}, {0x1556B, 0}, {0x1656B, 0}, {0x1756B, 0}, + {0x1856B, 0}, {0x1066B, 0}, {0x1166B, 0}, {0x1266B, 0}, + {0x1366B, 0}, {0x1466B, 0}, {0x1566B, 0}, {0x1666B, 0}, + {0x1766B, 0}, {0x1866B, 0}, {0x1076B, 0}, {0x1176B, 0}, + {0x1276B, 0}, {0x1376B, 0}, {0x1476B, 0}, {0x1576B, 0}, + {0x1676B, 0}, {0x1776B, 0}, {0x1876B, 0}, {0x1086B, 0}, + {0x1186B, 0}, {0x1286B, 0}, {0x1386B, 0}, {0x1486B, 0}, + {0x1586B, 0}, {0x1686B, 0}, {0x1786B, 0}, {0x1886B, 0}, + {0x1008C, 0}, {0x1108C, 0}, {0x1208C, 0}, {0x1308C, 0}, + {0x1408C, 0}, {0x1508C, 0}, {0x1608C, 0}, {0x1708C, 0}, + {0x1808C, 0}, {0x1018C, 0}, {0x1118C, 0}, {0x1218C, 0}, + {0x1318C, 0}, {0x1418C, 0}, {0x1518C, 0}, {0x1618C, 0}, + {0x1718C, 0}, {0x1818C, 0}, {0x1008D, 0}, {0x1108D, 0}, + {0x1208D, 0}, {0x1308D, 0}, {0x1408D, 0}, {0x1508D, 0}, + {0x1608D, 0}, {0x1708D, 0}, {0x1808D, 0}, {0x1018D, 0}, + {0x1118D, 0}, {0x1218D, 0}, {0x1318D, 0}, {0x1418D, 0}, + {0x1518D, 0}, {0x1618D, 0}, {0x1718D, 0}, {0x1818D, 0}, + {0x1008E, 0}, {0x1108E, 0}, {0x1208E, 0}, {0x1308E, 0}, + {0x1408E, 0}, {0x1508E, 0}, {0x1608E, 0}, {0x1708E, 0}, + {0x1808E, 0}, {0x1018E, 0}, {0x1118E, 0}, {0x1218E, 0}, + {0x1318E, 0}, {0x1418E, 0}, {0x1518E, 0}, {0x1618E, 0}, + {0x1718E, 0}, {0x1818E, 0}, {0x1008F, 0}, {0x1108F, 0}, + {0x1208F, 0}, {0x1308F, 0}, {0x1408F, 0}, {0x1508F, 0}, + {0x1608F, 0}, {0x1708F, 0}, {0x1808F, 0}, {0x1018F, 0}, + {0x1118F, 0}, {0x1218F, 0}, {0x1318F, 0}, {0x1418F, 0}, + {0x1518F, 0}, {0x1618F, 0}, {0x1718F, 0}, {0x1818F, 0}, + {0x100C0, 0}, {0x110C0, 0}, {0x120C0, 0}, {0x130C0, 0}, + {0x140C0, 0}, {0x150C0, 0}, {0x160C0, 0}, {0x170C0, 0}, + {0x180C0, 0}, {0x101C0, 0}, {0x111C0, 0}, {0x121C0, 0}, + {0x131C0, 0}, {0x141C0, 0}, {0x151C0, 0}, {0x161C0, 0}, + {0x171C0, 0}, {0x181C0, 0}, {0x102C0, 0}, {0x112C0, 0}, + {0x122C0, 0}, {0x132C0, 0}, {0x142C0, 0}, {0x152C0, 0}, + {0x162C0, 0}, {0x172C0, 0}, {0x182C0, 0}, {0x103C0, 0}, + {0x113C0, 0}, {0x123C0, 0}, {0x133C0, 0}, {0x143C0, 0}, + {0x153C0, 0}, {0x163C0, 0}, {0x173C0, 0}, {0x183C0, 0}, + {0x104C0, 0}, {0x114C0, 0}, {0x124C0, 0}, {0x134C0, 0}, + {0x144C0, 0}, {0x154C0, 0}, {0x164C0, 0}, {0x174C0, 0}, + {0x184C0, 0}, {0x105C0, 0}, {0x115C0, 0}, {0x125C0, 0}, + {0x135C0, 0}, {0x145C0, 0}, {0x155C0, 0}, {0x165C0, 0}, + {0x175C0, 0}, {0x185C0, 0}, {0x106C0, 0}, {0x116C0, 0}, + {0x126C0, 0}, {0x136C0, 0}, {0x146C0, 0}, {0x156C0, 0}, + {0x166C0, 0}, {0x176C0, 0}, {0x186C0, 0}, {0x107C0, 0}, + {0x117C0, 0}, {0x127C0, 0}, {0x137C0, 0}, {0x147C0, 0}, + {0x157C0, 0}, {0x167C0, 0}, {0x177C0, 0}, {0x187C0, 0}, + {0x108C0, 0}, {0x118C0, 0}, {0x128C0, 0}, {0x138C0, 0}, + {0x148C0, 0}, {0x158C0, 0}, {0x168C0, 0}, {0x178C0, 0}, + {0x188C0, 0}, {0x100C1, 0}, {0x110C1, 0}, {0x120C1, 0}, + {0x130C1, 0}, {0x140C1, 0}, {0x150C1, 0}, {0x160C1, 0}, + {0x170C1, 0}, {0x180C1, 0}, {0x101C1, 0}, {0x111C1, 0}, + {0x121C1, 0}, {0x131C1, 0}, {0x141C1, 0}, {0x151C1, 0}, + {0x161C1, 0}, {0x171C1, 0}, {0x181C1, 0}, {0x102C1, 0}, + {0x112C1, 0}, {0x122C1, 0}, {0x132C1, 0}, {0x142C1, 0}, + {0x152C1, 0}, {0x162C1, 0}, {0x172C1, 0}, {0x182C1, 0}, + {0x103C1, 0}, {0x113C1, 0}, {0x123C1, 0}, {0x133C1, 0}, + {0x143C1, 0}, {0x153C1, 0}, {0x163C1, 0}, {0x173C1, 0}, + {0x183C1, 0}, {0x104C1, 0}, {0x114C1, 0}, {0x124C1, 0}, + {0x134C1, 0}, {0x144C1, 0}, {0x154C1, 0}, {0x164C1, 0}, + {0x174C1, 0}, {0x184C1, 0}, {0x105C1, 0}, {0x115C1, 0}, + {0x125C1, 0}, {0x135C1, 0}, {0x145C1, 0}, {0x155C1, 0}, + {0x165C1, 0}, {0x175C1, 0}, {0x185C1, 0}, {0x106C1, 0}, + {0x116C1, 0}, {0x126C1, 0}, {0x136C1, 0}, {0x146C1, 0}, + {0x156C1, 0}, {0x166C1, 0}, {0x176C1, 0}, {0x186C1, 0}, + {0x107C1, 0}, {0x117C1, 0}, {0x127C1, 0}, {0x137C1, 0}, + {0x147C1, 0}, {0x157C1, 0}, {0x167C1, 0}, {0x177C1, 0}, + {0x187C1, 0}, {0x108C1, 0}, {0x118C1, 0}, {0x128C1, 0}, + {0x138C1, 0}, {0x148C1, 0}, {0x158C1, 0}, {0x168C1, 0}, + {0x178C1, 0}, {0x188C1, 0}, {0x100C2, 0}, {0x110C2, 0}, + {0x120C2, 0}, {0x130C2, 0}, {0x140C2, 0}, {0x150C2, 0}, + {0x160C2, 0}, {0x170C2, 0}, {0x180C2, 0}, {0x101C2, 0}, + {0x111C2, 0}, {0x121C2, 0}, {0x131C2, 0}, {0x141C2, 0}, + {0x151C2, 0}, {0x161C2, 0}, {0x171C2, 0}, {0x181C2, 0}, + {0x102C2, 0}, {0x112C2, 0}, {0x122C2, 0}, {0x132C2, 0}, + {0x142C2, 0}, {0x152C2, 0}, {0x162C2, 0}, {0x172C2, 0}, + {0x182C2, 0}, {0x103C2, 0}, {0x113C2, 0}, {0x123C2, 0}, + {0x133C2, 0}, {0x143C2, 0}, {0x153C2, 0}, {0x163C2, 0}, + {0x173C2, 0}, {0x183C2, 0}, {0x104C2, 0}, {0x114C2, 0}, + {0x124C2, 0}, {0x134C2, 0}, {0x144C2, 0}, {0x154C2, 0}, + {0x164C2, 0}, {0x174C2, 0}, {0x184C2, 0}, {0x105C2, 0}, + {0x115C2, 0}, {0x125C2, 0}, {0x135C2, 0}, {0x145C2, 0}, + {0x155C2, 0}, {0x165C2, 0}, {0x175C2, 0}, {0x185C2, 0}, + {0x106C2, 0}, {0x116C2, 0}, {0x126C2, 0}, {0x136C2, 0}, + {0x146C2, 0}, {0x156C2, 0}, {0x166C2, 0}, {0x176C2, 0}, + {0x186C2, 0}, {0x107C2, 0}, {0x117C2, 0}, {0x127C2, 0}, + {0x137C2, 0}, {0x147C2, 0}, {0x157C2, 0}, {0x167C2, 0}, + {0x177C2, 0}, {0x187C2, 0}, {0x108C2, 0}, {0x118C2, 0}, + {0x128C2, 0}, {0x138C2, 0}, {0x148C2, 0}, {0x158C2, 0}, + {0x168C2, 0}, {0x178C2, 0}, {0x188C2, 0}, {0x100C3, 0}, + {0x110C3, 0}, {0x120C3, 0}, {0x130C3, 0}, {0x140C3, 0}, + {0x150C3, 0}, {0x160C3, 0}, {0x170C3, 0}, {0x180C3, 0}, + {0x101C3, 0}, {0x111C3, 0}, {0x121C3, 0}, {0x131C3, 0}, + {0x141C3, 0}, {0x151C3, 0}, {0x161C3, 0}, {0x171C3, 0}, + {0x181C3, 0}, {0x102C3, 0}, {0x112C3, 0}, {0x122C3, 0}, + {0x132C3, 0}, {0x142C3, 0}, {0x152C3, 0}, {0x162C3, 0}, + {0x172C3, 0}, {0x182C3, 0}, {0x103C3, 0}, {0x113C3, 0}, + {0x123C3, 0}, {0x133C3, 0}, {0x143C3, 0}, {0x153C3, 0}, + {0x163C3, 0}, {0x173C3, 0}, {0x183C3, 0}, {0x104C3, 0}, + {0x114C3, 0}, {0x124C3, 0}, {0x134C3, 0}, {0x144C3, 0}, + {0x154C3, 0}, {0x164C3, 0}, {0x174C3, 0}, {0x184C3, 0}, + {0x105C3, 0}, {0x115C3, 0}, {0x125C3, 0}, {0x135C3, 0}, + {0x145C3, 0}, {0x155C3, 0}, {0x165C3, 0}, {0x175C3, 0}, + {0x185C3, 0}, {0x106C3, 0}, {0x116C3, 0}, {0x126C3, 0}, + {0x136C3, 0}, {0x146C3, 0}, {0x156C3, 0}, {0x166C3, 0}, + {0x176C3, 0}, {0x186C3, 0}, {0x107C3, 0}, {0x117C3, 0}, + {0x127C3, 0}, {0x137C3, 0}, {0x147C3, 0}, {0x157C3, 0}, + {0x167C3, 0}, {0x177C3, 0}, {0x187C3, 0}, {0x108C3, 0}, + {0x118C3, 0}, {0x128C3, 0}, {0x138C3, 0}, {0x148C3, 0}, + {0x158C3, 0}, {0x168C3, 0}, {0x178C3, 0}, {0x188C3, 0}, + {0x10020, 0}, {0x11020, 0}, {0x12020, 0}, {0x13020, 0}, + {0x14020, 0}, {0x15020, 0}, {0x16020, 0}, {0x17020, 0}, + {0x18020, 0}, {0x2007D, 0}, {0x20077, 0} +}; + +/* + *Array to store the PHY 2D Training register addresses + */ +struct phy_training_values training_2D_values[] = { + {0x1008C, 0}, {0x1108C, 0}, {0x1208C, 0}, {0x1308C, 0}, + {0x1408C, 0}, {0x1508C, 0}, {0x1608C, 0}, {0x1708C, 0}, + {0x1808C, 0}, {0x1018C, 0}, {0x1118C, 0}, {0x1218C, 0}, + {0x1318C, 0}, {0x1418C, 0}, {0x1518C, 0}, {0x1618C, 0}, + {0x1718C, 0}, {0x1818C, 0}, {0x10040, 0}, {0x11040, 0}, + {0x12040, 0}, {0x13040, 0}, {0x14040, 0}, {0x15040, 0}, + {0x16040, 0}, {0x17040, 0}, {0x18040, 0}, {0x10140, 0}, + {0x11140, 0}, {0x12140, 0}, {0x13140, 0}, {0x14140, 0}, + {0x15140, 0}, {0x16140, 0}, {0x17140, 0}, {0x18140, 0}, + {0x10240, 0}, {0x11240, 0}, {0x12240, 0}, {0x13240, 0}, + {0x14240, 0}, {0x15240, 0}, {0x16240, 0}, {0x17240, 0}, + {0x18240, 0}, {0x10340, 0}, {0x11340, 0}, {0x12340, 0}, + {0x13340, 0}, {0x14340, 0}, {0x15340, 0}, {0x16340, 0}, + {0x17340, 0}, {0x18340, 0}, {0x10440, 0}, {0x11440, 0}, + {0x12440, 0}, {0x13440, 0}, {0x14440, 0}, {0x15440, 0}, + {0x16440, 0}, {0x17440, 0}, {0x18440, 0}, {0x10540, 0}, + {0x11540, 0}, {0x12540, 0}, {0x13540, 0}, {0x14540, 0}, + {0x15540, 0}, {0x16540, 0}, {0x17540, 0}, {0x18540, 0}, + {0x10640, 0}, {0x11640, 0}, {0x12640, 0}, {0x13640, 0}, + {0x14640, 0}, {0x15640, 0}, {0x16640, 0}, {0x17640, 0}, + {0x18640, 0}, {0x10740, 0}, {0x11740, 0}, {0x12740, 0}, + {0x13740, 0}, {0x14740, 0}, {0x15740, 0}, {0x16740, 0}, + {0x17740, 0}, {0x18740, 0}, {0x10840, 0}, {0x11840, 0}, + {0x12840, 0}, {0x13840, 0}, {0x14840, 0}, {0x15840, 0}, + {0x16840, 0}, {0x17840, 0}, {0x18840, 0}, {0x10030, 0}, + {0x11030, 0}, {0x12030, 0}, {0x13030, 0}, {0x14030, 0}, + {0x15030, 0}, {0x16030, 0}, {0x17030, 0}, {0x18030, 0}, + {0x10130, 0}, {0x11130, 0}, {0x12130, 0}, {0x13130, 0}, + {0x14130, 0}, {0x15130, 0}, {0x16130, 0}, {0x17130, 0}, + {0x18130, 0}, {0x10230, 0}, {0x11230, 0}, {0x12230, 0}, + {0x13230, 0}, {0x14230, 0}, {0x15230, 0}, {0x16230, 0}, + {0x17230, 0}, {0x18230, 0}, {0x10330, 0}, {0x11330, 0}, + {0x12330, 0}, {0x13330, 0}, {0x14330, 0}, {0x15330, 0}, + {0x16330, 0}, {0x17330, 0}, {0x18330, 0}, {0x10430, 0}, + {0x11430, 0}, {0x12430, 0}, {0x13430, 0}, {0x14430, 0}, + {0x15430, 0}, {0x16430, 0}, {0x17430, 0}, {0x18430, 0}, + {0x10530, 0}, {0x11530, 0}, {0x12530, 0}, {0x13530, 0}, + {0x14530, 0}, {0x15530, 0}, {0x16530, 0}, {0x17530, 0}, + {0x18530, 0}, {0x10630, 0}, {0x11630, 0}, {0x12630, 0}, + {0x13630, 0}, {0x14630, 0}, {0x15630, 0}, {0x16630, 0}, + {0x17630, 0}, {0x18630, 0}, {0x10730, 0}, {0x11730, 0}, + {0x12730, 0}, {0x13730, 0}, {0x14730, 0}, {0x15730, 0}, + {0x16730, 0}, {0x17730, 0}, {0x18730, 0}, {0x10830, 0}, + {0x11830, 0}, {0x12830, 0}, {0x13830, 0}, {0x14830, 0}, + {0x15830, 0}, {0x16830, 0}, {0x17830, 0}, {0x18830, 0} +}; + +#endif diff --git a/drivers/nxp/ddr/phy-gen2/pie.h b/drivers/nxp/ddr/phy-gen2/pie.h new file mode 100644 index 0000000..b89066a --- /dev/null +++ b/drivers/nxp/ddr/phy-gen2/pie.h @@ -0,0 +1,632 @@ +/* + * Copyright 2021 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef PIE_H +#define PIE_H + +struct pie { + uint32_t addr; + uint16_t data; +}; + +static const struct pie pie_udimm[] = { + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x2}, + {0x90033, 0x10}, + {0x90034, 0x139}, + {0x90035, 0xb}, + {0x90036, 0x7c0}, + {0x90037, 0x139}, + {0x90038, 0x44}, + {0x90039, 0x633}, + {0x9003a, 0x159}, + {0x9003b, 0x14f}, + {0x9003c, 0x630}, + {0x9003d, 0x159}, + {0x9003e, 0x47}, + {0x9003f, 0x633}, + {0x90040, 0x149}, + {0x90041, 0x4f}, + {0x90042, 0x633}, + {0x90043, 0x179}, + {0x90044, 0x8}, + {0x90045, 0xe0}, + {0x90046, 0x109}, + {0x90047, 0x0}, + {0x90048, 0x7c8}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x1}, + {0x9004c, 0x8}, + {0x9004d, 0x0}, + {0x9004e, 0x45a}, + {0x9004f, 0x9}, + {0x90050, 0x0}, + {0x90051, 0x448}, + {0x90052, 0x109}, + {0x90053, 0x40}, + {0x90054, 0x633}, + {0x90055, 0x179}, + {0x90056, 0x1}, + {0x90057, 0x618}, + {0x90058, 0x109}, + {0x90059, 0x40c0}, + {0x9005a, 0x633}, + {0x9005b, 0x149}, + {0x9005c, 0x8}, + {0x9005d, 0x4}, + {0x9005e, 0x48}, + {0x9005f, 0x4040}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x0}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x40}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x10}, + {0x90069, 0x4}, + {0x9006a, 0x18}, + {0x9006b, 0x0}, + {0x9006c, 0x4}, + {0x9006d, 0x78}, + {0x9006e, 0x549}, + {0x9006f, 0x633}, + {0x90070, 0x159}, + {0x90071, 0xd49}, + {0x90072, 0x633}, + {0x90073, 0x159}, + {0x90074, 0x94a}, + {0x90075, 0x633}, + {0x90076, 0x159}, + {0x90077, 0x441}, + {0x90078, 0x633}, + {0x90079, 0x149}, + {0x9007a, 0x42}, + {0x9007b, 0x633}, + {0x9007c, 0x149}, + {0x9007d, 0x1}, + {0x9007e, 0x633}, + {0x9007f, 0x149}, + {0x90080, 0x0}, + {0x90081, 0xe0}, + {0x90082, 0x109}, + {0x90083, 0xa}, + {0x90084, 0x10}, + {0x90085, 0x109}, + {0x90086, 0x9}, + {0x90087, 0x3c0}, + {0x90088, 0x149}, + {0x90089, 0x9}, + {0x9008a, 0x3c0}, + {0x9008b, 0x159}, + {0x9008c, 0x18}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x0}, + {0x90090, 0x3c0}, + {0x90091, 0x109}, + {0x90092, 0x18}, + {0x90093, 0x4}, + {0x90094, 0x48}, + {0x90095, 0x18}, + {0x90096, 0x4}, + {0x90097, 0x58}, + {0x90098, 0xb}, + {0x90099, 0x10}, + {0x9009a, 0x109}, + {0x9009b, 0x1}, + {0x9009c, 0x10}, + {0x9009d, 0x109}, + {0x9009e, 0x5}, + {0x9009f, 0x7c0}, + {0x900a0, 0x109}, + {0x900a1, 0x0}, + {0x900a2, 0x8140}, + {0x900a3, 0x10c}, + {0x900a4, 0x10}, + {0x900a5, 0x8138}, + {0x900a6, 0x10c}, + {0x900a7, 0x8}, + {0x900a8, 0x7c8}, + {0x900a9, 0x101}, + {0x900aa, 0x8}, + {0x900ab, 0x448}, + {0x900ac, 0x109}, + {0x900ad, 0xf}, + {0x900ae, 0x7c0}, + {0x900af, 0x109}, + {0x900b0, 0x47}, + {0x900b1, 0x630}, + {0x900b2, 0x109}, + {0x900b3, 0x8}, + {0x900b4, 0x618}, + {0x900b5, 0x109}, + {0x900b6, 0x8}, + {0x900b7, 0xe0}, + {0x900b8, 0x109}, + {0x900b9, 0x0}, + {0x900ba, 0x7c8}, + {0x900bb, 0x109}, + {0x900bc, 0x8}, + {0x900bd, 0x8140}, + {0x900be, 0x10c}, + {0x900bf, 0x0}, + {0x900c0, 0x478}, + {0x900c1, 0x109}, + {0x900c2, 0x0}, + {0x900c3, 0x1}, + {0x900c4, 0x8}, + {0x900c5, 0x8}, + {0x900c6, 0x4}, + {0x900c7, 0x8}, + {0x900c8, 0x8}, + {0x900c9, 0x7c8}, + {0x900ca, 0x101}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x8}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x90026, 0x2b}, +}; + +static const struct pie pie_rdimm[] = { + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x40000, 0x10}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x70a}, + {0x40021, 0x7005}, + {0x40041, 0x0}, + {0x40061, 0x2001}, + {0x40002, 0x4010}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x90029, 0x10}, + {0x9002a, 0x400}, + {0x9002b, 0x16e}, + {0x9002c, 0x8}, + {0x9002d, 0x370}, + {0x9002e, 0x169}, + {0x9002f, 0x8}, + {0x90030, 0x7aa}, + {0x90031, 0x6a}, + {0x90032, 0x10}, + {0x90033, 0x7b2}, + {0x90034, 0x6a}, + {0x90035, 0x0}, + {0x90036, 0x48a}, + {0x90037, 0x6a}, + {0x90038, 0x9}, + {0x90039, 0x480}, + {0x9003a, 0x16a}, + {0x9003b, 0x4}, + {0x9003c, 0x790}, + {0x9003d, 0x16a}, + {0x9003e, 0xc}, + {0x9003f, 0x408}, + {0x90040, 0x169}, + {0x90041, 0xa}, + {0x90042, 0x0}, + {0x90043, 0x68}, + {0x90044, 0x0}, + {0x90045, 0x408}, + {0x90046, 0x169}, + {0x90047, 0x1}, + {0x90048, 0x480}, + {0x90049, 0x16a}, + {0x9004a, 0xb}, + {0x9004b, 0x480}, + {0x9004c, 0x109}, + {0x9004d, 0x8}, + {0x9004e, 0x448}, + {0x9004f, 0x139}, + {0x90050, 0x78}, + {0x90051, 0x8}, + {0x90052, 0x139}, + {0x90053, 0x2}, + {0x90054, 0x10}, + {0x90055, 0x139}, + {0x90056, 0xb}, + {0x90057, 0x7c0}, + {0x90058, 0x139}, + {0x90059, 0x44}, + {0x9005a, 0x633}, + {0x9005b, 0x159}, + {0x9005c, 0x14f}, + {0x9005d, 0x630}, + {0x9005e, 0x159}, + {0x9005f, 0x47}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x4f}, + {0x90063, 0x633}, + {0x90064, 0x179}, + {0x90065, 0x8}, + {0x90066, 0xe0}, + {0x90067, 0x109}, + {0x90068, 0x0}, + {0x90069, 0x7c8}, + {0x9006a, 0x109}, + {0x9006b, 0x0}, + {0x9006c, 0x1}, + {0x9006d, 0x8}, + {0x9006e, 0x0}, + {0x9006f, 0x45a}, + {0x90070, 0x9}, + {0x90071, 0x0}, + {0x90072, 0x448}, + {0x90073, 0x109}, + {0x90074, 0x40}, + {0x90075, 0x633}, + {0x90076, 0x179}, + {0x90077, 0x1}, + {0x90078, 0x618}, + {0x90079, 0x109}, + {0x9007a, 0x40c0}, + {0x9007b, 0x633}, + {0x9007c, 0x149}, + {0x9007d, 0x8}, + {0x9007e, 0x4}, + {0x9007f, 0x48}, + {0x90080, 0x4040}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x0}, + {0x90084, 0x4}, + {0x90085, 0x48}, + {0x90086, 0x40}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x10}, + {0x9008a, 0x4}, + {0x9008b, 0x18}, + {0x9008c, 0x0}, + {0x9008d, 0x4}, + {0x9008e, 0x78}, + {0x9008f, 0x549}, + {0x90090, 0x633}, + {0x90091, 0x159}, + {0x90092, 0xd49}, + {0x90093, 0x633}, + {0x90094, 0x159}, + {0x90095, 0x94a}, + {0x90096, 0x633}, + {0x90097, 0x159}, + {0x90098, 0x441}, + {0x90099, 0x633}, + {0x9009a, 0x149}, + {0x9009b, 0x42}, + {0x9009c, 0x633}, + {0x9009d, 0x149}, + {0x9009e, 0x1}, + {0x9009f, 0x633}, + {0x900a0, 0x149}, + {0x900a1, 0x0}, + {0x900a2, 0xe0}, + {0x900a3, 0x109}, + {0x900a4, 0xa}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x9}, + {0x900a8, 0x3c0}, + {0x900a9, 0x149}, + {0x900aa, 0x9}, + {0x900ab, 0x3c0}, + {0x900ac, 0x159}, + {0x900ad, 0x18}, + {0x900ae, 0x10}, + {0x900af, 0x109}, + {0x900b0, 0x0}, + {0x900b1, 0x3c0}, + {0x900b2, 0x109}, + {0x900b3, 0x18}, + {0x900b4, 0x4}, + {0x900b5, 0x48}, + {0x900b6, 0x18}, + {0x900b7, 0x4}, + {0x900b8, 0x58}, + {0x900b9, 0xb}, + {0x900ba, 0x10}, + {0x900bb, 0x109}, + {0x900bc, 0x1}, + {0x900bd, 0x10}, + {0x900be, 0x109}, + {0x900bf, 0x5}, + {0x900c0, 0x7c0}, + {0x900c1, 0x109}, + {0x900c2, 0x3}, + {0x900c3, 0x370}, + {0x900c4, 0x169}, + {0x900c5, 0x3}, + {0x900c6, 0x8}, + {0x900c7, 0x139}, + {0x900c8, 0x0}, + {0x900c9, 0x400}, + {0x900ca, 0x16e}, + {0x900cb, 0x8}, + {0x900cc, 0x478}, + {0x900cd, 0x109}, + {0x900ce, 0x0}, + {0x900cf, 0x8140}, + {0x900d0, 0x10c}, + {0x900d1, 0x10}, + {0x900d2, 0x8138}, + {0x900d3, 0x10c}, + {0x900d4, 0x8}, + {0x900d5, 0x7c8}, + {0x900d6, 0x101}, + {0x900d7, 0x7a}, + {0x900d8, 0x8}, + {0x900d9, 0x109}, + {0x900da, 0x8}, + {0x900db, 0x448}, + {0x900dc, 0x109}, + {0x900dd, 0xf}, + {0x900de, 0x7c0}, + {0x900df, 0x109}, + {0x900e0, 0x47}, + {0x900e1, 0x630}, + {0x900e2, 0x109}, + {0x900e3, 0x8}, + {0x900e4, 0x618}, + {0x900e5, 0x109}, + {0x900e6, 0x8}, + {0x900e7, 0xe0}, + {0x900e8, 0x109}, + {0x900e9, 0x0}, + {0x900ea, 0x8}, + {0x900eb, 0x109}, + {0x900ec, 0x0}, + {0x900ed, 0x7c8}, + {0x900ee, 0x109}, + {0x900ef, 0x8}, + {0x900f0, 0x8140}, + {0x900f1, 0x10c}, + {0x900f2, 0x0}, + {0x900f3, 0x478}, + {0x900f4, 0x109}, + {0x900f5, 0x0}, + {0x900f6, 0x1}, + {0x900f7, 0x8}, + {0x900f8, 0x8}, + {0x900f9, 0x4}, + {0x900fa, 0x8}, + {0x900fb, 0x8}, + {0x900fc, 0x7c8}, + {0x900fd, 0x101}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x8}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x90026, 0x3a}, +}; + +static const struct pie pie_lrdimm[] = { + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x78}, + {0x90030, 0x8}, + {0x90031, 0x139}, + {0x90032, 0x2}, + {0x90033, 0x10}, + {0x90034, 0x139}, + {0x90035, 0xb}, + {0x90036, 0x7c0}, + {0x90037, 0x139}, + {0x90038, 0x44}, + {0x90039, 0x633}, + {0x9003a, 0x159}, + {0x9003b, 0x14f}, + {0x9003c, 0x630}, + {0x9003d, 0x159}, + {0x9003e, 0x47}, + {0x9003f, 0x633}, + {0x90040, 0x149}, + {0x90041, 0x4f}, + {0x90042, 0x633}, + {0x90043, 0x179}, + {0x90044, 0x8}, + {0x90045, 0xe0}, + {0x90046, 0x109}, + {0x90047, 0x0}, + {0x90048, 0x7c8}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x1}, + {0x9004c, 0x8}, + {0x9004d, 0x0}, + {0x9004e, 0x45a}, + {0x9004f, 0x9}, + {0x90050, 0x0}, + {0x90051, 0x448}, + {0x90052, 0x109}, + {0x90053, 0x40}, + {0x90054, 0x633}, + {0x90055, 0x179}, + {0x90056, 0x1}, + {0x90057, 0x618}, + {0x90058, 0x109}, + {0x90059, 0x40c0}, + {0x9005a, 0x633}, + {0x9005b, 0x149}, + {0x9005c, 0x8}, + {0x9005d, 0x4}, + {0x9005e, 0x48}, + {0x9005f, 0x4040}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x0}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x40}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x10}, + {0x90069, 0x4}, + {0x9006a, 0x18}, + {0x9006b, 0x0}, + {0x9006c, 0x4}, + {0x9006d, 0x78}, + {0x9006e, 0x549}, + {0x9006f, 0x633}, + {0x90070, 0x159}, + {0x90071, 0xd49}, + {0x90072, 0x633}, + {0x90073, 0x159}, + {0x90074, 0x94a}, + {0x90075, 0x633}, + {0x90076, 0x159}, + {0x90077, 0x441}, + {0x90078, 0x633}, + {0x90079, 0x149}, + {0x9007a, 0x42}, + {0x9007b, 0x633}, + {0x9007c, 0x149}, + {0x9007d, 0x1}, + {0x9007e, 0x633}, + {0x9007f, 0x149}, + {0x90080, 0x0}, + {0x90081, 0xe0}, + {0x90082, 0x109}, + {0x90083, 0xa}, + {0x90084, 0x10}, + {0x90085, 0x109}, + {0x90086, 0x9}, + {0x90087, 0x3c0}, + {0x90088, 0x149}, + {0x90089, 0x9}, + {0x9008a, 0x3c0}, + {0x9008b, 0x159}, + {0x9008c, 0x18}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x0}, + {0x90090, 0x3c0}, + {0x90091, 0x109}, + {0x90092, 0x18}, + {0x90093, 0x4}, + {0x90094, 0x48}, + {0x90095, 0x18}, + {0x90096, 0x4}, + {0x90097, 0x58}, + {0x90098, 0xb}, + {0x90099, 0x10}, + {0x9009a, 0x109}, + {0x9009b, 0x1}, + {0x9009c, 0x10}, + {0x9009d, 0x109}, + {0x9009e, 0x5}, + {0x9009f, 0x7c0}, + {0x900a0, 0x109}, + {0x900a1, 0x3}, + {0x900a2, 0x8}, + {0x900a3, 0x139}, + {0x900a4, 0x0}, + {0x900a5, 0x400}, + {0x900a6, 0x16e}, + {0x900a7, 0x8}, + {0x900a8, 0x478}, + {0x900a9, 0x109}, + {0x900aa, 0x0}, + {0x900ab, 0x8140}, + {0x900ac, 0x10c}, + {0x900ad, 0x10}, + {0x900ae, 0x8138}, + {0x900af, 0x10c}, + {0x900b0, 0x8}, + {0x900b1, 0x7c8}, + {0x900b2, 0x101}, + {0x900b3, 0x7a}, + {0x900b4, 0x8}, + {0x900b5, 0x109}, + {0x900b6, 0x8}, + {0x900b7, 0x448}, + {0x900b8, 0x109}, + {0x900b9, 0xf}, + {0x900ba, 0x7c0}, + {0x900bb, 0x109}, + {0x900bc, 0x47}, + {0x900bd, 0x630}, + {0x900be, 0x109}, + {0x900bf, 0x8}, + {0x900c0, 0x618}, + {0x900c1, 0x109}, + {0x900c2, 0x8}, + {0x900c3, 0xe0}, + {0x900c4, 0x109}, + {0x900c5, 0x0}, + {0x900c6, 0x8}, + {0x900c7, 0x109}, + {0x900c8, 0x0}, + {0x900c9, 0x7c8}, + {0x900ca, 0x109}, + {0x900cb, 0x8}, + {0x900cc, 0x8140}, + {0x900cd, 0x10c}, + {0x900ce, 0x0}, + {0x900cf, 0x478}, + {0x900d0, 0x109}, + {0x900d1, 0x0}, + {0x900d2, 0x1}, + {0x900d3, 0x8}, + {0x900d4, 0x8}, + {0x900d5, 0x4}, + {0x900d6, 0x8}, + {0x900d7, 0x8}, + {0x900d8, 0x7c8}, + {0x900d9, 0x101}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x8}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x90026, 0x2e}, +}; +#endif |