diff options
Diffstat (limited to '')
| -rw-r--r-- | drivers/nxp/gic/gic.mk | 46 | ||||
| -rw-r--r-- | drivers/nxp/gic/ls_gicv2.c | 76 | ||||
| -rw-r--r-- | drivers/nxp/gic/ls_gicv3.c | 78 |
3 files changed, 200 insertions, 0 deletions
diff --git a/drivers/nxp/gic/gic.mk b/drivers/nxp/gic/gic.mk new file mode 100644 index 0000000..d75e071 --- /dev/null +++ b/drivers/nxp/gic/gic.mk @@ -0,0 +1,46 @@ +# Copyright 2021 NXP +# +# SPDX-License-Identifier: BSD-3-Clause +# +# +#------------------------------------------------------------------------------ +# +# Select the GIC files +# +# ----------------------------------------------------------------------------- + +ifeq (${ADD_GIC},) +ADD_GIC := 1 +ifeq ($(GIC), GIC400) +include drivers/arm/gic/v2/gicv2.mk +GIC_SOURCES += ${GICV2_SOURCES} +GIC_SOURCES += ${PLAT_DRIVERS_PATH}/gic/ls_gicv2.c \ + plat/common/plat_gicv2.c + +PLAT_INCLUDES += -I${PLAT_DRIVERS_INCLUDE_PATH}/gic/gicv2 +else +ifeq ($(GIC), GIC500) +include drivers/arm/gic/v3/gicv3.mk +GIC_SOURCES += ${GICV3_SOURCES} +GIC_SOURCES += ${PLAT_DRIVERS_PATH}/gic/ls_gicv3.c \ + plat/common/plat_gicv3.c + +PLAT_INCLUDES += -I${PLAT_DRIVERS_INCLUDE_PATH}/gic/gicv3 +else + $(error -> GIC type not set!) +endif +endif + +ifeq (${BL_COMM_GIC_NEEDED},yes) +BL_COMMON_SOURCES += ${GIC_SOURCES} +else +ifeq (${BL2_GIC_NEEDED},yes) +BL2_SOURCES += ${GIC_SOURCES} +endif +ifeq (${BL31_GIC_NEEDED},yes) +BL31_SOURCES += ${GIC_SOURCES} +endif +endif +endif + +# ----------------------------------------------------------------------------- diff --git a/drivers/nxp/gic/ls_gicv2.c b/drivers/nxp/gic/ls_gicv2.c new file mode 100644 index 0000000..62bc8db --- /dev/null +++ b/drivers/nxp/gic/ls_gicv2.c @@ -0,0 +1,76 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include <gicv2.h> +#include <plat_gic.h> + + +/* + * NXP common helper to initialize the GICv3 only driver. + */ +void plat_ls_gic_driver_init(uintptr_t nxp_gicd_addr, + uintptr_t nxp_gicc_addr, + uint8_t plat_core_count, + interrupt_prop_t *ls_interrupt_props, + uint8_t ls_interrupt_prop_count, + uint32_t *target_mask_array) +{ + static struct gicv2_driver_data ls_gic_data; + + ls_gic_data.gicd_base = nxp_gicd_addr; + ls_gic_data.gicc_base = nxp_gicc_addr; + ls_gic_data.target_masks = target_mask_array; + ls_gic_data.target_masks_num = plat_core_count; + ls_gic_data.interrupt_props = ls_interrupt_props; + ls_gic_data.interrupt_props_num = ls_interrupt_prop_count; + + gicv2_driver_init(&ls_gic_data); +} + +void plat_ls_gic_init(void) +{ + gicv2_distif_init(); + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); +} + +/****************************************************************************** + * ARM common helper to enable the GICv2 CPU interface + *****************************************************************************/ +void plat_ls_gic_cpuif_enable(void) +{ + gicv2_cpuif_enable(); +} + +/****************************************************************************** + * ARM common helper to disable the GICv2 CPU interface + *****************************************************************************/ +void plat_ls_gic_cpuif_disable(void) +{ + gicv2_cpuif_disable(); +} + +/****************************************************************************** + * NXP common helper to initialize GICv2 per cpu + *****************************************************************************/ +void plat_gic_pcpu_init(void) +{ + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); +} + +/****************************************************************************** + * Stubs for Redistributor power management. Although GICv2 doesn't have + * Redistributor interface, these are provided for the sake of uniform GIC API + *****************************************************************************/ +void plat_ls_gic_redistif_on(void) +{ +} + +void plat_ls_gic_redistif_off(void) +{ +} diff --git a/drivers/nxp/gic/ls_gicv3.c b/drivers/nxp/gic/ls_gicv3.c new file mode 100644 index 0000000..9c02bd6 --- /dev/null +++ b/drivers/nxp/gic/ls_gicv3.c @@ -0,0 +1,78 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include <drivers/arm/gicv3.h> +#include <plat_gic.h> +#include <plat/common/platform.h> + +/* + * NXP common helper to initialize the GICv3 only driver. + */ +void plat_ls_gic_driver_init(uintptr_t nxp_gicd_addr, + uintptr_t nxp_gicr_addr, + uint8_t plat_core_count, + interrupt_prop_t *ls_interrupt_props, + uint8_t ls_interrupt_prop_count, + uintptr_t *target_mask_array, + mpidr_hash_fn mpidr_to_core_pos) +{ + static struct gicv3_driver_data ls_gic_data; + + ls_gic_data.gicd_base = nxp_gicd_addr; + ls_gic_data.gicr_base = nxp_gicr_addr; + ls_gic_data.interrupt_props = ls_interrupt_props; + ls_gic_data.interrupt_props_num = ls_interrupt_prop_count; + ls_gic_data.rdistif_num = plat_core_count; + ls_gic_data.rdistif_base_addrs = target_mask_array; + ls_gic_data.mpidr_to_core_pos = mpidr_to_core_pos; + + gicv3_driver_init(&ls_gic_data); +} + +void plat_ls_gic_init(void) +{ + gicv3_distif_init(); + gicv3_rdistif_init(plat_my_core_pos()); + gicv3_cpuif_enable(plat_my_core_pos()); +} + +/* + * NXP common helper to enable the GICv3 CPU interface + */ +void plat_ls_gic_cpuif_enable(void) +{ + gicv3_cpuif_enable(plat_my_core_pos()); +} + +/* + * NXP common helper to disable the GICv3 CPU interface + */ +void plat_ls_gic_cpuif_disable(void) +{ + gicv3_cpuif_disable(plat_my_core_pos()); +} + +/* + * NXP common helper to initialize the per cpu distributor interface in GICv3 + */ +void plat_gic_pcpu_init(void) +{ + gicv3_rdistif_init(plat_my_core_pos()); + gicv3_cpuif_enable(plat_my_core_pos()); +} + +/* + * Stubs for Redistributor power management. Although GICv3 doesn't have + * Redistributor interface, these are provided for the sake of uniform GIC API + */ +void plat_ls_gic_redistif_on(void) +{ +} + +void plat_ls_gic_redistif_off(void) +{ +} |