diff options
Diffstat (limited to 'fdts/stm32mp15-pinctrl.dtsi')
| -rw-r--r-- | fdts/stm32mp15-pinctrl.dtsi | 413 |
1 files changed, 413 insertions, 0 deletions
diff --git a/fdts/stm32mp15-pinctrl.dtsi b/fdts/stm32mp15-pinctrl.dtsi new file mode 100644 index 0000000..7d2be0b --- /dev/null +++ b/fdts/stm32mp15-pinctrl.dtsi @@ -0,0 +1,413 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved + * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. + */ +#include <dt-bindings/pinctrl/stm32-pinfunc.h> + +&pinctrl { + fmc_pins_a: fmc-0 { + pins1 { + pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ + <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */ + <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */ + <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */ + <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */ + <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */ + <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */ + <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */ + <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */ + <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */ + <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */ + <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */ + <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */ + bias-pull-up; + }; + }; + + i2c2_pins_a: i2c2-0 { + pins { + pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */ + <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + qspi_clk_pins_a: qspi-clk-0 { + pins { + pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + }; + + qspi_bk1_pins_a: qspi-bk1-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ + <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */ + <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */ + <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */ + bias-pull-up; + drive-push-pull; + slew-rate = <1>; + }; + }; + + qspi_bk2_pins_a: qspi-bk2-0 { + pins1 { + pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */ + <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */ + <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */ + <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */ + bias-pull-up; + drive-push-pull; + slew-rate = <1>; + }; + }; + + sdmmc1_b4_pins_a: sdmmc1-b4-0 { + pins1 { + pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ + <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ + slew-rate = <2>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc1_dir_pins_a: sdmmc1-dir-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ + <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ + <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ + bias-pull-up; + }; + }; + + sdmmc1_dir_pins_b: sdmmc1-dir-1 { + pins1 { + pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ + <STM32_PINMUX('E', 14, AF11)>, /* SDMMC1_D123DIR */ + <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2{ + pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ + bias-pull-up; + }; + }; + + sdmmc2_b4_pins_a: sdmmc2-b4-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ + <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_b4_pins_b: sdmmc2-b4-1 { + pins1 { + pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ + <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ + slew-rate = <2>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc2_d47_pins_a: sdmmc2-d47-0 { + pins { + pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ + <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ + <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_d47_pins_b: sdmmc2-d47-1 { + pins { + pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ + <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ + <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc2_d47_pins_c: sdmmc2-d47-2 { + pins { + pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */ + <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ + <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_d47_pins_d: sdmmc2-d47-3 { + pins { + pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ + <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ + <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ + }; + }; + + uart4_pins_a: uart4-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_pins_b: uart4-1 { + pins1 { + pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + + uart7_pins_a: uart7-0 { + pins1 { + pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART7_RX */ + <STM32_PINMUX('E', 10, AF7)>, /* UART7_CTS */ + <STM32_PINMUX('E', 9, AF7)>; /* UART7_RTS */ + bias-disable; + }; + }; + + uart7_pins_b: uart7-1 { + pins1 { + pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */ + bias-disable; + }; + }; + + uart7_pins_c: uart7-2 { + pins1 { + pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */ + bias-disable; + }; + }; + + uart8_pins_a: uart8-0 { + pins1 { + pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */ + bias-disable; + }; + }; + + usart2_pins_a: usart2-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ + <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */ + <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_pins_b: usart2-1 { + pins1 { + pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ + <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('F', 4, AF7)>, /* USART2_RX */ + <STM32_PINMUX('E', 15, AF7)>; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_pins_c: usart2-2 { + pins1 { + pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */ + <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins2 { + pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */ + <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart3_pins_a: usart3-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ + bias-disable; + }; + }; + + usart3_pins_b: usart3-1 { + pins1 { + pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ + <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ + <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */ + bias-disable; + }; + }; + + usart3_pins_c: usart3-2 { + pins1 { + pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ + <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ + <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */ + bias-disable; + }; + }; + + usbotg_hs_pins_a: usbotg-hs-0 { + pins { + pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */ + }; + }; + + usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 { + pins { + pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */ + <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */ + }; + }; +}; + +&pinctrl_z { + i2c4_pins_a: i2c4-0 { + pins { + pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */ + <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; +}; |