diff options
Diffstat (limited to '')
| -rw-r--r-- | include/drivers/nxp/dcfg/dcfg.h | 103 | ||||
| -rw-r--r-- | include/drivers/nxp/dcfg/dcfg_lsch2.h | 85 | ||||
| -rw-r--r-- | include/drivers/nxp/dcfg/dcfg_lsch3.h | 80 | ||||
| -rw-r--r-- | include/drivers/nxp/dcfg/scfg.h | 65 |
4 files changed, 333 insertions, 0 deletions
diff --git a/include/drivers/nxp/dcfg/dcfg.h b/include/drivers/nxp/dcfg/dcfg.h new file mode 100644 index 0000000..cf29b12 --- /dev/null +++ b/include/drivers/nxp/dcfg/dcfg.h @@ -0,0 +1,103 @@ +/* + * Copyright 2018-2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef DCFG_H +#define DCFG_H + +#include <endian.h> + +#if defined(CONFIG_CHASSIS_2) +#include <dcfg_lsch2.h> +#elif defined(CONFIG_CHASSIS_3_2) || defined(CONFIG_CHASSIS_3) +#include <dcfg_lsch3.h> +#endif + +#ifdef NXP_GUR_BE +#define gur_in32(a) bswap32(mmio_read_32((uintptr_t)(a))) +#define gur_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v)) +#elif defined(NXP_GUR_LE) +#define gur_in32(a) mmio_read_32((uintptr_t)(a)) +#define gur_out32(a, v) mmio_write_32((uintptr_t)(a), v) +#else +#error Please define CCSR GUR register endianness +#endif + +typedef struct { + union { + uint32_t val; + struct { + uint32_t min_ver:4; + uint32_t maj_ver:4; +#if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2) + uint32_t personality:6; + uint32_t rsv1:2; +#elif defined(CONFIG_CHASSIS_2) + uint32_t personality:8; + +#endif +#if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2) + uint32_t dev_id:6; + uint32_t rsv2:2; + uint32_t family:4; +#elif defined(CONFIG_CHASSIS_2) + uint32_t dev_id:12; +#endif + uint32_t mfr_id; + } __packed bf; + struct { + uint32_t maj_min:8; + uint32_t version; /* SoC version without major and minor info */ + } __packed bf_ver; + } __packed svr_reg; + bool sec_enabled; + bool is_populated; +} soc_info_t; + +typedef struct { + bool is_populated; + uint8_t ocram_present; + uint8_t ddrc1_present; +#if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2) + uint8_t ddrc2_present; +#endif +} devdisr5_info_t; + +typedef struct { + uint32_t porsr1; + uintptr_t g_nxp_dcfg_addr; + unsigned long nxp_sysclk_freq; + unsigned long nxp_ddrclk_freq; + unsigned int nxp_plat_clk_divider; +} dcfg_init_info_t; + + +struct sysinfo { + unsigned long freq_platform; + unsigned long freq_ddr_pll0; + unsigned long freq_ddr_pll1; +}; + +int get_clocks(struct sysinfo *sys); + +/* Read the PORSR1 register */ +uint32_t read_reg_porsr1(void); + +/******************************************************************************* + * Returns true if secur eboot is enabled on board + * mode = 0 (development mode - sb_en = 1) + * mode = 1 (production mode - ITS = 1) + ******************************************************************************/ +bool check_boot_mode_secure(uint32_t *mode); + +const soc_info_t *get_soc_info(); +const devdisr5_info_t *get_devdisr5_info(); + +void dcfg_init(dcfg_init_info_t *dcfg_init_data); +bool is_sec_enabled(void); + +void error_handler(int error_code); +#endif /* DCFG_H */ diff --git a/include/drivers/nxp/dcfg/dcfg_lsch2.h b/include/drivers/nxp/dcfg/dcfg_lsch2.h new file mode 100644 index 0000000..882ba5a --- /dev/null +++ b/include/drivers/nxp/dcfg/dcfg_lsch2.h @@ -0,0 +1,85 @@ +/* + * Copyright 2020-2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef DCFG_LSCH2_H +#define DCFG_LSCH2_H + +/* dcfg block register offsets and bitfields */ +#define DCFG_PORSR1_OFFSET 0x00 +#define DCFG_DEVDISR1_OFFSET 0x070 +#define DCFG_DEVDISR2_OFFSET 0x074 +#define DCFG_DEVDISR3_OFFSET 0x078 +#define DCFG_DEVDISR4_OFFSET 0x07C +#define DCFG_DEVDISR5_OFFSET 0x080 +#define DCFG_COREDISR_OFFSET 0x094 +#define RCWSR0_OFFSET 0x100 +#define RCWSR5_OFFSET 0x118 +#define DCFG_BOOTLOCPTRL_OFFSET 0x400 +#define DCFG_BOOTLOCPTRH_OFFSET 0x404 +#define DCFG_COREDISABLEDSR_OFFSET 0x990 +#define DCFG_SCRATCH4_OFFSET 0x20C +#define DCFG_SVR_OFFSET 0x0A4 +#define DCFG_BRR_OFFSET 0x0E4 + +#define DCFG_RSTCR_OFFSET 0x0B0 +#define RSTCR_RESET_REQ 0x2 + +#define DCFG_RSTRQSR1_OFFSET 0x0C8 +#define DCFG_RSTRQMR1_OFFSET 0x0C0 + +/* PORSR1 bit mask */ +#define PORSR1_RCW_MASK 0xff800000 +#define PORSR1_RCW_SHIFT 23 + +/* DCFG DCSR Macros */ +#define DCFG_DCSR_PORCR1_OFFSET 0x0 + +#define SVR_MFR_ID_MASK 0xF0000000 +#define SVR_MFR_ID_SHIFT 28 +#define SVR_DEV_ID_MASK 0xFFF0000 +#define SVR_DEV_ID_SHIFT 16 +#define SVR_PERSONALITY_MASK 0xFF00 +#define SVR_PERSONALITY_SHIFT 8 +#define SVR_SEC_MASK 0x100 +#define SVR_SEC_SHIFT 8 +#define SVR_MAJ_VER_MASK 0xF0 +#define SVR_MAJ_VER_SHIFT 4 +#define SVR_MIN_VER_MASK 0xF +#define SVR_MINOR_VER_0 0x00 +#define SVR_MINOR_VER_1 0x01 + +#define DISR5_DDRC1_MASK 0x1 +#define DISR5_OCRAM_MASK 0x40 + +/* DCFG regsiters bit masks */ +#define RCWSR0_SYS_PLL_RAT_SHIFT 25 +#define RCWSR0_SYS_PLL_RAT_MASK 0x1f +#define RCWSR0_MEM_PLL_RAT_SHIFT 16 +#define RCWSR0_MEM_PLL_RAT_MASK 0x3f +#define RCWSR0_MEM2_PLL_RAT_SHIFT 18 +#define RCWSR0_MEM2_PLL_RAT_MASK 0x3f + +#define RCWSR_SB_EN_OFFSET RCWSR5_OFFSET +#define RCWSR_SBEN_MASK 0x1 +#define RCWSR_SBEN_SHIFT 21 + +/* RCW SRC NAND */ +#define RCW_SRC_NAND_MASK (0x100) +#define RCW_SRC_NAND_VAL (0x100) +#define NAND_RESERVED_MASK (0xFC) +#define NAND_RESERVED_1 (0x0) +#define NAND_RESERVED_2 (0x80) + +/* RCW SRC NOR */ +#define RCW_SRC_NOR_MASK (0x1F0) +#define NOR_8B_VAL (0x10) +#define NOR_16B_VAL (0x20) +#define SD_VAL (0x40) +#define QSPI_VAL1 (0x44) +#define QSPI_VAL2 (0x45) + +#endif /* DCFG_LSCH2_H */ diff --git a/include/drivers/nxp/dcfg/dcfg_lsch3.h b/include/drivers/nxp/dcfg/dcfg_lsch3.h new file mode 100644 index 0000000..cde86fe --- /dev/null +++ b/include/drivers/nxp/dcfg/dcfg_lsch3.h @@ -0,0 +1,80 @@ +/* + * Copyright 2020-2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef DCFG_LSCH3_H +#define DCFG_LSCH3_H + +/* dcfg block register offsets and bitfields */ +#define DCFG_PORSR1_OFFSET 0x00 + +#define DCFG_DEVDISR1_OFFSET 0x70 +#define DCFG_DEVDISR1_SEC (1 << 22) + +#define DCFG_DEVDISR2_OFFSET 0x74 + +#define DCFG_DEVDISR3_OFFSET 0x78 +#define DCFG_DEVDISR3_QBMAIN (1 << 12) + +#define DCFG_DEVDISR4_OFFSET 0x7C +#define DCFG_DEVDISR4_SPI_QSPI (1 << 4 | 1 << 5) + +#define DCFG_DEVDISR5_OFFSET 0x80 +#define DISR5_DDRC1_MASK 0x1 +#define DISR5_DDRC2_MASK 0x2 +#define DISR5_OCRAM_MASK 0x1000 +#define DEVDISR5_MASK_ALL_MEM 0x00001003 +#define DEVDISR5_MASK_DDR 0x00000003 +#define DEVDISR5_MASK_DBG 0x00000400 + +#define DCFG_DEVDISR6_OFFSET 0x84 +//#define DEVDISR6_MASK 0x00000001 + +#define DCFG_COREDISR_OFFSET 0x94 + +#define DCFG_SVR_OFFSET 0x0A4 +#define SVR_MFR_ID_MASK 0xF0000000 +#define SVR_MFR_ID_SHIFT 28 +#define SVR_FAMILY_MASK 0xF000000 +#define SVR_FAMILY_SHIFT 24 +#define SVR_DEV_ID_MASK 0x3F0000 +#define SVR_DEV_ID_SHIFT 16 +#define SVR_PERSONALITY_MASK 0x3E00 +#define SVR_PERSONALITY_SHIFT 9 +#define SVR_SEC_MASK 0x100 +#define SVR_SEC_SHIFT 8 +#define SVR_MAJ_VER_MASK 0xF0 +#define SVR_MAJ_VER_SHIFT 4 +#define SVR_MIN_VER_MASK 0xF + +#define RCWSR0_OFFSET 0x100 +#define RCWSR0_SYS_PLL_RAT_SHIFT 2 +#define RCWSR0_SYS_PLL_RAT_MASK 0x1f +#define RCWSR0_MEM_PLL_RAT_SHIFT 10 +#define RCWSR0_MEM_PLL_RAT_MASK 0x3f +#define RCWSR0_MEM2_PLL_RAT_SHIFT 18 +#define RCWSR0_MEM2_PLL_RAT_MASK 0x3f + +#define RCWSR5_OFFSET 0x110 +#define RCWSR9_OFFSET 0x120 +#define RCWSR_SB_EN_OFFSET RCWSR9_OFFSET +#define RCWSR_SBEN_MASK 0x1 +#define RCWSR_SBEN_SHIFT 10 + +#define RCW_SR27_OFFSET 0x168 +/* DCFG register to dump error code */ +#define DCFG_SCRATCH4_OFFSET 0x20C +#define DCFG_SCRATCHRW5_OFFSET 0x210 +#define DCFG_SCRATCHRW6_OFFSET 0x214 +#define DCFG_SCRATCHRW7_OFFSET 0x218 +#define DCFG_BOOTLOCPTRL_OFFSET 0x400 +#define DCFG_BOOTLOCPTRH_OFFSET 0x404 +#define DCFG_COREDISABLEDSR_OFFSET 0x990 + +/* Reset module bit field */ +#define RSTCR_RESET_REQ 0x2 + +#endif /* DCFG_LSCH3_H */ diff --git a/include/drivers/nxp/dcfg/scfg.h b/include/drivers/nxp/dcfg/scfg.h new file mode 100644 index 0000000..8067de1 --- /dev/null +++ b/include/drivers/nxp/dcfg/scfg.h @@ -0,0 +1,65 @@ +/* + * Copyright 2020-2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef SCFG_H +#define SCFG_H + +#ifdef CONFIG_CHASSIS_2 + +/* SCFG register offsets */ +#define SCFG_CORE0_SFT_RST_OFFSET 0x0130 +#define SCFG_SNPCNFGCR_OFFSET 0x01A4 +#define SCFG_CORESRENCR_OFFSET 0x0204 +#define SCFG_RVBAR0_0_OFFSET 0x0220 +#define SCFG_RVBAR0_1_OFFSET 0x0224 +#define SCFG_COREBCR_OFFSET 0x0680 +#define SCFG_RETREQCR_OFFSET 0x0424 + +#define SCFG_COREPMCR_OFFSET 0x042C +#define COREPMCR_WFIL2 0x1 + +#define SCFG_GIC400_ADDR_ALIGN_OFFSET 0x0188 +#define SCFG_BOOTLOCPTRH_OFFSET 0x0600 +#define SCFG_BOOTLOCPTRL_OFFSET 0x0604 +#define SCFG_SCRATCHRW2_OFFSET 0x0608 +#define SCFG_SCRATCHRW3_OFFSET 0x060C + +/* SCFG bit fields */ +#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 +#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 + +/* GIC Address Align Register */ +#define SCFG_GIC400_ADDR_ALIGN_4KMODE_MASK 0x80000000 +#define SCFG_GIC400_ADDR_ALIGN_4KMODE_EN 0x80000000 +#define SCFG_GIC400_ADDR_ALIGN_4KMODE_DIS 0x0 + +#endif /* CONFIG_CHASSIS_2 */ + +#ifndef __ASSEMBLER__ +#include <endian.h> +#include <lib/mmio.h> + +#ifdef NXP_SCFG_BE +#define scfg_in32(a) bswap32(mmio_read_32((uintptr_t)(a))) +#define scfg_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v)) +#define scfg_setbits32(a, v) mmio_setbits_32((uintptr_t)(a), v) +#define scfg_clrbits32(a, v) mmio_clrbits_32((uintptr_t)(a), v) +#define scfg_clrsetbits32(a, clear, set) \ + mmio_clrsetbits_32((uintptr_t)(a), clear, set) +#elif defined(NXP_SCFG_LE) +#define scfg_in32(a) mmio_read_32((uintptr_t)(a)) +#define scfg_out32(a, v) mmio_write_32((uintptr_t)(a), v) +#define scfg_setbits32(a, v) mmio_setbits_32((uintptr_t)(a), v) +#define scfg_clrbits32(a, v) mmio_clrbits_32((uintptr_t)(a), v) +#define scfg_clrsetbits32(a, clear, set) \ + mmio_clrsetbits_32((uintptr_t)(a), clear, set) +#else +#error Please define CCSR SCFG register endianness +#endif +#endif /* __ASSEMBLER__ */ + +#endif /* SCFG_H */ |